diff options
author | 2008-01-29 19:35:27 +0000 | |
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committer | 2008-01-29 19:35:27 +0000 | |
commit | dbf80b011ccb7d43ff75bf4f8cae982c71e94559 (patch) | |
tree | 967c01b641edd700e16cfc61555d053afb250b64 /src/emu/cpu/mips/mips3com.c | |
parent | acd05b666f71a59aaec51e314a1d9d0182e73f8c (diff) |
Removed distinction between *_gettotalcycles() and *_gettotalcycles64().
All functions now return 64-bit results.
Updated all call sites appropriately.
Diffstat (limited to 'src/emu/cpu/mips/mips3com.c')
-rw-r--r-- | src/emu/cpu/mips/mips3com.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/emu/cpu/mips/mips3com.c b/src/emu/cpu/mips/mips3com.c index 7f616251ef2..49a74e2056a 100644 --- a/src/emu/cpu/mips/mips3com.c +++ b/src/emu/cpu/mips/mips3com.c @@ -144,7 +144,7 @@ void mips3com_reset(mips3_state *mips) mips->cpr[0][COP0_Count] = 0; mips->cpr[0][COP0_Config] = compute_config_register(mips); mips->cpr[0][COP0_PRId] = compute_prid_register(mips); - mips->count_zero_time = activecpu_gettotalcycles64(); + mips->count_zero_time = activecpu_gettotalcycles(); /* recompute the TLB table */ mips3com_recompute_tlb_table(mips); @@ -181,7 +181,7 @@ void mips3com_update_cycle_counting(mips3_state *mips) /* modify the timer to go off */ if ((mips->cpr[0][COP0_Status] & SR_IMEX5) && mips->cpr[0][COP0_Compare] != 0xffffffff) { - UINT32 count = (activecpu_gettotalcycles64() - mips->count_zero_time) / 2; + UINT32 count = (activecpu_gettotalcycles() - mips->count_zero_time) / 2; UINT32 compare = mips->cpr[0][COP0_Compare]; UINT32 cyclesleft = compare - count; attotime newtime = ATTOTIME_IN_CYCLES(((INT64)cyclesleft * 2), cpu_getactivecpu()); @@ -362,7 +362,7 @@ void mips3com_tlbwr(mips3_state *mips) /* "random" is based off of the current cycle counting through the non-wired pages */ if (unwired > 0) - index = ((activecpu_gettotalcycles64() - mips->count_zero_time) % unwired + wired) & 0x3f; + index = ((activecpu_gettotalcycles() - mips->count_zero_time) % unwired + wired) & 0x3f; /* use the common handler to write to this index */ tlb_write_common(mips, index); @@ -559,7 +559,7 @@ void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info) case CPUINFO_INT_REGISTER + MIPS3_SR: info->i = mips->cpr[0][COP0_Status]; break; case CPUINFO_INT_REGISTER + MIPS3_EPC: info->i = mips->cpr[0][COP0_EPC]; break; case CPUINFO_INT_REGISTER + MIPS3_CAUSE: info->i = mips->cpr[0][COP0_Cause]; break; - case CPUINFO_INT_REGISTER + MIPS3_COUNT: info->i = ((activecpu_gettotalcycles64() - mips->count_zero_time) / 2); break; + case CPUINFO_INT_REGISTER + MIPS3_COUNT: info->i = ((activecpu_gettotalcycles() - mips->count_zero_time) / 2); break; case CPUINFO_INT_REGISTER + MIPS3_COMPARE: info->i = mips->cpr[0][COP0_Compare]; break; case CPUINFO_INT_REGISTER + MIPS3_INDEX: info->i = mips->cpr[0][COP0_Index]; break; case CPUINFO_INT_REGISTER + MIPS3_RANDOM: info->i = mips->cpr[0][COP0_Random]; break; @@ -631,7 +631,7 @@ void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info) case CPUINFO_STR_REGISTER + MIPS3_SR: sprintf(info->s, "SR: %08X", (UINT32)mips->cpr[0][COP0_Status]); break; case CPUINFO_STR_REGISTER + MIPS3_EPC: sprintf(info->s, "EPC:%08X", (UINT32)mips->cpr[0][COP0_EPC]); break; case CPUINFO_STR_REGISTER + MIPS3_CAUSE: sprintf(info->s, "Cause:%08X", (UINT32)mips->cpr[0][COP0_Cause]); break; - case CPUINFO_STR_REGISTER + MIPS3_COUNT: sprintf(info->s, "Count:%08X", (UINT32)((activecpu_gettotalcycles64() - mips->count_zero_time) / 2)); break; + case CPUINFO_STR_REGISTER + MIPS3_COUNT: sprintf(info->s, "Count:%08X", (UINT32)((activecpu_gettotalcycles() - mips->count_zero_time) / 2)); break; case CPUINFO_STR_REGISTER + MIPS3_COMPARE: sprintf(info->s, "Compare:%08X", (UINT32)mips->cpr[0][COP0_Compare]); break; case CPUINFO_STR_REGISTER + MIPS3_INDEX: sprintf(info->s, "Index:%08X", (UINT32)mips->cpr[0][COP0_Index]); break; case CPUINFO_STR_REGISTER + MIPS3_RANDOM: sprintf(info->s, "Random:%08X", (UINT32)mips->cpr[0][COP0_Random]); break; |