diff options
| author | 2015-09-30 08:29:01 +0200 | |
|---|---|---|
| committer | 2015-09-30 08:29:01 +0200 | |
| commit | 8e4ced4b531ac52fb764d9374a7c215bc62a890a (patch) | |
| tree | c29767f6a9f305bac993eaaf1ca268e85cf0427c /src/devices | |
| parent | 9fd990dea821ddca94916fa3eed0aef824eb08ea (diff) | |
Cleanups and version bumpmame0166
Diffstat (limited to 'src/devices')
28 files changed, 1414 insertions, 1421 deletions
diff --git a/src/devices/bus/centronics/nec_p72.h b/src/devices/bus/centronics/nec_p72.h index dbea1353501..07335577ed4 100644 --- a/src/devices/bus/centronics/nec_p72.h +++ b/src/devices/bus/centronics/nec_p72.h @@ -17,15 +17,15 @@ // ======================> nec_p72_t class nec_p72_t : public device_t, - public device_centronics_peripheral_interface + public device_centronics_peripheral_interface { public: // construction/destruction nec_p72_t(const machine_config &mconfig, const char *tag, - device_t *owner, UINT32 clock); + device_t *owner, UINT32 clock); nec_p72_t(const machine_config &mconfig, device_type type, - const char *name, const char *tag, device_t *owner, - UINT32 clock, const char *shortname, const char *source); + const char *name, const char *tag, device_t *owner, + UINT32 clock, const char *shortname, const char *source); // optional information overrides virtual const rom_entry *device_rom_region() const; diff --git a/src/devices/bus/cpc/cpcexp.h b/src/devices/bus/cpc/cpcexp.h index e52c447b72b..1a61dc2b409 100644 --- a/src/devices/bus/cpc/cpcexp.h +++ b/src/devices/bus/cpc/cpcexp.h @@ -33,7 +33,7 @@ * GND 49 50 CLOCK * * Aleste 520EX expansion port is 62-pin. Same as the CPC above, except that pin 40 is not connected, plus the following: - * + * * MAP14 A26 B26 MAP15 * MAP16 A27 B27 MAP17 * MAP18 A28 B28 MAPBLK diff --git a/src/devices/bus/cpc/magicsound.c b/src/devices/bus/cpc/magicsound.c index 601672a2e58..16e4f7d51b8 100644 --- a/src/devices/bus/cpc/magicsound.c +++ b/src/devices/bus/cpc/magicsound.c @@ -6,7 +6,7 @@ * Magic Sound Board for the Aleste 520EX * */ - + #include "emu.h" #include "magicsound.h" #include "includes/amstrad.h" @@ -22,7 +22,7 @@ const device_type AL_MAGICSOUND = &device_creator<al_magicsound_device>; static MACHINE_CONFIG_FRAGMENT( al_magicsound ) MCFG_DEVICE_ADD( "dmac", AM9517A, XTAL_4MHz ) // CLK from expansion port // According to the schematics, the TC pin (EOP on western chips) is connected to NMI on the expansion port. - // NMIs seem to occur too quickly when this is active, so either EOP is not triggered at the correct time, or + // NMIs seem to occur too quickly when this is active, so either EOP is not triggered at the correct time, or // the K1810WT37 is different to the i8237/AM9517A //MCFG_I8237_OUT_EOP_CB(DEVWRITELINE("^", cpc_expansion_slot_device, nmi_w)) // MCFG_DEVCB_INVERT MCFG_I8237_OUT_HREQ_CB(DEVWRITELINE("dmac", am9517a_device, hack_w)) @@ -56,7 +56,7 @@ static MACHINE_CONFIG_FRAGMENT( al_magicsound ) MCFG_PIT8253_CLK2(XTAL_4MHz) MCFG_SPEAKER_STANDARD_MONO("mono") - MCFG_DAC_ADD("dac1") + MCFG_DAC_ADD("dac1") MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00) // no pass-through(?) MACHINE_CONFIG_END @@ -94,9 +94,9 @@ void al_magicsound_device::device_start() space.install_write_handler(0xf9d0,0xf9df,0,0,write8_delegate(FUNC(al_magicsound_device::timer_w),this)); space.install_write_handler(0xfad0,0xfadf,0,0,write8_delegate(FUNC(al_magicsound_device::volume_w),this)); space.install_write_handler(0xfbd0,0xfbdf,0,0,write8_delegate(FUNC(al_magicsound_device::mapper_w),this)); - + m_ramptr = machine().device<ram_device>(":" RAM_TAG); - + for(int x=0;x<4;x++) { save_item(NAME(m_output[x]),x); @@ -167,7 +167,7 @@ READ8_MEMBER(al_magicsound_device::dma_read_byte) { UINT8 ret = 0xff; UINT8 page = (offset & 0xc000) >> 14; - + if(m_current_channel != -1) ret = m_ramptr->read(m_page[m_current_channel][page] + (offset & 0x3fff)); return ret; @@ -187,4 +187,3 @@ void al_magicsound_device::set_timer_gate(bool state) m_timer2->write_gate1(state); m_timer2->write_gate2(state); } - diff --git a/src/devices/bus/cpc/magicsound.h b/src/devices/bus/cpc/magicsound.h index 3332dbee889..588ead99b40 100644 --- a/src/devices/bus/cpc/magicsound.h +++ b/src/devices/bus/cpc/magicsound.h @@ -6,7 +6,7 @@ * Magic Sound Board for the Aleste 520EX * * DMA-based 4-channel sound board - * + * * 1x K1810WT37 DMA controller (i8237/AM9517A) * 2x K1810WT54 programmable timers (i8254) * 1x K1118PA1 DAC (MC10318) @@ -72,9 +72,9 @@ private: required_device<am9517a_device> m_dmac; required_device<pit8254_device> m_timer1; required_device<pit8254_device> m_timer2; - + void set_timer_gate(bool state); - + UINT8 m_volume[4]; UINT32 m_page[4][4]; UINT8 m_output[4]; diff --git a/src/devices/bus/isa/pgc.c b/src/devices/bus/isa/pgc.c index 6ed1f4b3cb3..01ef4668b58 100644 --- a/src/devices/bus/isa/pgc.c +++ b/src/devices/bus/isa/pgc.c @@ -77,9 +77,9 @@ ROM_END static INPUT_PORTS_START( pgc ) PORT_START("DSW") /* - PORT_DIPNAME( 0x01, 0x00, "CGA emulator") - PORT_DIPSETTING( 0x00, DEF_STR(No) ) - PORT_DIPSETTING( 0x01, DEF_STR(Yes) ) + PORT_DIPNAME( 0x01, 0x00, "CGA emulator") + PORT_DIPSETTING( 0x00, DEF_STR(No) ) + PORT_DIPSETTING( 0x01, DEF_STR(Yes) ) */ PORT_DIPNAME( 0x02, 0x00, "Communication area") PORT_DIPSETTING( 0x00, "C6000" ) @@ -88,19 +88,19 @@ INPUT_PORTS_END /* write only - 30000 LUT WR O L - 30001 LUT WR I L - 32000 MODE WT L - 32001 NIBBLE WT L - 3200A ?? - 34000 FUNCTION WT L - 34001 STARTADD WT L - 36001 CURSOR WT L + 30000 LUT WR O L + 30001 LUT WR I L + 32000 MODE WT L + 32001 NIBBLE WT L + 3200A ?? + 34000 FUNCTION WT L + 34001 STARTADD WT L + 36001 CURSOR WT L read only - 38000 LUT RD O L - 38001 LUT RD I L - 3C001 INIT L/INIT H + 38000 LUT RD O L + 38001 LUT RD I L + 3C001 INIT L/INIT H */ static ADDRESS_MAP_START( pgc_map, AS_PROGRAM, 8, isa8_pgc_device ) @@ -108,10 +108,10 @@ static ADDRESS_MAP_START( pgc_map, AS_PROGRAM, 8, isa8_pgc_device ) AM_RANGE(0x00000, 0x07fff) AM_ROM AM_RANGE(0x08000, 0x0ffff) AM_ROM AM_REGION("maincpu", 0x8000) AM_RANGE(0x10000, 0x1001f) AM_READWRITE(stateparam_r, stateparam_w) -// AM_RANGE(0x18000, 0x18fff) AM_RAM // ?? +// AM_RANGE(0x18000, 0x18fff) AM_RAM // ?? AM_RANGE(0x28000, 0x287ff) AM_RAM AM_REGION("commarea", 0) AM_MIRROR(0x800) AM_RANGE(0x3c000, 0x3c001) AM_READ(init_r) -// AM_RANGE(0x3e000, 0x3efff) AM_RAM // ?? +// AM_RANGE(0x3e000, 0x3efff) AM_RAM // ?? AM_RANGE(0xf8000, 0xfffff) AM_ROM AM_REGION("maincpu", 0x8000) ADDRESS_MAP_END @@ -311,7 +311,7 @@ WRITE8_MEMBER( isa8_pgc_device::lut_w ) { if (offset & 1) { m_lut[o + 2] = (data & 15) << 4; m_palette->set_pen_color( offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] ); - DBG_LOG(1,"lut",("W @ %02X <- %d %d %d\n", + DBG_LOG(1,"lut",("W @ %02X <- %d %d %d\n", offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] )); } else { m_lut[o ] = data & 0xf0; @@ -330,7 +330,7 @@ READ8_MEMBER( isa8_pgc_device::init_r ) { DBG_LOG(1,"INIT",("mapping LUT\n")); space.install_write_handler(0xf8400, 0xf85ff, write8_delegate(FUNC(isa8_pgc_device::lut_w), this)); - + return 0; // XXX ignored } @@ -341,7 +341,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(isa8_pgc_device::scanline_callback) UINT8 *v; // XXX hpos shifts every frame -- fix - if (y == 0) DBG_LOG(2,"scanline_cb", + if (y == 0) DBG_LOG(2,"scanline_cb", ("frame %d x %.4d y %.3d\n", (int) m_screen->frame_number(), m_screen->hpos(), y)); diff --git a/src/devices/bus/lpci/vt82c505.c b/src/devices/bus/lpci/vt82c505.c index 8234a33d988..15ba12b403b 100644 --- a/src/devices/bus/lpci/vt82c505.c +++ b/src/devices/bus/lpci/vt82c505.c @@ -2,7 +2,7 @@ // copyright-holders:Barry Rodewald /* - VIA VT82C505 ISA/VL PCI bridge + VIA VT82C505 ISA/VL PCI bridge */ @@ -27,7 +27,7 @@ vt82c505_device::vt82c505_device(const machine_config &mconfig, const char *tag, UINT32 vt82c505_device::pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask) { UINT32 result = 0; - + if (function != 0) return result; @@ -94,4 +94,3 @@ void vt82c505_device::device_start() void vt82c505_device::device_reset() { } - diff --git a/src/devices/bus/lpci/vt82c505.h b/src/devices/bus/lpci/vt82c505.h index 7c34567c62d..8021077081f 100644 --- a/src/devices/bus/lpci/vt82c505.h +++ b/src/devices/bus/lpci/vt82c505.h @@ -2,7 +2,7 @@ // copyright-holders:Barry Rodewald /* - VIA VT82C505 PCI bridge + VIA VT82C505 PCI bridge */ diff --git a/src/devices/bus/pc_kbd/iskr1030.c b/src/devices/bus/pc_kbd/iskr1030.c index ecee5639129..581f30b5a77 100644 --- a/src/devices/bus/pc_kbd/iskr1030.c +++ b/src/devices/bus/pc_kbd/iskr1030.c @@ -416,7 +416,7 @@ WRITE8_MEMBER( iskr_1030_keyboard_device::ram_w ) READ8_MEMBER( iskr_1030_keyboard_device::ram_r ) { DBG_LOG(2,0,( "%s: ram_r[%02x] = %02x\n", tag(), offset, m_ram[offset])); - + return m_ram[offset]; } diff --git a/src/devices/cpu/m68000/m68kops.c b/src/devices/cpu/m68000/m68kops.c index 245f5fb3b0a..b0eeec4fad3 100644 --- a/src/devices/cpu/m68000/m68kops.c +++ b/src/devices/cpu/m68000/m68kops.c @@ -34872,5 +34872,3 @@ void m68ki_build_opcode_table(void) /* ======================================================================== */ /* ============================== END OF FILE ============================= */ /* ======================================================================== */ - - diff --git a/src/devices/cpu/mips/mips3.c b/src/devices/cpu/mips/mips3.c index ffed0db99c2..7ee13632695 100644 --- a/src/devices/cpu/mips/mips3.c +++ b/src/devices/cpu/mips/mips3.c @@ -2845,7 +2845,7 @@ void mips3_device::execute_run() case 0x2e: /* SWR */ (this->*m_swr)(op); break; case 0x2f: /* CACHE */ /* effective no-op */ break; case 0x30: /* LL */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; m_ll_value = RTVAL32; break; - case 0x31: /* LWC1 */ + case 0x31: /* LWC1 */ if (!(SR & SR_COP1)) { m_badcop_value = 1; @@ -2855,7 +2855,7 @@ void mips3_device::execute_run() case 0x32: /* LWC2 */ if (RWORD(SIMMVAL+RSVAL32, &temp)) set_cop2_reg(RTREG, temp); break; case 0x33: /* PREF */ /* effective no-op */ break; case 0x34: /* LLD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; m_lld_value = temp64; break; - case 0x35: /* LDC1 */ + case 0x35: /* LDC1 */ if (!(SR & SR_COP1)) { m_badcop_value = 1; @@ -2877,7 +2877,7 @@ void mips3_device::execute_run() } } break; - case 0x39: /* SWC1 */ + case 0x39: /* SWC1 */ if (!(SR & SR_COP1)) { m_badcop_value = 1; diff --git a/src/devices/cpu/rsp/rsp_dasm.c b/src/devices/cpu/rsp/rsp_dasm.c index 70e6d7e47e8..bf56b240652 100644 --- a/src/devices/cpu/rsp/rsp_dasm.c +++ b/src/devices/cpu/rsp/rsp_dasm.c @@ -10,10 +10,10 @@ /*static const char *const reg[32] = { - "0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" + "0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; */ diff --git a/src/devices/cpu/t11/t11.c b/src/devices/cpu/t11/t11.c index 97f53e74b34..4a012ec0505 100644 --- a/src/devices/cpu/t11/t11.c +++ b/src/devices/cpu/t11/t11.c @@ -365,7 +365,7 @@ void t11_device::device_reset() void k1801vm2_device::device_reset() { t11_device::device_reset(); - + PC = RWORD(c_initial_mode); PSW = RWORD(c_initial_mode+2); } diff --git a/src/devices/machine/68230pit.c b/src/devices/machine/68230pit.c index 46c8733f085..077703d2ee8 100644 --- a/src/devices/machine/68230pit.c +++ b/src/devices/machine/68230pit.c @@ -27,21 +27,21 @@ const device_type PIT68230 = &device_creator<pit68230_device>; // pit68230_device - constructors //------------------------------------------------- pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source) - : device_t (mconfig, type, name, tag, owner, clock, shortname, source), - device_execute_interface (mconfig, *this) - , m_icount (0) - , m_write_pa (*this) - , m_write_h2 (*this) + : device_t (mconfig, type, name, tag, owner, clock, shortname, source), + device_execute_interface (mconfig, *this) + , m_icount (0) + , m_write_pa (*this) + , m_write_h2 (*this) { } pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__), - device_execute_interface (mconfig, *this) - , m_icount (0) - , m_write_pa (*this) - , m_write_h2 (*this) + : device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__), + device_execute_interface (mconfig, *this) + , m_icount (0) + , m_write_pa (*this) + , m_write_h2 (*this) { } @@ -50,12 +50,12 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, //------------------------------------------------- void pit68230_device::device_start () { - LOG (logerror ("PIT68230 device started\n")); - m_icountptr = &m_icount; + LOG (logerror ("PIT68230 device started\n")); + m_icountptr = &m_icount; - // resolve callbacks - m_write_pa.resolve_safe (); - m_write_h2.resolve_safe (); + // resolve callbacks + m_write_pa.resolve_safe (); + m_write_h2.resolve_safe (); } //------------------------------------------------- @@ -63,17 +63,17 @@ void pit68230_device::device_start () //------------------------------------------------- void pit68230_device::device_reset () { - LOG (logerror ("PIT68230 device reseted\n")); - m_pgcr = 0; - m_psrr = 0; - m_paddr = 0; - m_pbddr = 0; - m_pcddr = 0; - m_pacr = 0; m_write_h2 (m_pacr); - m_pbcr = 0; - m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR - m_pbdr = 0; - m_psr = 0; + LOG (logerror ("PIT68230 device reseted\n")); + m_pgcr = 0; + m_psrr = 0; + m_paddr = 0; + m_pbddr = 0; + m_pcddr = 0; + m_pacr = 0; m_write_h2 (m_pacr); + m_pbcr = 0; + m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR + m_pbdr = 0; + m_psr = 0; } //------------------------------------------------- @@ -85,16 +85,16 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32 void pit68230_device::h1_set (UINT8 state) { - LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr)); - if (state) m_psr |= 1; else m_psr &= ~1; - LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ())); + LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr)); + if (state) m_psr |= 1; else m_psr &= ~1; + LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ())); } void pit68230_device::portb_setbit (UINT8 bit, UINT8 state) { - LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr)); - if (state) m_pbdr |= (1 << bit); else m_pbdr &= ~(1 << bit); - LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ())); + LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr)); + if (state) m_pbdr |= (1 << bit); else m_pbdr &= ~(1 << bit); + LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ())); } //------------------------------------------------- @@ -102,11 +102,11 @@ void pit68230_device::portb_setbit (UINT8 bit, UINT8 state) //------------------------------------------------- void pit68230_device::execute_run () { - do { - synchronize (); + do { + synchronize (); - m_icount--; - } while (m_icount > 0); + m_icount--; + } while (m_icount > 0); } LOG (static INT32 ow_cnt = 0); @@ -114,75 +114,75 @@ LOG (static INT32 ow_data = 0); LOG (static INT32 ow_ofs = 0); WRITE8_MEMBER (pit68230_device::write){ - switch (offset) { - case PIT_68230_PGCR: - m_pgcr = data; - break; - - case PIT_68230_PSRR: - m_psrr = data; - break; - - case PIT_68230_PADDR: - m_paddr = data; - break; - - case PIT_68230_PBDDR: - m_pbddr = data; - break; - - case PIT_68230_PCDDR: - m_pcddr = data; - break; - - case PIT_68230_PACR: - m_pacr = data; - // callbacks - /*PACR in Mode 0 - * 5 43 H2 Control in Submode 00 && 01 - * ------------------------------------ - * 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge. - * 1 00 Output pin - negated, H2S is always clear. - * 1 01 Output pin - asserted, H2S is always clear. - * 1 10 Output pin - interlocked input handshake protocol, H2S is always clear. - * 1 11 Output pin - pulsed input handshake protocol, H2S is always clear. - * - * 5 43 H2 Control in Submode 1x - * ------------------------------------ - * 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge. - * 1 X0 Output pin - negated, H2S is always cleared. - * 1 X1 Output pin - asserted, H2S is always cleared. - */ - m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes - break; - - case PIT_68230_PBCR: - m_pbcr = data; - break; - - case PIT_68230_PADR: - m_padr = data; - // callbacks - m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR - break; - - case PIT_68230_PSR: - m_psr = data; - break; - - default: - LOG (logerror ("unhandled register %02x", offset)); - } - - LOG (if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) { - logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt); - ow_cnt = 0; - ow_data = data; - ow_ofs = offset; - logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ()); - } - else - ow_cnt++; ) + switch (offset) { + case PIT_68230_PGCR: + m_pgcr = data; + break; + + case PIT_68230_PSRR: + m_psrr = data; + break; + + case PIT_68230_PADDR: + m_paddr = data; + break; + + case PIT_68230_PBDDR: + m_pbddr = data; + break; + + case PIT_68230_PCDDR: + m_pcddr = data; + break; + + case PIT_68230_PACR: + m_pacr = data; + // callbacks + /*PACR in Mode 0 + * 5 43 H2 Control in Submode 00 && 01 + * ------------------------------------ + * 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge. + * 1 00 Output pin - negated, H2S is always clear. + * 1 01 Output pin - asserted, H2S is always clear. + * 1 10 Output pin - interlocked input handshake protocol, H2S is always clear. + * 1 11 Output pin - pulsed input handshake protocol, H2S is always clear. + * + * 5 43 H2 Control in Submode 1x + * ------------------------------------ + * 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge. + * 1 X0 Output pin - negated, H2S is always cleared. + * 1 X1 Output pin - asserted, H2S is always cleared. + */ + m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes + break; + + case PIT_68230_PBCR: + m_pbcr = data; + break; + + case PIT_68230_PADR: + m_padr = data; + // callbacks + m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR + break; + + case PIT_68230_PSR: + m_psr = data; + break; + + default: + LOG (logerror ("unhandled register %02x", offset)); + } + + LOG (if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) { + logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt); + ow_cnt = 0; + ow_data = data; + ow_ofs = offset; + logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ()); + } + else + ow_cnt++; ) } LOG (static INT32 or_cnt = 0); @@ -190,76 +190,76 @@ LOG (static INT32 or_data = 0); LOG (static INT32 or_ofs = 0); READ8_MEMBER (pit68230_device::read){ - UINT8 data = 0; - - switch (offset) { - case PIT_68230_PGCR: - data = m_pgcr; - break; - - case PIT_68230_PSRR: - data = m_psrr; - break; - - case PIT_68230_PADDR: - data = m_paddr; - break; - - case PIT_68230_PBDDR: - data = m_pbddr; - break; - - case PIT_68230_PCDDR: - data = m_pcddr; - break; - - case PIT_68230_PACR: - data = m_pacr; - break; - - case PIT_68230_PBCR: - data = m_pbcr; - break; - - case PIT_68230_PADR: - data = m_padr; - break; - - case PIT_68230_PBDR: - /* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding - * register for moving data to and from port B pins. The port B data direction - * register determines whether each pin is an input (zero) or an output (one). - * This register is readable and writable at all times. Depending on the chosen - * mode/submode, reading or writing may affect the double-buffered handshake - * mechanism. The port B data register is not affected by the assertion of the - * RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */ - data = m_pbdr; - break; - - case PIT_68230_PSR: - /* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about - * handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake - * pin, and are independent of the handshake pin sense bits in the port general control - * register. Bits 3-0 are the respective status bits referred to throughout this document. - * Their interpretation depends on the programmed mode/submode of the PI/T. For bits - * 3-0 a one is the active or asserted state. */ - data = m_psr; - break; - - default: - LOG (logerror ("unhandled register %02x", offset)); - data = 0; - } - - LOG (if (offset != or_ofs || data != or_data || or_cnt >= 1000) { - logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt); - or_cnt = 0; - or_data = data; - or_ofs = offset; - logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ()); - } - else - or_cnt++; ) - - return data; + UINT8 data = 0; + + switch (offset) { + case PIT_68230_PGCR: + data = m_pgcr; + break; + + case PIT_68230_PSRR: + data = m_psrr; + break; + + case PIT_68230_PADDR: + data = m_paddr; + break; + + case PIT_68230_PBDDR: + data = m_pbddr; + break; + + case PIT_68230_PCDDR: + data = m_pcddr; + break; + + case PIT_68230_PACR: + data = m_pacr; + break; + + case PIT_68230_PBCR: + data = m_pbcr; + break; + + case PIT_68230_PADR: + data = m_padr; + break; + + case PIT_68230_PBDR: + /* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding + * register for moving data to and from port B pins. The port B data direction + * register determines whether each pin is an input (zero) or an output (one). + * This register is readable and writable at all times. Depending on the chosen + * mode/submode, reading or writing may affect the double-buffered handshake + * mechanism. The port B data register is not affected by the assertion of the + * RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */ + data = m_pbdr; + break; + + case PIT_68230_PSR: + /* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about + * handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake + * pin, and are independent of the handshake pin sense bits in the port general control + * register. Bits 3-0 are the respective status bits referred to throughout this document. + * Their interpretation depends on the programmed mode/submode of the PI/T. For bits + * 3-0 a one is the active or asserted state. */ + data = m_psr; + break; + + default: + LOG (logerror ("unhandled register %02x", offset)); + data = 0; + } + + LOG (if (offset != or_ofs || data != or_data || or_cnt >= 1000) { + logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt); + or_cnt = 0; + or_data = data; + or_ofs = offset; + logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ()); + } + else + or_cnt++; ) + + return data; } diff --git a/src/devices/machine/68230pit.h b/src/devices/machine/68230pit.h index b32cb25e928..b78dbc887aa 100644 --- a/src/devices/machine/68230pit.h +++ b/src/devices/machine/68230pit.h @@ -44,13 +44,13 @@ //************************************************************************** #define MCFG_PIT68230_PA_OUTPUT_CALLBACK(_write) \ - devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write); + devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write); #define MCFG_PIT68230_PB_OUTPUT_CALLBACK(_write) \ - devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write); + devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write); #define MCFG_PIT68230_H2_CALLBACK(_write) \ - devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write); + devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write); /*----------------------------------------------------------------------- * Registers RS1-RS5 R/W Description @@ -90,11 +90,11 @@ pit68230_device(const machine_config &mconfig, device_type type, const char *nam pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); template<class _Object> static devcb_base &set_pa_wr_callback (device_t &device, _Object object) { - return downcast<pit68230_device &>(device).m_write_pa.set_callback (object); + return downcast<pit68230_device &>(device).m_write_pa.set_callback (object); } template<class _Object> static devcb_base &set_h2_wr_callback (device_t &device, _Object object) { - return downcast<pit68230_device &>(device).m_write_h2.set_callback (object); + return downcast<pit68230_device &>(device).m_write_h2.set_callback (object); } DECLARE_WRITE8_MEMBER (write); diff --git a/src/devices/machine/i8271.c b/src/devices/machine/i8271.c index ab1daddc2b2..58188b2e156 100644 --- a/src/devices/machine/i8271.c +++ b/src/devices/machine/i8271.c @@ -501,7 +501,7 @@ void i8271_device::live_run(attotime limit) scan_cnt[1] = slot >> 9; scan_done = true; rr = command[4] & 0xc0 ? ERR_SMNE : ERR_SMEQ; - } + } else { scan_match = true; @@ -753,7 +753,7 @@ void i8271_device::start_command(int cmd) { floppy_info &fi = flopi[BIT(command[0], 7)]; rr = (get_ready(1) ? 0x40 : 0) | (fi.dev->idx_r() ? 0x10 : 0) | (fi.dev->wpt_r() ? 0 : 8) | - (get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0); + (get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0); flopi[0].ready = true; flopi[1].ready = true; main_phase = PHASE_IDLE; @@ -819,7 +819,7 @@ void i8271_device::start_command(int cmd) case 0x22: { floppy_info &fi = flopi[BIT(command[0], 7)]; rr = (get_ready(1) ? 0x40 : 0) | (fi.dev->idx_r() ? 0x10 : 0) | (fi.dev->wpt_r() ? 0 : 8) | - (get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0); + (get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0); break; } case 0x23: diff --git a/src/devices/machine/vt82c496.c b/src/devices/machine/vt82c496.c index 8c012bb002a..0a05d9cf17a 100644 --- a/src/devices/machine/vt82c496.c +++ b/src/devices/machine/vt82c496.c @@ -2,7 +2,7 @@ // copyright-holders:Barry Rodewald /* - VIA VT82C496G "Green PC" system chipset + VIA VT82C496G "Green PC" system chipset */ @@ -30,9 +30,9 @@ void vt82c496_device::device_start() /* get rom region */ m_rom = machine().root_device().memregion(m_region_tag)->base(); - + save_pointer(m_reg,"Registers",0x100); - + m_ram = machine().device<ram_device>(RAM_TAG); } @@ -106,7 +106,7 @@ void vt82c496_device::update_mem_c0(UINT8 data) } else m_space->nop_write(0xcc000,0xcffff,0,0); - + if(data & 0x20) machine().root_device().membank("bios_c8_r")->set_base(m_ram->pointer()+0xc8000); else @@ -118,7 +118,7 @@ void vt82c496_device::update_mem_c0(UINT8 data) } else m_space->nop_write(0xc8000,0xcbfff,0,0); - + if(data & 0x08) machine().root_device().membank("bios_c4_r")->set_base(m_ram->pointer()+0xc4000); else @@ -130,7 +130,7 @@ void vt82c496_device::update_mem_c0(UINT8 data) } else m_space->nop_write(0xc4000,0xc7fff,0,0); - + if(data & 0x02) machine().root_device().membank("bios_c0_r")->set_base(m_ram->pointer()+0xc0000); else @@ -157,7 +157,7 @@ void vt82c496_device::update_mem_d0(UINT8 data) } else m_space->nop_write(0xdc000,0xdffff,0,0); - + if(data & 0x20) machine().root_device().membank("bios_d8_r")->set_base(m_ram->pointer()+0xd8000); else @@ -169,7 +169,7 @@ void vt82c496_device::update_mem_d0(UINT8 data) } else m_space->nop_write(0xd8000,0xdbfff,0,0); - + if(data & 0x08) machine().root_device().membank("bios_d4_r")->set_base(m_ram->pointer()+0xd4000); else @@ -181,7 +181,7 @@ void vt82c496_device::update_mem_d0(UINT8 data) } else m_space->nop_write(0xd4000,0xd7fff,0,0); - + if(data & 0x02) machine().root_device().membank("bios_d0_r")->set_base(m_ram->pointer()+0xd0000); else @@ -214,7 +214,7 @@ void vt82c496_device::update_mem_e0(UINT8 data) machine().root_device().membank("bios_f0_r")->set_base(m_ram->pointer()+0xf0000); else machine().root_device().membank("bios_f0_r")->set_base(m_rom+0x30000); - + if(data & 0x10) { m_space->install_write_bank(0xf0000,0xfffff,0,0,"bios_f0_w"); @@ -223,4 +223,3 @@ void vt82c496_device::update_mem_e0(UINT8 data) else m_space->nop_write(0xf0000,0xfffff,0,0); } - diff --git a/src/devices/machine/vt82c496.h b/src/devices/machine/vt82c496.h index d4ee6c559aa..4e1a79a0943 100644 --- a/src/devices/machine/vt82c496.h +++ b/src/devices/machine/vt82c496.h @@ -2,7 +2,7 @@ // copyright-holders:Barry Rodewald /* - VIA VT82C496G "Green PC" system chipset + VIA VT82C496G "Green PC" system chipset */ @@ -40,14 +40,14 @@ protected: private: const char* m_cpu_tag; const char* m_region_tag; -// cpu_device* m_maincpu; +// cpu_device* m_maincpu; address_space* m_space; ram_device* m_ram; UINT8* m_rom; - + UINT8 m_reg[0x100]; UINT8 m_reg_select; - + void update_mem_c0(UINT8 data); void update_mem_d0(UINT8 data); void update_mem_e0(UINT8 data); @@ -58,4 +58,3 @@ extern const device_type VT82C496; #endif /* __VT82C496_H__ */ - diff --git a/src/devices/machine/z80scc.c b/src/devices/machine/z80scc.c index 586bd0a14d8..62b8c1c87b6 100644 --- a/src/devices/machine/z80scc.c +++ b/src/devices/machine/z80scc.c @@ -161,29 +161,29 @@ z80scc_device::z80scc_device(const machine_config &mconfig, device_type type, co z80scc_device::z80scc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, Z80SCC, "Z80 SCC", tag, owner, clock, "z80scc", __FILE__), - device_z80daisy_interface(mconfig, *this), - m_chanA(*this, CHANA_TAG), - m_chanB(*this, CHANB_TAG), - m_rxca(0), - m_txca(0), - m_rxcb(0), - m_txcb(0), - m_out_txda_cb(*this), - m_out_dtra_cb(*this), - m_out_rtsa_cb(*this), - m_out_wrdya_cb(*this), - m_out_synca_cb(*this), - m_out_txdb_cb(*this), - m_out_dtrb_cb(*this), - m_out_rtsb_cb(*this), - m_out_wrdyb_cb(*this), - m_out_syncb_cb(*this), - m_out_int_cb(*this), - m_out_rxdrqa_cb(*this), - m_out_txdrqa_cb(*this), - m_out_rxdrqb_cb(*this), - m_out_txdrqb_cb(*this), - m_variant(TYPE_Z80SCC) + device_z80daisy_interface(mconfig, *this), + m_chanA(*this, CHANA_TAG), + m_chanB(*this, CHANB_TAG), + m_rxca(0), + m_txca(0), + m_rxcb(0), + m_txcb(0), + m_out_txda_cb(*this), + m_out_dtra_cb(*this), + m_out_rtsa_cb(*this), + m_out_wrdya_cb(*this), + m_out_synca_cb(*this), + m_out_txdb_cb(*this), + m_out_dtrb_cb(*this), + m_out_rtsb_cb(*this), + m_out_wrdyb_cb(*this), + m_out_syncb_cb(*this), + m_out_int_cb(*this), + m_out_rxdrqa_cb(*this), + m_out_txdrqa_cb(*this), + m_out_rxdrqb_cb(*this), + m_out_txdrqb_cb(*this), + m_variant(TYPE_Z80SCC) { for (int i = 0; i < 6; i++) m_int_state[i] = 0; @@ -219,7 +219,7 @@ scc8523L_device::scc8523L_device(const machine_config &mconfig, const char *tag, void z80scc_device::device_start() { - LOG(("%s\n", FUNCNAME)); + LOG(("%s\n", FUNCNAME)); // resolve callbacks m_out_txda_cb.resolve_safe(); m_out_dtra_cb.resolve_safe(); @@ -256,15 +256,15 @@ void z80scc_device::device_start() void z80scc_device::device_reset() { - LOG(("%s %s \n",FUNCNAME, tag())); + LOG(("%s %s \n",FUNCNAME, tag())); m_chanA->reset(); m_chanB->reset(); } -/* +/* * Interrupts -Each of the SCC’s two channels contain three sources of interrupts, making a total of six interrupt +Each of the SCC's two channels contain three sources of interrupts, making a total of six interrupt sources. These three sources of interrupts are: 1) Receiver, 2) Transmitter, and 3) External/Status conditions. In addition, there are several conditions that may cause these interrupts.*/ //------------------------------------------------- @@ -277,8 +277,8 @@ int z80scc_device::z80daisy_irq_state() int i; LOG(("Z80SCC \"%s\" : Interrupt State A:%d%d%d%d B:%d%d%d%d\n", tag(), - m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], - m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); + m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], + m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); // loop over all interrupt sources for (i = 0; i < 6; i++) @@ -365,7 +365,7 @@ void z80scc_device::z80daisy_irq_reti() void z80scc_device::check_interrupts() { int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE; - LOG(("Z80SCC \"%s\" : %s() state = %d\n", m_owner->tag(), __func__, state)); + LOG(("Z80SCC \"%s\" : %s() state = %d\n", m_owner->tag(), __func__, state)); m_out_int_cb(state); } @@ -376,44 +376,44 @@ void z80scc_device::check_interrupts() void z80scc_device::reset_interrupts() { - // reset internal interrupi sources + // reset internal interrupi sources for (int i = 0; i < 6; i++) { m_int_state[i] = 0; } - // check external interrupt sources + // check external interrupt sources check_interrupts(); } UINT8 z80scc_device::modify_vector(UINT8 vec, int i, UINT8 src) { - /* - Interrupt Vector Modification - V3 V2 V1 Status High/Status Low =0 - V4 V5 V6 Status High/Status Low =1 - 0 0 0 Ch B Transmit Buffer Empty - 0 0 1 Ch B External/Status Change - 0 1 0 Ch B Receive Char. Available - 0 1 1 Ch B Special Receive Condition - 1 0 0 Ch A Transmit Buffer Empty - 1 0 1 Ch A External/Status Change - 1 1 0 Ch A Receive Char. Available - 1 1 1 Ch A Special Receive Condition - */ - // Add channel offset according to table above - src |= (i == CHANNEL_A ? 0x04 : 0x00 ); - - // Modify vector according to Hi/lo bit of WR9 - if (m_chanA->m_wr9 & z80scc_channel::WR9_BIT_SHSL) // Affect V4-V6 - { - vec |= src << 4; - } - else // Affect V1-V3 - { - vec |= src << 1; - } - return vec; + /* + Interrupt Vector Modification + V3 V2 V1 Status High/Status Low =0 + V4 V5 V6 Status High/Status Low =1 + 0 0 0 Ch B Transmit Buffer Empty + 0 0 1 Ch B External/Status Change + 0 1 0 Ch B Receive Char. Available + 0 1 1 Ch B Special Receive Condition + 1 0 0 Ch A Transmit Buffer Empty + 1 0 1 Ch A External/Status Change + 1 1 0 Ch A Receive Char. Available + 1 1 1 Ch A Special Receive Condition + */ + // Add channel offset according to table above + src |= (i == CHANNEL_A ? 0x04 : 0x00 ); + + // Modify vector according to Hi/lo bit of WR9 + if (m_chanA->m_wr9 & z80scc_channel::WR9_BIT_SHSL) // Affect V4-V6 + { + vec |= src << 4; + } + else // Affect V1-V3 + { + vec |= src << 1; + } + return vec; } @@ -423,86 +423,86 @@ UINT8 z80scc_device::modify_vector(UINT8 vec, int i, UINT8 src) void z80scc_device::trigger_interrupt(int index, int state) { UINT8 vector = m_chanB->m_wr2; - UINT8 source = 0; + UINT8 source = 0; int priority; - - int prio_level = 0; - /* The Master Interrupt Enable (MIE) bit, WR9 D3, must be set to enable the SCC to generate interrupts.*/ - if (!(m_chanA->m_wr9 & z80scc_channel::WR9_BIT_MIE)) - { - LOG(("Master Interrupt Enable is not set, blocking attempt to interrupt\n")); - return; - } + int prio_level = 0; + + /* The Master Interrupt Enable (MIE) bit, WR9 D3, must be set to enable the SCC to generate interrupts.*/ + if (!(m_chanA->m_wr9 & z80scc_channel::WR9_BIT_MIE)) + { + LOG(("Master Interrupt Enable is not set, blocking attempt to interrupt\n")); + return; + } - switch(state) + switch(state) { - case z80scc_channel::INT_RECEIVE: - /*The sources of receive interrupts consist of Receive Character Available and Special Receive Condition. - The Special Receive Condition can be subdivided into Receive Overrun, Framing Error (Asynchronous) or - End of Frame (SDLC). In addition, a parity error can be a special receive condition by programming*/ - source = 2; - prio_level = 2; - break; - case z80scc_channel::INT_TRANSMIT: - /*The NMOS/CMOS version of the SCC only has a one byte deep transmit buffer. The status of the - transmit buffer can be determined through TBE bit in RR0, bit D2, which shows whether the - transmit buffer is empty or not. After a hardware reset (including a hardware reset by software), or - a channel reset, this bit is set to 1. - While transmit interrupts are enabled, the NMOS/CMOS version sets the Transmit Interrupt Pending - (TxIP) bit whenever the transmit buffer becomes empty. This means that the transmit buffer - must be full before the TxIP can be set. Thus, when transmit interrupts are first enabled, the TxIP - will not be set until after the first character is written to the NMOS/CMOS.*/ - source = 0; - prio_level = 1; - break; - case z80scc_channel::INT_SPECIAL: - /*This mode allows the receiver to interrupt only on - characters with a special receive condition. When an interrupt occurs, the data containing the error - is held in the Receive FIFO until an Error Reset command is issued. When using this mode in conjunction - with a DMA, the DMA is initialized and enabled before any characters have been - received by the ESCC. This eliminates the time-critical section of code required in the Receive - Interrupt on First Character or Special Condition mode. Hence, all data can be transferred via the - DMA so that the CPU need not handle the first received character as a special case. In SDLC - mode, if the SDLC Frame Status FIFO is enabled and an EOF is received, an interrupt with vector - for receive data available is generated and the Receive FIFO is not locked.*/ - source = 3; - prio_level = 0; - break; - default: - logerror("Attempt to trigger interrupt of unknown origin blocked: %02x on channel %c\n", state, 'A' + index); - return; - } - - // Vector modification requested? - if (m_chanA->m_wr9 & z80scc_channel::WR9_BIT_VIS) - { - vector = modify_vector(vector, index, source); - } + case z80scc_channel::INT_RECEIVE: + /*The sources of receive interrupts consist of Receive Character Available and Special Receive Condition. + The Special Receive Condition can be subdivided into Receive Overrun, Framing Error (Asynchronous) or + End of Frame (SDLC). In addition, a parity error can be a special receive condition by programming*/ + source = 2; + prio_level = 2; + break; + case z80scc_channel::INT_TRANSMIT: + /*The NMOS/CMOS version of the SCC only has a one byte deep transmit buffer. The status of the + transmit buffer can be determined through TBE bit in RR0, bit D2, which shows whether the + transmit buffer is empty or not. After a hardware reset (including a hardware reset by software), or + a channel reset, this bit is set to 1. + While transmit interrupts are enabled, the NMOS/CMOS version sets the Transmit Interrupt Pending + (TxIP) bit whenever the transmit buffer becomes empty. This means that the transmit buffer + must be full before the TxIP can be set. Thus, when transmit interrupts are first enabled, the TxIP + will not be set until after the first character is written to the NMOS/CMOS.*/ + source = 0; + prio_level = 1; + break; + case z80scc_channel::INT_SPECIAL: + /*This mode allows the receiver to interrupt only on + characters with a special receive condition. When an interrupt occurs, the data containing the error + is held in the Receive FIFO until an Error Reset command is issued. When using this mode in conjunction + with a DMA, the DMA is initialized and enabled before any characters have been + received by the ESCC. This eliminates the time-critical section of code required in the Receive + Interrupt on First Character or Special Condition mode. Hence, all data can be transferred via the + DMA so that the CPU need not handle the first received character as a special case. In SDLC + mode, if the SDLC Frame Status FIFO is enabled and an EOF is received, an interrupt with vector + for receive data available is generated and the Receive FIFO is not locked.*/ + source = 3; + prio_level = 0; + break; + default: + logerror("Attempt to trigger interrupt of unknown origin blocked: %02x on channel %c\n", state, 'A' + index); + return; + } + + // Vector modification requested? + if (m_chanA->m_wr9 & z80scc_channel::WR9_BIT_VIS) + { + vector = modify_vector(vector, index, source); + } LOG(("Z80SCC \"%s\" Channel %c : Interrupt Request %u\n", tag(), 'A' + index, state)); // update vector register // TODO: What if interrupts are nested? May we loose the modified vector or even get the wrong one? m_chanB->m_wr2 = vector; - - /* Check the interrupt source and build the vector modification */ - /*Interrupt Source Priority order - Channel A Receive - Channel A Transmit - Channel A External/Status - Channel B Receive - Channel B Transmit - Channel B External/Status - */ - // Add channel offset to priority according to table above - priority = prio_level + (index == CHANNEL_A ? 3 : 0 ); + + /* Check the interrupt source and build the vector modification */ + /*Interrupt Source Priority order + Channel A Receive + Channel A Transmit + Channel A External/Status + Channel B Receive + Channel B Transmit + Channel B External/Status + */ + // Add channel offset to priority according to table above + priority = prio_level + (index == CHANNEL_A ? 3 : 0 ); // trigger interrupt m_int_state[priority] |= Z80_DAISY_INT; - // Based on the fact that prio levels are aligned with the bitorder of rr3 we can do this... - m_chanA->m_rr3 |= (prio_level << (index == CHANNEL_A ? 3 : 0 )); - + // Based on the fact that prio levels are aligned with the bitorder of rr3 we can do this... + m_chanA->m_rr3 |= (prio_level << (index == CHANNEL_A ? 3 : 0 )); + // check for interrupt check_interrupts(); } @@ -519,7 +519,7 @@ int z80scc_device::m1_r() //------------------------------------------------- -// cd_ba_r - Universal Bus read +// cd_ba_r - Universal Bus read //------------------------------------------------- READ8_MEMBER( z80scc_device::cd_ba_r ) { @@ -527,19 +527,19 @@ READ8_MEMBER( z80scc_device::cd_ba_r ) int cd = BIT(offset, 1); z80scc_channel *channel = ba ? m_chanB : m_chanA; - /* Expell non-Universal Bus variants */ - if ( !(m_variant & SET_Z85X3X)) - { - logerror("Z80SCC cd_ba_r not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); - return 0; - } + /* Expell non-Universal Bus variants */ + if ( !(m_variant & SET_Z85X3X)) + { + logerror("Z80SCC cd_ba_r not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); + return 0; + } - // LOG(("z80scc_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); + // LOG(("z80scc_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); return cd ? channel->control_read() : channel->data_read(); } //------------------------------------------------- -// cd_ba_w - Universal Bus write +// cd_ba_w - Universal Bus write //------------------------------------------------- WRITE8_MEMBER( z80scc_device::cd_ba_w ) { @@ -547,14 +547,14 @@ WRITE8_MEMBER( z80scc_device::cd_ba_w ) int cd = BIT(offset, 1); z80scc_channel *channel = ba ? m_chanB : m_chanA; - /* Expell non-Universal Bus variants */ - if ( !(m_variant & SET_Z85X3X) ) - { - logerror("Z80SCC cd_ba_w not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); - return; - } + /* Expell non-Universal Bus variants */ + if ( !(m_variant & SET_Z85X3X) ) + { + logerror("Z80SCC cd_ba_w not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); + return; + } - // LOG(("z80scc_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); + // LOG(("z80scc_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); if (cd) channel->control_write(data); else @@ -572,14 +572,14 @@ READ8_MEMBER( z80scc_device::ba_cd_r ) int cd = BIT(offset, 0); z80scc_channel *channel = ba ? m_chanB : m_chanA; - /* Expell non-Universal Bus variants */ - if ( !(m_variant & SET_Z85X3X) ) - { - logerror("Z80SCC ba_cd_r not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); - return 0; - } + /* Expell non-Universal Bus variants */ + if ( !(m_variant & SET_Z85X3X) ) + { + logerror("Z80SCC ba_cd_r not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); + return 0; + } - // LOG(("z80scc_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); + // LOG(("z80scc_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); return cd ? channel->control_read() : channel->data_read(); } @@ -594,14 +594,14 @@ WRITE8_MEMBER( z80scc_device::ba_cd_w ) int cd = BIT(offset, 0); z80scc_channel *channel = ba ? m_chanB : m_chanA; - /* Expell non-Universal Bus variants */ - if ( !(m_variant & SET_Z85X3X) ) - { - logerror("Z80SCC ba_cd_w not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); - return; - } + /* Expell non-Universal Bus variants */ + if ( !(m_variant & SET_Z85X3X) ) + { + logerror("Z80SCC ba_cd_w not supported by this device variant, you should probably use combinations of c*_r/w and d*_r/w (see z80scc.h)\n"); + return; + } - LOG(("z80scc_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd)); + LOG(("z80scc_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd)); if (cd) channel->control_write(data); else @@ -617,14 +617,14 @@ WRITE8_MEMBER( z80scc_device::ba_cd_w ) //------------------------------------------------- z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : z80sio_channel( mconfig, tag, owner, clock) + : z80sio_channel( mconfig, tag, owner, clock) { - // Reset all SCC specific registers; z80sio_channel:: manages the base registers - m_rr0 = m_rr1 = m_rr2 = - m_rr3 = m_rr4 = m_rr5 = m_rr6 = m_rr7 = m_rr8 = m_rr9 = - m_rr10 = m_rr11 = m_rr12 = m_rr13 = m_rr14 = m_rr15 = 0; - m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = - m_wr8 = m_wr9 = m_wr10 = m_wr11 = m_wr12 = m_wr13 = m_wr14 = m_wr15 = 0; + // Reset all SCC specific registers; z80sio_channel:: manages the base registers + m_rr0 = m_rr1 = m_rr2 = + m_rr3 = m_rr4 = m_rr5 = m_rr6 = m_rr7 = m_rr8 = m_rr9 = + m_rr10 = m_rr11 = m_rr12 = m_rr13 = m_rr14 = m_rr15 = 0; + m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = + m_wr8 = m_wr9 = m_wr10 = m_wr11 = m_wr12 = m_wr13 = m_wr14 = m_wr15 = 0; for (int i = 0; i < 3; i++) // TODO adapt to SCC fifos { @@ -641,16 +641,16 @@ z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, d void z80scc_channel::device_start() { m_uart = downcast<z80scc_device *>(owner()); - LOG(("%s\n", FUNCNAME)); + LOG(("%s\n", FUNCNAME)); m_index = m_uart->get_channel_index(this); - m_ph = 0; - m_variant = ((z80scc_device *)m_owner)->m_variant; + m_ph = 0; + m_variant = ((z80scc_device *)m_owner)->m_variant; - m_rx_fifo_sz = (m_variant & SET_ESCC) ? 8 : 3; - m_rx_fifo_wp = m_rx_fifo_rp = 0; + m_rx_fifo_sz = (m_variant & SET_ESCC) ? 8 : 3; + m_rx_fifo_wp = m_rx_fifo_rp = 0; // state saving - // m_rr0-m_rr2 is handled by the z80sio_channel driver, our base class + // m_rr0-m_rr2 is handled by the z80sio_channel driver, our base class save_item(NAME(m_rr0)); save_item(NAME(m_rr1)); save_item(NAME(m_rr2)); @@ -667,7 +667,7 @@ void z80scc_channel::device_start() save_item(NAME(m_rr13)); save_item(NAME(m_rr14)); save_item(NAME(m_rr15)); - // m_wr0-m_wr7 is handled by the z80sio_channel driver, our base class + // m_wr0-m_wr7 is handled by the z80sio_channel driver, our base class save_item(NAME(m_wr0)); save_item(NAME(m_wr1)); save_item(NAME(m_wr2)); @@ -712,39 +712,39 @@ void z80scc_channel::device_start() void z80scc_channel::device_reset() { - LOG(("Z80SCC \"%s\" Channel %c : %s\n", m_owner->tag(), 'A' + m_index, FUNCNAME)); + LOG(("Z80SCC \"%s\" Channel %c : %s\n", m_owner->tag(), 'A' + m_index, FUNCNAME)); - // Reset RS232 emulation + // Reset RS232 emulation receive_register_reset(); transmit_register_reset(); - // Soft/Channel Reset values according to SCC users manual - m_wr0 = 0x00; - m_wr1 &= 0x24; - m_wr3 &= 0x01; - m_wr4 |= 0x04; - m_wr5 &= 0x61; - if (m_variant & (z80scc_device::TYPE_SCC85C30 | SET_ESCC)) - m_wr7 = 0x20; - m_wr9 &= 0xdf; // WR9 has a different hard reset value - m_wr10 &= 0x60; // WR10 has a different hard reset value - m_wr11 &= 0xff; // WR11 has a different hard reset value - m_wr14 &= 0xc3; // WR14 has a different hard reset value - m_wr14 |= 0x20; - m_wr15 = 0xf8; - m_rr0 &= 0xfc; - m_rr0 |= 0x44; - m_rr1 &= 0x07; - m_rr1 |= 0x06; - m_rr3 = 0x00; - m_rr10 &= 0x40; + // Soft/Channel Reset values according to SCC users manual + m_wr0 = 0x00; + m_wr1 &= 0x24; + m_wr3 &= 0x01; + m_wr4 |= 0x04; + m_wr5 &= 0x61; + if (m_variant & (z80scc_device::TYPE_SCC85C30 | SET_ESCC)) + m_wr7 = 0x20; + m_wr9 &= 0xdf; // WR9 has a different hard reset value + m_wr10 &= 0x60; // WR10 has a different hard reset value + m_wr11 &= 0xff; // WR11 has a different hard reset value + m_wr14 &= 0xc3; // WR14 has a different hard reset value + m_wr14 |= 0x20; + m_wr15 = 0xf8; + m_rr0 &= 0xfc; + m_rr0 |= 0x44; + m_rr1 &= 0x07; + m_rr1 |= 0x06; + m_rr3 = 0x00; + m_rr10 &= 0x40; #if 0 // old reset code // disable transmitter m_wr5 &= ~WR5_TX_ENABLE; m_rr0 |= RR0_TX_BUFFER_EMPTY; #endif - // TODO: check dependencies on RR1_ALL_SENT and (re)move this setting + // TODO: check dependencies on RR1_ALL_SENT and (re)move this setting m_rr1 |= RR1_ALL_SENT; // It is a don't care in the SCC user manual // reset external lines TODO: check relation to control bits and reset @@ -772,8 +772,7 @@ void z80scc_channel::tra_callback() { if (!(m_wr5 & WR5_TX_ENABLE)) { - - LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); // transmit mark if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_txda_cb(1); @@ -782,7 +781,7 @@ void z80scc_channel::tra_callback() } else if (m_wr5 & WR5_SEND_BREAK) { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); // transmit break if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_txda_cb(0); @@ -791,20 +790,20 @@ void z80scc_channel::tra_callback() } else if (!is_transmit_register_empty()) { - int db = transmit_register_get_data_bit(); + int db = transmit_register_get_data_bit(); - LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5)); // transmit data if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_txda_cb(db); else m_uart->m_out_txdb_cb(db); } - else - { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); - logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index); - } + else + { + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index); + } } @@ -816,7 +815,7 @@ void z80scc_channel::tra_complete() { if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK) && !(m_rr0 & RR0_TX_BUFFER_EMPTY)) { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5)); transmit_register_setup(m_tx_data); @@ -828,7 +827,7 @@ void z80scc_channel::tra_complete() } else if (m_wr5 & WR5_SEND_BREAK) { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); // transmit break if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_txda_cb(0); @@ -837,7 +836,7 @@ void z80scc_channel::tra_complete() } else { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); // transmit mark if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_txda_cb(1); @@ -848,7 +847,7 @@ void z80scc_channel::tra_complete() // if transmit buffer is empty if (m_rr0 & RR0_TX_BUFFER_EMPTY) { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5)); // then all characters have been sent m_rr1 |= RR1_ALL_SENT; @@ -867,14 +866,14 @@ void z80scc_channel::rcv_callback() { if (m_wr3 & WR3_RX_ENABLE) { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data Bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data Bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd)); receive_register_update_bit(m_rxd); } - else - { - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index)); - logerror("Z80SCC %s() \"%s \"Channel %c Received data dit but receiver is disabled\n", __func__, m_owner->tag(), 'A' + m_index); - } + else + { + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index)); + logerror("Z80SCC %s() \"%s \"Channel %c Received data dit but receiver is disabled\n", __func__, m_owner->tag(), 'A' + m_index); + } } @@ -884,11 +883,11 @@ void z80scc_channel::rcv_callback() void z80scc_channel::rcv_complete() { - UINT8 data; + UINT8 data; receive_register_extract(); - data = get_received_char(); - LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, data)); + data = get_received_char(); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data %c\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, data)); receive_data(data); } @@ -918,14 +917,14 @@ outputs or with the Auto Enable feature. When used with Auto Enable ON (WR3, D5= in asynchronous mode, the /RTS pin goes High after the transmitter is empty. When Auto Enable is OFF, the /RTS pins are used as general-purpose outputs, and, they strictly follow the inverse state of WR5, bit D1. -ESCC and 85C30: In SDLC mode, the /RTS pins can be programmed to be deasserted when the closing +ESCC and 85C30: In SDLC mode, the /RTS pins can be programmed to be deasserted when the closing flag of the message clears the TxD pin, if WR7' D2 is set." TODO: - SDLC mode behaviour for ESCC/85C30 */ void z80scc_channel::set_rts(int state) { - LOG(("Z80SCC \"%s\" Channel %c : %s(%d)\n", m_owner->tag(), 'A' + m_index, __func__, state)); + LOG(("Z80SCC \"%s\" Channel %c : %s(%d)\n", m_owner->tag(), 'A' + m_index, __func__, state)); if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_rtsa_cb(state); else @@ -934,21 +933,21 @@ void z80scc_channel::set_rts(int state) void z80scc_channel::update_rts() { - LOG(("Z80SCC \"%s\" Channel %c : %s\n", m_owner->tag(), 'A' + m_index, __func__)); - if (m_wr5 & WR5_RTS) - { - // when the RTS bit is set, the _RTS output goes low - set_rts(0); - m_rts = 1; - } - else - { - // when the RTS bit is reset, the _RTS output goes high after the transmitter empties - m_rts = 0; - } + LOG(("Z80SCC \"%s\" Channel %c : %s\n", m_owner->tag(), 'A' + m_index, __func__)); + if (m_wr5 & WR5_RTS) + { + // when the RTS bit is set, the _RTS output goes low + set_rts(0); + m_rts = 1; + } + else + { + // when the RTS bit is reset, the _RTS output goes high after the transmitter empties + m_rts = 0; + } - // data terminal ready output follows the state programmed into the DTR bit*/ - set_dtr((m_wr5 & WR5_DTR) ? 0 : 1); + // data terminal ready output follows the state programmed into the DTR bit*/ + set_dtr((m_wr5 & WR5_DTR) ? 0 : 1); } //------------------------------------------------- @@ -1015,26 +1014,26 @@ on the state of the Status High/Status Low bit in WR9 and independent of the sta in WR9."*/ UINT8 z80scc_channel::do_sccreg_rr2() { - LOG(("Z80SCC %s()\n", __func__)); + LOG(("Z80SCC %s()\n", __func__)); - // Assume the unmodified in polled mode - m_rr2 = m_uart->m_chanA->m_wr2; + // Assume the unmodified in polled mode + m_rr2 = m_uart->m_chanA->m_wr2; - // If we are chan B we have to modify the vector regardless of the VIS bit + // If we are chan B we have to modify the vector regardless of the VIS bit if (m_index == z80scc_device::CHANNEL_B) - { - // loop over all interrupt sources - for (int i = 0; i < 6; i++) - { - // find the first channel with an interrupt requested - if (m_uart->m_int_state[i] & Z80_DAISY_INT) - { - m_rr2 = m_uart->modify_vector(m_rr2, i < 3 ? z80scc_device::CHANNEL_A : z80scc_device::CHANNEL_B, i & 3); - break; - } - } - } - return m_rr2; + { + // loop over all interrupt sources + for (int i = 0; i < 6; i++) + { + // find the first channel with an interrupt requested + if (m_uart->m_int_state[i] & Z80_DAISY_INT) + { + m_rr2 = m_uart->modify_vector(m_rr2, i < 3 ? z80scc_device::CHANNEL_A : z80scc_device::CHANNEL_B, i & 3); + break; + } + } + } + return m_rr2; } /* From Zilog SCC/ESCC USers manual, UM010902-0609: @@ -1044,8 +1043,8 @@ B, all 0s are returned. The two unused bits are always returned as 0. Figure dis */ UINT8 z80scc_channel::do_sccreg_rr3() { - LOG(("Z80SCC %s()\n", __func__)); - return m_rr3; // TODO Update all bits of this status register + LOG(("Z80SCC %s()\n", __func__)); + return m_rr3; // TODO Update all bits of this status register } @@ -1055,24 +1054,24 @@ UINT8 z80scc_channel::do_sccreg_rr3() a read to this location returns an image of RR0.*/ UINT8 z80scc_channel::do_sccreg_rr4() { - LOG(("Z80SCC %s()\n", __func__)); - if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) - return (BIT(m_wr7, 6) ? m_wr4 : m_rr0); - else - return m_rr0; + LOG(("Z80SCC %s()\n", __func__)); + if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) + return (BIT(m_wr7, 6) ? m_wr4 : m_rr0); + else + return m_rr0; } - /* (ESCC and 85C30 Only) */ + /* (ESCC and 85C30 Only) */ /*On the ESCC, Read Register 5 reflects the contents of Write Register 5 provided the Extended Read option is enabled. Otherwise, this register returns an image of RR1. On the NMOS/CMOS version, a read to this register returns an image of RR1.*/ UINT8 z80scc_channel::do_sccreg_rr5() { - LOG(("Z80SCC %s()\n", __func__)); - if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) - return BIT(m_wr7, 6) ? m_wr5 : m_rr1; - else - return m_rr1; + LOG(("Z80SCC %s()\n", __func__)); + if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) + return BIT(m_wr7, 6) ? m_wr5 : m_rr1; + else + return m_rr1; } /* (not on NMOS) @@ -1083,13 +1082,13 @@ UINT8 z80scc_channel::do_sccreg_rr5() On the NMOS version, a read to this register location returns an image of RR2.*/ UINT8 z80scc_channel::do_sccreg_rr6() { - LOG(("Z80SCC %s()\n", __func__)); - if (!(m_variant & (SET_NMOS))) - { - logerror("Z80SCC %s() not implemented feature\n", __func__); - return 0; - } - return m_rr2; + LOG(("Z80SCC %s()\n", __func__)); + if (!(m_variant & (SET_NMOS))) + { + logerror("Z80SCC %s() not implemented feature\n", __func__); + return 0; + } + return m_rr2; } /* (not on NMOS) @@ -1102,42 +1101,42 @@ UINT8 z80scc_channel::do_sccreg_rr6() RR7, RR6, RR1.*/ UINT8 z80scc_channel::do_sccreg_rr7() { - LOG(("Z80SCC %s()\n", __func__)); - if (!(m_variant & (SET_NMOS))) - { - logerror("Z80SCC %s() not implemented feature\n", __func__); - return 0; - } - return m_rr3; + LOG(("Z80SCC %s()\n", __func__)); + if (!(m_variant & (SET_NMOS))) + { + logerror("Z80SCC %s() not implemented feature\n", __func__); + return 0; + } + return m_rr3; } #if 0 // Short cutted in control_read() /* RR8 is the Receive Data register. */ UINT8 z80scc_channel::do_sccreg_rr8() { - return data_read(): + return data_read(): } #endif /* (ESCC and 85C30 Only) On the ESCC, Read Register 9 reflects the contents of Write Register 3 provided the Extended - Read option has been enabled. On the NMOS/CMOS version, a read to this location returns an image + Read option has been enabled. On the NMOS/CMOS version, a read to this location returns an image of RR13. TODO: Check what is returned if Extended Read option is turned off */ UINT8 z80scc_channel::do_sccreg_rr9() { - LOG(("Z80SCC %s()\n", __func__)); - if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) - return BIT(m_wr7, 6) ? m_wr3 : m_rr13; - else - return m_rr13; + LOG(("Z80SCC %s()\n", __func__)); + if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) + return BIT(m_wr7, 6) ? m_wr3 : m_rr13; + else + return m_rr13; } /* RR10 contains some SDLC related miscellaneous status bits. Unused bits are always 0. */ UINT8 z80scc_channel::do_sccreg_rr10() { - LOG(("Z80SCC %s()\n", __func__)); - logerror("Z80SCC %s() not implemented feature\n", __func__); - return m_rr10; + LOG(("Z80SCC %s()\n", __func__)); + logerror("Z80SCC %s() not implemented feature\n", __func__); + return m_rr10; } /* (ESCC and 85C30 Only) @@ -1146,25 +1145,25 @@ UINT8 z80scc_channel::do_sccreg_rr10() On the NMOS/CMOS version, a read to this location returns an image of RR15.*/ UINT8 z80scc_channel::do_sccreg_rr11() { - LOG(("Z80SCC %s()\n", __func__)); - if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) - return BIT(m_wr7, 6) ? m_wr10 : m_rr15; - else - return m_rr15; + LOG(("Z80SCC %s()\n", __func__)); + if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) + return BIT(m_wr7, 6) ? m_wr10 : m_rr15; + else + return m_rr15; } /* RR12 returns the value stored in WR12, the lower byte of the time constant, for the BRG.*/ UINT8 z80scc_channel::do_sccreg_rr12() { - return m_wr12; + return m_wr12; } /* RR13 returns the value stored in WR13, the upper byte of the time constant for the BRG. */ UINT8 z80scc_channel::do_sccreg_rr13() { - return m_wr13; + return m_wr13; } /* (ESCC and 85C30 Only) @@ -1173,11 +1172,11 @@ Extended Read option has been enabled. Otherwise, this register returns an image On the NMOS/CMOS version, a read to this location returns an image of RR10.*/ UINT8 z80scc_channel::do_sccreg_rr14() { - LOG(("Z80SCC %s()\n", __func__)); - if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) - return BIT(m_wr7, 6) ? m_wr7 : m_rr10; - else - return m_rr10; + LOG(("Z80SCC %s()\n", __func__)); + if (m_variant & (SET_ESCC | z80scc_device::TYPE_SCC85C30)) + return BIT(m_wr7, 6) ? m_wr7 : m_rr10; + else + return m_rr10; } /* @@ -1185,9 +1184,9 @@ UINT8 z80scc_channel::do_sccreg_rr14() always returned as Os. */ UINT8 z80scc_channel::do_sccreg_rr15() { - LOG(("Z80SCC %s()\n", __func__)); - logerror("Z80SCC %s() not implemented feature\n", __func__); - return m_wr15 & 0xf5; // Mask out the used bits + LOG(("Z80SCC %s()\n", __func__)); + logerror("Z80SCC %s() not implemented feature\n", __func__); + return m_wr15 & 0xf5; // Mask out the used bits } //------------------------------------------------- @@ -1196,14 +1195,14 @@ UINT8 z80scc_channel::do_sccreg_rr15() UINT8 z80scc_channel::control_read() { UINT8 data = 0; - int reg = m_wr0; - int regmask = (WR0_REGISTER_MASK | m_ph); + int reg = m_wr0; + int regmask = (WR0_REGISTER_MASK | m_ph); - // LOG(("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", __func__, data, reg, regmask, m_wr0)); + // LOG(("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", __func__, data, reg, regmask, m_wr0)); m_ph = 0; // The "Point High" command is only valid for one access - reg &= regmask; + reg &= regmask; if (reg != 0) { @@ -1211,29 +1210,29 @@ UINT8 z80scc_channel::control_read() m_wr0 &= ~regmask; } - /* TODO. Sort out 80X30 limitations in register access */ + /* TODO. Sort out 80X30 limitations in register access */ switch (reg) { case REG_RR0_STATUS: data = do_sioreg_rr0(); break; // TODO: verify handling of SCC specific bits: D6 and D1 - case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break; + case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break; case REG_RR2_INTERRUPT_VECT: data = do_sccreg_rr2(); break; // Channel dependent and SCC specific handling compared to SIO - /* registers 3-7 are specific to SCC. TODO: Check variant and log/stop misuse */ + /* registers 3-7 are specific to SCC. TODO: Check variant and log/stop misuse */ case REG_RR3_INTERUPPT_PEND: data = do_sccreg_rr3(); break; - case REG_RR4_WR4_OR_RR0: data = do_sccreg_rr4(); break; - case REG_RR5_WR5_OR_RR0: data = do_sccreg_rr5(); break; - case REG_RR6_LSB_OR_RR2: data = do_sccreg_rr6(); break; - case REG_RR7_MSB_OR_RR3: data = do_sccreg_rr7(); break; - /* registers 8-15 are specific to SCC */ - case REG_RR8_RECEIVE_DATA: data = data_read(); break; - case REG_RR9_WR3_OR_RR13: data = do_sccreg_rr9(); break; - case REG_RR10_MISC_STATUS: data = do_sccreg_rr10(); break; - case REG_RR11_WR10_OR_RR15: data = do_sccreg_rr11(); break; - case REG_RR12_LO_TIME_CONST: data = do_sccreg_rr12(); break; - case REG_RR13_HI_TIME_CONST: data = do_sccreg_rr13(); break; - case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break; - case REG_RR15_WR15_EXT_STAT: data = do_sccreg_rr15(); break; + case REG_RR4_WR4_OR_RR0: data = do_sccreg_rr4(); break; + case REG_RR5_WR5_OR_RR0: data = do_sccreg_rr5(); break; + case REG_RR6_LSB_OR_RR2: data = do_sccreg_rr6(); break; + case REG_RR7_MSB_OR_RR3: data = do_sccreg_rr7(); break; + /* registers 8-15 are specific to SCC */ + case REG_RR8_RECEIVE_DATA: data = data_read(); break; + case REG_RR9_WR3_OR_RR13: data = do_sccreg_rr9(); break; + case REG_RR10_MISC_STATUS: data = do_sccreg_rr10(); break; + case REG_RR11_WR10_OR_RR15: data = do_sccreg_rr11(); break; + case REG_RR12_LO_TIME_CONST: data = do_sccreg_rr12(); break; + case REG_RR13_HI_TIME_CONST: data = do_sccreg_rr13(); break; + case REG_RR14_WR7_OR_R10: data = do_sccreg_rr14(); break; + case REG_RR15_WR15_EXT_STAT: data = do_sccreg_rr15(); break; default: - logerror("Z80SCC \"%s\" %s Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), __func__, 'A' + m_index, reg); + logerror("Z80SCC \"%s\" %s Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), __func__, 'A' + m_index, reg); } //LOG(("Z80SCC \"%s\" Channel %c : Register R%d read '%02x'\n", m_owner->tag(), 'A' + m_index, reg, data)); @@ -1244,119 +1243,119 @@ UINT8 z80scc_channel::control_read() /**/ void z80scc_channel::do_sccreg_wr0(UINT8 data) { - m_wr0 = data; + m_wr0 = data; - /* Sort out SCC specific behaviours from legacy SIO behaviour */ - /* WR0_Z_* are Z80X30 specific commands */ - switch (data & WR0_COMMAND_MASK) + /* Sort out SCC specific behaviours from legacy SIO behaviour */ + /* WR0_Z_* are Z80X30 specific commands */ + switch (data & WR0_COMMAND_MASK) { - case WR0_POINT_HIGH: - /*This command effectively adds eight to the Register Pointer (D2-D0) by allowing - WR8 through WR15 to be accessed. The Point High command and the Register - Pointer bits are written simultaneously. This command is used in the Z85X30 - version of the SCC. Note that WR0 changes form depending upon the SCC version. - Register access for the Z80X30 version of the SCC is accomplished through direct - addressing*/ - if (m_variant & SET_Z85X3X) - { - LOG(("Z80SCC \"%s\" %s Channel %c : %s - Point High command\n", m_owner->tag(), __func__, 'A' + m_index, __func__)); - m_ph = 8; - } - else - LOG(("Z80SCC \"%s\" %s Channel %c : %s - NULL command 2\n", m_owner->tag(), __func__, 'A' + m_index, __func__)); - break; - case WR0_RESET_EXT_STATUS: // TODO: Take care of the Zero Count flag and the 2 slot fifo - /*After an External/Status interrupt (a change on a modem line or a break condition, - for example), the status bits in RR0 are latched. This command re-enables the bits - and allows interrupts to occur again as a result of a status change. Latching the - status bits captures short pulses until the CPU has time to read the change. - The SCC contains simple queueing logic associated with most of the external status - bits in RR0. If another External/Status condition changes while a previous condition - is still pending (Reset External/Status Interrupt has not yet been issued) and this - condition persists until after the command is issued, this second change causes another - External/Status interrupt. However, if this second status change does not persist - (there are two transitions), another interrupt is not generated. Exceptions to this - rule are detailed in the RR0 description.*/ - do_sioreg_wr0(data); - if (!m_zc) - { - m_rr0 |= RR0_ZC; - } - LOG(("Z80SCC \"%s\" %s Channel %c : %s - Reset External/Status Interrupt\n", m_owner->tag(), __func__, 'A' + m_index, __func__)); - break; - case WR0_RESET_HIGHEST_IUS: - /* This command resets the highest priority Interrupt Under Service (IUS) bit, allowing lower - priority conditions to request interrupts. This command allows the use of the internal - daisy chain (even in systems without an external daisy chain) and is the last operation in - an interrupt service routine.TODO: Implement internal Daisychain */ - LOG(("Z80SCC \"%s\" %s Channel %c : Reset Highest IUS\n", m_owner->tag(), __func__, 'A' + m_index)); - break; - case WR0_ERROR_RESET: - /*Error Reset Command (110). This command resets the error bits in RR1. If interrupt on first Rx - Character or Interrupt on Special Condition modes is selected and a special condition exists, the - data with the special condition is held in the Receive FIFO until this command is issued. If either - of these modes is selected and this command is issued before the data has been read from the - Receive FIFO, the data is lost */ - LOG(("Z80SCC \"%s\" %s Channel %c : WR0_ERROR_RESET\n", m_owner->tag(), __func__, 'A' + m_index)); - do_sioreg_wr0(data); // reset status registers - m_rx_fifo_rp_step(); // Reset error state in fifo and unlock it. unlock == step to next slot in fifo. - break; - case WR0_SEND_ABORT: - data &= 0xef; // convert SCC SEND_ABORT command to a SIO SEND_ABORT command and fall through - /* The following commands relies on the SIO default behviour */ - case WR0_NULL: - case WR0_ENABLE_INT_NEXT_RX: - case WR0_RESET_TX_INT: - default: - do_sioreg_wr0(data); - } - do_sioreg_wr0_resets(data); - if ( m_variant & SET_Z80X30) // TODO: Implement adress decoding for Z80X30 using the shift logic described below - { - /*The registers in the Z80X30 are addressed via the address on AD7-AD0 and are latched by the rising - edge of /AS. The Shift Right/Shift Left bit in the Channel B WR0 controls which bits are - decoded to form the register address. It is placed in this register to simplify programming when the - current state of the Shift Right/Shift Left bit is not known. - A hardware reset forces Shift Left mode where the address is decoded from AD5-AD1. In Shift - Right mode, the address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written via a - command to make the software writing to WR0 independent of the state of the Shift Right/Shift - Left bit. - While in the Shift Left mode, the register address is placed on AD4-AD1 and the Channel Select - bit, A/B, is decoded from AD5. The register map for this case is listed in Table on page 21. In - Shift Right mode, the register address is again placed on AD4-AD1 but the channel select A/B is - decoded from AD0. The register map for this case is listed in Table on page 23. - Because the Z80X30 does not contain 16 read registers, the decoding of the read registers is not - complete; this is listed in Table on page 21 and Table on page 23 by parentheses around the register - name. These addresses may also be used to access the read registers. Also, note that the - Z80X30 contains only one WR2 and WR9; these registers may be written from either channel. - Shift Left Mode is used when Channel A and B are to be programmed differently. This allows the - software to sequence through the registers of one channel at a time. The Shift Right Mode is used - when the channels are programmed the same. By incrementing the address, the user can program - the same data value into both the Channel A and Channel B register.*/ - switch(data & WR0_Z_SHIFT_MASK) - { - case WR0_Z_SEL_SHFT_LEFT: - LOG(("Z80SCC \"%s\" Channel %c : %s - Shift Left Addressing Mode - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR0_Z_SEL_SHFT_RIGHT: - LOG(("Z80SCC \"%s\" Channel %c : %s - Shift Right Addressing Mode - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - default: - break; - // LOG(("Z80SCC \"%s\" Channel %c : %s - Null commands\n", m_owner->tag(), 'A' + m_index, __func__)); - } - } + case WR0_POINT_HIGH: + /*This command effectively adds eight to the Register Pointer (D2-D0) by allowing + WR8 through WR15 to be accessed. The Point High command and the Register + Pointer bits are written simultaneously. This command is used in the Z85X30 + version of the SCC. Note that WR0 changes form depending upon the SCC version. + Register access for the Z80X30 version of the SCC is accomplished through direct + addressing*/ + if (m_variant & SET_Z85X3X) + { + LOG(("Z80SCC \"%s\" %s Channel %c : %s - Point High command\n", m_owner->tag(), __func__, 'A' + m_index, __func__)); + m_ph = 8; + } + else + LOG(("Z80SCC \"%s\" %s Channel %c : %s - NULL command 2\n", m_owner->tag(), __func__, 'A' + m_index, __func__)); + break; + case WR0_RESET_EXT_STATUS: // TODO: Take care of the Zero Count flag and the 2 slot fifo + /*After an External/Status interrupt (a change on a modem line or a break condition, + for example), the status bits in RR0 are latched. This command re-enables the bits + and allows interrupts to occur again as a result of a status change. Latching the + status bits captures short pulses until the CPU has time to read the change. + The SCC contains simple queueing logic associated with most of the external status + bits in RR0. If another External/Status condition changes while a previous condition + is still pending (Reset External/Status Interrupt has not yet been issued) and this + condition persists until after the command is issued, this second change causes another + External/Status interrupt. However, if this second status change does not persist + (there are two transitions), another interrupt is not generated. Exceptions to this + rule are detailed in the RR0 description.*/ + do_sioreg_wr0(data); + if (!m_zc) + { + m_rr0 |= RR0_ZC; + } + LOG(("Z80SCC \"%s\" %s Channel %c : %s - Reset External/Status Interrupt\n", m_owner->tag(), __func__, 'A' + m_index, __func__)); + break; + case WR0_RESET_HIGHEST_IUS: + /* This command resets the highest priority Interrupt Under Service (IUS) bit, allowing lower + priority conditions to request interrupts. This command allows the use of the internal + daisy chain (even in systems without an external daisy chain) and is the last operation in + an interrupt service routine.TODO: Implement internal Daisychain */ + LOG(("Z80SCC \"%s\" %s Channel %c : Reset Highest IUS\n", m_owner->tag(), __func__, 'A' + m_index)); + break; + case WR0_ERROR_RESET: + /*Error Reset Command (110). This command resets the error bits in RR1. If interrupt on first Rx + Character or Interrupt on Special Condition modes is selected and a special condition exists, the + data with the special condition is held in the Receive FIFO until this command is issued. If either + of these modes is selected and this command is issued before the data has been read from the + Receive FIFO, the data is lost */ + LOG(("Z80SCC \"%s\" %s Channel %c : WR0_ERROR_RESET\n", m_owner->tag(), __func__, 'A' + m_index)); + do_sioreg_wr0(data); // reset status registers + m_rx_fifo_rp_step(); // Reset error state in fifo and unlock it. unlock == step to next slot in fifo. + break; + case WR0_SEND_ABORT: + data &= 0xef; // convert SCC SEND_ABORT command to a SIO SEND_ABORT command and fall through + /* The following commands relies on the SIO default behviour */ + case WR0_NULL: + case WR0_ENABLE_INT_NEXT_RX: + case WR0_RESET_TX_INT: + default: + do_sioreg_wr0(data); + } + do_sioreg_wr0_resets(data); + if ( m_variant & SET_Z80X30) // TODO: Implement adress decoding for Z80X30 using the shift logic described below + { + /*The registers in the Z80X30 are addressed via the address on AD7-AD0 and are latched by the rising + edge of /AS. The Shift Right/Shift Left bit in the Channel B WR0 controls which bits are + decoded to form the register address. It is placed in this register to simplify programming when the + current state of the Shift Right/Shift Left bit is not known. + A hardware reset forces Shift Left mode where the address is decoded from AD5-AD1. In Shift + Right mode, the address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written via a + command to make the software writing to WR0 independent of the state of the Shift Right/Shift + Left bit. + While in the Shift Left mode, the register address is placed on AD4-AD1 and the Channel Select + bit, A/B, is decoded from AD5. The register map for this case is listed in Table on page 21. In + Shift Right mode, the register address is again placed on AD4-AD1 but the channel select A/B is + decoded from AD0. The register map for this case is listed in Table on page 23. + Because the Z80X30 does not contain 16 read registers, the decoding of the read registers is not + complete; this is listed in Table on page 21 and Table on page 23 by parentheses around the register + name. These addresses may also be used to access the read registers. Also, note that the + Z80X30 contains only one WR2 and WR9; these registers may be written from either channel. + Shift Left Mode is used when Channel A and B are to be programmed differently. This allows the + software to sequence through the registers of one channel at a time. The Shift Right Mode is used + when the channels are programmed the same. By incrementing the address, the user can program + the same data value into both the Channel A and Channel B register.*/ + switch(data & WR0_Z_SHIFT_MASK) + { + case WR0_Z_SEL_SHFT_LEFT: + LOG(("Z80SCC \"%s\" Channel %c : %s - Shift Left Addressing Mode - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR0_Z_SEL_SHFT_RIGHT: + LOG(("Z80SCC \"%s\" Channel %c : %s - Shift Right Addressing Mode - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + default: + break; + // LOG(("Z80SCC \"%s\" Channel %c : %s - Null commands\n", m_owner->tag(), 'A' + m_index, __func__)); + } + } } /* Write Register 1 is the control register for the various SCC interrupt and Wait/Request modes.*/ void z80scc_channel::do_sccreg_wr1(UINT8 data) { - LOG(("Z80SCC \"%s\" Channel %c : %s - %02x\n", m_owner->tag(), 'A' + m_index, __func__, data)); - /* TODO: Sort out SCC specific behaviours from legacy SIO behaviours: - - Channel B only bits vs - - Parity Is Special Condition, bit2 */ - do_sioreg_wr1(data & ~0x40); // Lets SIO code handle it for now but mask out dangerous bits - m_uart->check_interrupts(); + LOG(("Z80SCC \"%s\" Channel %c : %s - %02x\n", m_owner->tag(), 'A' + m_index, __func__, data)); + /* TODO: Sort out SCC specific behaviours from legacy SIO behaviours: + - Channel B only bits vs + - Parity Is Special Condition, bit2 */ + do_sioreg_wr1(data & ~0x40); // Lets SIO code handle it for now but mask out dangerous bits + m_uart->check_interrupts(); } /*WR2 is the interrupt vector register. Only one vector register exists in the SCC, and it can be @@ -1364,12 +1363,12 @@ accessed through either channel. The interrupt vector can be modified by status is controlled by the Vector Includes Status (VIS) and the Status High/Status Low bits in WR9.*/ void z80scc_channel::do_sccreg_wr2(UINT8 data) { - LOG(("Z80SCC \"%s\" Channel %c : %s - Setting the interrupt vector to: %02x \n", m_owner->tag(), 'A' + m_index, __func__, data)); - m_wr2 = data; - m_uart->m_chanA->m_rr2 = data; - m_uart->m_chanB->m_rr2 = data; /* TODO: Sort out the setting of ChanB depending on bits in WR9 */ + LOG(("Z80SCC \"%s\" Channel %c : %s - Setting the interrupt vector to: %02x \n", m_owner->tag(), 'A' + m_index, __func__, data)); + m_wr2 = data; + m_uart->m_chanA->m_rr2 = data; + m_uart->m_chanB->m_rr2 = data; /* TODO: Sort out the setting of ChanB depending on bits in WR9 */ - m_uart->check_interrupts(); + m_uart->check_interrupts(); } /* @@ -1379,48 +1378,48 @@ void z80scc_channel::do_sccreg_wr2(UINT8 data) /* WR8 is the transmit buffer register */ void z80scc_channel::do_sccreg_wr8(UINT8 data) { - LOG(("Z80SCC \"%s\" Channel %c : Transmit Buffer read %02x\n", m_owner->tag(), 'A' + m_index, data)); - data_write(data); + LOG(("Z80SCC \"%s\" Channel %c : Transmit Buffer read %02x\n", m_owner->tag(), 'A' + m_index, data)); + data_write(data); } /*WR9 is the Master Interrupt Control register and contains the Reset command bits. Only one WR9 exists in the SCC and is accessed from either channel. The Interrupt control bits are programmed -at the same time as the Reset command, because these bits are only reset by a hardware reset +at the same time as the Reset command, because these bits are only reset by a hardware reset note that the Z80X30 contains only one WR2 and WR9; these registers may be written from either channel.*/ void z80scc_channel::do_sccreg_wr9(UINT8 data) { - if (m_variant & SET_Z80X30) - { - m_uart->m_chanA->m_wr9 = data; - m_uart->m_chanB->m_wr9 = data; - } - else - m_wr9 = data; - - switch (data & WR9_CMD_MASK) - { - case WR9_CMD_NORESET: - LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - No reset %02x\n", m_owner->tag(), 'A' + m_index, data)); - break; - case WR9_CMD_CHNB_RESET: - LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - Channel B reset %02x\n", m_owner->tag(), 'A' + m_index, data)); - m_uart->m_chanB->reset(); - break; - case WR9_CMD_CHNA_RESET: - LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - Channel A reset %02x\n", m_owner->tag(), 'A' + m_index, data)); - m_uart->m_chanA->reset(); - break; - case WR9_CMD_HW_RESET: - LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - Device reset %02x\n", m_owner->tag(), 'A' + m_index, data)); - /*"The effects of this command are identical to those of a hardware reset, except that the Shift Right/Shift Left bit is - not changed and the MIE, Status High/Status Low and DLC bits take the programmed values that accompany this command." - The Shift Right/Shift Left bits of the WR0 is only valid on SCC8030 device hence not implemented yet, just the SCC8530 */ - if (data & (WR9_BIT_MIE | WR9_BIT_IACK | WR9_BIT_SHSL | WR9_BIT_DLC | WR9_BIT_NV)) - logerror("Z80SCC: SCC Interrupt system not yet implemented, please be patient!\n"); - m_uart->device_reset(); - default: - logerror("Z80SCC Code is broken in WR9, please report!\n"); - } + if (m_variant & SET_Z80X30) + { + m_uart->m_chanA->m_wr9 = data; + m_uart->m_chanB->m_wr9 = data; + } + else + m_wr9 = data; + + switch (data & WR9_CMD_MASK) + { + case WR9_CMD_NORESET: + LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - No reset %02x\n", m_owner->tag(), 'A' + m_index, data)); + break; + case WR9_CMD_CHNB_RESET: + LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - Channel B reset %02x\n", m_owner->tag(), 'A' + m_index, data)); + m_uart->m_chanB->reset(); + break; + case WR9_CMD_CHNA_RESET: + LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - Channel A reset %02x\n", m_owner->tag(), 'A' + m_index, data)); + m_uart->m_chanA->reset(); + break; + case WR9_CMD_HW_RESET: + LOG(("Z80SCC \"%s\" Channel %c : Master Interrupt Control - Device reset %02x\n", m_owner->tag(), 'A' + m_index, data)); + /*"The effects of this command are identical to those of a hardware reset, except that the Shift Right/Shift Left bit is + not changed and the MIE, Status High/Status Low and DLC bits take the programmed values that accompany this command." + The Shift Right/Shift Left bits of the WR0 is only valid on SCC8030 device hence not implemented yet, just the SCC8530 */ + if (data & (WR9_BIT_MIE | WR9_BIT_IACK | WR9_BIT_SHSL | WR9_BIT_DLC | WR9_BIT_NV)) + logerror("Z80SCC: SCC Interrupt system not yet implemented, please be patient!\n"); + m_uart->device_reset(); + default: + logerror("Z80SCC Code is broken in WR9, please report!\n"); + } } /* WR10 contains miscellaneous control bits for both the receiver and the transmitter. Bit positions @@ -1428,8 +1427,8 @@ for WR10 are displayed in Figure . On the ESCC and 85C30 with the Extended Read enabled, this register may be read as RR11.*/ void z80scc_channel::do_sccreg_wr10(UINT8 data) { - m_wr10 = data; - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Tx/Rx Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); + m_wr10 = data; + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Tx/Rx Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); } /* WR11 is the Clock Mode Control register. The bits in this register control the sources of both the @@ -1437,70 +1436,70 @@ receive and transmit clocks, the type of signal on the /SYNC and /RTxC pins, and the /TRxC pin.*/ void z80scc_channel::do_sccreg_wr11(UINT8 data) { - LOG(("Z80SCC \"%s\" Channel %c : %s Clock Mode Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); - m_wr11 = data; - /*Bit 7: This bit controls the type of input signal the SCC expects to see on the /RTxC pin. If this bit is set - to 0, the SCC expects a TTL-compatible signal as an input to this pin. If this bit is set to 1, the SCC - connects a high-gain amplifier between the /RTxC and /SYNC pins in expectation of a quartz - crystal being placed across the pins. - The output of this oscillator is available for use as a clocking source. In this mode of operation, the - /SYNC pin is unavailable for other use. The /SYNC signal is forced to zero internally. A hardware - reset forces /NO XTAL. (At least 20 ms should be allowed after this bit is set to allow the oscillator - to stabilize.)*/ - LOG((" Clock type %s\n", data & WR11_RCVCLK_TYPE ? "Crystal oscillator between RTxC and /SYNC pins" : "TTL level on RTxC pin")); - /*Bits 6 and 5: Receiver Clock select bits 1 and 0 - These bits determine the source of the receive clock as listed below. They do not - interfere with any of the modes of operation in the SCC, but simply control a multiplexer just - before the internal receive clock input. A hardware reset forces the receive clock to come from the - /RTxC pin.*/ - LOG((" Receive clock source is: ")); - switch (data & WR11_RCVCLK_SRC_MASK) - { - case WR11_RCVCLK_SRC_RTXC: LOG(("RTxC\n")); break; - case WR11_RCVCLK_SRC_TRXC: LOG(("TRxC\n")); break; - case WR11_RCVCLK_SRC_BR: LOG(("Baudrate Generator\n")); break; - case WR11_RCVCLK_SRC_DPLL: LOG(("DPLL\n")); break; - default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ - } - /*Bits 4 and 3: Transmit Clock select bits 1 and 0. - These bits determine the source of the transmit clock as listed in Table . They do not interfere with - any of the modes of operation of the SCC, but simply control a multiplexer just before the internal - transmit clock input. The DPLL output that is used to feed the transmitter in FM modes lags by 90 - degrees the output of the DPLL used by the receiver. This makes the received and transmitted bit - cells occur simultaneously, neglecting delays. A hardware reset selects the /TRxC pin as the - source of the transmit clocks.*/ - LOG((" Transmit clock source is: ")); - switch (data & WR11_TRACLK_SRC_MASK) - { - case WR11_TRACLK_SRC_RTXC: LOG(("RTxC\n")); break; - case WR11_TRACLK_SRC_TRXC: LOG(("TRxC\n")); break; - case WR11_TRACLK_SRC_BR: LOG(("Baudrate Generator\n")); break; - case WR11_TRACLK_SRC_DPLL: LOG(("DPLL\n")); break; - default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ - } - /* Bit 2: TRxC Pin I/O control bit - This bit determines the direction of the /TRxC pin. If this bit is set to 1, the /TRxC pin is an output - and carries the signal selected by D1 and D0 of this register. However, if either the receive or the - transmit clock is programmed to come from the /TRxC pin, /TRxC is an input, regardless of the - state of this bit. The /TRxC pin is also an input if this bit is set to 0. A hardware reset forces this bit - to 0.*/ - LOG((" TRxC pin is %s\n", data & WR11_TRXC_DIRECTION ? "Output" : "Input")); - /*Bits 1 and 0: /TRxC Output Source select bits 1 and 0 - These bits determine the signal to be echoed out of the SCC via the /TRxC pin as listed in Table - on page 167. No signal is produced if /TRxC has been programmed as the source of either the - receive or the transmit clock. If /TRxC O/I (bit 2) is set to 0, these bits are ignored. - If the XTAL oscillator output is programmed to be echoed, and the XTAL oscillator is not enabled, - the /TRxC pin goes High. The DPLL signal that is echoed is the DPLL signal used by the receiver. - Hardware reset selects the XTAL oscillator as the output source*/ - LOG((" TRxC clock source is: ")); - switch (data & WR11_TRXSRC_SRC_MASK) - { - case WR11_TRXSRC_SRC_XTAL: LOG(("the Oscillator\n")); break; - case WR11_TRXSRC_SRC_TRA: LOG(("Transmit clock\n")); break; - case WR11_TRXSRC_SRC_BR: LOG(("Baudrate Generator\n")); break; - case WR11_TRXSRC_SRC_DPLL: LOG(("DPLL\n")); break; - default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ - } + LOG(("Z80SCC \"%s\" Channel %c : %s Clock Mode Control %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); + m_wr11 = data; + /*Bit 7: This bit controls the type of input signal the SCC expects to see on the /RTxC pin. If this bit is set + to 0, the SCC expects a TTL-compatible signal as an input to this pin. If this bit is set to 1, the SCC + connects a high-gain amplifier between the /RTxC and /SYNC pins in expectation of a quartz + crystal being placed across the pins. + The output of this oscillator is available for use as a clocking source. In this mode of operation, the + /SYNC pin is unavailable for other use. The /SYNC signal is forced to zero internally. A hardware + reset forces /NO XTAL. (At least 20 ms should be allowed after this bit is set to allow the oscillator + to stabilize.)*/ + LOG((" Clock type %s\n", data & WR11_RCVCLK_TYPE ? "Crystal oscillator between RTxC and /SYNC pins" : "TTL level on RTxC pin")); + /*Bits 6 and 5: Receiver Clock select bits 1 and 0 + These bits determine the source of the receive clock as listed below. They do not + interfere with any of the modes of operation in the SCC, but simply control a multiplexer just + before the internal receive clock input. A hardware reset forces the receive clock to come from the + /RTxC pin.*/ + LOG((" Receive clock source is: ")); + switch (data & WR11_RCVCLK_SRC_MASK) + { + case WR11_RCVCLK_SRC_RTXC: LOG(("RTxC\n")); break; + case WR11_RCVCLK_SRC_TRXC: LOG(("TRxC\n")); break; + case WR11_RCVCLK_SRC_BR: LOG(("Baudrate Generator\n")); break; + case WR11_RCVCLK_SRC_DPLL: LOG(("DPLL\n")); break; + default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ + } + /*Bits 4 and 3: Transmit Clock select bits 1 and 0. + These bits determine the source of the transmit clock as listed in Table . They do not interfere with + any of the modes of operation of the SCC, but simply control a multiplexer just before the internal + transmit clock input. The DPLL output that is used to feed the transmitter in FM modes lags by 90 + degrees the output of the DPLL used by the receiver. This makes the received and transmitted bit + cells occur simultaneously, neglecting delays. A hardware reset selects the /TRxC pin as the + source of the transmit clocks.*/ + LOG((" Transmit clock source is: ")); + switch (data & WR11_TRACLK_SRC_MASK) + { + case WR11_TRACLK_SRC_RTXC: LOG(("RTxC\n")); break; + case WR11_TRACLK_SRC_TRXC: LOG(("TRxC\n")); break; + case WR11_TRACLK_SRC_BR: LOG(("Baudrate Generator\n")); break; + case WR11_TRACLK_SRC_DPLL: LOG(("DPLL\n")); break; + default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ + } + /* Bit 2: TRxC Pin I/O control bit + This bit determines the direction of the /TRxC pin. If this bit is set to 1, the /TRxC pin is an output + and carries the signal selected by D1 and D0 of this register. However, if either the receive or the + transmit clock is programmed to come from the /TRxC pin, /TRxC is an input, regardless of the + state of this bit. The /TRxC pin is also an input if this bit is set to 0. A hardware reset forces this bit + to 0.*/ + LOG((" TRxC pin is %s\n", data & WR11_TRXC_DIRECTION ? "Output" : "Input")); + /*Bits 1 and 0: /TRxC Output Source select bits 1 and 0 + These bits determine the signal to be echoed out of the SCC via the /TRxC pin as listed in Table + on page 167. No signal is produced if /TRxC has been programmed as the source of either the + receive or the transmit clock. If /TRxC O/I (bit 2) is set to 0, these bits are ignored. + If the XTAL oscillator output is programmed to be echoed, and the XTAL oscillator is not enabled, + the /TRxC pin goes High. The DPLL signal that is echoed is the DPLL signal used by the receiver. + Hardware reset selects the XTAL oscillator as the output source*/ + LOG((" TRxC clock source is: ")); + switch (data & WR11_TRXSRC_SRC_MASK) + { + case WR11_TRXSRC_SRC_XTAL: LOG(("the Oscillator\n")); break; + case WR11_TRXSRC_SRC_TRA: LOG(("Transmit clock\n")); break; + case WR11_TRXSRC_SRC_BR: LOG(("Baudrate Generator\n")); break; + case WR11_TRXSRC_SRC_DPLL: LOG(("DPLL\n")); break; + default: logerror("Wrong!\n");/* Will not happen unless someone messes with the mask */ + } } /*WR12 contains the lower byte of the time constant for the baud rate generator. The time constant @@ -1520,79 +1519,79 @@ This is then fed to a toggle flip-flop to make the output a square wave. */ void z80scc_channel::do_sccreg_wr12(UINT8 data) { - m_wr12 = data; - LOG(("Z80SCC \"%s\" Channel %c : %s %02x Low byte of Time Constant for Baudrate generator - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); + m_wr12 = data; + LOG(("Z80SCC \"%s\" Channel %c : %s %02x Low byte of Time Constant for Baudrate generator - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); } /* WR13 contains the upper byte of the time constant for the baud rate generator. */ void z80scc_channel::do_sccreg_wr13(UINT8 data) { - m_wr13 = data; - LOG(("Z80SCC \"%s\" Channel %c : %s %02x High byte of Time Constant for Baudrate generator - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); + m_wr13 = data; + LOG(("Z80SCC \"%s\" Channel %c : %s %02x High byte of Time Constant for Baudrate generator - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); } /* WR14 contains some miscellaneous control bits */ void z80scc_channel::do_sccreg_wr14(UINT8 data) { - switch (data & WR14_DPLL_CMD_MASK) - { - case WR14_CMD_NULL: - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Null Command %02x\n", m_owner->tag(), 'A' + m_index, __func__, data)); - break; - case WR14_CMD_ESM: -/* Issuing this command causes the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the - incoming data stream. The action taken by the DPLL upon receipt of this command depends on the operating mode of - the DPLL. In NRZI mode, the output of the DPLL is High while the DPLL is waiting for an edge in the incoming data - stream. After the Search mode is entered, the first edge the DPLL sees is assumed to be a valid data edge, and - the DPLL begins the clock recovery operation from that point. The DPLL clock rate must be 32x the data rate in - NRZI mode. Upon leaving the Search mode, the first sampling edge of the DPLL occurs 16 of these 32x clocks after - the first data edge, and the second sampling occurs 48 of these 32x clocks after the first data edge. Beyond - this point, the DPLL begins normal operation, adjusting the output to remain in sync with the incoming data. - In FM mode, the output of the DPLL is Low while the DPLL is waiting for an edge in the incoming data stream. - The first edge the DPLL detects is assumed to be a valid clock edge. For this to be the case, the line must - contain only clock edges; i.e. with FM1 encoding, the line must be continuous 0s. With FM0 encoding the line must - be continuous 1s, whereas Manchester encoding requires alternating 1s and 0s on the line. The DPLL clock rate must - be 16 times the data rate in FM mode. The DPLL output causes the receiver to sample the data stream in the nominal - center of the two halves of the bit to decide whether the data was a 1 or a 0. After this command is issued, as in - NRZI mode, the DPLL starts sampling immediately after the first edge is detected. (In FM mode, the DPLL examines - the clock edge of every other bit to decide what correction must be made to remain in sync.) If the DPLL does not - see an edge during the expected window, the one clock missing bit in RR10 is set. If the DPLL does not see an edge - after two successive attempts, the two clocks missing bits in RR10 are set and the DPLL automatically enters the + switch (data & WR14_DPLL_CMD_MASK) + { + case WR14_CMD_NULL: + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Null Command %02x\n", m_owner->tag(), 'A' + m_index, __func__, data)); + break; + case WR14_CMD_ESM: +/* Issuing this command causes the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the + incoming data stream. The action taken by the DPLL upon receipt of this command depends on the operating mode of + the DPLL. In NRZI mode, the output of the DPLL is High while the DPLL is waiting for an edge in the incoming data + stream. After the Search mode is entered, the first edge the DPLL sees is assumed to be a valid data edge, and + the DPLL begins the clock recovery operation from that point. The DPLL clock rate must be 32x the data rate in + NRZI mode. Upon leaving the Search mode, the first sampling edge of the DPLL occurs 16 of these 32x clocks after + the first data edge, and the second sampling occurs 48 of these 32x clocks after the first data edge. Beyond + this point, the DPLL begins normal operation, adjusting the output to remain in sync with the incoming data. + In FM mode, the output of the DPLL is Low while the DPLL is waiting for an edge in the incoming data stream. + The first edge the DPLL detects is assumed to be a valid clock edge. For this to be the case, the line must + contain only clock edges; i.e. with FM1 encoding, the line must be continuous 0s. With FM0 encoding the line must + be continuous 1s, whereas Manchester encoding requires alternating 1s and 0s on the line. The DPLL clock rate must + be 16 times the data rate in FM mode. The DPLL output causes the receiver to sample the data stream in the nominal + center of the two halves of the bit to decide whether the data was a 1 or a 0. After this command is issued, as in + NRZI mode, the DPLL starts sampling immediately after the first edge is detected. (In FM mode, the DPLL examines + the clock edge of every other bit to decide what correction must be made to remain in sync.) If the DPLL does not + see an edge during the expected window, the one clock missing bit in RR10 is set. If the DPLL does not see an edge + after two successive attempts, the two clocks missing bits in RR10 are set and the DPLL automatically enters the Search mode. This command resets both clocks missing latches.*/ - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Enter Search Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR14_CMD_RMC: + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Enter Search Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR14_CMD_RMC: /* Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state */ - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Reset Missing Clocks Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR14_CMD_DISABLE_DPLL: + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Reset Missing Clocks Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR14_CMD_DISABLE_DPLL: /* Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state.*/ - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Disable DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR14_CMD_SS_BGR: + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Disable DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR14_CMD_SS_BGR: /* Issuing this command forces the clock for the DPLL to come from the output of the BRG. */ - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Baudrate Generator Input DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR14_CMD_SS_RTXC: -/* Issuing the command forces the clock for the DPLL to come from the /RTxC pin or the crystal oscillator, depending on + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Baudrate Generator Input DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR14_CMD_SS_RTXC: +/* Issuing the command forces the clock for the DPLL to come from the /RTxC pin or the crystal oscillator, depending on the state of the XTAL/no XTAL bit in WR11. This mode is selected by a channel or hardware reset*/ - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits RTxC Input DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR14_CMD_SET_FM: -/* This command forces the DPLL to operate in the FM mode and is used to recover the clock from FM or Manchester-Encoded + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits RTxC Input DPLL Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR14_CMD_SET_FM: +/* This command forces the DPLL to operate in the FM mode and is used to recover the clock from FM or Manchester-Encoded data. (Manchester is decoded by placing the receiver in NRZ mode while the DPLL is in FM mode.)*/ - LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Set FM Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - case WR14_CMD_SET_NRZI: + LOG(("Z80SCC \"%s\" Channel %c : %s Misc Control Bits Set FM Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + case WR14_CMD_SET_NRZI: /* Issuing this command forces the DPLL to operate in the NRZI mode. This mode is also selected by a hardware or channel reset.*/ - LOG(("Z80SCC \"%s\" Channel %c : %s Mics Control Bits Set NRZI Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); - break; - default: - logerror("Z80SCC \"%s\" Channel %c : %s Mics Control Bits command %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data); - } - // TODO: Add info on the other bits of this register - m_wr14 = data; + LOG(("Z80SCC \"%s\" Channel %c : %s Mics Control Bits Set NRZI Mode Command - not implemented\n", m_owner->tag(), 'A' + m_index, __func__)); + break; + default: + logerror("Z80SCC \"%s\" Channel %c : %s Mics Control Bits command %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data); + } + // TODO: Add info on the other bits of this register + m_wr14 = data; } /* WR15 is the External/Status Source Control register. If the External/Status interrupts are enabled @@ -1601,8 +1600,8 @@ Only the External/Status conditions that occur after the controlling bit is set interrupt. This is true, even if an External/Status condition is pending at the time the bit is set*/ void z80scc_channel::do_sccreg_wr15(UINT8 data) { - LOG(("Z80SCC \"%s\" Channel %c : %s External/Status Source Control Bits %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); - m_wr15 = data; + LOG(("Z80SCC \"%s\" Channel %c : %s External/Status Source Control Bits %02x - not implemented \n", m_owner->tag(), 'A' + m_index, __func__, data)); + m_wr15 = data; } @@ -1612,12 +1611,12 @@ void z80scc_channel::do_sccreg_wr15(UINT8 data) void z80scc_channel::control_write(UINT8 data) { - UINT8 reg = m_wr0; - UINT8 regmask = (WR0_REGISTER_MASK | m_ph); + UINT8 reg = m_wr0; + UINT8 regmask = (WR0_REGISTER_MASK | m_ph); m_ph = 0; // The "Point High" command is only valid for one access - reg &= regmask; + reg &= regmask; if (reg != 0) { @@ -1627,43 +1626,43 @@ void z80scc_channel::control_write(UINT8 data) LOG(("%s(%02x) reg %02x, regmask %02x, WR0 %02x\n", __func__, data, reg, regmask, m_wr0)); - /* TODO. Sort out 80X30 & other SCC variants limitations in register access */ + /* TODO. Sort out 80X30 & other SCC variants limitations in register access */ switch (reg) { case REG_WR0_COMMAND_REGPT: do_sccreg_wr0(data); break; case REG_WR1_INT_DMA_ENABLE: do_sccreg_wr1(data); m_uart->check_interrupts(); break; case REG_WR2_INT_VECTOR: do_sccreg_wr2(data); break; - case REG_WR3_RX_CONTROL: - do_sioreg_wr3(data); - update_serial(); - receive_register_reset(); - break; - case REG_WR4_RX_TX_MODES: - do_sioreg_wr4(data); - update_serial(); - transmit_register_reset(); - receive_register_reset(); - break; - case REG_WR5_TX_CONTROL: - do_sioreg_wr5(data); - update_serial(); - transmit_register_reset(); - update_rts(); - break; + case REG_WR3_RX_CONTROL: + do_sioreg_wr3(data); + update_serial(); + receive_register_reset(); + break; + case REG_WR4_RX_TX_MODES: + do_sioreg_wr4(data); + update_serial(); + transmit_register_reset(); + receive_register_reset(); + break; + case REG_WR5_TX_CONTROL: + do_sioreg_wr5(data); + update_serial(); + transmit_register_reset(); + update_rts(); + break; case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break; case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break; case REG_WR8_TRANSMIT_DATA: do_sccreg_wr8(data); break; case REG_WR9_MASTER_INT_CTRL: do_sccreg_wr9(data); break; - case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break; - case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break; - case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break; - case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break; - case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break; - case REG_WR15_EXT_ST_INT_CTRL: + case REG_WR10_MSC_RX_TX_CTRL: do_sccreg_wr10(data); break; + case REG_WR11_CLOCK_MODES: do_sccreg_wr11(data); break; + case REG_WR12_LO_BAUD_GEN: do_sccreg_wr12(data); break; + case REG_WR13_HI_BAUD_GEN: do_sccreg_wr13(data); break; + case REG_WR14_MISC_CTRL: do_sccreg_wr14(data); break; + case REG_WR15_EXT_ST_INT_CTRL: LOG(("Z80SCC \"%s\" Channel %c : unsupported command: External/Status Control Bits %02x\n", m_owner->tag(), 'A' + m_index, data)); - break; + break; default: - logerror("Z80SCC \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); + logerror("Z80SCC \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); } } @@ -1676,56 +1675,56 @@ UINT8 z80scc_channel::data_read() { UINT8 data = 0; - if (m_rx_fifo_wp != m_rx_fifo_rp) + if (m_rx_fifo_wp != m_rx_fifo_rp) { - /* Special Receive Condition interrupts are generated after the character is read from - the FIFO, not when the special condition is first detected. This is done so that when - using receive interrupt on first or Special Condition or Special Condition Only, data is - directly read out of the data FIFO without checking the status first. If a special condi- - tion interrupted the CPU when first detected, it would be necessary to read RR1 - before each byte in the FIFO to determine which byte had the special condition. - Therefore, by not generating the interrupt until after the byte has been read and then - locking the FIFO, only one status read is necessary. A DMA can be used to do all data - transfers (otherwise, it would be necessary to disable the DMA to allow the CPU to - read the status on each byte). Consequently, since the special condition locks the - FIFO to preserve the status, it is necessary to issue the Error Reset command to - unlock it. Only the exit location of the FIFO is locked allowing more data to be - received into the other bytes of the Receive FIFO.*/ + /* Special Receive Condition interrupts are generated after the character is read from + the FIFO, not when the special condition is first detected. This is done so that when + using receive interrupt on first or Special Condition or Special Condition Only, data is + directly read out of the data FIFO without checking the status first. If a special condi- + tion interrupted the CPU when first detected, it would be necessary to read RR1 + before each byte in the FIFO to determine which byte had the special condition. + Therefore, by not generating the interrupt until after the byte has been read and then + locking the FIFO, only one status read is necessary. A DMA can be used to do all data + transfers (otherwise, it would be necessary to disable the DMA to allow the CPU to + read the status on each byte). Consequently, since the special condition locks the + FIFO to preserve the status, it is necessary to issue the Error Reset command to + unlock it. Only the exit location of the FIFO is locked allowing more data to be + received into the other bytes of the Receive FIFO.*/ // load data from the FIFO data = m_rx_fifo_rp_data(); - // load error status from the FIFO + // load error status from the FIFO m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp]; - // trigger interrup and lock the fifo if an error is present - if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) - { - switch (m_wr1 & WR1_RX_INT_MODE_MASK) - { - case WR1_RX_INT_FIRST: - if (!m_rx_first) - { - m_uart->trigger_interrupt(m_index, INT_SPECIAL); - } - break; - - case WR1_RX_INT_ALL_PARITY: - case WR1_RX_INT_ALL: - m_uart->trigger_interrupt(m_index, INT_SPECIAL); - break; - } - } - else - { - // decrease FIFO pointer - m_rx_fifo_rp_step(); - } + // trigger interrup and lock the fifo if an error is present + if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) + { + switch (m_wr1 & WR1_RX_INT_MODE_MASK) + { + case WR1_RX_INT_FIRST: + if (!m_rx_first) + { + m_uart->trigger_interrupt(m_index, INT_SPECIAL); + } + break; + + case WR1_RX_INT_ALL_PARITY: + case WR1_RX_INT_ALL: + m_uart->trigger_interrupt(m_index, INT_SPECIAL); + break; + } + } + else + { + // decrease FIFO pointer + m_rx_fifo_rp_step(); + } } - else - { - logerror("data_read: Attempt to read out character from empty FIFO\n"); - } + else + { + logerror("data_read: Attempt to read out character from empty FIFO\n"); + } LOG(("Z80SCC \"%s\" Channel %c : Data Register Read '%02x'\n", m_owner->tag(), 'A' + m_index, data)); @@ -1735,30 +1734,30 @@ UINT8 z80scc_channel::data_read() /* Get data from top of fifo data but restore read pointer in case of exit latch lock */ UINT8 z80scc_channel::m_rx_fifo_rp_data() { - UINT8 data; - UINT8 old_rp = m_rx_fifo_rp; - m_rx_fifo_rp_step(); - data = m_rx_data_fifo[m_rx_fifo_rp]; - m_rx_fifo_rp = old_rp; + UINT8 data; + UINT8 old_rp = m_rx_fifo_rp; + m_rx_fifo_rp_step(); + data = m_rx_data_fifo[m_rx_fifo_rp]; + m_rx_fifo_rp = old_rp; - return data; + return data; } /* Step read pointer */ void z80scc_channel::m_rx_fifo_rp_step() { - m_rx_fifo_rp++; - if (m_rx_fifo_rp >= m_rx_fifo_sz) - { - m_rx_fifo_rp = 0; - } - - // check if FIFO is empty - if (m_rx_fifo_rp == m_rx_fifo_wp) - { - // no more characters available in the FIFO - m_rr0 &= ~ RR0_RX_CHAR_AVAILABLE; - } + m_rx_fifo_rp++; + if (m_rx_fifo_rp >= m_rx_fifo_sz) + { + m_rx_fifo_rp = 0; + } + + // check if FIFO is empty + if (m_rx_fifo_rp == m_rx_fifo_wp) + { + // no more characters available in the FIFO + m_rr0 &= ~ RR0_RX_CHAR_AVAILABLE; + } } //------------------------------------------------- @@ -1769,7 +1768,7 @@ void z80scc_channel::data_write(UINT8 data) { m_tx_data = data; - if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty()) + if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty()) { LOG(("Z80SCC \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data)); @@ -1779,9 +1778,9 @@ void z80scc_channel::data_write(UINT8 data) m_rr0 |= RR0_TX_BUFFER_EMPTY; if (m_wr1 & WR1_TX_INT_ENABLE) - { + { m_uart->trigger_interrupt(m_index, INT_TRANSMIT); - } + } } else { @@ -1802,21 +1801,21 @@ void z80scc_channel::receive_data(UINT8 data) { LOG(("Z80SCC \"%s\" Channel %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data)); - if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || - ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) )) + if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || + ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) )) { // receive overrun error detected - m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR; // = m_rx_error; - } - else - { - m_rx_error_fifo[m_rx_fifo_wp] &= ~RR1_RX_OVERRUN_ERROR; // = m_rx_error; - m_rx_fifo_wp++; - if (m_rx_fifo_wp >= m_rx_fifo_sz) - { - m_rx_fifo_wp = 0; - } - } + m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR; // = m_rx_error; + } + else + { + m_rx_error_fifo[m_rx_fifo_wp] &= ~RR1_RX_OVERRUN_ERROR; // = m_rx_error; + m_rx_fifo_wp++; + if (m_rx_fifo_wp >= m_rx_fifo_sz) + { + m_rx_fifo_wp = 0; + } + } // store received character m_rx_data_fifo[m_rx_fifo_wp] = data; @@ -1881,7 +1880,7 @@ WRITE_LINE_MEMBER( z80scc_channel::cts_w ) } } } - // m_rr0 &= ~RR0_CTS; // Remove, just to test + // m_rr0 &= ~RR0_CTS; // Remove, just to test } @@ -2022,8 +2021,8 @@ void z80scc_channel::update_serial() else parity = PARITY_NONE; - LOG(("%" I64FMT "d %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1, - data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2)); + LOG(("%" I64FMT "d %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1, + data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2)); set_data_frame(1, data_bit_count, parity, stop_bits); int clocks = get_clock_mode(); @@ -2031,13 +2030,13 @@ void z80scc_channel::update_serial() if (m_rxc > 0) { set_rcv_rate(m_rxc / clocks); - LOG((" - Receiver clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); + LOG((" - Receiver clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); } if (m_txc > 0) { set_tra_rate(m_txc / clocks); - LOG((" - Transmit clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); + LOG((" - Transmit clock: %d mode: %d rate: %d/%xh\n", m_rxc, clocks, m_rxc / clocks, m_rxc / clocks)); } } @@ -2048,7 +2047,7 @@ void z80scc_channel::set_dtr(int state) { m_dtr = state; - LOG(("Z80SCC \"%s\" Channel %c : %s(%d)\n", m_owner->tag(), 'A' + m_index, __func__, state)); + LOG(("Z80SCC \"%s\" Channel %c : %s(%d)\n", m_owner->tag(), 'A' + m_index, __func__, state)); if (m_index == z80scc_device::CHANNEL_A) m_uart->m_out_dtra_cb(m_dtr); else @@ -2058,12 +2057,12 @@ void z80scc_channel::set_dtr(int state) //------------------------------------------------- -// write_rx - called by terminal through rs232/diserial +// write_rx - called by terminal through rs232/diserial // when character is sent to board //------------------------------------------------- WRITE_LINE_MEMBER(z80scc_channel::write_rx) { - // printf("%c", state ? '+' : 'o'); + // printf("%c", state ? '+' : 'o'); m_rxd = state; //only use rx_w when self-clocked if(m_rxc) diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h index 5e483f7be22..14ccf86dd76 100644 --- a/src/devices/machine/z80scc.h +++ b/src/devices/machine/z80scc.h @@ -126,41 +126,41 @@ public: virtual void rcv_callback(); virtual void rcv_complete(); - // read register handlers - UINT8 do_sccreg_rr0(); - UINT8 do_sccreg_rr1(); - UINT8 do_sccreg_rr2(); - UINT8 do_sccreg_rr3(); - UINT8 do_sccreg_rr4(); - UINT8 do_sccreg_rr5(); - UINT8 do_sccreg_rr6(); - UINT8 do_sccreg_rr7(); - UINT8 do_sccreg_rr8(); - UINT8 do_sccreg_rr9(); - UINT8 do_sccreg_rr10(); - UINT8 do_sccreg_rr11(); - UINT8 do_sccreg_rr12(); - UINT8 do_sccreg_rr13(); - UINT8 do_sccreg_rr14(); - UINT8 do_sccreg_rr15(); - - // write register handlers - void do_sccreg_wr0(UINT8 data); - void do_sccreg_wr1(UINT8 data); - void do_sccreg_wr2(UINT8 data); - void do_sccreg_wr3(UINT8 data); - void do_sccreg_wr4(UINT8 data); - void do_sccreg_wr5(UINT8 data); - void do_sccreg_wr6(UINT8 data); - void do_sccreg_wr7(UINT8 data); - void do_sccreg_wr8(UINT8 data); - void do_sccreg_wr9(UINT8 data); - void do_sccreg_wr10(UINT8 data); - void do_sccreg_wr11(UINT8 data); - void do_sccreg_wr12(UINT8 data); - void do_sccreg_wr13(UINT8 data); - void do_sccreg_wr14(UINT8 data); - void do_sccreg_wr15(UINT8 data); + // read register handlers + UINT8 do_sccreg_rr0(); + UINT8 do_sccreg_rr1(); + UINT8 do_sccreg_rr2(); + UINT8 do_sccreg_rr3(); + UINT8 do_sccreg_rr4(); + UINT8 do_sccreg_rr5(); + UINT8 do_sccreg_rr6(); + UINT8 do_sccreg_rr7(); + UINT8 do_sccreg_rr8(); + UINT8 do_sccreg_rr9(); + UINT8 do_sccreg_rr10(); + UINT8 do_sccreg_rr11(); + UINT8 do_sccreg_rr12(); + UINT8 do_sccreg_rr13(); + UINT8 do_sccreg_rr14(); + UINT8 do_sccreg_rr15(); + + // write register handlers + void do_sccreg_wr0(UINT8 data); + void do_sccreg_wr1(UINT8 data); + void do_sccreg_wr2(UINT8 data); + void do_sccreg_wr3(UINT8 data); + void do_sccreg_wr4(UINT8 data); + void do_sccreg_wr5(UINT8 data); + void do_sccreg_wr6(UINT8 data); + void do_sccreg_wr7(UINT8 data); + void do_sccreg_wr8(UINT8 data); + void do_sccreg_wr9(UINT8 data); + void do_sccreg_wr10(UINT8 data); + void do_sccreg_wr11(UINT8 data); + void do_sccreg_wr12(UINT8 data); + void do_sccreg_wr13(UINT8 data); + void do_sccreg_wr14(UINT8 data); + void do_sccreg_wr15(UINT8 data); UINT8 control_read(); void control_write(UINT8 data); @@ -170,7 +170,7 @@ public: void receive_data(UINT8 data); void m_rx_fifo_rp_step(); - UINT8 m_rx_fifo_rp_data(); + UINT8 m_rx_fifo_rp_data(); DECLARE_WRITE_LINE_MEMBER( write_rx ); DECLARE_WRITE_LINE_MEMBER( cts_w ); @@ -184,9 +184,9 @@ public: int m_txc; // Register state - // read registers enum + // read registers enum #if 0 //defined by z80sio.h - UINT8 m_rr0; // REG_RR0_STATUS + UINT8 m_rr0; // REG_RR0_STATUS UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT #endif @@ -204,18 +204,18 @@ public: UINT8 m_rr14; // REG_RR14_WR7_OR_R10 UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT - // write registers enum + // write registers enum #if 0 //defined by z80sio.h UINT8 m_wr0; // REG_WR0_COMMAND_REGPT - UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE - UINT8 m_wr2; // REG_WR2_INT_VECTOR - UINT8 m_wr3; // REG_WR3_RX_CONTROL - UINT8 m_wr4; // REG_WR4_RX_TX_MODES - UINT8 m_wr5; // REG_WR5_TX_CONTROL - UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A - UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F + UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE + UINT8 m_wr2; // REG_WR2_INT_VECTOR + UINT8 m_wr3; // REG_WR3_RX_CONTROL + UINT8 m_wr4; // REG_WR4_RX_TX_MODES + UINT8 m_wr5; // REG_WR5_TX_CONTROL + UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A + UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F #endif - UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA + UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA UINT8 m_wr9; // REG_WR9_MASTER_INT_CTRL UINT8 m_wr10; // REG_WR10_MSC_RX_TX_CTRL UINT8 m_wr11; // REG_WR11_CLOCK_MODES @@ -223,7 +223,7 @@ public: UINT8 m_wr13; // REG_WR13_HI_BAUD_GEN UINT8 m_wr14; // REG_WR14_MISC_CTRL UINT8 m_wr15; // REG_WR15_EXT_ST_INT_CTRL - + protected: enum @@ -231,50 +231,50 @@ protected: INT_TRANSMIT = 0, INT_EXTERNAL = 1, INT_RECEIVE = 2, - INT_SPECIAL = 3 + INT_SPECIAL = 3 }; - // Read registers - enum - { - REG_RR0_STATUS = 0, // SIO - REG_RR1_SPEC_RCV_COND = 1, // SIO - REG_RR2_INTERRUPT_VECT = 2, // SIO - REG_RR3_INTERUPPT_PEND = 3, - REG_RR4_WR4_OR_RR0 = 4, - REG_RR5_WR5_OR_RR0 = 5, - REG_RR6_LSB_OR_RR2 = 6, - REG_RR7_MSB_OR_RR3 = 7, - REG_RR8_RECEIVE_DATA = 8, - REG_RR9_WR3_OR_RR13 = 9, - REG_RR10_MISC_STATUS = 10, - REG_RR11_WR10_OR_RR15 = 11, - REG_RR12_LO_TIME_CONST = 12, - REG_RR13_HI_TIME_CONST = 13, - REG_RR14_WR7_OR_R10 = 14, - REG_RR15_WR15_EXT_STAT = 15 - }; - - // Write registers - enum - { - REG_WR0_COMMAND_REGPT = 0, // SIO - REG_WR1_INT_DMA_ENABLE = 1, // SIO - REG_WR2_INT_VECTOR = 2, // SIO - REG_WR3_RX_CONTROL = 3, // SIO - REG_WR4_RX_TX_MODES = 4, // SIO - REG_WR5_TX_CONTROL = 5, // SIO - REG_WR6_SYNC_OR_SDLC_A = 6, // SIO - REG_WR7_SYNC_OR_SDLC_F = 7, // SIO - REG_WR8_TRANSMIT_DATA = 8, - REG_WR9_MASTER_INT_CTRL = 9, - REG_WR10_MSC_RX_TX_CTRL = 10, - REG_WR11_CLOCK_MODES = 11, - REG_WR12_LO_BAUD_GEN = 12, - REG_WR13_HI_BAUD_GEN = 13, - REG_WR14_MISC_CTRL = 14, - REG_WR15_EXT_ST_INT_CTRL= 15 - }; + // Read registers + enum + { + REG_RR0_STATUS = 0, // SIO + REG_RR1_SPEC_RCV_COND = 1, // SIO + REG_RR2_INTERRUPT_VECT = 2, // SIO + REG_RR3_INTERUPPT_PEND = 3, + REG_RR4_WR4_OR_RR0 = 4, + REG_RR5_WR5_OR_RR0 = 5, + REG_RR6_LSB_OR_RR2 = 6, + REG_RR7_MSB_OR_RR3 = 7, + REG_RR8_RECEIVE_DATA = 8, + REG_RR9_WR3_OR_RR13 = 9, + REG_RR10_MISC_STATUS = 10, + REG_RR11_WR10_OR_RR15 = 11, + REG_RR12_LO_TIME_CONST = 12, + REG_RR13_HI_TIME_CONST = 13, + REG_RR14_WR7_OR_R10 = 14, + REG_RR15_WR15_EXT_STAT = 15 + }; + + // Write registers + enum + { + REG_WR0_COMMAND_REGPT = 0, // SIO + REG_WR1_INT_DMA_ENABLE = 1, // SIO + REG_WR2_INT_VECTOR = 2, // SIO + REG_WR3_RX_CONTROL = 3, // SIO + REG_WR4_RX_TX_MODES = 4, // SIO + REG_WR5_TX_CONTROL = 5, // SIO + REG_WR6_SYNC_OR_SDLC_A = 6, // SIO + REG_WR7_SYNC_OR_SDLC_F = 7, // SIO + REG_WR8_TRANSMIT_DATA = 8, + REG_WR9_MASTER_INT_CTRL = 9, + REG_WR10_MSC_RX_TX_CTRL = 10, + REG_WR11_CLOCK_MODES = 11, + REG_WR12_LO_BAUD_GEN = 12, + REG_WR13_HI_BAUD_GEN = 13, + REG_WR14_MISC_CTRL = 14, + REG_WR15_EXT_ST_INT_CTRL= 15 + }; enum { @@ -282,7 +282,7 @@ protected: RR0_ZC = 0x02, // SCC bit RR0_TX_BUFFER_EMPTY = 0x04, // SIO RR0_DCD = 0x08, // SIO - RR0_RI = 0x10, // DART bit? TODO: investigate function and remove + RR0_RI = 0x10, // DART bit? TODO: investigate function and remove RR0_SYNC_HUNT = 0x10, // SIO bit, not supported RR0_CTS = 0x20, // SIO bit RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported @@ -299,30 +299,30 @@ protected: RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported }; - enum - { // TODO: overload SIO functionality - RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) - RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B - }; - - enum - { - RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers - RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels) - RR3_CHANB_RX_IP = 0x04, // channel B return all zero - RR3_CHANA_EXT_IP = 0x08, - RR3_CHANA_TX_IP = 0x10, - RR3_CHANA_RX_IP = 0x20 - }; + enum + { // TODO: overload SIO functionality + RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) + RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B + }; + + enum + { + RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers + RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels) + RR3_CHANB_RX_IP = 0x04, // channel B return all zero + RR3_CHANA_EXT_IP = 0x08, + RR3_CHANA_TX_IP = 0x10, + RR3_CHANA_RX_IP = 0x20 + }; enum // Universal Bus WR0 commands for 85X30 { WR0_REGISTER_MASK = 0x07, WR0_COMMAND_MASK = 0x38, // COMMANDS WR0_NULL = 0x00, // 0 0 0 - WR0_POINT_HIGH = 0x08, // 0 0 1 + WR0_POINT_HIGH = 0x08, // 0 0 1 WR0_RESET_EXT_STATUS = 0x10, // 0 1 0 WR0_SEND_ABORT = 0x18, // 0 1 1 WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 @@ -340,17 +340,17 @@ protected: { WR0_Z_COMMAND_MASK = 0x38, // COMMANDS WR0_Z_NULL_1 = 0x00, // 0 0 0 - WR0_Z_NULL_2 = 0x08, // 0 0 1 - WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0 + WR0_Z_NULL_2 = 0x08, // 0 0 1 + WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0 WR0_Z_SEND_ABORT = 0x18, // 0 1 1 WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 WR0_Z_RESET_TX_INT = 0x28, // 1 0 1 WR0_Z_ERROR_RESET = 0x30, // 1 1 0 WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1 - WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B - WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0 - WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1 - }; + WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B + WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0 + WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1 + }; enum { @@ -417,62 +417,62 @@ protected: WR5_DTR = 0x80 }; - /* SCC specifics */ - enum - { - WR9_CMD_MASK = 0xC0, - WR9_CMD_NORESET = 0x00, - WR9_CMD_CHNB_RESET = 0x40, - WR9_CMD_CHNA_RESET = 0x80, - WR9_CMD_HW_RESET = 0xC0, - WR9_BIT_VIS = 0x01, - WR9_BIT_NV = 0x02, - WR9_BIT_DLC = 0x04, - WR9_BIT_MIE = 0x08, - WR9_BIT_SHSL = 0x10, - WR9_BIT_IACK = 0x20 - }; - - enum - { - WR11_RCVCLK_TYPE = 0x80, - WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK - WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0 - WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1 - WR11_RCVCLK_SRC_BR = 0x40, // 1 0 - WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1 - WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK - WR11_TRACLK_SRC_RTXC = 0x00, // 0 0 - WR11_TRACLK_SRC_TRXC = 0x08, // 0 1 - WR11_TRACLK_SRC_BR = 0x10, // 1 0 - WR11_TRACLK_SRC_DPLL = 0x18, // 1 1 - WR11_TRXC_DIRECTION = 0x04, - WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK - WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0 - WR11_TRXSRC_SRC_TRA = 0x01, // 0 1 - WR11_TRXSRC_SRC_BR = 0x02, // 1 0 - WR11_TRXSRC_SRC_DPLL = 0x03, // 1 1 - }; - - enum - { - WR14_DPLL_CMD_MASK = 0xe0, // Command - WR14_CMD_NULL = 0x00, // 0 0 0 - WR14_CMD_ESM = 0x20, // 0 0 1 - WR14_CMD_RMC = 0x40, // 0 1 0 - WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1 - WR14_CMD_SS_BGR = 0x80, // 1 0 0 - WR14_CMD_SS_RTXC = 0xa0, // 1 0 1 - WR14_CMD_SET_FM = 0xc0, // 1 1 0 - WR14_CMD_SET_NRZI = 0xe0 // 1 1 1 - }; + /* SCC specifics */ + enum + { + WR9_CMD_MASK = 0xC0, + WR9_CMD_NORESET = 0x00, + WR9_CMD_CHNB_RESET = 0x40, + WR9_CMD_CHNA_RESET = 0x80, + WR9_CMD_HW_RESET = 0xC0, + WR9_BIT_VIS = 0x01, + WR9_BIT_NV = 0x02, + WR9_BIT_DLC = 0x04, + WR9_BIT_MIE = 0x08, + WR9_BIT_SHSL = 0x10, + WR9_BIT_IACK = 0x20 + }; + + enum + { + WR11_RCVCLK_TYPE = 0x80, + WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK + WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0 + WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1 + WR11_RCVCLK_SRC_BR = 0x40, // 1 0 + WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1 + WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK + WR11_TRACLK_SRC_RTXC = 0x00, // 0 0 + WR11_TRACLK_SRC_TRXC = 0x08, // 0 1 + WR11_TRACLK_SRC_BR = 0x10, // 1 0 + WR11_TRACLK_SRC_DPLL = 0x18, // 1 1 + WR11_TRXC_DIRECTION = 0x04, + WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK + WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0 + WR11_TRXSRC_SRC_TRA = 0x01, // 0 1 + WR11_TRXSRC_SRC_BR = 0x02, // 1 0 + WR11_TRXSRC_SRC_DPLL = 0x03, // 1 1 + }; + + enum + { + WR14_DPLL_CMD_MASK = 0xe0, // Command + WR14_CMD_NULL = 0x00, // 0 0 0 + WR14_CMD_ESM = 0x20, // 0 0 1 + WR14_CMD_RMC = 0x40, // 0 1 0 + WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1 + WR14_CMD_SS_BGR = 0x80, // 1 0 0 + WR14_CMD_SS_RTXC = 0xa0, // 1 0 1 + WR14_CMD_SET_FM = 0xc0, // 1 1 0 + WR14_CMD_SET_NRZI = 0xe0 // 1 1 1 + }; void update_serial(); void set_dtr(int state); void set_rts(int state); int get_clock_mode(); - void update_rts(); + void update_rts(); stop_bits_t get_stop_bits(); int get_rx_word_length(); int get_tx_word_length(); @@ -482,7 +482,7 @@ protected: UINT8 m_rx_error_fifo[8]; // receive error FIFO UINT8 m_rx_error; // current receive error //int m_rx_fifo // receive FIFO pointer - int m_rx_fifo_rp; // receive FIFO read pointer + int m_rx_fifo_rp; // receive FIFO read pointer int m_rx_fifo_wp; // receive FIFO write pointer int m_rx_fifo_sz; // receive FIFO size @@ -506,19 +506,19 @@ protected: // synchronous state UINT16 m_sync; // sync character - // int m_index; + // int m_index; z80scc_device *m_uart; // SCC specifics int m_ph; // Point high command to access regs 08-0f - UINT8 m_zc; + UINT8 m_zc; }; // ======================> z80scc_device class z80scc_device : public device_t - ,public device_z80daisy_interface + ,public device_z80daisy_interface { friend class z80scc_channel; @@ -604,7 +604,7 @@ protected: void trigger_interrupt(int index, int state); int get_channel_index(z80scc_channel *ch) { return (ch == m_chanA) ? 0 : 1; } - // Variants in the SCC family + // Variants in the SCC family enum { TYPE_Z80SCC = 0x001, @@ -615,7 +615,7 @@ protected: TYPE_SCC85C30 = 0x020, TYPE_SCC85230 = 0x040, TYPE_SCC85233 = 0x080, - TYPE_SCC8523L = 0x100 + TYPE_SCC8523L = 0x100 }; #define SET_NMOS ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC8530 ) @@ -624,7 +624,7 @@ protected: #define SET_EMSCC z80scc_device::TYPE_SCC85233 #define SET_Z80X30 ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC80230 ) #define SET_Z85X3X ( z80scc_device::TYPE_SCC8530 | z80scc_device::TYPE_SCC85C30 | z80scc_device::TYPE_SCC85230 \ - | z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 ) + | z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 ) enum { diff --git a/src/devices/machine/z80sio.c b/src/devices/machine/z80sio.c index 25c779ab40a..41e841a3ea6 100644 --- a/src/devices/machine/z80sio.c +++ b/src/devices/machine/z80sio.c @@ -5,13 +5,13 @@ Z80-SIO Serial Input/Output emulation The variants in the SIO family are only different in the packaging - but has the same register features. However, since some signals are + but has the same register features. However, since some signals are not connected to the pins on the package or share a pin with another signal the functionality is limited. However, this driver does not check that an operation is invalid because of package type but relies on the software to be adapated for the particular version. - Package: DIP40 SIO/0, SIO/1, SIO/2, + Package: DIP40 SIO/0, SIO/1, SIO/2, QFP44 SIO/3 PLCC44 SIO/4 ------------------------------------------------------------------- @@ -21,25 +21,25 @@ 6MHz 1200Kbps 10MHz 2500Kbps -- Asynchrounous features ------------------------------------------- - 5-8 bit per char Y - 1,1.5,2 stop bits Y - odd/even parity Y - x1,x16,x32,x64 Y - break det/gen Y - parity, framing & Y - overrun error det Y + 5-8 bit per char Y + 1,1.5,2 stop bits Y + odd/even parity Y + x1,x16,x32,x64 Y + break det/gen Y + parity, framing & Y + overrun error det Y -- Byte oriented synchrounous features ------------------------------- - Int/ext char sync Y - 1/2 synch chars Y - Aut synch char insertion Y - Aut CRC gen/det Y + Int/ext char sync Y + 1/2 synch chars Y + Aut synch char insertion Y + Aut CRC gen/det Y -- SDLC/HDLC capabilities -------------------------------------------- - Abort seq gen/chk Y - Aut zero ins/det Y - Aut flag insert Y - Addr field rec Y - 1-fld resid hand Y - Valid rec msg protection Y + Abort seq gen/chk Y + Aut zero ins/det Y + Aut flag insert Y + Addr field rec Y + 1-fld resid hand Y + Valid rec msg protection Y -- Receiver FIFO 3 Transmitter FIFO 1 @@ -135,29 +135,29 @@ z80sio_device::z80sio_device(const machine_config &mconfig, device_type type, co z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, Z80SIO, "Z80 SIO", tag, owner, clock, "z80sio", __FILE__), - device_z80daisy_interface(mconfig, *this), - m_chanA(*this, CHANA_TAG), - m_chanB(*this, CHANB_TAG), - m_rxca(0), - m_txca(0), - m_rxcb(0), - m_txcb(0), - m_out_txda_cb(*this), - m_out_dtra_cb(*this), - m_out_rtsa_cb(*this), - m_out_wrdya_cb(*this), - m_out_synca_cb(*this), - m_out_txdb_cb(*this), - m_out_dtrb_cb(*this), - m_out_rtsb_cb(*this), - m_out_wrdyb_cb(*this), - m_out_syncb_cb(*this), - m_out_int_cb(*this), - m_out_rxdrqa_cb(*this), - m_out_txdrqa_cb(*this), - m_out_rxdrqb_cb(*this), - m_out_txdrqb_cb(*this), - m_variant(TYPE_Z80SIO) + device_z80daisy_interface(mconfig, *this), + m_chanA(*this, CHANA_TAG), + m_chanB(*this, CHANB_TAG), + m_rxca(0), + m_txca(0), + m_rxcb(0), + m_txcb(0), + m_out_txda_cb(*this), + m_out_dtra_cb(*this), + m_out_rtsa_cb(*this), + m_out_wrdya_cb(*this), + m_out_synca_cb(*this), + m_out_txdb_cb(*this), + m_out_dtrb_cb(*this), + m_out_rtsb_cb(*this), + m_out_wrdyb_cb(*this), + m_out_syncb_cb(*this), + m_out_int_cb(*this), + m_out_rxdrqa_cb(*this), + m_out_txdrqa_cb(*this), + m_out_rxdrqb_cb(*this), + m_out_txdrqb_cb(*this), + m_variant(TYPE_Z80SIO) { for (int i = 0; i < 8; i++) m_int_state[i] = 0; @@ -169,7 +169,7 @@ z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, dev void z80sio_device::device_start() { - LOG(("%s\n", FUNCNAME)); + LOG(("%s\n", FUNCNAME)); // resolve callbacks m_out_txda_cb.resolve_safe(); m_out_dtra_cb.resolve_safe(); @@ -222,8 +222,8 @@ int z80sio_device::z80daisy_irq_state() int i; LOG(("Z80SIO \"%s\" : Interrupt State A:%d%d%d%d B:%d%d%d%d\n", tag(), - m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], - m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); + m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], + m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); // loop over all interrupt sources for (i = 0; i < 8; i++) @@ -386,7 +386,7 @@ void z80sio_device::trigger_interrupt(int index, int state) // status affects vector vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (state << 1); } -// } +// } LOG(("Z80SIO \"%s\" Channel %c : Interrupt Request %u\n", tag(), 'A' + index, state)); @@ -422,7 +422,7 @@ READ8_MEMBER( z80sio_device::cd_ba_r ) int cd = BIT(offset, 1); z80sio_channel *channel = ba ? m_chanB : m_chanA; - // LOG(("z80sio_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); + // LOG(("z80sio_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); return cd ? channel->control_read() : channel->data_read(); } @@ -438,7 +438,7 @@ WRITE8_MEMBER( z80sio_device::cd_ba_w ) int cd = BIT(offset, 1); z80sio_channel *channel = ba ? m_chanB : m_chanA; - LOG(("z80sio_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); + LOG(("z80sio_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); if (cd) channel->control_write(data); @@ -457,7 +457,7 @@ READ8_MEMBER( z80sio_device::ba_cd_r ) int cd = BIT(offset, 0); z80sio_channel *channel = ba ? m_chanB : m_chanA; - // LOG(("z80sio_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); + // LOG(("z80sio_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); return cd ? channel->control_read() : channel->data_read(); } @@ -473,7 +473,7 @@ WRITE8_MEMBER( z80sio_device::ba_cd_w ) int cd = BIT(offset, 0); z80sio_channel *channel = ba ? m_chanB : m_chanA; - LOG(("z80sio_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd)); + LOG(("z80sio_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd)); if (cd) channel->control_write(data); @@ -508,9 +508,9 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d m_rts(0), m_sync(0) { - // Reset all registers - m_rr0 = m_rr1 = m_rr2 = 0; - m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0; + // Reset all registers + m_rr0 = m_rr1 = m_rr2 = 0; + m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0; for (int i = 0; i < 3; i++) { @@ -526,7 +526,7 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d void z80sio_channel::device_start() { - LOG(("%s\n",FUNCNAME)); + LOG(("%s\n",FUNCNAME)); m_uart = downcast<z80sio_device *>(owner()); m_index = m_uart->get_channel_index(this); @@ -568,7 +568,7 @@ void z80sio_channel::device_start() void z80sio_channel::device_reset() { - LOG(("%s\n", FUNCNAME)); + LOG(("%s\n", FUNCNAME)); receive_register_reset(); transmit_register_reset(); @@ -722,11 +722,11 @@ int z80sio_channel::get_clock_mode() } /* From "uPD7201/7201A MULTI PROTOCOL SERIAL COMMUNICATION CONTROLLER" by NEC: -"RTSA (Request to Send A): The state of the RTS bit (01 of the CR5 register) controls this pin. If -the RTS bit is reset in the asynchronous mode, a high level will not be output on the RTS pin until -all transmit characters are written and the all sent bit (D0 of the SR1 register) is set. In the -synchronous mode, the state of the RTS bit is used as is. That is, when the RTS bit is 0, the RTS -pin is 1. When the RTS bit is 1, the RTS pin is O." +"RTSA (Request to Send A): The state of the RTS bit (01 of the CR5 register) controls this pin. If +the RTS bit is reset in the asynchronous mode, a high level will not be output on the RTS pin until +all transmit characters are written and the all sent bit (D0 of the SR1 register) is set. In the +synchronous mode, the state of the RTS bit is used as is. That is, when the RTS bit is 0, the RTS +pin is 1. When the RTS bit is 1, the RTS pin is O." CR5 = m_wr5 and SR1 = m_rr1 @@ -742,20 +742,20 @@ void z80sio_channel::set_rts(int state) void z80sio_channel::update_rts() { - if (m_wr5 & WR5_RTS) - { - // when the RTS bit is set, the _RTS output goes low - set_rts(0); - m_rts = 1; - } - else - { - // when the RTS bit is reset, the _RTS output goes high after the transmitter empties - m_rts = 0; - } - - // data terminal ready output follows the state programmed into the DTR bit*/ - set_dtr((m_wr5 & WR5_DTR) ? 0 : 1); + if (m_wr5 & WR5_RTS) + { + // when the RTS bit is set, the _RTS output goes low + set_rts(0); + m_rts = 1; + } + else + { + // when the RTS bit is reset, the _RTS output goes high after the transmitter empties + m_rts = 0; + } + + // data terminal ready output follows the state programmed into the DTR bit*/ + set_dtr((m_wr5 & WR5_DTR) ? 0 : 1); } //------------------------------------------------- @@ -820,14 +820,14 @@ int z80sio_channel::get_tx_word_length() * Break/Abort latch. */ UINT8 z80sio_channel::do_sioreg_rr0() { - return m_rr0; + return m_rr0; } /* * This register contains the Special Receive condition status bits and Residue * codes for the I-Field in the SDLC Receive Mode. */ UINT8 z80sio_channel::do_sioreg_rr1() { - return m_rr1; + return m_rr1; } /* * This register contains the interrupt vector written into WR2 if the Status @@ -839,8 +839,8 @@ no interrupts are pending, the vector is modified with V3 = 0, V2 = 1, and V1 = 1. This register is read only through Channel B. */ UINT8 z80sio_channel::do_sioreg_rr2() { - // channel B only - return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0; + // channel B only + return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0; } @@ -851,7 +851,7 @@ UINT8 z80sio_channel::do_sioreg_rr2() UINT8 z80sio_channel::control_read() { UINT8 data = 0; - UINT8 reg = m_wr0 & WR0_REGISTER_MASK; + UINT8 reg = m_wr0 & WR0_REGISTER_MASK; if (reg != 0) { @@ -865,7 +865,7 @@ UINT8 z80sio_channel::control_read() case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break; case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break; default: - logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); + logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); } //LOG(("Z80SIO \"%s\" Channel %c : Register R%d read '%02x'\n", m_owner->tag(), 'A' + m_index, reg, data)); @@ -876,158 +876,158 @@ UINT8 z80sio_channel::control_read() Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */ void z80sio_channel::do_sioreg_wr0_resets(UINT8 data) { - switch (data & WR0_CRC_RESET_CODE_MASK) - { - case WR0_CRC_RESET_NULL: - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index)); - break; - case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */ - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index)); - break; - case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */ - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index)); - break; - case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the SRO register) */ - LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index)); - break; - default: /* Will not happen unless someone messes with the mask */ - logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK); - } + switch (data & WR0_CRC_RESET_CODE_MASK) + { + case WR0_CRC_RESET_NULL: + LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index)); + break; + case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */ + LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index)); + break; + case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */ + LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index)); + break; + case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the SRO register) */ + LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index)); + break; + default: /* Will not happen unless someone messes with the mask */ + logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK); + } } void z80sio_channel::do_sioreg_wr0(UINT8 data) { - m_wr0 = data; - switch (data & WR0_COMMAND_MASK) + m_wr0 = data; + switch (data & WR0_COMMAND_MASK) { - case WR0_NULL: - LOG(("Z80SIO \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index)); - break; - case WR0_RESET_EXT_STATUS: - // reset external/status interrupt - m_rr0 &= ~(RR0_DCD | RR0_SYNC_HUNT | RR0_CTS | RR0_BREAK_ABORT); - // release the latch - m_rx_rr0_latch = 0; - // update register to reflect wire values TODO: Check if this will fire new interrupts - if (!m_dcd) m_rr0 |= RR0_DCD; - if (m_sync) m_rr0 |= RR0_SYNC_HUNT; - if (m_cts) m_rr0 |= RR0_CTS; - - LOG(("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index)); - break; - case WR0_CHANNEL_RESET: - // channel reset - LOG(("Z80SIO \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index)); - device_reset(); - break; - case WR0_ENABLE_INT_NEXT_RX: - // enable interrupt on next receive character - LOG(("Z80SIO \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index)); - m_rx_first = 1; - break; - case WR0_RESET_TX_INT: - // reset transmitter interrupt pending - LOG(("Z80SIO \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index)); - logerror("Z80SIO \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index); - break; - case WR0_ERROR_RESET: - // error reset - LOG(("Z80SIO \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index)); - m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR); - break; - case WR0_RETURN_FROM_INT: - // return from interrupt - LOG(("Z80SIO \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index)); - m_uart->z80daisy_irq_reti(); - break; - default: - LOG(("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK)); - - } - do_sioreg_wr0_resets(data); + case WR0_NULL: + LOG(("Z80SIO \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index)); + break; + case WR0_RESET_EXT_STATUS: + // reset external/status interrupt + m_rr0 &= ~(RR0_DCD | RR0_SYNC_HUNT | RR0_CTS | RR0_BREAK_ABORT); + // release the latch + m_rx_rr0_latch = 0; + // update register to reflect wire values TODO: Check if this will fire new interrupts + if (!m_dcd) m_rr0 |= RR0_DCD; + if (m_sync) m_rr0 |= RR0_SYNC_HUNT; + if (m_cts) m_rr0 |= RR0_CTS; + + LOG(("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index)); + break; + case WR0_CHANNEL_RESET: + // channel reset + LOG(("Z80SIO \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index)); + device_reset(); + break; + case WR0_ENABLE_INT_NEXT_RX: + // enable interrupt on next receive character + LOG(("Z80SIO \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index)); + m_rx_first = 1; + break; + case WR0_RESET_TX_INT: + // reset transmitter interrupt pending + LOG(("Z80SIO \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index)); + logerror("Z80SIO \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index); + break; + case WR0_ERROR_RESET: + // error reset + LOG(("Z80SIO \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index)); + m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR); + break; + case WR0_RETURN_FROM_INT: + // return from interrupt + LOG(("Z80SIO \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index)); + m_uart->z80daisy_irq_reti(); + break; + default: + LOG(("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK)); + + } + do_sioreg_wr0_resets(data); } void z80sio_channel::do_sioreg_wr1(UINT8 data) { /* TODO: implement vector modifications when WR1 bit D2 is changed */ - m_wr1 = data; - LOG(("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait")); - LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit")); - - switch (data & WR1_RX_INT_MODE_MASK) - { - case WR1_RX_INT_DISABLE: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index)); - break; - - case WR1_RX_INT_FIRST: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index)); - break; - - case WR1_RX_INT_ALL_PARITY: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index)); - break; - - case WR1_RX_INT_ALL: - LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index)); - break; - } + m_wr1 = data; + LOG(("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait")); + LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit")); + + switch (data & WR1_RX_INT_MODE_MASK) + { + case WR1_RX_INT_DISABLE: + LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index)); + break; + + case WR1_RX_INT_FIRST: + LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index)); + break; + + case WR1_RX_INT_ALL_PARITY: + LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index)); + break; + + case WR1_RX_INT_ALL: + LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index)); + break; + } } void z80sio_channel::do_sioreg_wr2(UINT8 data) { - m_wr2 = data; - if (m_index == z80sio_device::CHANNEL_B) - { - if (m_wr1 & z80sio_channel::WR1_STATUS_VECTOR) - m_rr2 = ( m_rr2 & 0x0e ) | ( m_wr2 & 0xF1); - else - m_rr2 = m_wr2; - } - m_uart->check_interrupts(); - LOG(("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data)); + m_wr2 = data; + if (m_index == z80sio_device::CHANNEL_B) + { + if (m_wr1 & z80sio_channel::WR1_STATUS_VECTOR) + m_rr2 = ( m_rr2 & 0x0e ) | ( m_wr2 & 0xF1); + else + m_rr2 = m_wr2; + } + m_uart->check_interrupts(); + LOG(("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data)); } void z80sio_channel::do_sioreg_wr3(UINT8 data) { - m_wr3 = data; - LOG(("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length())); + m_wr3 = data; + LOG(("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length())); } void z80sio_channel::do_sioreg_wr4(UINT8 data) { - m_wr4 = data; - LOG(("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd")); - LOG(("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()))); - LOG(("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode())); + m_wr4 = data; + LOG(("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd")); + LOG(("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits()))); + LOG(("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode())); } void z80sio_channel::do_sioreg_wr5(UINT8 data) { - m_wr5 = data; - LOG(("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length())); - LOG(("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0)); - LOG(("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0)); + m_wr5 = data; + LOG(("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length())); + LOG(("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0)); + LOG(("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0)); } void z80sio_channel::do_sioreg_wr6(UINT8 data) { - LOG(("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data)); - m_sync = (m_sync & 0xff00) | data; + LOG(("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data)); + m_sync = (m_sync & 0xff00) | data; } void z80sio_channel::do_sioreg_wr7(UINT8 data) { - LOG(("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data)); - m_sync = (data << 8) | (m_sync & 0xff); + LOG(("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data)); + m_sync = (data << 8) | (m_sync & 0xff); } //------------------------------------------------- @@ -1036,7 +1036,7 @@ void z80sio_channel::do_sioreg_wr7(UINT8 data) void z80sio_channel::control_write(UINT8 data) { - UINT8 reg = m_wr0 & WR0_REGISTER_MASK; + UINT8 reg = m_wr0 & WR0_REGISTER_MASK; if (reg != 0) { @@ -1057,7 +1057,7 @@ void z80sio_channel::control_write(UINT8 data) case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break; case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break; default: - logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); + logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); } } @@ -1142,9 +1142,9 @@ void z80sio_channel::receive_data(UINT8 data) { case WR1_RX_INT_FIRST: if (!m_rx_first) - { - m_uart->trigger_interrupt(m_index, INT_SPECIAL); - } + { + m_uart->trigger_interrupt(m_index, INT_SPECIAL); + } break; case WR1_RX_INT_ALL_PARITY: @@ -1347,7 +1347,7 @@ void z80sio_channel::update_serial() stop_bits_t stop_bits = get_stop_bits(); parity_t parity; - LOG(("Z80SIO update_serial\n")); + LOG(("Z80SIO update_serial\n")); if (m_wr4 & WR4_PARITY_ENABLE) { diff --git a/src/devices/machine/z80sio.h b/src/devices/machine/z80sio.h index fa3471e8adb..d378544425c 100644 --- a/src/devices/machine/z80sio.h +++ b/src/devices/machine/z80sio.h @@ -10,44 +10,44 @@ D3 2| |39 D2 : |39 D2 : |39 D2 D5 3| |38 D4 : |38 D4 : |38 D4 D7 4| |37 D6 : |37 D6 : |37 D6 - _INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ - IEO 6| |35 _CE : |35 _CE : |35 _CE + _INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ + IEO 6| |35 _CE : |35 _CE : |35 _CE IEI 7| |34 B/_A : |34 B/_A : |34 B/_A _M1 8| |33 C/_D : |33 C/_D : |33 C/_D - VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD - _W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND + VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD + _W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND _SYNCA 11| SIO/0 |30 _W/_RDYB: SIO/1 |30 _W/_RDYB: SIO/2 |30 _W/_RDYB RxDA 12| |29 _SYNCB : |29 _SYNCB : |29 _SYNCB - _RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB - _TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB + _RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB + _TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB TxDA 15| |26 TxDB : |26 _TxCB : |26 TxDB - _DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB - _RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB - _CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB - _DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB + _DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB + _RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB + _CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB + _DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB CLK 20|_____________|21 _RESET :_______|21 _RESET :_______|21 _RESET *I *I - *I N O *I O - N D D D D / D D D D R N D D D D D D D D R*C - T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E - +----------------------+ +----------------------+ + *I N O *I O + N D D D D / D D D D R N D D D D D D D D R*C + T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E + +----------------------+ +----------------------+ IEI|34 22| *CE IEI|6 5 4 3 2 1 44 42 40|B/ *A - IEO|35 21| B/ *A IEO|8 43 41 |C/ *D + IEO|35 21| B/ *A IEO|8 43 41 |C/ *D *M1| | C/ *D *M1|9 37|*RD - +5v| | *RD +5V|10 36|GND + +5v| | *RD +5V|10 36|GND *W/ *RDYA| QFP44 | GND *W/ *RDYA|11 PLCC44 35|*W/ *RDYB - N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB - *SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB + N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB + *SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB RxDA| | *SYNCB *RxCA|14 32|*RxCB *RxCA|42 | RxDB *TxCA|15 31|*TxCB *TxCA|43 1 1 | *RxCB TxDA| 19 21 23 25 30|TxDB - TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C - `--------------------+ +----------------------+ - *D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N - T T T C L E C*T T T x T T T C L E C T T T / + TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C + `--------------------+ +----------------------+ + *D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N + T T T C L E C*T T T x T T T C L E C T T T / R S S D K S D S S R D R S S D K S D S S R C - A A A A E B B B B B A A A A E B B B B + A A A A E B B B B B A A A A E B B B B T T ***************************************************************************/ @@ -124,7 +124,7 @@ class z80sio_device; class z80sio_channel : public device_t, - public device_serial_interface + public device_serial_interface { friend class z80sio_device; @@ -142,21 +142,21 @@ public: virtual void rcv_callback(); virtual void rcv_complete(); - // read register handlers - UINT8 do_sioreg_rr0(); - UINT8 do_sioreg_rr1(); - UINT8 do_sioreg_rr2(); - - // write register handlers - void do_sioreg_wr0(UINT8 data); - void do_sioreg_wr0_resets(UINT8 data); - void do_sioreg_wr1(UINT8 data); - void do_sioreg_wr2(UINT8 data); - void do_sioreg_wr3(UINT8 data); - void do_sioreg_wr4(UINT8 data); - void do_sioreg_wr5(UINT8 data); - void do_sioreg_wr6(UINT8 data); - void do_sioreg_wr7(UINT8 data); + // read register handlers + UINT8 do_sioreg_rr0(); + UINT8 do_sioreg_rr1(); + UINT8 do_sioreg_rr2(); + + // write register handlers + void do_sioreg_wr0(UINT8 data); + void do_sioreg_wr0_resets(UINT8 data); + void do_sioreg_wr1(UINT8 data); + void do_sioreg_wr2(UINT8 data); + void do_sioreg_wr3(UINT8 data); + void do_sioreg_wr4(UINT8 data); + void do_sioreg_wr5(UINT8 data); + void do_sioreg_wr6(UINT8 data); + void do_sioreg_wr7(UINT8 data); UINT8 control_read(); void control_write(UINT8 data); @@ -178,19 +178,19 @@ public: int m_txc; // Register state - // read registers enum - UINT8 m_rr0; // REG_RR0_STATUS + // read registers enum + UINT8 m_rr0; // REG_RR0_STATUS UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT - // write registers enum + // write registers enum UINT8 m_wr0; // REG_WR0_COMMAND_REGPT - UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE - UINT8 m_wr2; // REG_WR2_INT_VECTOR - UINT8 m_wr3; // REG_WR3_RX_CONTROL + UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE + UINT8 m_wr2; // REG_WR2_INT_VECTOR + UINT8 m_wr3; // REG_WR3_RX_CONTROL UINT8 m_wr4; // REG_WR4_RX_TX_MODES UINT8 m_wr5; // REG_WR5_TX_CONTROL - UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A - UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F + UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A + UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F int m_variant; // Set in device @@ -203,26 +203,26 @@ protected: INT_SPECIAL }; - // Read registers - enum - { - REG_RR0_STATUS = 0, - REG_RR1_SPEC_RCV_COND = 1, - REG_RR2_INTERRUPT_VECT = 2, - }; - - // Write registers - enum - { - REG_WR0_COMMAND_REGPT = 0, - REG_WR1_INT_DMA_ENABLE = 1, - REG_WR2_INT_VECTOR = 2, - REG_WR3_RX_CONTROL = 3, - REG_WR4_RX_TX_MODES = 4, - REG_WR5_TX_CONTROL = 5, - REG_WR6_SYNC_OR_SDLC_A = 6, - REG_WR7_SYNC_OR_SDLC_F = 7, - }; + // Read registers + enum + { + REG_RR0_STATUS = 0, + REG_RR1_SPEC_RCV_COND = 1, + REG_RR2_INTERRUPT_VECT = 2, + }; + + // Write registers + enum + { + REG_WR0_COMMAND_REGPT = 0, + REG_WR1_INT_DMA_ENABLE = 1, + REG_WR2_INT_VECTOR = 2, + REG_WR3_RX_CONTROL = 3, + REG_WR4_RX_TX_MODES = 4, + REG_WR5_TX_CONTROL = 5, + REG_WR6_SYNC_OR_SDLC_A = 6, + REG_WR7_SYNC_OR_SDLC_F = 7, + }; enum { @@ -233,7 +233,7 @@ protected: RR0_SYNC_HUNT = 0x10, RR0_CTS = 0x20, RR0_TX_UNDERRUN = 0x40, - RR0_BREAK_ABORT = 0x80 + RR0_BREAK_ABORT = 0x80 }; enum @@ -243,16 +243,16 @@ protected: RR1_PARITY_ERROR = 0x10, RR1_RX_OVERRUN_ERROR = 0x20, RR1_CRC_FRAMING_ERROR = 0x40, - RR1_END_OF_FRAME = 0x80 + RR1_END_OF_FRAME = 0x80 }; - enum - { // TODO: overload SIO functionality - RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) - RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B - }; + enum + { // TODO: overload SIO functionality + RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) + RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B + }; enum { @@ -356,7 +356,7 @@ protected: }; void update_serial(); - void update_rts(); + void update_rts(); void set_dtr(int state); void set_rts(int state); @@ -399,7 +399,7 @@ protected: // ======================> z80sio_device class z80sio_device : public device_t, - public device_z80daisy_interface + public device_z80daisy_interface { friend class z80sio_channel; diff --git a/src/devices/sound/315-5641.c b/src/devices/sound/315-5641.c index a0de2fce330..9a14be61469 100644 --- a/src/devices/sound/315-5641.c +++ b/src/devices/sound/315-5641.c @@ -67,4 +67,4 @@ void sega_315_5641_pcm_device::device_reset() m_fifo_write = 0x00; upd775x_device::device_reset(); -}
\ No newline at end of file +} diff --git a/src/devices/sound/315-5641.h b/src/devices/sound/315-5641.h index c8fb0f6270f..108db11800c 100644 --- a/src/devices/sound/315-5641.h +++ b/src/devices/sound/315-5641.h @@ -16,9 +16,9 @@ public: DECLARE_WRITE8_MEMBER(port_w); UINT8 m_fifo_data[0x40]; - UINT8 m_fifo_read; // last read offset (will read in m_fifo_read+1) - UINT8 m_fifo_write; // write offset - + UINT8 m_fifo_read; // last read offset (will read in m_fifo_read+1) + UINT8 m_fifo_write; // write offset + protected: // device-level overrides virtual void device_start(); @@ -27,4 +27,4 @@ protected: }; -extern const device_type SEGA_315_5641_PCM;
\ No newline at end of file +extern const device_type SEGA_315_5641_PCM; diff --git a/src/devices/sound/c352.c b/src/devices/sound/c352.c index 98f8f3a9fed..e0bc39918b8 100644 --- a/src/devices/sound/c352.c +++ b/src/devices/sound/c352.c @@ -13,10 +13,10 @@ Supports 8-bit linear and 8-bit muLaw samples Output: digital, 16 bit, 4 channels Output sample rate is the input clock / (288 * 2). - + superctr: The clock divider appears to be configurable for each system. Below is a list of the divider values followed by the systems that use it. - + * 228: System 11. * 288: System 22, Super 22, NB-1/2, ND-1, FL. * 296: System 23, Super 23. diff --git a/src/devices/sound/sn76496.c b/src/devices/sound/sn76496.c index 7909d65a3e9..2f65392174d 100644 --- a/src/devices/sound/sn76496.c +++ b/src/devices/sound/sn76496.c @@ -109,7 +109,7 @@ 27/06/2012: Michael Zapf Converted to modern device, legacy devices were gradually removed afterwards. - + 16/09/2015: Lord Nightmare Fix PSG chips to have volume reg inited on reset to 0x0 based on tests by ValleyBell. Made Sega PSG chips start up with register 0x3 selected (volume diff --git a/src/devices/sound/tms5110.c b/src/devices/sound/tms5110.c index 2b09037ab51..17c52f2146c 100644 --- a/src/devices/sound/tms5110.c +++ b/src/devices/sound/tms5110.c @@ -525,9 +525,9 @@ void tms5110_device::process(INT16 *buffer, unsigned int size) fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]); fprintf(stderr,"Out:%06d ", this_sample); //#ifdef PERFECT_INTERPOLATION_HACK -// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar); +// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar); //#else -// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar); +// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar); //#endif fprintf(stderr,"\n"); #endif diff --git a/src/devices/sound/tms5110r.inc b/src/devices/sound/tms5110r.inc index c2ae6907df3..45fe4c984b2 100644 --- a/src/devices/sound/tms5110r.inc +++ b/src/devices/sound/tms5110r.inc @@ -568,7 +568,7 @@ NOTE FROM DECAP: immediately to the left of each of the K1,2,3,4,5,and 6 patent 4,335,277. They are likely related to the multiplicative interpolator described in us patent 4,419,540; whether the 5200/2501E and the 5220 or 5220C actually implement this interpolator or not is unclear. This interpolator - seems intended for chips with variable frame rate, so if it exists at all, + seems intended for chips with variable frame rate, so if it exists at all, it may only exist on the TMS/TSP5220C and CD2501ECD. */ diff --git a/src/devices/sound/tms5220.c b/src/devices/sound/tms5220.c index cf7a6120c6c..feb3a8e01fe 100644 --- a/src/devices/sound/tms5220.c +++ b/src/devices/sound/tms5220.c @@ -919,9 +919,9 @@ void tms5220_device::process(INT16 *buffer, unsigned int size) fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]); fprintf(stderr,"Out:%06d ", this_sample); //#ifdef PERFECT_INTERPOLATION_HACK -// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar); +// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar); //#else -// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar); +// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar); //#endif fprintf(stderr,"\n"); #endif |
