summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/machine/z80sio.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/machine/z80sio.h')
-rw-r--r--src/devices/machine/z80sio.h156
1 files changed, 78 insertions, 78 deletions
diff --git a/src/devices/machine/z80sio.h b/src/devices/machine/z80sio.h
index fa3471e8adb..d378544425c 100644
--- a/src/devices/machine/z80sio.h
+++ b/src/devices/machine/z80sio.h
@@ -10,44 +10,44 @@
D3 2| |39 D2 : |39 D2 : |39 D2
D5 3| |38 D4 : |38 D4 : |38 D4
D7 4| |37 D6 : |37 D6 : |37 D6
- _INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ
- IEO 6| |35 _CE : |35 _CE : |35 _CE
+ _INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ
+ IEO 6| |35 _CE : |35 _CE : |35 _CE
IEI 7| |34 B/_A : |34 B/_A : |34 B/_A
_M1 8| |33 C/_D : |33 C/_D : |33 C/_D
- VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD
- _W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND
+ VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD
+ _W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND
_SYNCA 11| SIO/0 |30 _W/_RDYB: SIO/1 |30 _W/_RDYB: SIO/2 |30 _W/_RDYB
RxDA 12| |29 _SYNCB : |29 _SYNCB : |29 _SYNCB
- _RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB
- _TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB
+ _RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB
+ _TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB
TxDA 15| |26 TxDB : |26 _TxCB : |26 TxDB
- _DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB
- _RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB
- _CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB
- _DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB
+ _DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB
+ _RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB
+ _CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB
+ _DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB
CLK 20|_____________|21 _RESET :_______|21 _RESET :_______|21 _RESET
*I *I
- *I N O *I O
- N D D D D / D D D D R N D D D D D D D D R*C
- T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E
- +----------------------+ +----------------------+
+ *I N O *I O
+ N D D D D / D D D D R N D D D D D D D D R*C
+ T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E
+ +----------------------+ +----------------------+
IEI|34 22| *CE IEI|6 5 4 3 2 1 44 42 40|B/ *A
- IEO|35 21| B/ *A IEO|8 43 41 |C/ *D
+ IEO|35 21| B/ *A IEO|8 43 41 |C/ *D
*M1| | C/ *D *M1|9 37|*RD
- +5v| | *RD +5V|10 36|GND
+ +5v| | *RD +5V|10 36|GND
*W/ *RDYA| QFP44 | GND *W/ *RDYA|11 PLCC44 35|*W/ *RDYB
- N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB
- *SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB
+ N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB
+ *SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB
RxDA| | *SYNCB *RxCA|14 32|*RxCB
*RxCA|42 | RxDB *TxCA|15 31|*TxCB
*TxCA|43 1 1 | *RxCB TxDA| 19 21 23 25 30|TxDB
- TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C
- `--------------------+ +----------------------+
- *D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N
- T T T C L E C*T T T x T T T C L E C T T T /
+ TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C
+ `--------------------+ +----------------------+
+ *D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N
+ T T T C L E C*T T T x T T T C L E C T T T /
R S S D K S D S S R D R S S D K S D S S R C
- A A A A E B B B B B A A A A E B B B B
+ A A A A E B B B B B A A A A E B B B B
T T
***************************************************************************/
@@ -124,7 +124,7 @@
class z80sio_device;
class z80sio_channel : public device_t,
- public device_serial_interface
+ public device_serial_interface
{
friend class z80sio_device;
@@ -142,21 +142,21 @@ public:
virtual void rcv_callback();
virtual void rcv_complete();
- // read register handlers
- UINT8 do_sioreg_rr0();
- UINT8 do_sioreg_rr1();
- UINT8 do_sioreg_rr2();
-
- // write register handlers
- void do_sioreg_wr0(UINT8 data);
- void do_sioreg_wr0_resets(UINT8 data);
- void do_sioreg_wr1(UINT8 data);
- void do_sioreg_wr2(UINT8 data);
- void do_sioreg_wr3(UINT8 data);
- void do_sioreg_wr4(UINT8 data);
- void do_sioreg_wr5(UINT8 data);
- void do_sioreg_wr6(UINT8 data);
- void do_sioreg_wr7(UINT8 data);
+ // read register handlers
+ UINT8 do_sioreg_rr0();
+ UINT8 do_sioreg_rr1();
+ UINT8 do_sioreg_rr2();
+
+ // write register handlers
+ void do_sioreg_wr0(UINT8 data);
+ void do_sioreg_wr0_resets(UINT8 data);
+ void do_sioreg_wr1(UINT8 data);
+ void do_sioreg_wr2(UINT8 data);
+ void do_sioreg_wr3(UINT8 data);
+ void do_sioreg_wr4(UINT8 data);
+ void do_sioreg_wr5(UINT8 data);
+ void do_sioreg_wr6(UINT8 data);
+ void do_sioreg_wr7(UINT8 data);
UINT8 control_read();
void control_write(UINT8 data);
@@ -178,19 +178,19 @@ public:
int m_txc;
// Register state
- // read registers enum
- UINT8 m_rr0; // REG_RR0_STATUS
+ // read registers enum
+ UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
- // write registers enum
+ // write registers enum
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
- UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
- UINT8 m_wr2; // REG_WR2_INT_VECTOR
- UINT8 m_wr3; // REG_WR3_RX_CONTROL
+ UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
+ UINT8 m_wr2; // REG_WR2_INT_VECTOR
+ UINT8 m_wr3; // REG_WR3_RX_CONTROL
UINT8 m_wr4; // REG_WR4_RX_TX_MODES
UINT8 m_wr5; // REG_WR5_TX_CONTROL
- UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
- UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
+ UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
+ UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
int m_variant; // Set in device
@@ -203,26 +203,26 @@ protected:
INT_SPECIAL
};
- // Read registers
- enum
- {
- REG_RR0_STATUS = 0,
- REG_RR1_SPEC_RCV_COND = 1,
- REG_RR2_INTERRUPT_VECT = 2,
- };
-
- // Write registers
- enum
- {
- REG_WR0_COMMAND_REGPT = 0,
- REG_WR1_INT_DMA_ENABLE = 1,
- REG_WR2_INT_VECTOR = 2,
- REG_WR3_RX_CONTROL = 3,
- REG_WR4_RX_TX_MODES = 4,
- REG_WR5_TX_CONTROL = 5,
- REG_WR6_SYNC_OR_SDLC_A = 6,
- REG_WR7_SYNC_OR_SDLC_F = 7,
- };
+ // Read registers
+ enum
+ {
+ REG_RR0_STATUS = 0,
+ REG_RR1_SPEC_RCV_COND = 1,
+ REG_RR2_INTERRUPT_VECT = 2,
+ };
+
+ // Write registers
+ enum
+ {
+ REG_WR0_COMMAND_REGPT = 0,
+ REG_WR1_INT_DMA_ENABLE = 1,
+ REG_WR2_INT_VECTOR = 2,
+ REG_WR3_RX_CONTROL = 3,
+ REG_WR4_RX_TX_MODES = 4,
+ REG_WR5_TX_CONTROL = 5,
+ REG_WR6_SYNC_OR_SDLC_A = 6,
+ REG_WR7_SYNC_OR_SDLC_F = 7,
+ };
enum
{
@@ -233,7 +233,7 @@ protected:
RR0_SYNC_HUNT = 0x10,
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
- RR0_BREAK_ABORT = 0x80
+ RR0_BREAK_ABORT = 0x80
};
enum
@@ -243,16 +243,16 @@ protected:
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
- RR1_END_OF_FRAME = 0x80
+ RR1_END_OF_FRAME = 0x80
};
- enum
- { // TODO: overload SIO functionality
- RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
- RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
- RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
- RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
- };
+ enum
+ { // TODO: overload SIO functionality
+ RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
+ RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
+ RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
+ RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
+ };
enum
{
@@ -356,7 +356,7 @@ protected:
};
void update_serial();
- void update_rts();
+ void update_rts();
void set_dtr(int state);
void set_rts(int state);
@@ -399,7 +399,7 @@ protected:
// ======================> z80sio_device
class z80sio_device : public device_t,
- public device_z80daisy_interface
+ public device_z80daisy_interface
{
friend class z80sio_channel;