diff options
author | Miodrag Milanovic <mmicko@gmail.com> | 2016-05-25 08:19:21 +0200 |
---|---|---|
committer | Miodrag Milanovic <mmicko@gmail.com> | 2016-05-25 08:19:21 +0200 |
commit | 68785dccfee3208163c8169abc5c6d01becf36d4 (patch) | |
tree | d6967331fd0e938981777aa32b5f246e04fb701b /src/devices/machine | |
parent | c1230f8b9bf4373d396ecb970c966ec2ce6dfc15 (diff) |
Cleanups and version bumpmame0174
Diffstat (limited to 'src/devices/machine')
-rw-r--r-- | src/devices/machine/gen_latch.h | 2 | ||||
-rw-r--r-- | src/devices/machine/gt64xxx.cpp | 12 | ||||
-rw-r--r-- | src/devices/machine/gt64xxx.h | 2 | ||||
-rw-r--r-- | src/devices/machine/pci-ide.h | 2 | ||||
-rw-r--r-- | src/devices/machine/stvcd.h | 1 | ||||
-rw-r--r-- | src/devices/machine/vrc4373.h | 2 | ||||
-rw-r--r-- | src/devices/machine/z80scc.cpp | 34 | ||||
-rw-r--r-- | src/devices/machine/z80scc.h | 384 |
8 files changed, 219 insertions, 220 deletions
diff --git a/src/devices/machine/gen_latch.h b/src/devices/machine/gen_latch.h index 8696353fff4..07938a7b5d9 100644 --- a/src/devices/machine/gen_latch.h +++ b/src/devices/machine/gen_latch.h @@ -40,7 +40,7 @@ public: DECLARE_WRITE8_MEMBER( clear_w ); DECLARE_WRITE_LINE_MEMBER( preset_w ); DECLARE_WRITE_LINE_MEMBER( clear_w ); - + void preset_w(UINT16 value) { m_latched_value = value; } protected: diff --git a/src/devices/machine/gt64xxx.cpp b/src/devices/machine/gt64xxx.cpp index a92326f3c4a..263024010c8 100644 --- a/src/devices/machine/gt64xxx.cpp +++ b/src/devices/machine/gt64xxx.cpp @@ -241,7 +241,7 @@ void gt64xxx_device::map_cpu_space() dma_addr_map[index].low_addr = (m_reg[GREG_PCI_MEM1_LO] << 21); dma_addr_map[index].high_addr = (dma_addr_map[index].low_addr & 0xf0000000) | (m_reg[GREG_PCI_MEM1_HI] << 21) | 0x1fffff; } - + switch (index) { case proc_addr_bank::ADDR_PCI_IO: dma_addr_map[index].space = &this->space(AS_IO); @@ -262,7 +262,7 @@ void gt64xxx_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_ { int ramIndex; UINT32 winStart, winEnd, winSize; - + // Not sure if GREG_RAS_1_0_LO should be added on PCI address map side. // RAS0 ramIndex = 0; @@ -273,7 +273,7 @@ void gt64xxx_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_ memory_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(gt64xxx_device::ras_0_w), this)); if (LOG_GALILEO) logerror("%s: map_extra RAS0 start=%08X end=%08X size=%08X\n", tag(), winStart, winEnd, winSize); - + // RAS1 ramIndex = 1; winStart = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex / 2)] << 21) | (m_reg[GREG_RAS0_LO + 0x8 / 4 * ramIndex] << 20); @@ -283,7 +283,7 @@ void gt64xxx_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_ memory_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(gt64xxx_device::ras_1_w), this)); if (LOG_GALILEO) logerror("%s: map_extra RAS1 start=%08X end=%08X size=%08X\n", tag(), winStart, winEnd, winSize); - + // RAS2 ramIndex = 2; winStart = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex / 2)] << 21) | (m_reg[GREG_RAS0_LO + 0x8 / 4 * ramIndex] << 20); @@ -293,7 +293,7 @@ void gt64xxx_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_ memory_space->install_write_handler(winStart, winEnd, 0, 0, write32_delegate(FUNC(gt64xxx_device::ras_2_w), this)); if (LOG_GALILEO) logerror("%s: map_extra RAS2 start=%08X end=%08X size=%08X\n", tag(), winStart, winEnd, winSize); - + // RAS3 ramIndex = 3; winStart = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex / 2)] << 21) | (m_reg[GREG_RAS0_LO + 0x8 / 4 * ramIndex] << 20); @@ -818,7 +818,7 @@ TIMER_CALLBACK_MEMBER (gt64xxx_device::perform_dma) which = (m_last_dma + i) % 4; if ((m_dma_active & (1 << which)) && (m_reg[GREG_DMA0_CONTROL + which] & 0x1000)) break; - + } // Save which dma is processed for arbitration next time m_last_dma = which; diff --git a/src/devices/machine/gt64xxx.h b/src/devices/machine/gt64xxx.h index 69cde74d34b..6433dcbabde 100644 --- a/src/devices/machine/gt64xxx.h +++ b/src/devices/machine/gt64xxx.h @@ -47,7 +47,7 @@ #define TIMER_PERIOD attotime::from_hz(m_clock) #define PCI_BUS_CLOCK 33000000 // Number of dma words to transfer at a time, real hardware configurable between 8-32 -#define DMA_BURST_SIZE 32 +#define DMA_BURST_SIZE 32 #define DMA_TIMER_PERIOD attotime::from_hz(PCI_BUS_CLOCK / 48) /* Galileo registers - 0x000-0x3ff */ diff --git a/src/devices/machine/pci-ide.h b/src/devices/machine/pci-ide.h index 349173ae590..7768a7a44cd 100644 --- a/src/devices/machine/pci-ide.h +++ b/src/devices/machine/pci-ide.h @@ -8,7 +8,7 @@ Generic PCI IDE controller implementation. Based on datasheet for National Semiconductor PC87415 TODO: - Add pci configuration write to PIF byte + Add pci configuration write to PIF byte ***************************************************************************/ #ifndef PCI_IDE_H diff --git a/src/devices/machine/stvcd.h b/src/devices/machine/stvcd.h index 7e75fe11255..165407d736e 100644 --- a/src/devices/machine/stvcd.h +++ b/src/devices/machine/stvcd.h @@ -1,3 +1,2 @@ // license:LGPL-2.1+ // copyright-holders:Angelo Salese, R. Belmont - diff --git a/src/devices/machine/vrc4373.h b/src/devices/machine/vrc4373.h index bf2ed1fd153..ce7a3f11e92 100644 --- a/src/devices/machine/vrc4373.h +++ b/src/devices/machine/vrc4373.h @@ -50,7 +50,7 @@ #define PCI_BUS_CLOCK 33000000 // Number of dma words to transfer at a time, real hardware bursts 8 -#define DMA_BURST_SIZE 128 +#define DMA_BURST_SIZE 128 #define DMA_TIMER_PERIOD attotime::from_hz(PCI_BUS_CLOCK / 32) #define DMA_BUSY 0x80000000 diff --git a/src/devices/machine/z80scc.cpp b/src/devices/machine/z80scc.cpp index f49b7e9363d..5c3c76abba6 100644 --- a/src/devices/machine/z80scc.cpp +++ b/src/devices/machine/z80scc.cpp @@ -27,10 +27,10 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC p 5-8 bit per char Y Y Y Y p 1,1.5,2 stop bits Y Y Y Y x odd/even parity Y Y Y Y - x x1,x16,x32,x64 Y Y Y Y + x x1,x16,x32,x64 Y Y Y Y p break det/gen Y Y Y Y x parity, framing & Y Y Y Y - overrun error det + overrun error det -- byte oriented synchrounous features ------------------------------- Int/ext char sync Y Y Y Y 1/2 synch chars Y Y Y Y @@ -81,7 +81,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC #define VERBOSE 0 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) -#define LOGR(x) +#define LOGR(x) #if VERBOSE == 2 #define logerror printf #endif @@ -692,7 +692,7 @@ z80scc_channel::z80scc_channel(const machine_config &mconfig, const char *tag, d m_dtr(0), m_rts(0), m_sync(0) -#if START_BIT_HUNT +#if START_BIT_HUNT ,m_rcv_mode(RCV_IDLE) #endif { @@ -854,9 +854,9 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para //int brconst = m_wr13 << 8 | m_wr12 | 1; // If the counter is 1 the effect is passthrough ehh?! To avoid div0... if (m_wr14 & WR14_BRG_ENABLE) { - // int rate = m_owner->clock() / brconst; - // attotime attorate = attotime::from_hz(rate); - // timer.adjust(attorate, id, attorate); + // int rate = m_owner->clock() / brconst; + // attotime attorate = attotime::from_hz(rate); + // timer.adjust(attorate, id, attorate); txc_w(m_brg_counter & 1); rxc_w(m_brg_counter & 1); m_brg_counter++; // Will just keep track of state in timer mode, not hardware counter value. @@ -869,11 +869,11 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para } break; default: - logerror("Spurious timer %d event\n", id); + logerror("Spurious timer %d event\n", id); } #else // TODO: Hmmm, either the above default clause is called OR the bellow call is not needed since we handled our local event anyway...?! - // and the above default is not called unless we implement the BRG timer using diserial timer interfaces... + // and the above default is not called unless we implement the BRG timer using diserial timer interfaces... device_serial_interface::device_timer(timer, id, param, ptr); #endif } @@ -1131,7 +1131,7 @@ int z80scc_channel::get_tx_word_length() * Break/Abort latch. */ UINT8 z80scc_channel::do_sccreg_rr0() { - LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_rr0)); + LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_rr0)); return m_rr0; } @@ -1836,7 +1836,7 @@ void z80scc_channel::do_sccreg_wr14(UINT8 data) if ( !(m_wr14 & WR14_BRG_ENABLE) && (data & WR14_BRG_ENABLE) ) // baud rate generator beeing enabled? { LOG(("\"%s\": %c : %s Mics Control Bits Baudrate generator enabled with \n", m_owner->tag(), 'A' + m_index, FUNCNAME)); - m_brg_const = 2 + (m_wr13 << 8 | m_wr12); + m_brg_const = 2 + (m_wr13 << 8 | m_wr12); if (data & WR14_BRG_SOURCE) // Do we use the PCLK as baudrate source { int rate = m_owner->clock() / (m_brg_const == 0 ? 1 : m_brg_const); @@ -1999,7 +1999,7 @@ UINT8 z80scc_channel::data_read() // trigger interrup and lock the fifo if an error is present if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) { - logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)); + logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)); switch (m_wr1 & WR1_RX_INT_MODE_MASK) { case WR1_RX_INT_FIRST: @@ -2074,7 +2074,7 @@ void z80scc_channel::data_write(UINT8 data) if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty()) { - LOG(("%s(%02x) \"%s\": %c : Transmit Data Byte '%02x' %c\n", FUNCNAME, data, m_owner->tag(), 'A' + m_index, m_tx_data, m_tx_data)); + LOG(("%s(%02x) \"%s\": %c : Transmit Data Byte '%02x' %c\n", FUNCNAME, data, m_owner->tag(), 'A' + m_index, m_tx_data, m_tx_data)); transmit_register_setup(m_tx_data); // empty transmit buffer @@ -2103,7 +2103,7 @@ void z80scc_channel::receive_data(UINT8 data) { LOG(("\"%s\": %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data)); - if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) )) + if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) )) { // receive overrun error detected m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR; // = m_rx_error; @@ -2308,7 +2308,7 @@ WRITE_LINE_MEMBER( z80scc_channel::rxc_w ) rx_clock_w(state); else if(state) { - if (m_rx_clock == clocks/2 && m_rcv_mode == RCV_SAMPLING) + if (m_rx_clock == clocks/2 && m_rcv_mode == RCV_SAMPLING) rx_clock_w(m_rx_clock < clocks/2); m_rx_clock++; @@ -2359,8 +2359,8 @@ void z80scc_channel::update_serial() else parity = PARITY_NONE; - LOG((LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1, - data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2)); + LOG((LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1, + data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2)); set_data_frame(1, data_bit_count, parity, stop_bits); #if START_BIT_HUNT diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h index cc20c783bdf..e754a3dd544 100644 --- a/src/devices/machine/z80scc.h +++ b/src/devices/machine/z80scc.h @@ -229,7 +229,7 @@ public: UINT8 m_rr6; // REG_RR6_LSB_OR_RR2 UINT8 m_rr7; // REG_RR7_MSB_OR_RR3 UINT8 m_rr8; // REG_RR8_RECEIVE_DATA - UINT8 m_rr9; // REG_RR9_WR3_OR_RR13 + UINT8 m_rr9; // REG_RR9_WR3_OR_RR13 UINT8 m_rr10; // REG_RR10_MISC_STATUS UINT8 m_rr11; // REG_RR11_WR10_OR_RR15 UINT8 m_rr12; // REG_RR12_LO_TIME_CONST @@ -274,239 +274,239 @@ protected: // Read registers enum { - REG_RR0_STATUS = 0, - REG_RR1_SPEC_RCV_COND = 1, - REG_RR2_INTERRUPT_VECT = 2, - REG_RR3_INTERUPPT_PEND = 3, - REG_RR4_WR4_OR_RR0 = 4, - REG_RR5_WR5_OR_RR0 = 5, - REG_RR6_LSB_OR_RR2 = 6, - REG_RR7_MSB_OR_RR3 = 7, - REG_RR8_RECEIVE_DATA = 8, - REG_RR9_WR3_OR_RR13 = 9, - REG_RR10_MISC_STATUS = 10, - REG_RR11_WR10_OR_RR15 = 11, - REG_RR12_LO_TIME_CONST = 12, - REG_RR13_HI_TIME_CONST = 13, - REG_RR14_WR7_OR_R10 = 14, - REG_RR15_WR15_EXT_STAT = 15 + REG_RR0_STATUS = 0, + REG_RR1_SPEC_RCV_COND = 1, + REG_RR2_INTERRUPT_VECT = 2, + REG_RR3_INTERUPPT_PEND = 3, + REG_RR4_WR4_OR_RR0 = 4, + REG_RR5_WR5_OR_RR0 = 5, + REG_RR6_LSB_OR_RR2 = 6, + REG_RR7_MSB_OR_RR3 = 7, + REG_RR8_RECEIVE_DATA = 8, + REG_RR9_WR3_OR_RR13 = 9, + REG_RR10_MISC_STATUS = 10, + REG_RR11_WR10_OR_RR15 = 11, + REG_RR12_LO_TIME_CONST = 12, + REG_RR13_HI_TIME_CONST = 13, + REG_RR14_WR7_OR_R10 = 14, + REG_RR15_WR15_EXT_STAT = 15 }; // Write registers enum { - REG_WR0_COMMAND_REGPT = 0, - REG_WR1_INT_DMA_ENABLE = 1, - REG_WR2_INT_VECTOR = 2, - REG_WR3_RX_CONTROL = 3, - REG_WR4_RX_TX_MODES = 4, - REG_WR5_TX_CONTROL = 5, - REG_WR6_SYNC_OR_SDLC_A = 6, - REG_WR7_SYNC_OR_SDLC_F = 7, - REG_WR8_TRANSMIT_DATA = 8, + REG_WR0_COMMAND_REGPT = 0, + REG_WR1_INT_DMA_ENABLE = 1, + REG_WR2_INT_VECTOR = 2, + REG_WR3_RX_CONTROL = 3, + REG_WR4_RX_TX_MODES = 4, + REG_WR5_TX_CONTROL = 5, + REG_WR6_SYNC_OR_SDLC_A = 6, + REG_WR7_SYNC_OR_SDLC_F = 7, + REG_WR8_TRANSMIT_DATA = 8, REG_WR9_MASTER_INT_CTRL = 9, REG_WR10_MSC_RX_TX_CTRL = 10, - REG_WR11_CLOCK_MODES = 11, - REG_WR12_LO_BAUD_GEN = 12, - REG_WR13_HI_BAUD_GEN = 13, - REG_WR14_MISC_CTRL = 14, + REG_WR11_CLOCK_MODES = 11, + REG_WR12_LO_BAUD_GEN = 12, + REG_WR13_HI_BAUD_GEN = 13, + REG_WR14_MISC_CTRL = 14, REG_WR15_EXT_ST_INT_CTRL= 15 }; enum { - RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit - RR0_ZC = 0x02, // SCC bit - RR0_TX_BUFFER_EMPTY = 0x04, // SIO - RR0_DCD = 0x08, // SIO - RR0_RI = 0x10, // DART bit? TODO: investigate function and remove - RR0_SYNC_HUNT = 0x10, // SIO bit, not supported - RR0_CTS = 0x20, // SIO bit - RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported - RR0_BREAK_ABORT = 0x80 // SIO bit, not supported + RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit + RR0_ZC = 0x02, // SCC bit + RR0_TX_BUFFER_EMPTY = 0x04, // SIO + RR0_DCD = 0x08, // SIO + RR0_RI = 0x10, // DART bit? TODO: investigate function and remove + RR0_SYNC_HUNT = 0x10, // SIO bit, not supported + RR0_CTS = 0x20, // SIO bit + RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported + RR0_BREAK_ABORT = 0x80 // SIO bit, not supported }; enum { - RR1_ALL_SENT = 0x01, // SIO/SCC bit - RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported - RR1_PARITY_ERROR = 0x10, // SIO/SCC bits - RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits - RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits - RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported + RR1_ALL_SENT = 0x01, // SIO/SCC bit + RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported + RR1_PARITY_ERROR = 0x10, // SIO/SCC bits + RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits + RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits + RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported }; enum - { // TODO: overload SIO functionality - RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) - RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B - RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B + { // TODO: overload SIO functionality + RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case) + RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B + RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B }; enum { - RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers - RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels) - RR3_CHANB_RX_IP = 0x04, // channel B return all zero - RR3_CHANA_EXT_IP = 0x08, - RR3_CHANA_TX_IP = 0x10, - RR3_CHANA_RX_IP = 0x20 + RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers + RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels) + RR3_CHANB_RX_IP = 0x04, // channel B return all zero + RR3_CHANA_EXT_IP = 0x08, + RR3_CHANA_TX_IP = 0x10, + RR3_CHANA_RX_IP = 0x20 }; enum // Universal Bus WR0 commands for 85X30 { - WR0_REGISTER_MASK = 0x07, - WR0_COMMAND_MASK = 0x38, // COMMANDS - WR0_NULL = 0x00, // 0 0 0 - WR0_POINT_HIGH = 0x08, // 0 0 1 - WR0_RESET_EXT_STATUS = 0x10, // 0 1 0 - WR0_SEND_ABORT = 0x18, // 0 1 1 - WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 - WR0_RESET_TX_INT = 0x28, // 1 0 1 - WR0_ERROR_RESET = 0x30, // 1 1 0 - WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1 - WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET - WR0_CRC_RESET_NULL = 0x00, // 0 0 - WR0_CRC_RESET_RX = 0x40, // 0 1 - WR0_CRC_RESET_TX = 0x80, // 1 0 + WR0_REGISTER_MASK = 0x07, + WR0_COMMAND_MASK = 0x38, // COMMANDS + WR0_NULL = 0x00, // 0 0 0 + WR0_POINT_HIGH = 0x08, // 0 0 1 + WR0_RESET_EXT_STATUS = 0x10, // 0 1 0 + WR0_SEND_ABORT = 0x18, // 0 1 1 + WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0 + WR0_RESET_TX_INT = 0x28, // 1 0 1 + WR0_ERROR_RESET = 0x30, // 1 1 0 + WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1 + WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET + WR0_CRC_RESET_NULL = 0x00, // 0 0 + WR0_CRC_RESET_RX = 0x40, // 0 1 + WR0_CRC_RESET_TX = 0x80, // 1 0 WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1 }; enum // ZBUS WR0 commands or 80X30 { - WR0_Z_COMMAND_MASK = 0x38, // COMMANDS - WR0_Z_NULL_1 = 0x00, // 0 0 0 - WR0_Z_NULL_2 = 0x08, // 0 0 1 - WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0 - WR0_Z_SEND_ABORT = 0x18, // 0 1 1 + WR0_Z_COMMAND_MASK = 0x38, // COMMANDS + WR0_Z_NULL_1 = 0x00, // 0 0 0 + WR0_Z_NULL_2 = 0x08, // 0 0 1 + WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0 + WR0_Z_SEND_ABORT = 0x18, // 0 1 1 WR0_Z_ENABLE_INT_NEXT_RX= 0x20, // 1 0 0 - WR0_Z_RESET_TX_INT = 0x28, // 1 0 1 - WR0_Z_ERROR_RESET = 0x30, // 1 1 0 + WR0_Z_RESET_TX_INT = 0x28, // 1 0 1 + WR0_Z_ERROR_RESET = 0x30, // 1 1 0 WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1 - WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B - WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0 - WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1 + WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B + WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0 + WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1 }; enum { - WR1_EXT_INT_ENABLE = 0x01, - WR1_TX_INT_ENABLE = 0x02, - WR1_PARITY_IS_SPEC_COND = 0x04, - WR1_RX_INT_MODE_MASK = 0x18, - WR1_RX_INT_DISABLE = 0x00, - WR1_RX_INT_FIRST = 0x08, - WR1_RX_INT_ALL_PARITY = 0x10, // not supported - WR1_RX_INT_ALL = 0x18, - WR1_WRDY_ON_RX_TX = 0x20, // not supported - WR1_WRDY_FUNCTION = 0x40, // not supported - WR1_WRDY_ENABLE = 0x80 // not supported + WR1_EXT_INT_ENABLE = 0x01, + WR1_TX_INT_ENABLE = 0x02, + WR1_PARITY_IS_SPEC_COND = 0x04, + WR1_RX_INT_MODE_MASK = 0x18, + WR1_RX_INT_DISABLE = 0x00, + WR1_RX_INT_FIRST = 0x08, + WR1_RX_INT_ALL_PARITY = 0x10, // not supported + WR1_RX_INT_ALL = 0x18, + WR1_WRDY_ON_RX_TX = 0x20, // not supported + WR1_WRDY_FUNCTION = 0x40, // not supported + WR1_WRDY_ENABLE = 0x80 // not supported }; enum { - WR3_RX_ENABLE = 0x01, - WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02, // not supported - WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported - WR3_RX_CRC_ENABLE = 0x08, // not supported - WR3_ENTER_HUNT_PHASE = 0x10, // not supported - WR3_AUTO_ENABLES = 0x20, - WR3_RX_WORD_LENGTH_MASK = 0xc0, - WR3_RX_WORD_LENGTH_5 = 0x00, - WR3_RX_WORD_LENGTH_7 = 0x40, - WR3_RX_WORD_LENGTH_6 = 0x80, - WR3_RX_WORD_LENGTH_8 = 0xc0 + WR3_RX_ENABLE = 0x01, + WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02, // not supported + WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported + WR3_RX_CRC_ENABLE = 0x08, // not supported + WR3_ENTER_HUNT_PHASE = 0x10, // not supported + WR3_AUTO_ENABLES = 0x20, + WR3_RX_WORD_LENGTH_MASK = 0xc0, + WR3_RX_WORD_LENGTH_5 = 0x00, + WR3_RX_WORD_LENGTH_7 = 0x40, + WR3_RX_WORD_LENGTH_6 = 0x80, + WR3_RX_WORD_LENGTH_8 = 0xc0 }; enum { - WR4_PARITY_ENABLE = 0x01, - WR4_PARITY_EVEN = 0x02, - WR4_STOP_BITS_MASK = 0x0c, - WR4_STOP_BITS_1 = 0x04, - WR4_STOP_BITS_1_5 = 0x08, // not supported - WR4_STOP_BITS_2 = 0x0c, - WR4_SYNC_MODE_MASK = 0x30, // not supported - WR4_SYNC_MODE_8_BIT = 0x00, // not supported - WR4_SYNC_MODE_16_BIT = 0x10, // not supported - WR4_SYNC_MODE_SDLC = 0x20, // not supported - WR4_SYNC_MODE_EXT = 0x30, // not supported - WR4_CLOCK_RATE_MASK = 0xc0, - WR4_CLOCK_RATE_X1 = 0x00, - WR4_CLOCK_RATE_X16 = 0x40, - WR4_CLOCK_RATE_X32 = 0x80, - WR4_CLOCK_RATE_X64 = 0xc0 + WR4_PARITY_ENABLE = 0x01, + WR4_PARITY_EVEN = 0x02, + WR4_STOP_BITS_MASK = 0x0c, + WR4_STOP_BITS_1 = 0x04, + WR4_STOP_BITS_1_5 = 0x08, // not supported + WR4_STOP_BITS_2 = 0x0c, + WR4_SYNC_MODE_MASK = 0x30, // not supported + WR4_SYNC_MODE_8_BIT = 0x00, // not supported + WR4_SYNC_MODE_16_BIT = 0x10, // not supported + WR4_SYNC_MODE_SDLC = 0x20, // not supported + WR4_SYNC_MODE_EXT = 0x30, // not supported + WR4_CLOCK_RATE_MASK = 0xc0, + WR4_CLOCK_RATE_X1 = 0x00, + WR4_CLOCK_RATE_X16 = 0x40, + WR4_CLOCK_RATE_X32 = 0x80, + WR4_CLOCK_RATE_X64 = 0xc0 }; enum { - WR5_TX_CRC_ENABLE = 0x01, // not supported - WR5_RTS = 0x02, - WR5_CRC16 = 0x04, // not supported - WR5_TX_ENABLE = 0x08, - WR5_SEND_BREAK = 0x10, - WR5_TX_WORD_LENGTH_MASK = 0x60, - WR5_TX_WORD_LENGTH_5 = 0x00, - WR5_TX_WORD_LENGTH_6 = 0x40, - WR5_TX_WORD_LENGTH_7 = 0x20, - WR5_TX_WORD_LENGTH_8 = 0x60, - WR5_DTR = 0x80 + WR5_TX_CRC_ENABLE = 0x01, // not supported + WR5_RTS = 0x02, + WR5_CRC16 = 0x04, // not supported + WR5_TX_ENABLE = 0x08, + WR5_SEND_BREAK = 0x10, + WR5_TX_WORD_LENGTH_MASK = 0x60, + WR5_TX_WORD_LENGTH_5 = 0x00, + WR5_TX_WORD_LENGTH_6 = 0x40, + WR5_TX_WORD_LENGTH_7 = 0x20, + WR5_TX_WORD_LENGTH_8 = 0x60, + WR5_DTR = 0x80 }; /* SCC specifics */ enum { - WR9_CMD_MASK = 0xC0, - WR9_CMD_NORESET = 0x00, - WR9_CMD_CHNB_RESET = 0x40, - WR9_CMD_CHNA_RESET = 0x80, - WR9_CMD_HW_RESET = 0xC0, - WR9_BIT_VIS = 0x01, - WR9_BIT_NV = 0x02, - WR9_BIT_DLC = 0x04, - WR9_BIT_MIE = 0x08, - WR9_BIT_SHSL = 0x10, - WR9_BIT_IACK = 0x20 + WR9_CMD_MASK = 0xC0, + WR9_CMD_NORESET = 0x00, + WR9_CMD_CHNB_RESET = 0x40, + WR9_CMD_CHNA_RESET = 0x80, + WR9_CMD_HW_RESET = 0xC0, + WR9_BIT_VIS = 0x01, + WR9_BIT_NV = 0x02, + WR9_BIT_DLC = 0x04, + WR9_BIT_MIE = 0x08, + WR9_BIT_SHSL = 0x10, + WR9_BIT_IACK = 0x20 }; enum { - WR11_RCVCLK_TYPE = 0x80, - WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK - WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0 - WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1 - WR11_RCVCLK_SRC_BR = 0x40, // 1 0 - WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1 - WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK - WR11_TRACLK_SRC_RTXC = 0x00, // 0 0 - WR11_TRACLK_SRC_TRXC = 0x08, // 0 1 - WR11_TRACLK_SRC_BR = 0x10, // 1 0 - WR11_TRACLK_SRC_DPLL = 0x18, // 1 1 - WR11_TRXC_DIRECTION = 0x04, - WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK - WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0 - WR11_TRXSRC_SRC_TRA = 0x01, // 0 1 - WR11_TRXSRC_SRC_BR = 0x02, // 1 0 - WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1 + WR11_RCVCLK_TYPE = 0x80, + WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK + WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0 + WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1 + WR11_RCVCLK_SRC_BR = 0x40, // 1 0 + WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1 + WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK + WR11_TRACLK_SRC_RTXC = 0x00, // 0 0 + WR11_TRACLK_SRC_TRXC = 0x08, // 0 1 + WR11_TRACLK_SRC_BR = 0x10, // 1 0 + WR11_TRACLK_SRC_DPLL = 0x18, // 1 1 + WR11_TRXC_DIRECTION = 0x04, + WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK + WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0 + WR11_TRXSRC_SRC_TRA = 0x01, // 0 1 + WR11_TRXSRC_SRC_BR = 0x02, // 1 0 + WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1 }; enum { - WR14_DPLL_CMD_MASK = 0xe0, // Command - WR14_CMD_NULL = 0x00, // 0 0 0 - WR14_CMD_ESM = 0x20, // 0 0 1 - WR14_CMD_RMC = 0x40, // 0 1 0 - WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1 - WR14_CMD_SS_BRG = 0x80, // 1 0 0 - WR14_CMD_SS_RTXC = 0xa0, // 1 0 1 - WR14_CMD_SET_FM = 0xc0, // 1 1 0 - WR14_CMD_SET_NRZI = 0xe0, // 1 1 1 - WR14_BRG_ENABLE = 0x01, - WR14_BRG_SOURCE = 0x02, - WR14_DTR_REQ_FUNC = 0x04, - WR14_AUTO_ECHO = 0x08, - WR14_LOCAL_LOOPBACK = 0x010 + WR14_DPLL_CMD_MASK = 0xe0, // Command + WR14_CMD_NULL = 0x00, // 0 0 0 + WR14_CMD_ESM = 0x20, // 0 0 1 + WR14_CMD_RMC = 0x40, // 0 1 0 + WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1 + WR14_CMD_SS_BRG = 0x80, // 1 0 0 + WR14_CMD_SS_RTXC = 0xa0, // 1 0 1 + WR14_CMD_SET_FM = 0xc0, // 1 1 0 + WR14_CMD_SET_NRZI = 0xe0, // 1 1 1 + WR14_BRG_ENABLE = 0x01, + WR14_BRG_SOURCE = 0x02, + WR14_DTR_REQ_FUNC = 0x04, + WR14_AUTO_ECHO = 0x08, + WR14_LOCAL_LOOPBACK = 0x010 }; enum @@ -536,40 +536,40 @@ protected: int get_tx_word_length(); // receiver state - UINT8 m_rx_data_fifo[8]; // receive data FIFO - UINT8 m_rx_error_fifo[8]; // receive error FIFO - UINT8 m_rx_error; // current receive error - //int m_rx_fifo // receive FIFO pointer - int m_rx_fifo_rp; // receive FIFO read pointer - int m_rx_fifo_wp; // receive FIFO write pointer - int m_rx_fifo_sz; // receive FIFO size - - int m_rx_clock; // receive clock pulse count - int m_rx_first; // first character received - int m_rx_break; // receive break condition - UINT8 m_rx_rr0_latch; // read register 0 latched + UINT8 m_rx_data_fifo[8]; // receive data FIFO + UINT8 m_rx_error_fifo[8]; // receive error FIFO + UINT8 m_rx_error; // current receive error + //int m_rx_fifo // receive FIFO pointer + int m_rx_fifo_rp; // receive FIFO read pointer + int m_rx_fifo_wp; // receive FIFO write pointer + int m_rx_fifo_sz; // receive FIFO size + + int m_rx_clock; // receive clock pulse count + int m_rx_first; // first character received + int m_rx_break; // receive break condition + UINT8 m_rx_rr0_latch; // read register 0 latched int m_rxd; - int m_ri; // ring indicator latch - int m_cts; // clear to send latch - int m_dcd; // data carrier detect latch + int m_ri; // ring indicator latch + int m_cts; // clear to send latch + int m_dcd; // data carrier detect latch // transmitter state - UINT8 m_tx_data; // transmit data register - int m_tx_clock; // transmit clock pulse count + UINT8 m_tx_data; // transmit data register + int m_tx_clock; // transmit clock pulse count - int m_dtr; // data terminal ready - int m_rts; // request to send + int m_dtr; // data terminal ready + int m_rts; // request to send // synchronous state - UINT16 m_sync; // sync character + UINT16 m_sync; // sync character int m_rcv_mode; int m_index; z80scc_device *m_uart; // SCC specifics - int m_ph; // Point high command to access regs 08-0f + int m_ph; // Point high command to access regs 08-0f UINT8 m_zc; }; |