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author hap <happppp@users.noreply.github.com>2026-03-04 15:15:37 +0100
committer hap <happppp@users.noreply.github.com>2026-03-04 15:15:50 +0100
commitf0244b9f63d80afcc7dfda4ff71867205056aecc (patch)
tree0e2f2ddd3bd2561a250dc3c8f12fa8e1ff40aa93 /src/devices/cpu
parent32c3e44eb15cc767e5ba45f401160591d44c4a02 (diff)
v60,v30mz: correction to addc/subc overflow flag calculation
Diffstat (limited to 'src/devices/cpu')
-rw-r--r--src/devices/cpu/v30mz/v30mz.cpp128
-rw-r--r--src/devices/cpu/v30mz/v30mz.h8
-rw-r--r--src/devices/cpu/v60/op12.hxx58
-rw-r--r--src/devices/cpu/v60/op3.hxx20
-rw-r--r--src/devices/cpu/v60/v60.cpp12
-rw-r--r--src/devices/cpu/v810/v810.cpp12
6 files changed, 103 insertions, 135 deletions
diff --git a/src/devices/cpu/v30mz/v30mz.cpp b/src/devices/cpu/v30mz/v30mz.cpp
index cbdcf4aff47..e3c2fafcbb9 100644
--- a/src/devices/cpu/v30mz/v30mz.cpp
+++ b/src/devices/cpu/v30mz/v30mz.cpp
@@ -10,12 +10,12 @@
fetches limited on tight loops and is more than enough for the longest
instruction.
- Todo!
- - Double check cycle timing is 100%.
- - Add penalties when BW, BP, SP, IX, IY etc are changed in the immediately
- preceding instruction.
- - wswan mjkiwame (at 0x40141) has rep in al,$b5 (f3 e4 b5). Should this
- repeat the in instruction or is this a bug made by the programmer?
+ TODO:
+ - Double check cycle timing is 100%.
+ * Add penalties when BW, BP, SP, IX, IY etc are changed in the immediately
+ preceding instruction.
+ * wswan mjkiwame (at 0x40141) has rep in al,$b5 (f3 e4 b5). Should this
+ repeat the in instruction or is this a bug made by the programmer?
****************************************************************************/
@@ -1015,9 +1015,9 @@ inline void v30mz_cpu_device::i_popf()
}
-inline void v30mz_cpu_device::add_byte()
+inline void v30mz_cpu_device::add_byte(uint8_t c)
{
- uint32_t res = (m_dst & 0xff) + (m_src & 0xff);
+ uint32_t res = (m_dst & 0xff) + (m_src & 0xff) + c;
set_CF_byte(res);
set_OF_byte_add(res, m_src, m_dst);
@@ -1027,9 +1027,9 @@ inline void v30mz_cpu_device::add_byte()
}
-inline void v30mz_cpu_device::add_word()
+inline void v30mz_cpu_device::add_word(uint8_t c)
{
- uint32_t res = (m_dst & 0xffff) + (m_src & 0xffff);
+ uint32_t res = (m_dst & 0xffff) + (m_src & 0xffff) + c;
set_CF_word(res);
set_OF_word_add(res, m_src, m_dst);
@@ -1039,9 +1039,9 @@ inline void v30mz_cpu_device::add_word()
}
-inline void v30mz_cpu_device::sub_byte()
+inline void v30mz_cpu_device::sub_byte(uint8_t c)
{
- uint32_t res = (m_dst & 0xff) - (m_src & 0xff);
+ uint32_t res = (m_dst & 0xff) - (m_src & 0xff) - c;
set_CF_byte(res);
set_OF_byte_sub(res, m_src, m_dst);
@@ -1051,9 +1051,9 @@ inline void v30mz_cpu_device::sub_byte()
}
-inline void v30mz_cpu_device::sub_word()
+inline void v30mz_cpu_device::sub_word(uint8_t c)
{
- uint32_t res = (m_dst & 0xffff) - (m_src & 0xffff);
+ uint32_t res = (m_dst & 0xffff) - (m_src & 0xffff) - c;
set_CF_word(res);
set_OF_word_sub(res, m_src, m_dst);
@@ -1563,48 +1563,42 @@ void v30mz_cpu_device::execute_run()
case 0x10: // i_adc_br8
def_br8();
- m_src += CF ? 1 : 0;
- add_byte();
+ add_byte(CF ? 1 : 0);
store_ea_rm_byte(m_dst);
clkm(1,3);
break;
case 0x11: // i_adc_wr16
def_wr16();
- m_src += CF ? 1 : 0;
- add_word();
+ add_word(CF ? 1 : 0);
store_ea_rm_word(m_dst);
clkm(1,3);
break;
case 0x12: // i_adc_r8b
def_r8b();
- m_src += CF ? 1 : 0;
- add_byte();
+ add_byte(CF ? 1 : 0);
reg_byte(m_dst);
clkm(1,2);
break;
case 0x13: // i_adc_r16w
def_r16w();
- m_src += CF ? 1 : 0;
- add_word();
+ add_word(CF ? 1 : 0);
reg_word(m_dst);
clkm(1,2);
break;
case 0x14: // i_adc_ald8
def_ald8();
- m_src += CF ? 1 : 0;
- add_byte();
+ add_byte(CF ? 1 : 0);
m_regs.b[AL] = m_dst;
clk(1);
break;
case 0x15: // i_adc_axd16
def_awd16();
- m_src += CF ? 1 : 0;
- add_word();
+ add_word(CF ? 1 : 0);
m_regs.w[AW] = m_dst;
clk(1);
break;
@@ -1623,48 +1617,42 @@ void v30mz_cpu_device::execute_run()
case 0x18: // i_sbb_br8
def_br8();
- m_src += CF ? 1 : 0;
- sub_byte();
+ sub_byte(CF ? 1 : 0);
store_ea_rm_byte(m_dst);
clkm(1,3);
break;
case 0x19: // i_sbb_wr16
def_wr16();
- m_src += CF ? 1 : 0;
- sub_word();
+ sub_word(CF ? 1 : 0);
store_ea_rm_word(m_dst);
clkm(1,3);
break;
case 0x1a: // i_sbb_r8b
def_r8b();
- m_src += CF ? 1 : 0;
- sub_byte();
+ sub_byte(CF ? 1 : 0);
reg_byte(m_dst);
clkm(1,2);
break;
case 0x1b: // i_sbb_r16w
def_r16w();
- m_src += CF ? 1 : 0;
- sub_word();
+ sub_word(CF ? 1 : 0);
reg_word(m_dst);
clkm(1,2);
break;
case 0x1c: // i_sbb_ald8
def_ald8();
- m_src += CF ? 1 : 0;
- sub_byte();
+ sub_byte(CF ? 1 : 0);
m_regs.b[AL] = m_dst;
clk(1);
break;
case 0x1d: // i_sbb_axd16
def_awd16();
- m_src += CF ? 1 : 0;
- sub_word();
+ sub_word(CF ? 1 : 0);
m_regs.w[AW] = m_dst;
clk(1);
break;
@@ -2309,14 +2297,14 @@ void v30mz_cpu_device::execute_run()
else { clk(3); }
switch (m_modrm & 0x38)
{
- case 0x00: add_byte(); store_ea_rm_byte(m_dst); break;
- case 0x08: or_byte(); store_ea_rm_byte(m_dst); break;
- case 0x10: m_src += CF ? 1 : 0; add_byte(); store_ea_rm_byte(m_dst); break;
- case 0x18: m_src += CF ? 1 : 0; sub_byte(); store_ea_rm_byte(m_dst); break;
- case 0x20: and_byte(); store_ea_rm_byte(m_dst); break;
- case 0x28: sub_byte(); store_ea_rm_byte(m_dst); break;
- case 0x30: xor_byte(); store_ea_rm_byte(m_dst); break;
- case 0x38: sub_byte(); break; // CMP
+ case 0x00: add_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x08: or_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x10: add_byte(CF ? 1 : 0); store_ea_rm_byte(m_dst); break;
+ case 0x18: sub_byte(CF ? 1 : 0); store_ea_rm_byte(m_dst); break;
+ case 0x20: and_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x28: sub_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x30: xor_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x38: sub_byte(); break; // CMP
}
break;
@@ -2330,14 +2318,14 @@ void v30mz_cpu_device::execute_run()
else { clk(3); }
switch (m_modrm & 0x38)
{
- case 0x00: add_word(); store_ea_rm_word(m_dst); break;
- case 0x08: or_word(); store_ea_rm_word(m_dst); break;
- case 0x10: m_src += CF ? 1 : 0; add_word(); store_ea_rm_word(m_dst); break;
- case 0x18: m_src += CF ? 1 : 0; sub_word(); store_ea_rm_word(m_dst); break;
- case 0x20: and_word(); store_ea_rm_word(m_dst); break;
- case 0x28: sub_word(); store_ea_rm_word(m_dst); break;
- case 0x30: xor_word(); store_ea_rm_word(m_dst); break;
- case 0x38: sub_word(); break; // CMP
+ case 0x00: add_word(); store_ea_rm_word(m_dst); break;
+ case 0x08: or_word(); store_ea_rm_word(m_dst); break;
+ case 0x10: add_word(CF ? 1 : 0); store_ea_rm_word(m_dst); break;
+ case 0x18: sub_word(CF ? 1 : 0); store_ea_rm_word(m_dst); break;
+ case 0x20: and_word(); store_ea_rm_word(m_dst); break;
+ case 0x28: sub_word(); store_ea_rm_word(m_dst); break;
+ case 0x30: xor_word(); store_ea_rm_word(m_dst); break;
+ case 0x38: sub_word(); break; // CMP
}
break;
@@ -2351,14 +2339,14 @@ void v30mz_cpu_device::execute_run()
else { clk(3); }
switch (m_modrm & 0x38)
{
- case 0x00: add_byte(); store_ea_rm_byte(m_dst); break;
- case 0x08: or_byte(); store_ea_rm_byte(m_dst); break;
- case 0x10: m_src += CF ? 1 : 0; add_byte(); store_ea_rm_byte(m_dst); break;
- case 0x18: m_src += CF ? 1 : 0; sub_byte(); store_ea_rm_byte(m_dst); break;
- case 0x20: and_byte(); store_ea_rm_byte(m_dst); break;
- case 0x28: sub_byte(); store_ea_rm_byte(m_dst); break;
- case 0x30: xor_byte(); store_ea_rm_byte(m_dst); break;
- case 0x38: sub_byte(); break; // CMP
+ case 0x00: add_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x08: or_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x10: add_byte(CF ? 1 : 0); store_ea_rm_byte(m_dst); break;
+ case 0x18: sub_byte(CF ? 1 : 0); store_ea_rm_byte(m_dst); break;
+ case 0x20: and_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x28: sub_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x30: xor_byte(); store_ea_rm_byte(m_dst); break;
+ case 0x38: sub_byte(); break; // CMP
}
break;
@@ -2372,14 +2360,14 @@ void v30mz_cpu_device::execute_run()
else { clk(3); }
switch (m_modrm & 0x38)
{
- case 0x00: add_word(); store_ea_rm_word(m_dst); break;
- case 0x08: or_word(); store_ea_rm_word(m_dst); break;
- case 0x10: m_src += CF ? 1 : 0; add_word(); store_ea_rm_word(m_dst); break;
- case 0x18: m_src += CF ? 1 : 0; sub_word(); store_ea_rm_word(m_dst); break;
- case 0x20: and_word(); store_ea_rm_word(m_dst); break;
- case 0x28: sub_word(); store_ea_rm_word(m_dst); break;
- case 0x30: xor_word(); store_ea_rm_word(m_dst); break;
- case 0x38: sub_word(); break; // CMP
+ case 0x00: add_word(); store_ea_rm_word(m_dst); break;
+ case 0x08: or_word(); store_ea_rm_word(m_dst); break;
+ case 0x10: add_word(CF ? 1 : 0); store_ea_rm_word(m_dst); break;
+ case 0x18: sub_word(CF ? 1 : 0); store_ea_rm_word(m_dst); break;
+ case 0x20: and_word(); store_ea_rm_word(m_dst); break;
+ case 0x28: sub_word(); store_ea_rm_word(m_dst); break;
+ case 0x30: xor_word(); store_ea_rm_word(m_dst); break;
+ case 0x38: sub_word(); break; // CMP
}
break;
diff --git a/src/devices/cpu/v30mz/v30mz.h b/src/devices/cpu/v30mz/v30mz.h
index da1612977ff..6ea996675f5 100644
--- a/src/devices/cpu/v30mz/v30mz.h
+++ b/src/devices/cpu/v30mz/v30mz.h
@@ -132,10 +132,10 @@ protected:
inline void i_popf();
// sub implementations
- inline void add_byte();
- inline void add_word();
- inline void sub_byte();
- inline void sub_word();
+ inline void add_byte(uint8_t c = 0);
+ inline void add_word(uint8_t c = 0);
+ inline void sub_byte(uint8_t c = 0);
+ inline void sub_word(uint8_t c = 0);
inline void or_byte();
inline void or_word();
inline void and_byte();
diff --git a/src/devices/cpu/v60/op12.hxx b/src/devices/cpu/v60/op12.hxx
index 742a486e564..b4074eae34b 100644
--- a/src/devices/cpu/v60/op12.hxx
+++ b/src/devices/cpu/v60/op12.hxx
@@ -273,7 +273,7 @@ uint32_t v60_device::opADDB() /* TRUSTED (C too!)*/
F12LOADOP2BYTE();
- ADDB(appb, (uint8_t)m_op1);
+ ADDB(appb, (uint8_t)m_op1, 0);
F12STOREOP2BYTE();
F12END();
@@ -286,7 +286,7 @@ uint32_t v60_device::opADDH() /* TRUSTED (C too!)*/
F12LOADOP2HALF();
- ADDW(apph, (uint16_t)m_op1);
+ ADDW(apph, (uint16_t)m_op1, 0);
F12STOREOP2HALF();
F12END();
@@ -299,7 +299,7 @@ uint32_t v60_device::opADDW() /* TRUSTED (C too!) */
F12LOADOP2WORD();
- ADDL(appw, (uint32_t)m_op1);
+ ADDL(appw, (uint32_t)m_op1, 0);
F12STOREOP2WORD();
F12END();
@@ -307,14 +307,12 @@ uint32_t v60_device::opADDW() /* TRUSTED (C too!) */
uint32_t v60_device::opADDCB()
{
- uint8_t appb, temp;
-
+ uint8_t appb;
F12DecodeOperands(&v60_device::ReadAM, 0,&v60_device::ReadAMAddress, 0);
F12LOADOP2BYTE();
- temp = ((uint8_t)m_op1 + (_CY?1:0));
- ADDB(appb, temp);
+ ADDB(appb, (uint8_t)m_op1, _CY?1:0);
F12STOREOP2BYTE();
F12END();
@@ -322,14 +320,12 @@ uint32_t v60_device::opADDCB()
uint32_t v60_device::opADDCH()
{
- uint16_t apph, temp;
-
+ uint16_t apph;
F12DecodeOperands(&v60_device::ReadAM, 1,&v60_device::ReadAMAddress, 1);
F12LOADOP2HALF();
- temp = ((uint16_t)m_op1 + (_CY?1:0));
- ADDW(apph, temp);
+ ADDW(apph, (uint16_t)m_op1, _CY?1:0);
F12STOREOP2HALF();
F12END();
@@ -337,14 +333,12 @@ uint32_t v60_device::opADDCH()
uint32_t v60_device::opADDCW()
{
- uint32_t appw, temp;
-
+ uint32_t appw;
F12DecodeOperands(&v60_device::ReadAM, 2,&v60_device::ReadAMAddress, 2);
F12LOADOP2WORD();
- temp = m_op1 + (_CY?1:0);
- ADDL(appw, temp);
+ ADDL(appw, (uint32_t)m_op1, _CY?1:0);
F12STOREOP2WORD();
F12END();
@@ -501,7 +495,7 @@ uint32_t v60_device::opCMPB() /* TRUSTED (C too!) */
F12DecodeOperands(&v60_device::ReadAM, 0,&v60_device::ReadAM, 0);
appb = (uint8_t)m_op2;
- SUBB(appb, (uint8_t)m_op1);
+ SUBB(appb, (uint8_t)m_op1, 0);
F12END();
}
@@ -512,7 +506,7 @@ uint32_t v60_device::opCMPH() /* TRUSTED (C too!) */
F12DecodeOperands(&v60_device::ReadAM, 1,&v60_device::ReadAM, 1);
apph = (uint16_t)m_op2;
- SUBW(apph, (uint16_t)m_op1);
+ SUBW(apph, (uint16_t)m_op1, 0);
F12END();
}
@@ -522,7 +516,7 @@ uint32_t v60_device::opCMPW() /* TRUSTED (C too!)*/
{
F12DecodeOperands(&v60_device::ReadAM, 2,&v60_device::ReadAM, 2);
- SUBL(m_op2, (uint32_t)m_op1);
+ SUBL(m_op2, (uint32_t)m_op1, 0);
F12END();
}
@@ -1076,7 +1070,7 @@ uint32_t v60_device::opNEGB() /* TRUSTED (C too!)*/
F12DecodeFirstOperand(&v60_device::ReadAM, 0);
m_modwritevalb = 0;
- SUBB(m_modwritevalb, (int8_t)m_op1);
+ SUBB(m_modwritevalb, (int8_t)m_op1, 0);
_CY = m_modwritevalb ? 1 : 0;
F12WriteSecondOperand(0);
@@ -1088,7 +1082,7 @@ uint32_t v60_device::opNEGH() /* TRUSTED (C too!)*/
F12DecodeFirstOperand(&v60_device::ReadAM, 1);
m_modwritevalh = 0;
- SUBW(m_modwritevalh, (int16_t)m_op1);
+ SUBW(m_modwritevalh, (int16_t)m_op1, 0);
_CY = m_modwritevalh ? 1 : 0;
F12WriteSecondOperand(1);
@@ -1100,7 +1094,7 @@ uint32_t v60_device::opNEGW() /* TRUSTED (C too!)*/
F12DecodeFirstOperand(&v60_device::ReadAM, 2);
m_modwritevalw = 0;
- SUBL(m_modwritevalw, (int32_t)m_op1);
+ SUBL(m_modwritevalw, (int32_t)m_op1, 0);
_CY = m_modwritevalw ? 1 : 0;
F12WriteSecondOperand(2);
@@ -2048,7 +2042,7 @@ uint32_t v60_device::opSHLW() /* TRUSTED */
}
}
-// osd_printf_debug("SHLW: %x _CY: %d _Z: %d _OV: %d _S: %d\n", appw, _CY, _Z, _OV, _S);
+ //osd_printf_debug("SHLW: %x _CY: %d _Z: %d _OV: %d _S: %d\n", appw, _CY, _Z, _OV, _S);
F12STOREOP2WORD();
F12END();
@@ -2075,7 +2069,7 @@ uint32_t v60_device::opSUBB() /* TRUSTED (C too!) */
F12LOADOP2BYTE();
- SUBB(appb, (uint8_t)m_op1);
+ SUBB(appb, (uint8_t)m_op1, 0);
F12STOREOP2BYTE();
F12END();
@@ -2088,7 +2082,7 @@ uint32_t v60_device::opSUBH() /* TRUSTED (C too!) */
F12LOADOP2HALF();
- SUBW(apph, (uint16_t)m_op1);
+ SUBW(apph, (uint16_t)m_op1, 0);
F12STOREOP2HALF();
F12END();
@@ -2101,7 +2095,7 @@ uint32_t v60_device::opSUBW() /* TRUSTED (C too!) */
F12LOADOP2WORD();
- SUBL(appw, (uint32_t)m_op1);
+ SUBL(appw, (uint32_t)m_op1, 0);
F12STOREOP2WORD();
F12END();
@@ -2111,13 +2105,11 @@ uint32_t v60_device::opSUBW() /* TRUSTED (C too!) */
uint32_t v60_device::opSUBCB()
{
uint8_t appb;
- uint8_t src;
F12DecodeOperands(&v60_device::ReadAM, 0,&v60_device::ReadAMAddress, 0);
F12LOADOP2BYTE();
- src = (uint8_t)m_op1 + (_CY?1:0);
- SUBB(appb, src);
+ SUBB(appb, (uint8_t)m_op1, _CY?1:0);
F12STOREOP2BYTE();
F12END();
@@ -2126,14 +2118,11 @@ uint32_t v60_device::opSUBCB()
uint32_t v60_device::opSUBCH()
{
uint16_t apph;
- uint16_t src;
-
F12DecodeOperands(&v60_device::ReadAM, 1,&v60_device::ReadAMAddress, 1);
F12LOADOP2HALF();
- src = (uint16_t)m_op1 + (_CY?1:0);
- SUBW(apph, src);
+ SUBW(apph, (uint16_t)m_op1, _CY?1:0);
F12STOREOP2HALF();
F12END();
@@ -2142,14 +2131,11 @@ uint32_t v60_device::opSUBCH()
uint32_t v60_device::opSUBCW()
{
uint32_t appw;
- uint32_t src;
-
F12DecodeOperands(&v60_device::ReadAM, 2,&v60_device::ReadAMAddress, 2);
F12LOADOP2WORD();
- src = (uint32_t)m_op1 + (_CY?1:0);
- SUBL(appw, src);
+ SUBL(appw, (uint32_t)m_op1, _CY?1:0);
F12STOREOP2WORD();
F12END();
diff --git a/src/devices/cpu/v60/op3.hxx b/src/devices/cpu/v60/op3.hxx
index 0dac42beaaf..b139cef7dc2 100644
--- a/src/devices/cpu/v60/op3.hxx
+++ b/src/devices/cpu/v60/op3.hxx
@@ -13,7 +13,7 @@ uint32_t v60_device::opINCB() /* TRUSTED */
else
appb = m_program->read_byte(m_amout);
- ADDB(appb, 1);
+ ADDB(appb, 1, 0);
if (m_amflag)
SETREG8(m_reg[m_amout], appb);
@@ -36,7 +36,7 @@ uint32_t v60_device::opINCH() /* TRUSTED */
else
apph = m_program->read_word_unaligned(m_amout);
- ADDW(apph, 1);
+ ADDW(apph, 1, 0);
if (m_amflag)
SETREG16(m_reg[m_amout], apph);
@@ -59,7 +59,7 @@ uint32_t v60_device::opINCW() /* TRUSTED */
else
appw = m_program->read_dword_unaligned(m_amout);
- ADDL(appw, 1);
+ ADDL(appw, 1, 0);
if (m_amflag)
m_reg[m_amout] = appw;
@@ -82,7 +82,7 @@ uint32_t v60_device::opDECB() /* TRUSTED */
else
appb = m_program->read_byte(m_amout);
- SUBB(appb, 1);
+ SUBB(appb, 1, 0);
if (m_amflag)
SETREG8(m_reg[m_amout], appb);
@@ -105,7 +105,7 @@ uint32_t v60_device::opDECH() /* TRUSTED */
else
apph = m_program->read_word_unaligned(m_amout);
- SUBW(apph, 1);
+ SUBW(apph, 1, 0);
if (m_amflag)
SETREG16(m_reg[m_amout], apph);
@@ -128,7 +128,7 @@ uint32_t v60_device::opDECW() /* TRUSTED */
else
appw = m_program->read_dword_unaligned(m_amout);
- SUBL(appw, 1);
+ SUBL(appw, 1, 0);
if (m_amflag)
m_reg[m_amout] = appw;
@@ -417,18 +417,18 @@ uint32_t v60_device::opTASI()
// Load uint8_t from the address
if (m_amflag)
- appb = (uint8_t)m_reg[m_amout & 0x1F];
+ appb = (uint8_t)m_reg[m_amout & 0x1f];
else
appb = m_program->read_byte(m_amout);
// Set the flags for SUB appb, FF
- SUBB(appb, 0xff);
+ SUBB(appb, 0xff, 0);
// Write FF in the operand
if (m_amflag)
- SETREG8(m_reg[m_amout & 0x1F], 0xFF);
+ SETREG8(m_reg[m_amout & 0x1f], 0xff);
else
- m_program->write_byte(m_amout, 0xFF);
+ m_program->write_byte(m_amout, 0xff);
return m_amlength1 + 1;
}
diff --git a/src/devices/cpu/v60/v60.cpp b/src/devices/cpu/v60/v60.cpp
index 32cf642e34b..36671c7cee7 100644
--- a/src/devices/cpu/v60/v60.cpp
+++ b/src/devices/cpu/v60/v60.cpp
@@ -163,13 +163,13 @@ std::unique_ptr<util::disasm_interface> v60_device::create_disassembler()
#define XORW(dst, src) { (dst) ^= (src); _OV = 0; SetSZPF_Word(dst); }
#define XORL(dst, src) { (dst) ^= (src); _OV = 0; SetSZPF_Long(dst); }
-#define SUBB(dst, src) { unsigned res = (dst) - (src); SetCFB(res); SetOFB_Sub(res, src, dst); SetSZPF_Byte(res); dst = (uint8_t)res; }
-#define SUBW(dst, src) { unsigned res = (dst) - (src); SetCFW(res); SetOFW_Sub(res, src, dst); SetSZPF_Word(res); dst = (uint16_t)res; }
-#define SUBL(dst, src) { uint64_t res = (uint64_t)(dst) - (int64_t)(src); SetCFL(res); SetOFL_Sub(res, src, dst); SetSZPF_Long(res); dst = (uint32_t)res; }
+#define SUBB(dst, src, c) { unsigned res = (dst) - (src) - (c); SetCFB(res); SetOFB_Sub(res, src, dst); SetSZPF_Byte(res); dst = (uint8_t)res; }
+#define SUBW(dst, src, c) { unsigned res = (dst) - (src) - (c); SetCFW(res); SetOFW_Sub(res, src, dst); SetSZPF_Word(res); dst = (uint16_t)res; }
+#define SUBL(dst, src, c) { uint64_t res = (uint64_t)(dst) - (int64_t)(src) - (c); SetCFL(res); SetOFL_Sub(res, src, dst); SetSZPF_Long(res); dst = (uint32_t)res; }
-#define ADDB(dst, src) { unsigned res = (dst) + (src); SetCFB(res); SetOFB_Add(res, src, dst); SetSZPF_Byte(res); dst = (uint8_t)res; }
-#define ADDW(dst, src) { unsigned res = (dst) + (src); SetCFW(res); SetOFW_Add(res, src, dst); SetSZPF_Word(res); dst = (uint16_t)res; }
-#define ADDL(dst, src) { uint64_t res = (uint64_t)(dst) + (uint64_t)(src); SetCFL(res); SetOFL_Add(res, src, dst); SetSZPF_Long(res); dst = (uint32_t)res; }
+#define ADDB(dst, src, c) { unsigned res = (dst) + (src) + (c); SetCFB(res); SetOFB_Add(res, src, dst); SetSZPF_Byte(res); dst = (uint8_t)res; }
+#define ADDW(dst, src, c) { unsigned res = (dst) + (src) + (c); SetCFW(res); SetOFW_Add(res, src, dst); SetSZPF_Word(res); dst = (uint16_t)res; }
+#define ADDL(dst, src, c) { uint64_t res = (uint64_t)(dst) + (uint64_t)(src) + (c); SetCFL(res); SetOFL_Add(res, src, dst); SetSZPF_Long(res); dst = (uint32_t)res; }
#define SETREG8(a, b) (a) = ((a) & ~0xff) | ((b) & 0xff)
#define SETREG16(a, b) (a) = ((a) & ~0xffff) | ((b) & 0xffff)
diff --git a/src/devices/cpu/v810/v810.cpp b/src/devices/cpu/v810/v810.cpp
index 058a9f976cb..0c90b737c8f 100644
--- a/src/devices/cpu/v810/v810.cpp
+++ b/src/devices/cpu/v810/v810.cpp
@@ -179,15 +179,9 @@ std::unique_ptr<util::disasm_interface> v810_device::create_disassembler()
#define SO(opcode) (((opcode)&0xfc00)>>10)
#define CHECK_CY(x) PSW=(PSW & ~8)|(((x) & (((uint64_t)1) << 32)) ? 8 : 0)
-#define CHECK_OVADD(x,y,z) PSW=(PSW & ~0x00000004) |(( ((x) ^ (z)) & ((y) ^ (z)) & 0x80000000) ? 4: 0)
-#define CHECK_OVSUB(x,y,z) PSW=(PSW & ~0x00000004) |(( ((y) ^ (z)) & ((x) ^ (y)) & 0x80000000) ? 4: 0)
-#define CHECK_ZS(x) PSW=(PSW & ~3)|((uint32_t)(x)==0)|(((x)&0x80000000) ? 2: 0)
-
-
-#define ADD(dst, src) { uint64_t res=(uint64_t)(dst)+(uint64_t)(src); SetCF(res); SetOF_Add(res,src,dst); SetSZPF(res); dst=(uint32_t)res; }
-#define SUB(dst, src) { uint64_t res=(uint64_t)(dst)-(int64_t)(src); SetCF(res); SetOF_Sub(res,src,dst); SetSZPF(res); dst=(uint32_t)res; }
-
-
+#define CHECK_OVADD(x,y,z) PSW=(PSW & ~0x00000004) |(( ((x) ^ (z)) & ((y) ^ (z)) & 0x80000000) ? 4 : 0)
+#define CHECK_OVSUB(x,y,z) PSW=(PSW & ~0x00000004) |(( ((y) ^ (z)) & ((x) ^ (y)) & 0x80000000) ? 4 : 0)
+#define CHECK_ZS(x) PSW=(PSW & ~3)|((uint32_t)(x)==0)|(((x)&0x80000000) ? 2 : 0)
// r0 is literally a "register zero", reading returns 0, writing is ignored.