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author Hannes Janetzek <hannes.janetzek@gmail.com>2026-04-07 14:23:06 +0200
committer GitHub <noreply@github.com>2026-04-07 08:23:06 -0400
commit4a3ec26ee0f66f529c80081d8f231d0ebebd7c85 (patch)
tree3e04a11e2c8ff5b8aeef8599ae36f1b78262d5fe /src/devices/cpu
parentdb5b9d7a3cb1b1130a5ba1436f477b0df5438866 (diff)
z8: Fix disassembly of opcode D7 (LD x(r2), r1 - indexed register write) (#15199)
The register nibble roles were swapped and the operand order showed it as a read instead of a write. Both C7 and D7 encode byte 1 the same way (high nibble = r1, low nibble = r2). The only difference is operand order: C7 reads from indexed, D7 writes to indexed. Before: D7 DC 01 disassembles as "LD R12, 01h(R13)" After: D7 DC 01 disassembles as "LD 01h(R12), R13"
Diffstat (limited to 'src/devices/cpu')
-rw-r--r--src/devices/cpu/z8/z8dasm.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/cpu/z8/z8dasm.cpp b/src/devices/cpu/z8/z8dasm.cpp
index beef0da436a..109975a2fc7 100644
--- a/src/devices/cpu/z8/z8dasm.cpp
+++ b/src/devices/cpu/z8/z8dasm.cpp
@@ -336,7 +336,7 @@ offs_t z8_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_
case 0xd4: mnemonic("CALL"); arg_IRR(B0); bytes(2); step_over; break;
case 0xd5: illegal; break;
case 0xd6: mnemonic("CALL"); arg_DA; bytes(3); step_over; break;
- case 0xd7: mnemonic("LD"); arg_r(B0L); arg_X(B1, B0H); bytes(3); break;
+ case 0xd7: mnemonic("LD"); arg_X(B1, B0L); arg_r(B0H); bytes(3); break;
case 0xd8: mnemonic("LD"); arg_r(OPH); arg_R(B0); bytes(2); break;
case 0xd9: mnemonic("LD"); arg_R(B0); arg_r(OPH); bytes(2); break;
case 0xda: mnemonic("DJNZ"); arg_r(OPH); arg_RA; bytes(2); step_cond; break;