diff options
author | 2019-05-08 22:08:17 +0100 | |
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committer | 2019-05-08 17:08:17 -0400 | |
commit | b12fea69b299dd75dc73408b4a99625cebb46635 (patch) | |
tree | 273bbeca997c9167914bd962edb1fd50bfcd4a74 /src/devices/cpu/unsp/unspdasm_extended.cpp | |
parent | 6650d0c7bc9b19d88dd8e25b10268e41e85f3a87 (diff) |
smartfp clearly uses unsp isa20 push/pop instructions in the interrupt (#5015)
* smartfp clearly uses unsp isa20 push/pop instructions in the interrupt function even if nowhere else in the code (nw)
* (nw)
Diffstat (limited to 'src/devices/cpu/unsp/unspdasm_extended.cpp')
-rw-r--r-- | src/devices/cpu/unsp/unspdasm_extended.cpp | 96 |
1 files changed, 52 insertions, 44 deletions
diff --git a/src/devices/cpu/unsp/unspdasm_extended.cpp b/src/devices/cpu/unsp/unspdasm_extended.cpp index a64f726c332..85c252e06bf 100644 --- a/src/devices/cpu/unsp/unspdasm_extended.cpp +++ b/src/devices/cpu/unsp/unspdasm_extended.cpp @@ -30,10 +30,10 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of case 0x00: case 0x10: { // Ext Register Ra = Ra op Rb - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rb = (op & 0x000f) >> 0; - uint8_t ra = (op & 0x0e00) >> 9; - ra |= (op & 0x0100) >> 5; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rb = (ximm & 0x000f) >> 0; + uint8_t ra = (ximm & 0x0e00) >> 9; + ra |= (ximm & 0x0100) >> 5; util::stream_format(stream, "(Ext) %s = %s %s %s", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] @@ -43,28 +43,36 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of } case 0x02: { + // register decoding could be incorrect here + // Ext Push/Pop - if (op & 0x8000) + if (ximm & 0x8000) { - uint8_t rb = (op & 0x000f) >> 0; - uint8_t size = (op & 0x7000) >> 12; - uint8_t rx = (op & 0x0e00) >> 9; + uint8_t rb = (ximm & 0x000f) >> 0; + uint8_t size = (ximm & 0x7000) >> 12; + uint8_t rx = (ximm & 0x0e00) >> 9; + + if (size == 0) size = 8; + size -= 1; - if (rx+1 >= size && rx < size+7) + if ((rx-size) >= 0) util::stream_format(stream, "(Ext) push %s, %s to [%s]", - extregs[rx+1-size], extregs[rx], (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); + extregs[rx-size], extregs[rx], (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); else util::stream_format(stream, "(Ext) push <BAD>"); } else { - uint8_t rb = (op & 0x000f) >> 0; - uint8_t size = (op & 0x7000) >> 12; - uint8_t rx = (op & 0x0e00) >> 9; + uint8_t rb = (ximm & 0x000f) >> 0; + uint8_t size = (ximm & 0x7000) >> 12; + uint8_t rx = (ximm & 0x0e00) >> 9; + + if (size == 0) size = 8; + size -= 1; - if (rx+1 < 8 && rx+size < 8) + if ((rx-size) >= 0) util::stream_format(stream, "(Ext) pop %s, %s from [%s]", - extregs[rx+1], extregs[rx+size], (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); + extregs[rx-size], extregs[rx], (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7]); else util::stream_format(stream, "(Ext) pop <BAD>"); } @@ -75,10 +83,10 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of // Ra=Rb op IMM16 len = 3; uint16_t imm16_2 = opcodes.r16(pc + 2); - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rb = (op & 0x000f) >> 0; - uint8_t ra = (op & 0x0e00) >> 9; - ra |= (op & 0x0100) >> 5; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rb = (ximm & 0x000f) >> 0; + uint8_t ra = (ximm & 0x0e00) >> 9; + ra |= (ximm & 0x0100) >> 5; util::stream_format(stream, "(Ext) %s = %s %s %04x", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] @@ -93,10 +101,10 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of // Ra=Rb op [A16] len = 3; uint16_t imm16_2 = opcodes.r16(pc + 2); - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rb = (op & 0x000f) >> 0; - uint8_t ra = (op & 0x0e00) >> 9; - ra |= (op & 0x0100) >> 5; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rb = (ximm & 0x000f) >> 0; + uint8_t ra = (ximm & 0x0e00) >> 9; + ra |= (ximm & 0x0100) >> 5; util::stream_format(stream, "(Ext) %s = %s %s [%04x]", (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] , (rb & 0x8) ? extregs[rb & 0x7] : regs[rb & 0x7] @@ -111,10 +119,10 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of //[A16] = Ra op Rb len = 3; uint16_t imm16_2 = opcodes.r16(pc + 2); - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rb = (op & 0x000f) >> 0; - uint8_t ra = (op & 0x0e00) >> 9; - ra |= (op & 0x0100) >> 5; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rb = (ximm & 0x000f) >> 0; + uint8_t ra = (ximm & 0x0e00) >> 9; + ra |= (ximm & 0x0100) >> 5; util::stream_format(stream, "(Ext) [0x4x] = %s %s %s", imm16_2 , (ra & 0x8) ? extregs[ra & 0x7] : regs[ra & 0x7] @@ -127,10 +135,10 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of { // Ext Indirect Rx=Rx op [Ry@] - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t ry = (op & 0x0007) >> 0; - uint8_t form = (op & 0x0018) >> 3; - uint8_t rx = (op & 0x0e00) >> 9; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t ry = (ximm & 0x0007) >> 0; + uint8_t form = (ximm & 0x0018) >> 3; + uint8_t rx = (ximm & 0x0e00) >> 9; util::stream_format(stream, "(Ext) %s=%s %s", extregs[rx], extregs[rx], aluops[aluop]); util::stream_format(stream, forms[form], extregs[ry]); @@ -141,10 +149,10 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of { // Ext DS_Indirect Rx=Rx op ds:[Ry@] - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t ry = (op & 0x0007) >> 0; - uint8_t form = (op & 0x0018) >> 3; - uint8_t rx = (op & 0x0e00) >> 9; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t ry = (ximm & 0x0007) >> 0; + uint8_t form = (ximm & 0x0018) >> 3; + uint8_t rx = (ximm & 0x0e00) >> 9; util::stream_format(stream, "(Ext) %s=%s %s ds:", extregs[rx], extregs[rx], aluops[aluop]); util::stream_format(stream, forms[form], extregs[ry]); @@ -155,9 +163,9 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of { // Ext IM6 Rx=Rx op IM6 - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rx = (op & 0x0e00) >> 9; - uint8_t imm6 = (op & 0x003f) >> 0; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rx = (ximm & 0x0e00) >> 9; + uint8_t imm6 = (ximm & 0x003f) >> 0; util::stream_format(stream, "(Ext) %s=%s %s %02x", extregs[rx], extregs[rx], aluops[aluop], imm6 ); return UNSP_DASM_OK; @@ -167,9 +175,9 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of { // Ext Base+Disp6 Rx=Rx op [BP+IM6] - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rx = (op & 0x0e00) >> 9; - uint8_t imm6 = (op & 0x003f) >> 0; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rx = (ximm & 0x0e00) >> 9; + uint8_t imm6 = (ximm & 0x003f) >> 0; util::stream_format(stream, "(Ext) %s=%s %s [BP+%02x]", extregs[rx], extregs[rx], aluops[aluop], imm6 ); return UNSP_DASM_OK; @@ -179,9 +187,9 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of { // Ext A6 Rx=Rx op [A6] - uint8_t aluop = (op & 0xf000) >> 12; - uint8_t rx = (op & 0x0e00) >> 9; - uint8_t a6 = (op & 0x003f) >> 0; + uint8_t aluop = (ximm & 0xf000) >> 12; + uint8_t rx = (ximm & 0x0e00) >> 9; + uint8_t a6 = (ximm & 0x003f) >> 0; util::stream_format(stream, "(Ext) %s=%s %s [%02x]", extregs[rx], extregs[rx], aluops[aluop], a6 ); return UNSP_DASM_OK; |