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author Olivier Galibert <galibert@pobox.com>2024-05-18 12:42:41 +0200
committer Olivier Galibert <galibert@pobox.com>2024-05-18 12:43:16 +0200
commit8c5a984fa0ff8317d778e0b154b8959e396bdc2f (patch)
treedbadf7872d0676fd7f40e871b7edbafcb1df40a1 /docs/source/techspecs/cpu_device.rst
parentafa05a62f817b95269a557a7b839b768ccae770d (diff)
docs: Proofreading [Robert]
Diffstat (limited to 'docs/source/techspecs/cpu_device.rst')
-rw-r--r--docs/source/techspecs/cpu_device.rst6
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/source/techspecs/cpu_device.rst b/docs/source/techspecs/cpu_device.rst
index 971641fa1d3..a3ca460796e 100644
--- a/docs/source/techspecs/cpu_device.rst
+++ b/docs/source/techspecs/cpu_device.rst
@@ -30,9 +30,9 @@ TODO.
~~~~~~~~~~~~~~
An interruptible CPU is defined as a core which is able to suspend the
-execution of a instruction at any time, exit execute_run, then at the
-next call of ``execute_run`` keep going from where it was. This
-includes begin able to abort an issued memory access, quit
+execution of one instruction at any time, exit execute_run, then at
+the next call of ``execute_run`` keep going from where it was. This
+includes being able to abort an issued memory access, quit
execute_run, then upon the next call of execute_run reissue the exact
same access.