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author Olivier Galibert <galibert@pobox.com>2024-05-18 12:42:41 +0200
committer Olivier Galibert <galibert@pobox.com>2024-05-18 12:43:16 +0200
commit8c5a984fa0ff8317d778e0b154b8959e396bdc2f (patch)
treedbadf7872d0676fd7f40e871b7edbafcb1df40a1 /docs/source/techspecs
parentafa05a62f817b95269a557a7b839b768ccae770d (diff)
docs: Proofreading [Robert]
Diffstat (limited to 'docs/source/techspecs')
-rw-r--r--docs/source/techspecs/cpu_device.rst6
-rw-r--r--docs/source/techspecs/memory.rst4
2 files changed, 5 insertions, 5 deletions
diff --git a/docs/source/techspecs/cpu_device.rst b/docs/source/techspecs/cpu_device.rst
index 971641fa1d3..a3ca460796e 100644
--- a/docs/source/techspecs/cpu_device.rst
+++ b/docs/source/techspecs/cpu_device.rst
@@ -30,9 +30,9 @@ TODO.
~~~~~~~~~~~~~~
An interruptible CPU is defined as a core which is able to suspend the
-execution of a instruction at any time, exit execute_run, then at the
-next call of ``execute_run`` keep going from where it was. This
-includes begin able to abort an issued memory access, quit
+execution of one instruction at any time, exit execute_run, then at
+the next call of ``execute_run`` keep going from where it was. This
+includes being able to abort an issued memory access, quit
execute_run, then upon the next call of execute_run reissue the exact
same access.
diff --git a/docs/source/techspecs/memory.rst b/docs/source/techspecs/memory.rst
index 783771fbea5..9f0a31758c7 100644
--- a/docs/source/techspecs/memory.rst
+++ b/docs/source/techspecs/memory.rst
@@ -281,7 +281,7 @@ view can be re-enabled at any time.
3.5 Bus contention handling
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Some specific CPUs have be upgraded to be interruptible which allows
+Some specific CPUs have been upgraded to be interruptible which allows
to add bus contention and wait states capabitilites. Being
interruptible means, in practice, that an instruction can be
interrupted at any time and the execute_run method of the core exited.
@@ -328,7 +328,7 @@ cycle will be aborted for lack of remaining time, and the method will
eventually be called again. It will then give the time of when the
second dma will finish, and all will be well.
-It can also allow to reduce said earlier time when circonstances
+It can also allow to reduce said earlier time when circumstances
require it. For instance a PIO latch that waits up to 64 cycles that
data arrives can indicate that current time + 64 as a target (which
will trigger a bus error for instance) but if a timer elapses and