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author | 2016-04-12 08:36:14 -0400 | |
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committer | 2016-04-12 08:36:14 -0400 | |
commit | b47168d7e6e002a7c478a0a42e4f97c56ec280dc (patch) | |
tree | 94e4a1e9b0b108f399940a981044c824d371f552 | |
parent | 21a7aabf9e07f8900846cf91bd1711f9a208ad08 (diff) | |
parent | d630e05f982a6b2ba89119f47ad20376389b79cf (diff) |
Merge pull request #805 from Happy-yappH/master
mips3: Branch and Link instructions unconditionally set return addres…
-rw-r--r-- | src/devices/cpu/mips/mips3.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/devices/cpu/mips/mips3.cpp b/src/devices/cpu/mips/mips3.cpp index b3c19faf6fa..c09088fd669 100644 --- a/src/devices/cpu/mips/mips3.cpp +++ b/src/devices/cpu/mips/mips3.cpp @@ -67,7 +67,6 @@ #define FDVALL_FR1 (*(UINT64 *)&m_core->cpr[1][FDREG]) #define ADDPC(x) m_nextpc = m_core->pc + ((x) << 2) -#define ADDPCL(x,l) { m_nextpc = m_core->pc + ((x) << 2); m_core->r[l] = (INT32)(m_core->pc + 4); } #define ABSPC(x) m_nextpc = (m_core->pc & 0xf0000000) | ((x) << 2) #define ABSPCL(x,l) { m_nextpc = (m_core->pc & 0xf0000000) | ((x) << 2); m_core->r[l] = (INT32)(m_core->pc + 4); } #define SETPC(x) m_nextpc = (x) @@ -2551,10 +2550,10 @@ void mips3_device::handle_regimm(UINT32 op) case 0x0b: /* TLTIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; case 0x0c: /* TEQI */ if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; case 0x0e: /* TNEI */ if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break; - case 0x10: /* BLTZAL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31); break; - case 0x11: /* BGEZAL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31); break; - case 0x12: /* BLTZALL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break; - case 0x13: /* BGEZALL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break; + case 0x10: /* BLTZAL */ m_core->r[31] = (INT32)(m_core->pc + 4); if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); break; + case 0x11: /* BGEZAL */ m_core->r[31] = (INT32)(m_core->pc + 4); if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); break; + case 0x12: /* BLTZALL */ m_core->r[31] = (INT32)(m_core->pc + 4); if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break; + case 0x13: /* BGEZALL */ m_core->r[31] = (INT32)(m_core->pc + 4); if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break; default: /* ??? */ invalid_instruction(op); break; } } |