diff options
author | 2016-05-01 09:51:51 +0200 | |
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committer | 2016-05-01 09:51:51 +0200 | |
commit | 949fddaaa8d5f68d96226440aaf81ea82aa70280 (patch) | |
tree | ffdfb37cbc4c018ec158f4ab970758a85d9f9332 | |
parent | 58c42b6993a794b181311262b26c601ac2baa465 (diff) |
hec2hrp and arcompact fix (nw)
-rw-r--r-- | scripts/src/cpu.lua | 2 | ||||
-rw-r--r-- | scripts/target/mame/mess.lua | 3 | ||||
-rw-r--r-- | src/mame/machine/hec2hrp.cpp | 136 | ||||
-rw-r--r-- | src/mame/machine/hecdisk2.cpp | 148 | ||||
-rw-r--r-- | src/mame/video/hec2hrp.cpp (renamed from src/mame/video/hec2video.cpp) | 0 |
5 files changed, 137 insertions, 152 deletions
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua index 88fa672139b..69e9eace7ad 100644 --- a/scripts/src/cpu.lua +++ b/scripts/src/cpu.lua @@ -73,7 +73,7 @@ end -------------------------------------------------- -- ARcompact (ARCtangent-A5, ARC 600, ARC 700) ---@src/devices/cpu/arc/arc.h,CPUS["ARCOMPACT"] = true +--@src/devices/cpu/arcompact/arcompact.h,CPUS["ARCOMPACT"] = true -------------------------------------------------- if (CPUS["ARCOMPACT"]~=null) then diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua index 5fcbcb23c3f..8c9c9aca9f1 100644 --- a/scripts/target/mame/mess.lua +++ b/scripts/target/mame/mess.lua @@ -1841,8 +1841,7 @@ files { MAME_DIR .. "src/mame/drivers/hec2hrp.cpp", MAME_DIR .. "src/mame/includes/hec2hrp.h", MAME_DIR .. "src/mame/machine/hec2hrp.cpp", - MAME_DIR .. "src/mame/machine/hecdisk2.cpp", - MAME_DIR .. "src/mame/video/hec2video.cpp", + MAME_DIR .. "src/mame/video/hec2hrp.cpp", MAME_DIR .. "src/mame/drivers/interact.cpp", } diff --git a/src/mame/machine/hec2hrp.cpp b/src/mame/machine/hec2hrp.cpp index 6ed49982f7f..fce1e0bb453 100644 --- a/src/mame/machine/hec2hrp.cpp +++ b/src/mame/machine/hec2hrp.cpp @@ -1,7 +1,6 @@ // license:BSD-3-Clause // copyright-holders:JJ Stacino ///////////////////////////////////////////////////////////////////////// -// HEC2HRP.C in machine /* Hector 2HR+ Victor Hector 2HR @@ -49,6 +48,8 @@ #include "formats/hect_tap.h" #include "includes/hec2hrp.h" +#include "formats/hect_dsk.h" +#include "cpu/z80/z80.h" #ifndef DEBUG_TRACE_COM_HECTOR //#define DEBUG_TRACE_COM_HECTOR 1 @@ -820,3 +821,136 @@ MACHINE_CONFIG_FRAGMENT( hector_audio ) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) MACHINE_CONFIG_END + +/* Lecteur de disquette DISK II pour les machines : + Hector HRX + Hector MX40c + Hector MX80c + + JJStacino jj.stacino@aliceadsl.fr + + 15/02/2010 : Start of the disc2 project! JJStacino + 26/09/2010 : first sending with bug2 (the first "dir" command finih with a crash of the Z80 disc II proc) JJStacino + 01/11/2010 : first time ending boot sequence, probleme on the CP/M lauch JJStacino + 20/11/2010 : synchronization between uPD765 and Z80 are now OK, CP/M runnig! JJStacino + 28/11/2010 : Found at Bratislava that the disk writing with TRANS X: is NOT WORKING (the exchange Hector=>Disc2 ok) +*/ + +/* Callback uPD request */ + +/* How uPD765 works: + * First we send at uPD the string of command (p.e. 9 bytes for read starting by 0x46) on port 60h + between each byte, check the authorization of the uPD by reading the status register + * When the command is finish, the data arrive with DMA interrupt, then: + If read: in port 70 to retrieve the data, + If write: in port 70 send the data + * When all data had been send the uPD launch an INT + * The Z80 Disc2 writes in FF12 a flag + * if the flag is set, end of DMA function, + * At this point the Z80 can read the RESULT in port 61h +*/ + +/*****************************************************************************/ +/**** Management of the interrupts (NMI and INT)between uPD765 and Z80 ******/ +/*****************************************************************************/ + +/* upd765 INT is connected to interrupt of Z80 within a RNMI hardware authorization */ +WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_interrupt ) +{ + m_IRQ_current_state = state; + m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); +} + +/* upd765 DRQ is connected to NMI of Z80 within a RNMI hardware authorization */ +WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_dma_irq ) +{ + m_NMI_current_state = state; + m_disc2cpu->set_input_line(INPUT_LINE_NMI, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); +} + +// RESET the disc2 Unit ! +void hec2hrp_state::hector_disc2_reset() +{ + // Initialization Disc2 unit + m_disc2cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE); + machine().device<upd765a_device>("upd765")->reset(); + // Select ROM memory to cold restart + membank("bank3")->set_entry(DISCII_BANK_ROM); + + // Clear the Hardware's buffers + m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */ + m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */ + m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */ + m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */ + m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */ + m_IRQ_current_state=0; /* Clear the IRQ active request */ + m_NMI_current_state=0; /* Clear the DMA active request */ +} + +/*****************************************************************************/ +/******************** Port handling of the Z80 Disc II unit *****************/ +/*****************************************************************************/ +READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r) +{ + /* Switch Disc 2 to RAM to let full RAM acces */ + membank("bank3")->set_entry(DISCII_BANK_RAM); + return 0; +} +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w) +{ + /* Switch Disc 2 to RAM to let full RAM acces */ + membank("bank3")->set_entry(DISCII_BANK_RAM); +} +READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r) +{ + // You can implemente the 8251 chip communication here ! + return 0; +} +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w) +{ + // You can implemente the 8251 chip communication here ! +} +READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r) +{ + return m_hector_disc2_data_r_ready; +} +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w) +{ + // Nothing here ! +} + +READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r) +{ + /* Read data send by Hector, by Disc2*/ + m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/ + return m_hector_disc2_data_read; /* send the data !*/ +} + +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/ +{ + m_hector_disc2_data_write = data; /* Memorization data*/ + m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/ +} + +READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r) /*Read memory info write ready*/ +{ + return m_hector_disc2_data_w_ready; +} + +WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/ +{ + upd765a_device *fdc = machine().device<upd765a_device>("upd765"); + + /* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */ + machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A: + machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B: + + /* Write bit TC uPD765 on D4 of port I/O 50 */ + fdc->tc_w(BIT(data, 4)); + + + /* Authorization interrupt and NMI with RNMI signal*/ + m_hector_disc2_RNMI = BIT(data, 5); + m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_IRQ_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); + m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_NMI_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); +} diff --git a/src/mame/machine/hecdisk2.cpp b/src/mame/machine/hecdisk2.cpp deleted file mode 100644 index 16cc67300c9..00000000000 --- a/src/mame/machine/hecdisk2.cpp +++ /dev/null @@ -1,148 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:JJ Stacino -/*******************************************************/ -/************ HECDISK2.C in machine ******************/ -/*******************************************************/ - -/* Lecteur de disquette DISK II pour les machines : - Hector HRX - Hector MX40c - Hector MX80c - - JJStacino jj.stacino@aliceadsl.fr - - 15/02/2010 : Start of the disc2 project! JJStacino - 26/09/2010 : first sending with bug2 (the first "dir" command finih with a crash of the Z80 disc II proc) JJStacino - 01/11/2010 : first time ending boot sequence, probleme on the CP/M lauch JJStacino - 20/11/2010 : synchronization between uPD765 and Z80 are now OK, CP/M runnig! JJStacino - 28/11/2010 : Found at Bratislava that the disk writing with TRANS X: is NOT WORKING (the exchange Hector=>Disc2 ok) -*/ - -#include "emu.h" - -#include "sound/wave.h" /* for K7 sound*/ -#include "sound/discrete.h" /* for 1 Bit sound*/ -#include "machine/upd765.h" /* for floppy disc controller */ -#include "formats/hect_dsk.h" -#include "cpu/z80/z80.h" - -#include "includes/hec2hrp.h" - -/* Callback uPD request */ - -/* How uPD765 works: - * First we send at uPD the string of command (p.e. 9 bytes for read starting by 0x46) on port 60h - between each byte, check the authorization of the uPD by reading the status register - * When the command is finish, the data arrive with DMA interrupt, then: - If read: in port 70 to retrieve the data, - If write: in port 70 send the data - * When all data had been send the uPD launch an INT - * The Z80 Disc2 writes in FF12 a flag - * if the flag is set, end of DMA function, - * At this point the Z80 can read the RESULT in port 61h -*/ - -/*****************************************************************************/ -/**** Management of the interrupts (NMI and INT)between uPD765 and Z80 ******/ -/*****************************************************************************/ - -/* upd765 INT is connected to interrupt of Z80 within a RNMI hardware authorization */ -WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_interrupt ) -{ - m_IRQ_current_state = state; - m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); -} - -/* upd765 DRQ is connected to NMI of Z80 within a RNMI hardware authorization */ -WRITE_LINE_MEMBER( hec2hrp_state::disc2_fdc_dma_irq ) -{ - m_NMI_current_state = state; - m_disc2cpu->set_input_line(INPUT_LINE_NMI, state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); -} - -// RESET the disc2 Unit ! -void hec2hrp_state::hector_disc2_reset() -{ - // Initialization Disc2 unit - m_disc2cpu->set_input_line(INPUT_LINE_RESET, PULSE_LINE); - machine().device<upd765a_device>("upd765")->reset(); - // Select ROM memory to cold restart - membank("bank3")->set_entry(DISCII_BANK_ROM); - - // Clear the Hardware's buffers - m_hector_disc2_data_r_ready=0x0; /* =ff when PC2 = true and data in read buffer (state->m_hector_disc2_data_read) */ - m_hector_disc2_data_w_ready=0x0; /* =ff when Disc 2 Port 40 had send a data in write buffer (state->m_hector_disc2_data_write) */ - m_hector_disc2_data_read=0; /* Data send by Hector to Disc 2 when PC2=true */ - m_hector_disc2_data_write=0; /* Data send by Disc 2 to Hector when Write Port I/O 40 */ - m_hector_disc2_RNMI = 0; /* State of I/O 50 D5 = authorization for INT / NMI */ - m_IRQ_current_state=0; /* Clear the IRQ active request */ - m_NMI_current_state=0; /* Clear the DMA active request */ -} - -/*****************************************************************************/ -/******************** Port handling of the Z80 Disc II unit *****************/ -/*****************************************************************************/ -READ8_MEMBER( hec2hrp_state::hector_disc2_io00_port_r) -{ - /* Switch Disc 2 to RAM to let full RAM acces */ - membank("bank3")->set_entry(DISCII_BANK_RAM); - return 0; -} -WRITE8_MEMBER( hec2hrp_state::hector_disc2_io00_port_w) -{ - /* Switch Disc 2 to RAM to let full RAM acces */ - membank("bank3")->set_entry(DISCII_BANK_RAM); -} -READ8_MEMBER( hec2hrp_state::hector_disc2_io20_port_r) -{ - // You can implemente the 8251 chip communication here ! - return 0; -} -WRITE8_MEMBER( hec2hrp_state::hector_disc2_io20_port_w) -{ - // You can implemente the 8251 chip communication here ! -} -READ8_MEMBER( hec2hrp_state::hector_disc2_io30_port_r) -{ - return m_hector_disc2_data_r_ready; -} -WRITE8_MEMBER( hec2hrp_state::hector_disc2_io30_port_w) -{ - // Nothing here ! -} - -READ8_MEMBER( hec2hrp_state::hector_disc2_io40_port_r) -{ - /* Read data send by Hector, by Disc2*/ - m_hector_disc2_data_r_ready = 0x00; /* Clear memory info read ready*/ - return m_hector_disc2_data_read; /* send the data !*/ -} - -WRITE8_MEMBER( hec2hrp_state::hector_disc2_io40_port_w) /* Write data send by Disc2, to Hector*/ -{ - m_hector_disc2_data_write = data; /* Memorization data*/ - m_hector_disc2_data_w_ready = 0x80; /* Memorization data write ready in D7*/ -} - -READ8_MEMBER( hec2hrp_state::hector_disc2_io50_port_r) /*Read memory info write ready*/ -{ - return m_hector_disc2_data_w_ready; -} - -WRITE8_MEMBER( hec2hrp_state::hector_disc2_io50_port_w) /* I/O Port to the stuff of Disc2*/ -{ - upd765a_device *fdc = machine().device<upd765a_device>("upd765"); - - /* FDC Motor Control - Bit 0/1 defines the state of the FDD 0/1 motor */ - machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(BIT(data, 0)); // Moteur floppy A: - machine().device<floppy_connector>("upd765:1")->get_device()->mon_w(BIT(data, 1)); // Moteur floppy B: - - /* Write bit TC uPD765 on D4 of port I/O 50 */ - fdc->tc_w(BIT(data, 4)); - - - /* Authorization interrupt and NMI with RNMI signal*/ - m_hector_disc2_RNMI = BIT(data, 5); - m_disc2cpu->set_input_line(INPUT_LINE_IRQ0, m_IRQ_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); - m_disc2cpu->set_input_line(INPUT_LINE_NMI, m_NMI_current_state && m_hector_disc2_RNMI ? ASSERT_LINE : CLEAR_LINE); -} diff --git a/src/mame/video/hec2video.cpp b/src/mame/video/hec2hrp.cpp index f16f23b8363..f16f23b8363 100644 --- a/src/mame/video/hec2video.cpp +++ b/src/mame/video/hec2hrp.cpp |