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author Mark Garlanger <mgarlanger@users.noreply.github.com>2025-01-02 00:36:37 -0600
committer GitHub <noreply@github.com>2025-01-02 13:36:37 +0700
commit91710ed6690e05b324b6f09c055f9dd106b9728d (patch)
treeae6ce0d8deaa02739fc12c1d03da4ca0849b31a7
parente745009c30879e63c628b9c2556a6b6e22c5af17 (diff)
heathzenith/h19/tlb.cpp: Make the page 2 memory option configurable (#13082)
-rw-r--r--src/devices/bus/heathzenith/h19/tlb.cpp54
-rw-r--r--src/devices/bus/heathzenith/h19/tlb.h10
-rw-r--r--src/mame/heathzenith/h89.cpp8
3 files changed, 57 insertions, 15 deletions
diff --git a/src/devices/bus/heathzenith/h19/tlb.cpp b/src/devices/bus/heathzenith/h19/tlb.cpp
index 10b384b22cb..751547f42f6 100644
--- a/src/devices/bus/heathzenith/h19/tlb.cpp
+++ b/src/devices/bus/heathzenith/h19/tlb.cpp
@@ -835,6 +835,12 @@ static INPUT_PORTS_START( ultra19 )
PORT_DIPNAME( 0x80, 0x00, "Interlace Scan Mode") PORT_DIPLOCATION("SW402:8")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x80, DEF_STR( On ) )
+
+ PORT_MODIFY("CONFIG")
+ PORT_CONFNAME(0x10, 0x10, "Page 2 RAM present")
+ PORT_DIPSETTING( 0x00, DEF_STR( No ) )
+ PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
+
INPUT_PORTS_END
@@ -1316,10 +1322,23 @@ ioport_constructor heath_watz_tlb_device::device_input_ports() const
* Developed by William G. Parrott, III, sold by Software Wizardry, Inc.
*/
heath_ultra_tlb_device::heath_ultra_tlb_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
- heath_tlb_device(mconfig, HEATH_ULTRA, tag, owner, clock)
+ heath_tlb_device(mconfig, HEATH_ULTRA, tag, owner, clock),
+ m_maincpu_region(*this, "maincpu"),
+ m_page_2_ram(*this, "page2ram"),
+ m_mem_view(*this, "mem")
{
}
+void heath_ultra_tlb_device::device_reset()
+{
+ heath_tlb_device::device_reset();
+
+ ioport_value const cfg(m_config->read());
+
+ // Page 2 memory
+ m_mem_view.select(BIT(cfg, 4));
+}
+
void heath_ultra_tlb_device::device_add_mconfig(machine_config &config)
{
heath_tlb_device::device_add_mconfig(config);
@@ -1331,11 +1350,11 @@ void heath_ultra_tlb_device::mem_map(address_map &map)
{
heath_tlb_device::mem_map(map);
- // update rom mirror setting to allow page 2 memory
- map(0x0000, 0x0fff).mirror(0x2000).rom();
+ map(0x0000, 0x3fff).view(m_mem_view);
- // Page 2 memory
- map(0x1000, 0x1fff).mirror(0x2000).ram();
+ m_mem_view[0](0x0000, 0x0fff).mirror(0x3000).rom().region(m_maincpu_region, 0x0000).unmapw();
+ m_mem_view[1](0x0000, 0x0fff).mirror(0x2000).rom().region(m_maincpu_region, 0x0000).unmapw();
+ m_mem_view[1](0x1000, 0x1fff).mirror(0x2000).ram().share(m_page_2_ram);
}
const tiny_rom_entry *heath_ultra_tlb_device::device_rom_region() const
@@ -1954,13 +1973,26 @@ ioport_constructor heath_igc_super19_tlb_device::device_input_ports() const
*
*/
heath_igc_ultra_tlb_device::heath_igc_ultra_tlb_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
- heath_igc_tlb_device(mconfig, HEATH_IGC_ULTRA, tag, owner, clock)
+ heath_igc_tlb_device(mconfig, HEATH_IGC_ULTRA, tag, owner, clock),
+ m_maincpu_region(*this, "maincpu"),
+ m_page_2_ram(*this, "page2ram"),
+ m_mem_view(*this, "mem")
{
}
+void heath_igc_ultra_tlb_device::device_reset()
+{
+ heath_igc_tlb_device::device_reset();
+
+ ioport_value const cfg(m_config->read());
+
+ // Page 2 memory
+ m_mem_view.select(BIT(cfg, 4));
+}
+
void heath_igc_ultra_tlb_device::device_add_mconfig(machine_config &config)
{
- heath_tlb_device::device_add_mconfig(config);
+ heath_igc_tlb_device::device_add_mconfig(config);
m_maincpu->set_addrmap(AS_PROGRAM, &heath_igc_ultra_tlb_device::mem_map);
}
@@ -1969,11 +2001,11 @@ void heath_igc_ultra_tlb_device::mem_map(address_map &map)
{
heath_tlb_device::mem_map(map);
- // update rom mirror setting to allow page 2 memory
- map(0x0000, 0x0fff).mirror(0x2000).rom();
+ map(0x0000, 0x3fff).view(m_mem_view);
- // Page 2 memory
- map(0x1000, 0x1fff).mirror(0x2000).ram();
+ m_mem_view[0](0x0000, 0x0fff).mirror(0x3000).rom().region(m_maincpu_region, 0x0000).unmapw();
+ m_mem_view[1](0x0000, 0x0fff).mirror(0x2000).rom().region(m_maincpu_region, 0x0000).unmapw();
+ m_mem_view[1](0x1000, 0x1fff).mirror(0x2000).ram().share(m_page_2_ram);
}
const tiny_rom_entry *heath_igc_ultra_tlb_device::device_rom_region() const
diff --git a/src/devices/bus/heathzenith/h19/tlb.h b/src/devices/bus/heathzenith/h19/tlb.h
index db216209bca..1bdd3ac4fdf 100644
--- a/src/devices/bus/heathzenith/h19/tlb.h
+++ b/src/devices/bus/heathzenith/h19/tlb.h
@@ -220,9 +220,14 @@ public:
protected:
virtual const tiny_rom_entry *device_rom_region() const override ATTR_COLD;
virtual ioport_constructor device_input_ports() const override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
void mem_map(address_map &map) ATTR_COLD;
+
+ required_memory_region m_maincpu_region;
+ required_shared_ptr<u8> m_page_2_ram;
+ memory_view m_mem_view;
};
/**
@@ -374,9 +379,14 @@ public:
protected:
virtual const tiny_rom_entry *device_rom_region() const override ATTR_COLD;
virtual ioport_constructor device_input_ports() const override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
void mem_map(address_map &map) ATTR_COLD;
+
+ required_memory_region m_maincpu_region;
+ required_shared_ptr<u8> m_page_2_ram;
+ memory_view m_mem_view;
};
/**
diff --git a/src/mame/heathzenith/h89.cpp b/src/mame/heathzenith/h89.cpp
index fec89e8763f..acc8a460189 100644
--- a/src/mame/heathzenith/h89.cpp
+++ b/src/mame/heathzenith/h89.cpp
@@ -296,16 +296,16 @@ void h89_base_state::h89_mem(address_map &map)
// View 0 - ROM / Floppy RAM R/O
// View 1 - ROM / Floppy RAM R/W
// monitor ROM
- m_mem_view[0](0x0000, 0x0fff).rom().region("maincpu", 0).unmapw();
- m_mem_view[1](0x0000, 0x0fff).rom().region("maincpu", 0).unmapw();
+ m_mem_view[0](0x0000, 0x0fff).rom().region(m_maincpu_region, 0).unmapw();
+ m_mem_view[1](0x0000, 0x0fff).rom().region(m_maincpu_region, 0).unmapw();
// Floppy RAM
m_mem_view[0](0x1400, 0x17ff).readonly().share(m_floppy_ram);
m_mem_view[1](0x1400, 0x17ff).ram().share(m_floppy_ram);
// Floppy ROM
- m_mem_view[0](0x1800, 0x1fff).rom().region("maincpu", 0x1800).unmapw();
- m_mem_view[1](0x1800, 0x1fff).rom().region("maincpu", 0x1800).unmapw();
+ m_mem_view[0](0x1800, 0x1fff).rom().region(m_maincpu_region, 0x1800).unmapw();
+ m_mem_view[1](0x1800, 0x1fff).rom().region(m_maincpu_region, 0x1800).unmapw();
}
void h89_base_state::map_fetch(address_map &map)