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authorGravatarGravatar Aaron Giles <aaron@aarongiles.com>2008-10-23 09:15:58 +0000
committerGravatarGravatar Aaron Giles <aaron@aarongiles.com>2008-10-23 09:15:58 +0000
commit7f39a3503c76abb8f13b5cb839733ca26143e31d (patch)
treefc383f90ce66c7fa82fc82893d514d3fb915f6d7
parent6d55bb26f5104eb642a0c6324044cae18ad44ff1 (diff)
Cleanups and version bump.mame0128u1
-rw-r--r--src/emu/cpu/dsp56k/dsp56ops.c176
-rw-r--r--src/emu/cpu/i8051/i8051.c306
-rw-r--r--src/emu/cpu/i8051/i8051ops.c2
-rw-r--r--src/mame/drivers/cosmic.c30
-rw-r--r--src/mame/drivers/cps3.c206
-rw-r--r--src/mame/drivers/ddealer.c10
-rw-r--r--src/mame/drivers/itech8.c2
-rw-r--r--src/mame/drivers/m72.c18
-rw-r--r--src/mame/drivers/magictg.c174
-rw-r--r--src/mame/drivers/megadriv.c30
-rw-r--r--src/mame/drivers/megasys1.c2
-rw-r--r--src/mame/drivers/merit.c2
-rw-r--r--src/mame/drivers/micro3d.c4
-rw-r--r--src/mame/drivers/mirage.c4
-rw-r--r--src/mame/drivers/plygonet.c16
-rw-r--r--src/mame/drivers/psattack.c4
-rw-r--r--src/mame/drivers/shangha3.c4
-rw-r--r--src/mame/drivers/tnzs.c4
-rw-r--r--src/mame/drivers/yumefuda.c2
-rw-r--r--src/mame/video/itech8.c6
-rw-r--r--src/mame/video/taito_f3.c4
-rw-r--r--src/version.c2
22 files changed, 504 insertions, 504 deletions
diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c
index 4484a38f4cb..fee40c7bc5b 100644
--- a/src/emu/cpu/dsp56k/dsp56ops.c
+++ b/src/emu/cpu/dsp56k/dsp56ops.c
@@ -18,9 +18,9 @@
/************************/
/* Datatypes and macros */
/************************/
-enum dataType { DT_BYTE,
- DT_WORD,
- DT_DOUBLE_WORD,
+enum dataType { DT_BYTE,
+ DT_WORD,
+ DT_DOUBLE_WORD,
DT_LONG_WORD };
struct _typed_pointer
@@ -1073,7 +1073,7 @@ static void execute_one(void)
/***************************************************************************
- Opcode implementations
+ Opcode implementations
***************************************************************************/
/*******************************/
@@ -1360,7 +1360,7 @@ static size_t dsp56k_op_asl(const UINT16 op_byte, typed_pointer* d_register, UIN
/* S L E U N Z V C */
/* * * * * * * ? ? */
/* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significant
- bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
+ bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
/* C - Set if bit 39 of source operand is set. Cleared otherwise. */
return 0;
}
@@ -1370,18 +1370,18 @@ static size_t dsp56k_op_lsr(const UINT16 op_byte, typed_pointer* d_register, UIN
{
typed_pointer D = {NULL, DT_BYTE};
decode_F_table(BITS(op_byte,0x0008), &D);
-
+
*p_accum = *((UINT64*)D.addr);
-
+
((PAIR64*)D.addr)->w.h = (((PAIR64*)D.addr)->w.h) >> 1;
-
+
/* Make sure bit 31 gets a 0 */
((PAIR64*)D.addr)->w.h &= (~0x8000);
-
+
/* For the parallel move */
d_register->addr = D.addr;
d_register->data_type = D.data_type;
-
+
/* S L E U N Z V C */
/* * * - - ? ? 0 ? */
/* TODO: S, L */
@@ -1389,7 +1389,7 @@ static size_t dsp56k_op_lsr(const UINT16 op_byte, typed_pointer* d_register, UIN
if (((PAIR64*)D.addr)->w.h == 0) Z_bit_set(1);
V_bit_set(0);
if (*p_accum & U64(0x0000000000010000)) C_bit_set(1);
-
+
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
}
@@ -1421,7 +1421,7 @@ static size_t dsp56k_op_subl(const UINT16 op_byte, typed_pointer* d_register, UI
/* S L E U N Z V C */
/* * * * * * * ? * */
/* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significant
- bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
+ bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
return 0;
}
@@ -1564,12 +1564,12 @@ static size_t dsp56k_op_and(const UINT16 op_byte, typed_pointer* d_register, UIN
{
typed_pointer S = {NULL, DT_BYTE};
typed_pointer D = {NULL, DT_BYTE};
-
+
decode_JJF_table(BITS(op_byte,0x0003), BITS(op_byte,0x0008), &S, &D);
-
+
/* Save some data for the parallel move */
*p_accum = *((UINT64*)D.addr);
-
+
/* AND a word of S with A1|B1 */
((PAIR64*)D.addr)->w.h = *((UINT16*)S.addr) & ((PAIR64*)D.addr)->w.h;
@@ -1681,11 +1681,11 @@ static size_t dsp56k_op_andi(const UINT16 op, UINT8* cycles)
case 0x01: /* MR */
SR &= ((immediate << 8) | 0x00ff);
break;
-
+
case 0x02: /* CCR */
SR &= (immediate | 0xff00);
break;
-
+
case 0x03: /* OMR */
OMR &= (UINT8)(immediate);
break;
@@ -1697,7 +1697,7 @@ static size_t dsp56k_op_andi(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* - ? ? ? ? ? ? ? */
/* All ? bits - Cleared if the corresponding bit in the immediate data is cleared and if the operand
- is the CCR. Not affected otherwise. */
+ is the CCR. Not affected otherwise. */
cycles += 2;
return 1;
}
@@ -1708,7 +1708,7 @@ static size_t dsp56k_op_asl4(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* - ? * * * * ? ? */
/* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if bit 5 through 39 are
- not the same. */
+ not the same. */
/* C - Set if bit 36 of source operand is set. Cleared otherwise. */
return 0;
}
@@ -2089,12 +2089,12 @@ static size_t dsp56k_op_chkaau(const UINT16 op, UINT8* cycles)
{
/* S L E U N Z V C */
/* - - - - ? ? ? - */
- /* V - Set if the result of the last address ALU update performed a modulo wrap. Cleared if
- result of the last address ALU did not perform a modulo wrap.*/
+ /* V - Set if the result of the last address ALU update performed a modulo wrap. Cleared if
+ result of the last address ALU did not perform a modulo wrap.*/
/* Z - Set if the result of the last address ALU update is 0. Cleared if the result of the last
- address ALU is positive. */
+ address ALU is positive. */
/* N - Set if the result of the last address ALU update is negative. Cleared if the result of the
- last address ALU is positive. */
+ last address ALU is positive. */
return 0;
}
@@ -2120,8 +2120,8 @@ static size_t dsp56k_op_div(const UINT16 op, UINT8* cycles)
{
/* S L E U N Z V C */
/* - * - - - - ? ? */
- /* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significantst
- bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
+ /* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significantst
+ bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
/* C - Set if bit 39 of the result is cleared. Cleared otherwise. */
return 0;
}
@@ -2416,11 +2416,11 @@ static size_t dsp56k_op_macsuuu(const UINT16 op, UINT8* cycles)
void* D = NULL;
void* S1 = NULL;
void* S2 = NULL;
-
+
decode_QQF_special_table(BITS(op,0x0003), BITS(op,0x0008), &S1, &S2, &D);
-
+
s = BITS(op,0x0004);
-
+
/* Fixed-point 2's complement multiplication requires a shift */
if (s)
{
@@ -2436,9 +2436,9 @@ static size_t dsp56k_op_macsuuu(const UINT16 op, UINT8* cycles)
UINT32 s2 = (UINT32)(*((UINT16*)S2));
result = ( s1 * s2 ) << 1;
}
-
+
(*((UINT64*)D)) += result;
-
+
/* S L E U N Z V C */
/* - * * * * * * - */
/* TODO: L, E, U, V */
@@ -2487,8 +2487,8 @@ static size_t dsp56k_op_movec(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* * ? ? ? ? ? ? ? */
/* All ? bits - If SR is specified as a destination operand, set according to the corresponding
- bit of the source operand. If SR is not specified as a destination operand, L is set if data
- limiting occurred. All ? bits are not affected otherwise.*/
+ bit of the source operand. If SR is not specified as a destination operand, L is set if data
+ limiting occurred. All ? bits are not affected otherwise.*/
if (W && (SD.addr != &SR))
{
/* If you're writing to something other than the SR */
@@ -2528,8 +2528,8 @@ static size_t dsp56k_op_movec_1(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* * ? ? ? ? ? ? ? */
/* All ? bits - If SR is specified as a destination operand, set according to the corresponding
- bit of the source operand. If SR is not specified as a destination operand, L is set if data
- limiting occurred. All ? bits are not affected otherwise.*/
+ bit of the source operand. If SR is not specified as a destination operand, L is set if data
+ limiting occurred. All ? bits are not affected otherwise.*/
if (W && (SD.addr != &SR))
{
/* If you're writing to something other than the SR */
@@ -2573,8 +2573,8 @@ static size_t dsp56k_op_movec_2(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* * ? ? ? ? ? ? ? */
/* All ? bits - If SR is specified as a destination operand, set according to the corresponding
- bit of the source operand. If SR is not specified as a destination operand, L is set if data
- limiting occurred. All ? bits are not affected otherwise.*/
+ bit of the source operand. If SR is not specified as a destination operand, L is set if data
+ limiting occurred. All ? bits are not affected otherwise.*/
if (W && (SD.addr != &SR))
{
/* If you're writing to something other than the SR */
@@ -2631,8 +2631,8 @@ static size_t dsp56k_op_movec_3(const UINT16 op, const UINT16 op2, UINT8* cycles
/* S L E U N Z V C */
/* * ? ? ? ? ? ? ? */
/* All ? bits - If SR is specified as a destination operand, set according to the corresponding
- bit of the source operand. If SR is not specified as a destination operand, L is set if data
- limiting occurred. All ? bits are not affected otherwise.*/
+ bit of the source operand. If SR is not specified as a destination operand, L is set if data
+ limiting occurred. All ? bits are not affected otherwise.*/
if (W && (SD.addr != &SR))
{
/* If you're writing to something other than the SR */
@@ -2657,8 +2657,8 @@ static size_t dsp56k_op_movec_4(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* * ? ? ? ? ? ? ? */
/* All ? bits - If SR is specified as a destination operand, set according to the corresponding
- bit of the source operand. If SR is not specified as a destination operand, L is set if data
- limiting occurred. All ? bits are not affected otherwise.*/
+ bit of the source operand. If SR is not specified as a destination operand, L is set if data
+ limiting occurred. All ? bits are not affected otherwise.*/
if (D.addr != &SR)
{
/* If you're writing to something other than the SR */
@@ -2675,8 +2675,8 @@ static size_t dsp56k_op_movec_5(const UINT16 op, const UINT16 op2, UINT8* cycles
/* S L E U N Z V C */
/* * ? ? ? ? ? ? ? */
/* All ? bits - If SR is specified as a destination operand, set according to the corresponding
- bit of the source operand. If SR is not specified as a destination operand, L is set if data
- limiting occurred. All ? bits are not affected otherwise.*/
+ bit of the source operand. If SR is not specified as a destination operand, L is set if data
+ limiting occurred. All ? bits are not affected otherwise.*/
return 0;
}
@@ -2870,8 +2870,8 @@ static size_t dsp56k_op_norm(const UINT16 op, UINT8* cycles)
{
/* S L E U N Z V C */
/* - * * * * * ? - */
- /* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significantst
- bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
+ /* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significantst
+ bit of the destination operand is changed as a result of the left shift. Cleared otherwise. */
return 0;
}
@@ -2881,7 +2881,7 @@ static size_t dsp56k_op_ori(const UINT16 op, UINT8* cycles)
/* S L E U N Z V C */
/* - ? ? ? ? ? ? ? */
/* All ? bits - Set if the corresponding bit in the immediate data is set and if the operand is the
- CCR. Not affected otherwise. */
+ CCR. Not affected otherwise. */
return 0;
}
@@ -2898,23 +2898,23 @@ static size_t dsp56k_op_rep_1(const UINT16 op, UINT8* cycles)
{
/* TODO: This is non-interruptable, probably have to turn off interrupts here */
UINT16 iVal = op & 0x00ff;
-
+
if (iVal != 0)
{
TEMP = LC;
LC = iVal;
-
+
core.repFlag = 1;
core.repAddr = PC + WORD(1);
-
+
cycles += 4; /* TODO: + mv oscillator clock cycles */
}
else
{
cycles += 6; /* TODO: + mv oscillator clock cycles */
}
-
-
+
+
/* S L E U N Z V C */
/* - * - - - - - - */
/* TODO: L */
@@ -3084,10 +3084,10 @@ static size_t dsp56k_op_tst2(const UINT16 op, UINT8* cycles)
/* (L,E,U should be set to 0) */
L_bit_set(0);
E_bit_set(0);
- // U_bit_set(0); /* TODO: Conflicting opinions? "Set if unnormalized." Documentation is weird (A&B?) */
+ // U_bit_set(0); /* TODO: Conflicting opinions? "Set if unnormalized." Documentation is weird (A&B?) */
if ((*((UINT16*)D.addr)) & 0x8000) N_bit_set(1); else N_bit_set(0);
if ((*((UINT16*)D.addr)) == 0x0000) Z_bit_set(1); else Z_bit_set(0);
- // V_bit_set(0); /* TODO: Verify as well! */
+ // V_bit_set(0); /* TODO: Verify as well! */
C_bit_set(0);
cycles += 2;
@@ -3113,7 +3113,7 @@ static size_t dsp56k_op_zero(const UINT16 op, UINT8* cycles)
/***************************************************************************
- Table decoding
+ Table decoding
***************************************************************************/
static UINT16 decode_BBB_bitmask(UINT16 BBB, UINT16 *iVal)
{
@@ -3162,39 +3162,39 @@ static void decode_DDDDD_table(UINT16 DDDDD, typed_pointer* ret)
{
switch(DDDDD)
{
- case 0x00: ret->addr = &X0; ret->data_type = DT_WORD; break;
- case 0x01: ret->addr = &Y0; ret->data_type = DT_WORD; break;
- case 0x02: ret->addr = &X1; ret->data_type = DT_WORD; break;
- case 0x03: ret->addr = &Y1; ret->data_type = DT_WORD; break;
- case 0x04: ret->addr = &A ; ret->data_type = DT_LONG_WORD; break;
- case 0x05: ret->addr = &B ; ret->data_type = DT_LONG_WORD; break;
- case 0x06: ret->addr = &A0; ret->data_type = DT_WORD; break;
- case 0x07: ret->addr = &B0; ret->data_type = DT_WORD; break;
- case 0x08: ret->addr = &LC; ret->data_type = DT_WORD; break;
- case 0x09: ret->addr = &SR; ret->data_type = DT_WORD; break;
- case 0x0a: ret->addr = &OMR; ret->data_type = DT_BYTE; break;
- case 0x0b: ret->addr = &SP; ret->data_type = DT_BYTE; break;
- case 0x0c: ret->addr = &A1; ret->data_type = DT_WORD; break;
- case 0x0d: ret->addr = &B1; ret->data_type = DT_WORD; break;
- case 0x0e: ret->addr = &A2; ret->data_type = DT_BYTE; break;
- case 0x0f: ret->addr = &B2; ret->data_type = DT_BYTE; break;
-
- case 0x10: ret->addr = &R0; ret->data_type = DT_WORD; break;
- case 0x11: ret->addr = &R1; ret->data_type = DT_WORD; break;
- case 0x12: ret->addr = &R2; ret->data_type = DT_WORD; break;
- case 0x13: ret->addr = &R3; ret->data_type = DT_WORD; break;
- case 0x14: ret->addr = &M0; ret->data_type = DT_WORD; break;
- case 0x15: ret->addr = &M1; ret->data_type = DT_WORD; break;
- case 0x16: ret->addr = &M2; ret->data_type = DT_WORD; break;
- case 0x17: ret->addr = &M3; ret->data_type = DT_WORD; break;
- case 0x18: ret->addr = &SSH; ret->data_type = DT_WORD; break;
- case 0x19: ret->addr = &SSL; ret->data_type = DT_WORD; break;
- case 0x1a: ret->addr = &LA; ret->data_type = DT_WORD; break;
+ case 0x00: ret->addr = &X0; ret->data_type = DT_WORD; break;
+ case 0x01: ret->addr = &Y0; ret->data_type = DT_WORD; break;
+ case 0x02: ret->addr = &X1; ret->data_type = DT_WORD; break;
+ case 0x03: ret->addr = &Y1; ret->data_type = DT_WORD; break;
+ case 0x04: ret->addr = &A ; ret->data_type = DT_LONG_WORD; break;
+ case 0x05: ret->addr = &B ; ret->data_type = DT_LONG_WORD; break;
+ case 0x06: ret->addr = &A0; ret->data_type = DT_WORD; break;
+ case 0x07: ret->addr = &B0; ret->data_type = DT_WORD; break;
+ case 0x08: ret->addr = &LC; ret->data_type = DT_WORD; break;
+ case 0x09: ret->addr = &SR; ret->data_type = DT_WORD; break;
+ case 0x0a: ret->addr = &OMR; ret->data_type = DT_BYTE; break;
+ case 0x0b: ret->addr = &SP; ret->data_type = DT_BYTE; break;
+ case 0x0c: ret->addr = &A1; ret->data_type = DT_WORD; break;
+ case 0x0d: ret->addr = &B1; ret->data_type = DT_WORD; break;
+ case 0x0e: ret->addr = &A2; ret->data_type = DT_BYTE; break;
+ case 0x0f: ret->addr = &B2; ret->data_type = DT_BYTE; break;
+
+ case 0x10: ret->addr = &R0; ret->data_type = DT_WORD; break;
+ case 0x11: ret->addr = &R1; ret->data_type = DT_WORD; break;
+ case 0x12: ret->addr = &R2; ret->data_type = DT_WORD; break;
+ case 0x13: ret->addr = &R3; ret->data_type = DT_WORD; break;
+ case 0x14: ret->addr = &M0; ret->data_type = DT_WORD; break;
+ case 0x15: ret->addr = &M1; ret->data_type = DT_WORD; break;
+ case 0x16: ret->addr = &M2; ret->data_type = DT_WORD; break;
+ case 0x17: ret->addr = &M3; ret->data_type = DT_WORD; break;
+ case 0x18: ret->addr = &SSH; ret->data_type = DT_WORD; break;
+ case 0x19: ret->addr = &SSL; ret->data_type = DT_WORD; break;
+ case 0x1a: ret->addr = &LA; ret->data_type = DT_WORD; break;
//no 0x1b
- case 0x1c: ret->addr = &N0; ret->data_type = DT_WORD; break;
- case 0x1d: ret->addr = &N1; ret->data_type = DT_WORD; break;
- case 0x1e: ret->addr = &N2; ret->data_type = DT_WORD; break;
- case 0x1f: ret->addr = &N3; ret->data_type = DT_WORD; break;
+ case 0x1c: ret->addr = &N0; ret->data_type = DT_WORD; break;
+ case 0x1d: ret->addr = &N1; ret->data_type = DT_WORD; break;
+ case 0x1e: ret->addr = &N2; ret->data_type = DT_WORD; break;
+ case 0x1f: ret->addr = &N3; ret->data_type = DT_WORD; break;
}
}
@@ -3496,7 +3496,7 @@ static void dsp56k_process_loop(void)
/* End of loop processing */
SR = SSL; /* TODO: A-83. I believe only the Loop Flag comes back here. */
SP--;
-
+
LA = SSH;
LC = SSL;
SP--;
@@ -3536,7 +3536,7 @@ static void dsp56k_process_rep(size_t repSize)
/***************************************************************************
- Parallel Memory Ops
+ Parallel Memory Ops
***************************************************************************/
/* Register to Register Data Move : 0100 IIII ---- ---- */
static void execute_register_to_register_data_move(const UINT16 op, typed_pointer* d_register, UINT64* prev_accum_value)
@@ -3636,7 +3636,7 @@ static void execute_x_memory_data_move2(const UINT16 op, typed_pointer* d_regist
/***************************************************************************
- Helper Functions
+ Helper Functions
***************************************************************************/
static UINT16 Dsp56kOpMask(UINT16 cur, UINT16 mask)
{
diff --git a/src/emu/cpu/i8051/i8051.c b/src/emu/cpu/i8051/i8051.c
index 47e74bb942f..217d7ab4efe 100644
--- a/src/emu/cpu/i8051/i8051.c
+++ b/src/emu/cpu/i8051/i8051.c
@@ -58,8 +58,8 @@
* to output a page offset into external ram, but it is totally based on the hardware setup.
*
* Timing needs to be implemented via MAME timers perhaps?
- *
- * October, 2008, Couriersud - Major rewrite
+ *
+ * October, 2008, Couriersud - Major rewrite
*
*****************************************************************************/
@@ -67,21 +67,21 @@
* - EA pin - defined by architecture, must implement:
* 1 means external access, bypassing internal ROM
* - T0 output clock ?
- *
+ *
* - Full Timer support (all modes)
* - Implement cmos features
* - Fix serial communication - This is a big hack (but working) right now.
- * - Implement 87C751 in sslam.c
- * - Fix cardline.c
- * - Fix sslam.c and cardline.c
+ * - Implement 87C751 in sslam.c
+ * - Fix cardline.c
+ * - Fix sslam.c and cardline.c
* most likely due to different behaviour of I/O pins. The boards
* actually use 80CXX, i.e. CMOS versions.
- * "Normal" 805X will return a 0 if reading from a output port which has
- * a 0 written to it's latch. At least cardline expects a 1 here.
- *
+ * "Normal" 805X will return a 0 if reading from a output port which has
+ * a 0 written to it's latch. At least cardline expects a 1 here.
+ *
* Done:
- * - Fix segas18.c (segaic16.c) memory handling.
- * - Fix sslam.c
+ * - Fix segas18.c (segaic16.c) memory handling.
+ * - Fix sslam.c
* - Fix limenko.c videopkr.c : Issue with core allocation of ram (duplicate savestate)
* - Handle internal ram better (debugger visible)
* - Fixed port reading
@@ -90,7 +90,7 @@
* - Now returns INTERNAL_DIVIDER, adjusted cycle counts
* - Remove unnecessary and duplicated code
* - Remove unnecessary functions
- * - Rewrite to have sfr-registers stored in int_ram.
+ * - Rewrite to have sfr-registers stored in int_ram.
* - Debugger may now watch sfr-registers as well.
* - implemented interrupt callbacks (HOLD_LINE now supported)
* - Runtime switch for processor type - remove ifdefs
@@ -162,7 +162,7 @@ enum
V_IE1 = 0x013, /* External Interrupt 1 */
V_TF1 = 0x01b, /* Timer 1 Overflow */
V_RITI = 0x023, /* Serial Receive/Transmit */
-
+
/* 8052 Only Vectors */
V_TF2 = 0x02b, /* Timer 2 Overflow */
};
@@ -172,11 +172,11 @@ enum
***************************************************************************/
typedef struct _mcs51_uart mcs51_uart;
-struct _mcs51_uart
+struct _mcs51_uart
{
UINT8 data_out; //Data to send out
UINT8 bits_to_send; //How many bits left to send when transmitting out the serial port
-
+
int smod_div; /* signal divided by 2^SMOD */
int rx_clk; /* rx clock */
int tx_clk; /* tx clock */
@@ -184,7 +184,7 @@ struct _mcs51_uart
};
typedef struct _mcs51_regs mcs51_regs;
-struct _mcs51_regs
+struct _mcs51_regs
{
//Internal stuff
UINT16 ppc; //previous pc
@@ -195,7 +195,7 @@ struct _mcs51_regs
UINT8 rwm; //Signals that the current instruction is a read/write/modify instruction
int inst_cycles; /* cycles for the current instruction */
- int ram_mask; /* second ram bank for indirect access available ? */
+ int ram_mask; /* second ram bank for indirect access available ? */
int num_interrupts; /* number of interrupts supported */
int recalc_parity; /* recalculate parity before next instruction */
int last_line_state; /* last state of input lines line */
@@ -213,11 +213,11 @@ struct _mcs51_regs
// SFR Callbacks
void (*sfr_write)(size_t offset, UINT8 data);
UINT8 (*sfr_read)(size_t offset);
-
+
//Interrupt Callback
int (*irq_callback)(int irqline);
- //Serial Port TX/RX Callbacks
+ //Serial Port TX/RX Callbacks
// TODO: Move to special port r/w
void (*serial_tx_callback)(int data); //Call back funciton when sending data out of serial port
int (*serial_rx_callback)(void); //Call back function to retrieve data when receiving serial port data
@@ -241,8 +241,8 @@ struct _mcs51_regs
/* Read/Write a byte from/to External Data Memory (Usually RAM or other I/O) */
#define DATAMEM_R(a) (UINT8)io_read_byte_8le(a)
#define DATAMEM_W(a,v) io_write_byte_8le(a,v)
-//#define DATAMEM_R(a) (UINT8)data_read_byte_8le(a)
-//#define DATAMEM_W(a,v) data_write_byte_8le(a,v)
+//#define DATAMEM_R(a) (UINT8)data_read_byte_8le(a)
+//#define DATAMEM_W(a,v) data_write_byte_8le(a,v)
/* Read/Write a byte from/to the Internal RAM */
@@ -276,12 +276,12 @@ struct _mcs51_regs
#define RWM mcs51.rwm
/* SFR Registers - These are accessed directly for speed on read */
-/* Read accessors */
+/* Read accessors */
#define SFR_A(a) mcs51.sfr_ram[(a)]
#define SET_SFR_A(a,v) do { SFR_A(a) = (v); } while (0)
-#define ACC ((const UINT8) SFR_A(ADDR_ACC))
+#define ACC ((const UINT8) SFR_A(ADDR_ACC))
#define PSW ((const UINT8) SFR_A(ADDR_PSW))
#define P0 ((const UINT8) SFR_A(ADDR_P0))
@@ -545,7 +545,7 @@ INLINE void update_ptrs(void)
There is no way external hardware can distinguish between 8bit access and 16 bit access.
During 16bit access the high order byte of the address is output on port 2. We therefore
assume that most hardware will use port 2 for 8bit access as well.
-
+
On configurations where 8 bit access in conjunction with other ports is used,
it is up to the driver to use AM_MIRROR to mask out the high level address and
provide it's own mapping.
@@ -573,9 +573,9 @@ INLINE UINT8 iram_read(size_t offset)
INLINE void iram_write(size_t offset, UINT8 data)
{
- if ((offset) < 0x80)
+ if ((offset) < 0x80)
data_write_byte_8le(offset, data);
- else
+ else
mcs51.sfr_write(offset, data);
}
@@ -606,7 +606,7 @@ INLINE void set_parity(void)
UINT8 p = 0;
int i;
UINT8 a = ACC;
-
+
for (i=0; i<8; i++) { //Test for each of the 8 bits in the ACC!
p ^= (a & 1);
a = (a >> 1);
@@ -657,9 +657,9 @@ INLINE void bit_address_w(UINT8 offset, UINT8 bit)
bit_pos = offset & 0x7;
bit = (bit & 0x1) << bit_pos;
mask = ~(1 << bit_pos) & 0xff;
- result = IRAM_R(word) & mask;
+ result = IRAM_R(word) & mask;
result = result | bit;
- IRAM_W(word, result);
+ IRAM_W(word, result);
}
/* SFR bit addressable registers */
else {
@@ -668,9 +668,9 @@ INLINE void bit_address_w(UINT8 offset, UINT8 bit)
bit_pos = offset & 0x7;
bit = (bit & 0x1) << bit_pos;
mask = ~(1 << bit_pos) & 0xff;
- result = IRAM_R(word) & mask;
+ result = IRAM_R(word) & mask;
result = result | bit;
- IRAM_W(word, result);
+ IRAM_W(word, result);
}
}
@@ -699,7 +699,7 @@ INLINE void do_sub_flags(UINT8 a, UINT8 data, UINT8 c)
INLINE void transmit_receive(int source)
{
int mode = (GET_SM0<<1) | GET_SM1;
-
+
if (source == 1) /* timer1 */
mcs51.uart.smod_div = (mcs51.uart.smod_div + 1) & (2-GET_SMOD);
@@ -744,9 +744,9 @@ INLINE void transmit_receive(int source)
//Set Interrupt Flag
SET_TI(1);
//Note: we'll let the main loop catch the interrupt
- }
+ }
}
-
+
}
/* receive */
if (mcs51.uart.rx_clk >= 16)
@@ -769,33 +769,33 @@ INLINE void transmit_receive(int source)
}
}
}
-
+
INLINE void update_timer_t0(int cycles)
{
int mode = (GET_M0_1<<1) | GET_M0_0;
UINT32 count = 0;
- if (GET_TR0)
+ if (GET_TR0)
{
UINT32 delta;
-
+
/* counter / external input */
delta = GET_CT0 ? mcs51.t0_cnt : cycles;
/* taken, reset */
mcs51.t0_cnt = 0;
/* TODO: Not sure about IE0. The manual specifies INT0=high,
- * which in turn means CLEAR_LINE.
- * IE0 may be edge triggered depending on IT0 */
+ * which in turn means CLEAR_LINE.
+ * IE0 may be edge triggered depending on IT0 */
if (GET_GATE0 && !GET_IE0)
delta = 0;
-
+
switch(mode) {
case 0: /* 13 Bit Timer Mode */
count = ((TH0<<5) | ( TL0 & 0x1f ) );
count += delta;
if ( count & 0xffffe000 ) /* Check for overflow */
- SET_TF0(1);
+ SET_TF0(1);
TH0 = (count>>5) & 0xff;
TL0 = count & 0x1f ;
break;
@@ -817,7 +817,7 @@ INLINE void update_timer_t0(int cycles)
/* Update new values of the counter */
TL0 = count & 0xff;
break;
- case 3:
+ case 3:
/* Split Timer 1 */
count = (UINT16) TL0 + delta;
if ( count & 0xffffff00 ) /* Check for overflow */
@@ -826,11 +826,11 @@ INLINE void update_timer_t0(int cycles)
break;
}
}
- if (GET_TR1)
+ if (GET_TR1)
{
- switch(mode)
+ switch(mode)
{
- case 3:
+ case 3:
/* Split Timer 2 */
count = (UINT16) TH0 + cycles; /* No gate control or counting !*/
if ( count & 0xffffff00 ) /* Check for overflow */
@@ -846,18 +846,18 @@ INLINE void update_timer_t1(int cycles)
int mode = (GET_M1_1<<1) | GET_M1_0;
UINT32 count = 0;
- if (GET_TR1)
+ if (GET_TR1)
{
UINT32 delta;
int overflow = 0;
-
+
/* counter / external input */
delta = GET_CT1 ? mcs51.t1_cnt : cycles;
/* taken, reset */
mcs51.t1_cnt = 0;
/* TODO: Not sure about IE0. The manual specifies INT0=high,
- * which in turn means CLEAR_LINE. Change to access last_state?
- * IE0 may be edge triggered depending on IT0 */
+ * which in turn means CLEAR_LINE. Change to access last_state?
+ * IE0 may be edge triggered depending on IT0 */
if (GET_GATE1 && !GET_IE1)
delta = 0;
@@ -867,8 +867,8 @@ INLINE void update_timer_t1(int cycles)
count = ((TH1<<5) | ( TL1 & 0x1f ) );
count += delta;
overflow = count & 0xffffe000; /* Check for overflow */
- if ( overflow )
- SET_TF1(1);
+ if ( overflow )
+ SET_TF1(1);
TH1 = (count>>5) & 0xff;
TL1 = count & 0x1f ;
break;
@@ -894,7 +894,7 @@ INLINE void update_timer_t1(int cycles)
/* Update new values of the counter */
TL1 = count & 0xff;
break;
- case 3:
+ case 3:
/* do nothing */
break;
}
@@ -920,7 +920,7 @@ INLINE void update_timer_t2(int cycles)
{
SET_TF2(1);
count += ((RCAP2H<<8) | RCAP2L);
- }
+ }
else if (GET_EXEN2 && mcs51.t2ex_cnt>0)
{
count += ((RCAP2H<<8) | RCAP2L);
@@ -934,7 +934,7 @@ INLINE void update_timer_t2(int cycles)
SET_TF2(1);
TH2 = (count>>8) & 0xff;
TL2 = count & 0xff;
-
+
if (GET_EXEN2 && mcs51.t2ex_cnt>0)
{
RCAP2H = TH2;
@@ -1058,17 +1058,17 @@ static void execute_op(UINT8 op)
set_parity();
mcs51.recalc_parity = 0;
}
-
+
switch( op )
{
-
+
case 0x00: nop(); break; //NOP
case 0x01: ajmp(op); break; //AJMP code addr
case 0x02: ljmp(); break; //LJMP code addr
case 0x03: rr_a(); break; //RR A
case 0x04: inc_a(); break; //INC A
case 0x05: RWM=1; inc_mem(); RWM=0; break; //INC data addr
-
+
case 0x06:
case 0x07: inc_ir(op&1); break; //INC @R0/@R1
@@ -1080,35 +1080,35 @@ static void execute_op(UINT8 op)
case 0x0d:
case 0x0e:
case 0x0f: inc_r(op&7); break; //INC R0 to R7
-
+
case 0x10: RWM=1; jbc(); RWM=0; break; //JBC bit addr, code addr
case 0x11: acall(op); break; //ACALL code addr
case 0x12: lcall(); break; //LCALL code addr
case 0x13: rrc_a(); break; //RRC A
case 0x14: dec_a(); break; //DEC A
case 0x15: RWM=1; dec_mem(); RWM=0; break; //DEC data addr
-
+
case 0x16:
- case 0x17: dec_ir(op&1); break; //DEC @R0/@R1
-
- case 0x18:
+ case 0x17: dec_ir(op&1); break; //DEC @R0/@R1
+
+ case 0x18:
case 0x19:
case 0x1a:
case 0x1b:
case 0x1c:
case 0x1d:
case 0x1e:
- case 0x1f: dec_r(op&7); break; //DEC R0 to R7
-
+ case 0x1f: dec_r(op&7); break; //DEC R0 to R7
+
case 0x20: jb(); break; //JB bit addr, code addr
- case 0x21: ajmp(op); break; //AJMP code addr
+ case 0x21: ajmp(op); break; //AJMP code addr
case 0x22: ret(); break; //RET
case 0x23: rl_a(); break; //RL A
case 0x24: add_a_byte(); break; //ADD A, #data
case 0x25: add_a_mem(); break; //ADD A, data addr
case 0x26:
- case 0x27: add_a_ir(op&1); break; //ADD A, @R0/@R1
+ case 0x27: add_a_ir(op&1); break; //ADD A, @R0/@R1
case 0x28:
case 0x29:
@@ -1117,15 +1117,15 @@ static void execute_op(UINT8 op)
case 0x2c:
case 0x2d:
case 0x2e:
- case 0x2f: add_a_r(op&7); break; //ADD A, R0 to R7
-
+ case 0x2f: add_a_r(op&7); break; //ADD A, R0 to R7
+
case 0x30: jnb(); break; //JNB bit addr, code addr
case 0x31: acall(op); break; //ACALL code addr
case 0x32: reti(); break; //RETI
case 0x33: rlc_a(); break; //RLC A
case 0x34: addc_a_byte(); break; //ADDC A, #data
case 0x35: addc_a_mem(); break; //ADDC A, data addr
-
+
case 0x36:
case 0x37: addc_a_ir(op&1); break; //ADDC A, @R0/@R1
@@ -1136,17 +1136,17 @@ static void execute_op(UINT8 op)
case 0x3c:
case 0x3d:
case 0x3e:
- case 0x3f: addc_a_r(op&7); break; //ADDC A, R0 to R7
-
+ case 0x3f: addc_a_r(op&7); break; //ADDC A, R0 to R7
+
case 0x40: jc(); break; //JC code addr
case 0x41: ajmp(op); break; //AJMP code addr
case 0x42: RWM=1; orl_mem_a(); RWM=0; break; //ORL data addr, A
case 0x43: RWM=1; orl_mem_byte(); RWM=0; break; //ORL data addr, #data
case 0x44: orl_a_byte(); break;
case 0x45: orl_a_mem(); break; //ORL A, data addr
-
+
case 0x46:
- case 0x47: orl_a_ir(op&1); break; //ORL A, @RO/@R1
+ case 0x47: orl_a_ir(op&1); break; //ORL A, @RO/@R1
case 0x48:
case 0x49:
@@ -1155,17 +1155,17 @@ static void execute_op(UINT8 op)
case 0x4c:
case 0x4d:
case 0x4e:
- case 0x4f: orl_a_r(op&7); break; //ORL A, RO to R7
-
+ case 0x4f: orl_a_r(op&7); break; //ORL A, RO to R7
+
case 0x50: jnc(); break; //JNC code addr
- case 0x51: acall(op); break; //ACALL code addr
+ case 0x51: acall(op); break; //ACALL code addr
case 0x52: RWM=1; anl_mem_a(); RWM=0; break; //ANL data addr, A
case 0x53: RWM=1; anl_mem_byte(); RWM=0; break; //ANL data addr, #data
case 0x54: anl_a_byte(); break; //ANL A, #data
case 0x55: anl_a_mem(); break; //ANL A, data addr
-
+
case 0x56:
- case 0x57: anl_a_ir(op&1); break; //ANL A, @RO/@R1
+ case 0x57: anl_a_ir(op&1); break; //ANL A, @RO/@R1
case 0x58:
case 0x59:
@@ -1175,16 +1175,16 @@ static void execute_op(UINT8 op)
case 0x5d:
case 0x5e:
case 0x5f: anl_a_r(op&7); break; //ANL A, RO to R7
-
+
case 0x60: jz(); break; //JZ code addr
- case 0x61: ajmp(op); break; //AJMP code addr
+ case 0x61: ajmp(op); break; //AJMP code addr
case 0x62: RWM=1; xrl_mem_a(); RWM=0; break; //XRL data addr, A
case 0x63: RWM=1; xrl_mem_byte(); RWM=0; break; //XRL data addr, #data
case 0x64: xrl_a_byte(); break; //XRL A, #data
case 0x65: xrl_a_mem(); break; //XRL A, data addr
case 0x66:
- case 0x67: xrl_a_ir(op&1); break; //XRL A, @R0/@R1
+ case 0x67: xrl_a_ir(op&1); break; //XRL A, @R0/@R1
case 0x68:
case 0x69:
@@ -1193,17 +1193,17 @@ static void execute_op(UINT8 op)
case 0x6c:
case 0x6d:
case 0x6e:
- case 0x6f: xrl_a_r(op&7); break; //XRL A, R0 to R7
-
+ case 0x6f: xrl_a_r(op&7); break; //XRL A, R0 to R7
+
case 0x70: jnz(); break; //JNZ code addr
- case 0x71: acall(op); break; //ACALL code addr
+ case 0x71: acall(op); break; //ACALL code addr
case 0x72: orl_c_bitaddr(); break; //ORL C, bit addr
case 0x73: jmp_iadptr(); break; //JMP @A+DPTR
case 0x74: mov_a_byte(); break; //MOV A, #data
case 0x75: mov_mem_byte(); break; //MOV data addr, #data
case 0x76:
- case 0x77: mov_ir_byte(op&1); break; //MOV @R0/@R1, #data
+ case 0x77: mov_ir_byte(op&1); break; //MOV @R0/@R1, #data
case 0x78:
case 0x79:
@@ -1212,17 +1212,17 @@ static void execute_op(UINT8 op)
case 0x7c:
case 0x7d:
case 0x7e:
- case 0x7f: mov_r_byte(op&7); break; //MOV R0 to R7, #data
+ case 0x7f: mov_r_byte(op&7); break; //MOV R0 to R7, #data
case 0x80: sjmp(); break; //SJMP code addr
- case 0x81: ajmp(op); break; //AJMP code addr
+ case 0x81: ajmp(op); break; //AJMP code addr
case 0x82: anl_c_bitaddr(); break; //ANL C, bit addr
case 0x83: movc_a_iapc(); break; //MOVC A, @A + PC
case 0x84: div_ab(); break; //DIV AB
case 0x85: mov_mem_mem(); break; //MOV data addr, data addr
case 0x86:
- case 0x87: mov_mem_ir(op&1); break; //MOV data addr, @R0/@R1
+ case 0x87: mov_mem_ir(op&1); break; //MOV data addr, @R0/@R1
case 0x88:
case 0x89:
@@ -1231,17 +1231,17 @@ static void execute_op(UINT8 op)
case 0x8c:
case 0x8d:
case 0x8e:
- case 0x8f: mov_mem_r(op&7); break; //MOV data addr,R0 to R7
+ case 0x8f: mov_mem_r(op&7); break; //MOV data addr,R0 to R7
case 0x90: mov_dptr_byte(); break; //MOV DPTR, #data
- case 0x91: acall(op); break; //ACALL code addr
+ case 0x91: acall(op); break; //ACALL code addr
case 0x92: RWM = 1; mov_bitaddr_c(); RWM = 0; break; //MOV bit addr, C
case 0x93: movc_a_iadptr(); break; //MOVC A, @A + DPTR
case 0x94: subb_a_byte(); break; //SUBB A, #data
case 0x95: subb_a_mem(); break; //SUBB A, data addr
case 0x96:
- case 0x97: subb_a_ir(op&1); break; //SUBB A, @R0/@R1
+ case 0x97: subb_a_ir(op&1); break; //SUBB A, @R0/@R1
case 0x98:
case 0x99:
@@ -1250,10 +1250,10 @@ static void execute_op(UINT8 op)
case 0x9c:
case 0x9d:
case 0x9e:
- case 0x9f: subb_a_r(op&7); break; //SUBB A, R0 to R7
+ case 0x9f: subb_a_r(op&7); break; //SUBB A, R0 to R7
case 0xa0: orl_c_nbitaddr(); break; //ORL C, /bit addr
- case 0xa1: ajmp(op); break; //AJMP code addr
+ case 0xa1: ajmp(op); break; //AJMP code addr
case 0xa2: mov_c_bitaddr(); break; //MOV C, bit addr
case 0xa3: inc_dptr(); break; //INC DPTR
case 0xa4: mul_ab(); break; //MUL AB
@@ -1269,17 +1269,17 @@ static void execute_op(UINT8 op)
case 0xac:
case 0xad:
case 0xae:
- case 0xaf: mov_r_mem(op&7); break; //MOV R0 to R7, data addr
+ case 0xaf: mov_r_mem(op&7); break; //MOV R0 to R7, data addr
case 0xb0: anl_c_nbitaddr(); break; //ANL C,/bit addr
- case 0xb1: acall(op); break; //ACALL code addr
+ case 0xb1: acall(op); break; //ACALL code addr
case 0xb2: RWM=1; cpl_bitaddr(); RWM=0; break; //CPL bit addr
case 0xb3: cpl_c(); break; //CPL C
case 0xb4: cjne_a_byte(); break; //CJNE A, #data, code addr
case 0xb5: cjne_a_mem(); break; //CJNE A, data addr, code addr
case 0xb6:
- case 0xb7: cjne_ir_byte(op&1); break; //CJNE @R0/@R1, #data, code addr
+ case 0xb7: cjne_ir_byte(op&1); break; //CJNE @R0/@R1, #data, code addr
case 0xb8:
case 0xb9:
@@ -1298,7 +1298,7 @@ static void execute_op(UINT8 op)
case 0xc5: xch_a_mem(); break; //XCH A, data addr
case 0xc6:
- case 0xc7: xch_a_ir(op&1); break; //XCH A, @RO/@R1
+ case 0xc7: xch_a_ir(op&1); break; //XCH A, @RO/@R1
case 0xc8:
case 0xc9:
@@ -1307,17 +1307,17 @@ static void execute_op(UINT8 op)
case 0xcc:
case 0xcd:
case 0xce:
- case 0xcf: xch_a_r(op&7); break; //XCH A, RO to R7
+ case 0xcf: xch_a_r(op&7); break; //XCH A, RO to R7
case 0xd0: pop(); break; //POP data addr
- case 0xd1: acall(op); break; //ACALL code addr
+ case 0xd1: acall(op); break; //ACALL code addr
case 0xd2: RWM=1; setb_bitaddr(); RWM=0; break; //SETB bit addr
case 0xd3: setb_c(); break; //SETB C
case 0xd4: da_a(); break; //DA A
case 0xd5: RWM=1; djnz_mem(); RWM=0; break; //DJNZ data addr, code addr
case 0xd6:
- case 0xd7: xchd_a_ir(op&1); break; //XCHD A, @R0/@R1
+ case 0xd7: xchd_a_ir(op&1); break; //XCHD A, @R0/@R1
case 0xd8:
case 0xd9:
@@ -1326,10 +1326,10 @@ static void execute_op(UINT8 op)
case 0xdc:
case 0xdd:
case 0xde:
- case 0xdf: djnz_r(op&7); break; //DJNZ R0 to R7,code addr
+ case 0xdf: djnz_r(op&7); break; //DJNZ R0 to R7,code addr
case 0xe0: movx_a_idptr(); break; //MOVX A,@DPTR
- case 0xe1: ajmp(op); break; //AJMP code addr
+ case 0xe1: ajmp(op); break; //AJMP code addr
case 0xe2:
case 0xe3: movx_a_ir(op&1); break; //MOVX A, @R0/@R1
@@ -1337,7 +1337,7 @@ static void execute_op(UINT8 op)
case 0xe4: clr_a(); break; //CLR A
case 0xe5: mov_a_mem(); break; //MOV A, data addr
case 0xe6:
- case 0xe7: mov_a_ir(op&1); break; //MOV A,@RO/@R1
+ case 0xe7: mov_a_ir(op&1); break; //MOV A,@RO/@R1
case 0xe8:
case 0xe9:
@@ -1346,19 +1346,19 @@ static void execute_op(UINT8 op)
case 0xec:
case 0xed:
case 0xee:
- case 0xef: mov_a_r(op&7); break; //MOV A,R0 to R7
+ case 0xef: mov_a_r(op&7); break; //MOV A,R0 to R7
case 0xf0: movx_idptr_a(); break; //MOVX @DPTR,A
- case 0xf1: acall(op); break; //ACALL code addr
+ case 0xf1: acall(op); break; //ACALL code addr
case 0xf2:
- case 0xf3: movx_ir_a(op&1); break; //MOVX @R0/@R1,A
-
+ case 0xf3: movx_ir_a(op&1); break; //MOVX @R0/@R1,A
+
case 0xf4: cpl_a(); break; //CPL A
case 0xf5: mov_mem_a(); break; //MOV data addr, A
-
+
case 0xf6:
- case 0xf7: mov_ir_a(op&1); break; //MOV @R0/@R1, A
+ case 0xf7: mov_ir_a(op&1); break; //MOV @R0/@R1, A
case 0xf8:
case 0xf9:
@@ -1416,7 +1416,7 @@ static const UINT8 mcs51_cycles[] = {
**********************************************************************************/
static void check_irqs(void)
{
- UINT8 ints = (GET_IE0 | (GET_TF0<<1) | (GET_IE1<<2) | (GET_TF1<<3)
+ UINT8 ints = (GET_IE0 | (GET_TF0<<1) | (GET_IE1<<2) | (GET_TF1<<3)
| ((GET_RI|GET_TI)<<4));
UINT8 ip = IP;
UINT8 int_vec = 0;
@@ -1428,18 +1428,18 @@ static void check_irqs(void)
if (mcs51.features & FEATURE_I8052_UART)
ints |= ((GET_TF2|GET_EXF2)<<5);
-
+
/* mask out interrupts not enabled */
ints &= IE;
if (!ints) return;
- if(mcs51.irq_priority)
+ if(mcs51.irq_priority)
{
- LOG(("high priority irq in progress, skipping irq request\n"));
- return;
+ LOG(("high priority irq in progress, skipping irq request\n"));
+ return;
}
-
+
for (i=0; i<mcs51.num_interrupts; i++)
{
if (ints & (1<<i))
@@ -1453,16 +1453,16 @@ static void check_irqs(void)
//Skip the interrupt request if currently processing is lo priority, and the new request IS NOT HI PRIORITY!
if(mcs51.cur_irq < 0xff && !priority_request)
- {
- LOG(("low priority irq in progress already, skipping low irq request\n"));
- return;
+ {
+ LOG(("low priority irq in progress already, skipping low irq request\n"));
+ return;
}
//Save current pc to stack, set pc to new interrupt vector
push_pc();
PC = int_vec;
change_pc(PC);
-
+
/* interrupts take 24 cycles */
mcs51.inst_cycles += 2;
@@ -1476,7 +1476,7 @@ static void check_irqs(void)
//External Int Flag only cleared when configured as Edge Triggered..
if(GET_IT0) /* for some reason having this, breaks alving dmd games */
SET_IE0(0);
-
+
/* indicate we took the external IRQ */
if (mcs51.irq_callback != NULL)
(*mcs51.irq_callback)(0);
@@ -1516,7 +1516,7 @@ INLINE void burn_cycles(int cycles)
/* Update Serial (only for mode 0) */
update_serial(cycles);
-
+
/* check_irqs */
check_irqs();
}
@@ -1524,20 +1524,20 @@ INLINE void burn_cycles(int cycles)
static void mcs51_set_irq_line(int irqline, int state)
{
/* From the manual:
- *
- * <cite>In operatiom all the interrupt tlags are latched into the
- * interrupt control system during State 5 of every ma-
- * chine cycle. The samples are polled during the follow-
- * ing machine cycle.</cite>
- *
- * ==> Since we do not emulate substates, this assumes that the signal is present
- * for at least one cycle (12 states)
- *
- */
+ *
+ * <cite>In operatiom all the interrupt tlags are latched into the
+ * interrupt control system during State 5 of every ma-
+ * chine cycle. The samples are polled during the follow-
+ * ing machine cycle.</cite>
+ *
+ * ==> Since we do not emulate substates, this assumes that the signal is present
+ * for at least one cycle (12 states)
+ *
+ */
int new_state = (mcs51.last_line_state & ~(1 << irqline)) | ((state != CLEAR_LINE) << irqline);
/* detect 0->1 transistions */
int tr_state = (~mcs51.last_line_state) & new_state;
-
+
switch( irqline )
{
//External Interrupt 0
@@ -1560,7 +1560,7 @@ static void mcs51_set_irq_line(int irqline, int state)
if (!GET_IT0) /* clear if level triggered */
SET_IE0(0);
}
-
+
break;
//External Interrupt 1
@@ -1589,7 +1589,7 @@ static void mcs51_set_irq_line(int irqline, int state)
if (GET_BIT(tr_state, MCS51_T0_LINE))
mcs51.t0_cnt++;
break;
-
+
case MCS51_T1_LINE:
if (GET_BIT(tr_state, MCS51_T1_LINE))
mcs51.t1_cnt++;
@@ -1601,21 +1601,21 @@ static void mcs51_set_irq_line(int irqline, int state)
if (GET_BIT(tr_state, MCS51_T2_LINE))
mcs51.t2_cnt++;
}
- else
+ else
fatalerror("mcs51: Trying to set T2_LINE on a non I8052 type cpu.\n");
break;
case MCS51_T2EX_LINE:
if (mcs51.features & FEATURE_I8052_UART)
{
- if (GET_TR2 && GET_EXEN2)
+ if (GET_TR2 && GET_EXEN2)
if (GET_BIT(tr_state, MCS51_T2EX_LINE))
{
SET_EXF2(1);
mcs51.t2ex_cnt++;
}
}
- else
+ else
fatalerror("mcs51: Trying to set T2EX_LINE on a non I8052 type cpu.\n");
break;
//Serial Port Receive
@@ -1634,7 +1634,7 @@ static void mcs51_set_irq_line(int irqline, int state)
static int mcs51_execute(int cycles)
{
UINT8 op;
-
+
mcs51_icount = cycles;
/* external interrupts may have been set since we last checked */
@@ -1657,7 +1657,7 @@ static int mcs51_execute(int cycles)
/* burn the cycles */
mcs51_icount -= mcs51.inst_cycles;
burn_cycles(mcs51.inst_cycles);
-
+
} while( mcs51_icount > 0 );
return cycles - mcs51_icount;
@@ -1672,7 +1672,7 @@ static void mcs51_sfr_write(size_t offset, UINT8 data)
{
/* update register */
assert(offset >= 0x80 && offset <= 0xff);
-
+
/* TODO: Move to memory map */
switch (offset)
{
@@ -1728,10 +1728,10 @@ static UINT8 mcs51_sfr_read(size_t offset)
case ADDR_DPL:
case ADDR_DPH:
case ADDR_PCON:
- case ADDR_TCON:
+ case ADDR_TCON:
case ADDR_TMOD:
case ADDR_TL0:
- case ADDR_TL1:
+ case ADDR_TL1:
case ADDR_TH0:
case ADDR_TH1:
case ADDR_SCON:
@@ -1775,7 +1775,7 @@ static void mcs51_init(int index, int clock, const void *config, int (*irqcallba
static void i80c51_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
mcs51_init(index, clock, config, irqcallback);
-
+
mcs51.features |= (FEATURE_CMOS_IDLE | FEATURE_CMOS_POWERDOWN);
}
@@ -1788,13 +1788,13 @@ static void mcs51_reset(void)
hold_serial_tx_callback = NULL;
mcs51.serial_rx_callback = hold_serial_rx_callback;
hold_serial_rx_callback = NULL;
-
+
mcs51.last_line_state = 0;
mcs51.t0_cnt = 0;
mcs51.t1_cnt = 0;
mcs51.t2_cnt = 0;
mcs51.t2ex_cnt = 0;
-
+
/* these are all defined reset states */
PC = 0;
SP = 0x7;
@@ -1837,7 +1837,7 @@ static void i8052_sfr_write(size_t offset, UINT8 data)
switch (offset)
{
/* 8052 family specific */
- case ADDR_T2CON:
+ case ADDR_T2CON:
case ADDR_RCAP2L:
case ADDR_RCAP2H:
case ADDR_TL2:
@@ -1855,11 +1855,11 @@ static UINT8 i8052_sfr_read(size_t offset)
switch (offset)
{
/* 8052 family specific */
- case ADDR_T2CON:
+ case ADDR_T2CON:
case ADDR_RCAP2L:
- case ADDR_RCAP2H:
+ case ADDR_RCAP2H:
case ADDR_TL2:
- case ADDR_TH2:
+ case ADDR_TH2:
return data_read_byte_8le((size_t) offset | 0x100);
default:
return mcs51_sfr_read(offset);
@@ -1868,7 +1868,7 @@ static UINT8 i8052_sfr_read(size_t offset)
static void i8052_init (int index, int clock, const void *config, int (*irqcallback)(int))
{
- mcs51_init(index, clock, config, irqcallback);
+ mcs51_init(index, clock, config, irqcallback);
mcs51.ram_mask = 0xFF; /* 256 bytes of ram */
mcs51.num_interrupts = 6; /* 6 interrupts */
@@ -1881,14 +1881,14 @@ static void i8052_init (int index, int clock, const void *config, int (*irqcallb
static void i80c52_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
i8052_init(index, clock, config, irqcallback);
-
+
mcs51.features |= (FEATURE_CMOS_IDLE | FEATURE_CMOS_POWERDOWN);
}
static void i8052_reset(void)
{
mcs51_reset();
-
+
//8052 Only registers
T2CON = 0;
RCAP2L = 0;
@@ -2032,7 +2032,7 @@ static void mcs51_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_INT_REGISTER + I8051_R5: info->i = R_REG(5); break;
case CPUINFO_INT_REGISTER + I8051_R6: info->i = R_REG(6); break;
case CPUINFO_INT_REGISTER + I8051_R7: info->i = R_REG(7); break;
- case CPUINFO_INT_REGISTER + I8051_RB: info->i = R_REG(8); break;
+ case CPUINFO_INT_REGISTER + I8051_RB: info->i = R_REG(8); break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = mcs51_set_info; break;
diff --git a/src/emu/cpu/i8051/i8051ops.c b/src/emu/cpu/i8051/i8051ops.c
index 240b77c749a..d0b6c2e4886 100644
--- a/src/emu/cpu/i8051/i8051ops.c
+++ b/src/emu/cpu/i8051/i8051ops.c
@@ -170,7 +170,7 @@ INLINE void cjne_a_byte(void)
if(ACC != data) //Jump if values are not equal
{
- PC = PC + rel_addr;
+ PC = PC + rel_addr;
change_pc(PC);
}
diff --git a/src/mame/drivers/cosmic.c b/src/mame/drivers/cosmic.c
index b2818a6bdbe..42a7f232ecc 100644
--- a/src/mame/drivers/cosmic.c
+++ b/src/mame/drivers/cosmic.c
@@ -200,7 +200,7 @@ static WRITE8_HANDLER( cosmica_sound_output_w )
{
static int sound_enabled=1;
static int dive_bomb_b_select=0;
-
+
/* Sound Enable / Disable */
if (offset == 11)
{
@@ -231,7 +231,7 @@ static WRITE8_HANDLER( cosmica_sound_output_w )
{
case 2:
-
+
if (sample_playing(2))
{
sample_stop(2);
@@ -239,8 +239,8 @@ static WRITE8_HANDLER( cosmica_sound_output_w )
}
else
sample_start(2, 3, 0); break;
-
-
+
+
case 3:
if (sample_playing(3))
@@ -259,7 +259,7 @@ static WRITE8_HANDLER( cosmica_sound_output_w )
sample_start(4, 5, 0); break;
}
else
- sample_start(4, 5, 0); break;
+ sample_start(4, 5, 0); break;
@@ -293,7 +293,7 @@ static WRITE8_HANDLER( cosmica_sound_output_w )
sample_start(7, 8, 0); break;
}
}
-
+
case 3: /*Dive Bombing Type B (G.S.B)*/
if (data)
@@ -322,17 +322,17 @@ static WRITE8_HANDLER( cosmica_sound_output_w )
case 6: if (data) sample_start(8, 9, 0); break; /*Fire Control*/
-
+
case 7: if (data) sample_start(9, 10, 0); break; /*Small Explosion*/
case 8: if (data) sample_start(10, 11, 0); break; /*Loud Explosion*/
-
+
case 9:
if (data)
sample_start(11, 1, 1);
else
sample_stop(11);
-
+
break; /*Extend Sound control*/
case 12:
@@ -1001,7 +1001,7 @@ GFXDECODE_END
static const char *cosmica_sample_names[] =
{
"*cosmica",
- "backgr.wav",
+ "backgr.wav",
"extend.wav",
"divea.wav",
"diveb1.wav",
@@ -1009,11 +1009,11 @@ static const char *cosmica_sample_names[] =
"diveb3.wav",
"diveb4.wav",
"diveb5.wav",
- "diveb6.wav",
- "fire.wav",
- "loudexp.wav",
- "smallexp.wav",
- "coin.wav",
+ "diveb6.wav",
+ "fire.wav",
+ "loudexp.wav",
+ "smallexp.wav",
+ "coin.wav",
0 /* end of array */
};
diff --git a/src/mame/drivers/cps3.c b/src/mame/drivers/cps3.c
index 1170928cc0b..3c4892a12cf 100644
--- a/src/mame/drivers/cps3.c
+++ b/src/mame/drivers/cps3.c
@@ -691,14 +691,14 @@ static void cps3_decrypt_bios(running_machine *machine)
UINT32 xormask = cps3_mask(i, cps3_key1, cps3_key2);
/* a bit of a hack, don't decrypt the FLASH commands which are transfered by SH2 DMA */
-// if (((i<0x1ff00) || (i>0x1ff6b)) && (i<0x20000) )
-// {
+// if (((i<0x1ff00) || (i>0x1ff6b)) && (i<0x20000) )
+// {
decrypted_bios[i/4] = dword ^ xormask;
-// }
-// else
-// {
-// decrypted_bios[i/4] = dword;
-// }
+// }
+// else
+// {
+// decrypted_bios[i/4] = dword;
+// }
}
#if 0
/* Dump to file */
@@ -2569,13 +2569,13 @@ static NVRAM_HANDLER( cps3 )
static UINT32 cps3_dma_callback(UINT32 src, UINT32 dst, UINT32 data, int size)
{
/*
- on the actual CPS3 hardware the SH2 DMA bypasses the encryption.
+ on the actual CPS3 hardware the SH2 DMA bypasses the encryption.
- to handle this in MAME we use this callback, and reverse the effect of the
- encryption that would otherwise be applied. this allows us to avoid per-game,
- per-PC hacks. this approach is however still a little messy.
+ to handle this in MAME we use this callback, and reverse the effect of the
+ encryption that would otherwise be applied. this allows us to avoid per-game,
+ per-PC hacks. this approach is however still a little messy.
- */
+ */
/* I doubt this is endian safe.. needs checking / fixing */
if (size==0)
@@ -2946,138 +2946,138 @@ ROM_END
/*****************************************************************************************
- JoJo's Venture
+ JoJo's Venture
- XXXXXX 0
- JAPAN 1
- ASIA 2
- EURO 3
- USA 4
- HISPANIC 5
- BRAZIL 6
- OCEANIA 7
+ XXXXXX 0
+ JAPAN 1
+ ASIA 2
+ EURO 3
+ USA 4
+ HISPANIC 5
+ BRAZIL 6
+ OCEANIA 7
- DEVELOPMENT VERSION add 0x70 mask!
+ DEVELOPMENT VERSION add 0x70 mask!
- UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
- rom[0x1fec8/4]^=0x00000001; // region hack (clear jpn)
+ UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
+ rom[0x1fec8/4]^=0x00000001; // region hack (clear jpn)
- rom[0x1fec8/4]^=0x00000004; // region
- rom[0x1fec8/4]^=0x00000070; // DEV mode
- rom[0x1fecc/4]^=0x01000000; // nocd
+ rom[0x1fec8/4]^=0x00000004; // region
+ rom[0x1fec8/4]^=0x00000070; // DEV mode
+ rom[0x1fecc/4]^=0x01000000; // nocd
*****************************************************************************************/
/*****************************************************************************************
- JoJo's Bizarre Adventure: Heritage for the Future
+ JoJo's Bizarre Adventure: Heritage for the Future
- XXXXXX 0
- JAPAN 1
- ASIA 2
- EURO 3
- USA 4
- HISPANIC 5
- BRAZIL 6
- OCEANIA 7
+ XXXXXX 0
+ JAPAN 1
+ ASIA 2
+ EURO 3
+ USA 4
+ HISPANIC 5
+ BRAZIL 6
+ OCEANIA 7
- DEVELOPMENT VERSION add 0x70 mask!
+ DEVELOPMENT VERSION add 0x70 mask!
- UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
- rom[0x1fec8/4]^=0x00000001; // region (clear jpn)
- rom[0x1fec8/4]^=0x00000002; // region
- rom[0x1fec8/4]^=0x00000070; // DEV mode
- rom[0x1fecc/4]^=0x01000000; // nocd
+ UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
+ rom[0x1fec8/4]^=0x00000001; // region (clear jpn)
+ rom[0x1fec8/4]^=0x00000002; // region
+ rom[0x1fec8/4]^=0x00000070; // DEV mode
+ rom[0x1fecc/4]^=0x01000000; // nocd
*****************************************************************************************/
/*****************************************************************************************
- Red Earth / Warzard
-
- JAPAN 1
- ASIA 2
- EURO 3
- USA 4
- HISPANIC 5
- BRAZIL 6
- OCEANIA 7
- ASIA NCD 8
-
- UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
- rom[0x1fed8/4]^=0x00000001; // clear region to 0 (invalid)
- rom[0x1fed8/4]^=0x00000008; // region 8 - ASIA NO CD - doesn't actually skip the CD
- // test on startup, only during game, must be another flag
- // somewhere too, and we don't have any actual NCD dumps
- // to compare (or it expects SCSI to report there being
- // no cd drive?)
+ Red Earth / Warzard
+
+ JAPAN 1
+ ASIA 2
+ EURO 3
+ USA 4
+ HISPANIC 5
+ BRAZIL 6
+ OCEANIA 7
+ ASIA NCD 8
+
+ UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
+ rom[0x1fed8/4]^=0x00000001; // clear region to 0 (invalid)
+ rom[0x1fed8/4]^=0x00000008; // region 8 - ASIA NO CD - doesn't actually skip the CD
+ // test on startup, only during game, must be another flag
+ // somewhere too, and we don't have any actual NCD dumps
+ // to compare (or it expects SCSI to report there being
+ // no cd drive?)
*****************************************************************************************/
/*****************************************************************************************
- Street Fighter III: New Generation
+ Street Fighter III: New Generation
- JAPAN 1
- ASIA NCD 2
- EURO 3
- USA 4
- HISPANIC 5
- BRAZIL 6
- OCEANIA 7
- ASIA 8
+ JAPAN 1
+ ASIA NCD 2
+ EURO 3
+ USA 4
+ HISPANIC 5
+ BRAZIL 6
+ OCEANIA 7
+ ASIA 8
- // bios rom also lists korea, but game rom does not.
+ // bios rom also lists korea, but game rom does not.
- UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
- rom[0x1fec8/4]^=0x00000001; // region (clear region)
- rom[0x1fec8/4]^=0x00000008; // region
- rom[0x1fecc/4]^=0x01000000; // nocd - this ONLY skips the cd check in the bios test
- // menu is region is ASIA NCD, otherwise it will report
- // NG, Asia was probably the only NCD region for this
+ UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
+ rom[0x1fec8/4]^=0x00000001; // region (clear region)
+ rom[0x1fec8/4]^=0x00000008; // region
+ rom[0x1fecc/4]^=0x01000000; // nocd - this ONLY skips the cd check in the bios test
+ // menu is region is ASIA NCD, otherwise it will report
+ // NG, Asia was probably the only NCD region for this
*****************************************************************************************/
/*****************************************************************************************
- Street Fighter III 2nd Impact
+ Street Fighter III 2nd Impact
- JAPAN 1
- ASIA NCD 2
- EURO 3
- USA 4
- HISPANIC 5
- BRAZIL 6
- OCEANIA 7
- ASIA 8
+ JAPAN 1
+ ASIA NCD 2
+ EURO 3
+ USA 4
+ HISPANIC 5
+ BRAZIL 6
+ OCEANIA 7
+ ASIA 8
- UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
- rom[0x1fec8/4]^=0x00000001; // region (clear region)
- rom[0x1fec8/4]^=0x00000008; // region
- rom[0x1fecc/4]^=0x01000000; // nocd - this ONLY skips the cd check in the bios test
- // menu is region is ASIA NCD, otherwise it will report
- // NG, Asia was probably the only NCD region for this
+ UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
+ rom[0x1fec8/4]^=0x00000001; // region (clear region)
+ rom[0x1fec8/4]^=0x00000008; // region
+ rom[0x1fecc/4]^=0x01000000; // nocd - this ONLY skips the cd check in the bios test
+ // menu is region is ASIA NCD, otherwise it will report
+ // NG, Asia was probably the only NCD region for this
*****************************************************************************************/
/*****************************************************************************************
- Street Fighter III 3rd Strike
+ Street Fighter III 3rd Strike
- JAPAN 1
- ASIA 2
- EURO 3
- USA 4
- HISPANIC 5
- BRAZIL 6
- OCEANIA 7
+ JAPAN 1
+ ASIA 2
+ EURO 3
+ USA 4
+ HISPANIC 5
+ BRAZIL 6
+ OCEANIA 7
- UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
- rom[0x1fec8/4]^=0x00000004; // region (clear region)
- rom[0x1fec8/4]^=0x00000001; // region
- rom[0x1fecc/4]^=0x01000000; // nocd
+ UINT32 *rom = (UINT32*)memory_region ( machine, "user1" );
+ rom[0x1fec8/4]^=0x00000004; // region (clear region)
+ rom[0x1fec8/4]^=0x00000001; // region
+ rom[0x1fecc/4]^=0x01000000; // nocd
*****************************************************************************************/
diff --git a/src/mame/drivers/ddealer.c b/src/mame/drivers/ddealer.c
index 15cd60553fb..139531f82d4 100644
--- a/src/mame/drivers/ddealer.c
+++ b/src/mame/drivers/ddealer.c
@@ -235,10 +235,10 @@ static VIDEO_UPDATE( ddealer )
tilemap_draw(bitmap,cliprect,back_tilemap,0,0);
/* the fg tilemap handling is a little hacky right now,
- i'm not sure if it should be a single tilemap with
- rowscroll / linescroll, or two tilemaps which can be
- combined, the flipscreen case makes things more
- difficult to understand */
+ i'm not sure if it should be a single tilemap with
+ rowscroll / linescroll, or two tilemaps which can be
+ combined, the flipscreen case makes things more
+ difficult to understand */
if (!ddealer_flipscreen)
{
@@ -306,7 +306,7 @@ static TIMER_DEVICE_CALLBACK( ddealer_mcu_sim )
input_pressed = (input_pressed & 0xfb);
/*0x104/2 is some sort of "start-lock",i.e. used on the girl selection.
- Without it,the game "steals" one credit if you press the start button on that.*/
+ Without it,the game "steals" one credit if you press the start button on that.*/
if(mcu_shared_ram[0x000/2] > 0 && work_ram[0x104/2] & 1)
{
if(coin_input & 0x08)//start 1
diff --git a/src/mame/drivers/itech8.c b/src/mame/drivers/itech8.c
index d93d11afa49..43b10cad76f 100644
--- a/src/mame/drivers/itech8.c
+++ b/src/mame/drivers/itech8.c
@@ -1866,7 +1866,7 @@ static MACHINE_DRIVER_START( grmatch )
MDRV_SCREEN_MODIFY("main")
MDRV_SCREEN_VISIBLE_AREA(0, 399, 0, 239)
MDRV_VIDEO_UPDATE(itech8_grmatch)
-
+
/* palette updater */
MDRV_TIMER_ADD_SCANLINE("palette", grmatch_palette_update, "main", 0, 0)
MACHINE_DRIVER_END
diff --git a/src/mame/drivers/m72.c b/src/mame/drivers/m72.c
index fe0e641cffb..0a643cb8901 100644
--- a/src/mame/drivers/m72.c
+++ b/src/mame/drivers/m72.c
@@ -125,7 +125,7 @@ static MACHINE_RESET( m72 )
mcu_snd_cmd_latch = 0;
MACHINE_RESET_CALL(m72_sound);
-
+
state_save_register_global(mcu_sample_addr);
state_save_register_global(mcu_snd_cmd_latch);
@@ -219,9 +219,9 @@ static WRITE16_HANDLER( m72_main_mcu_w)
COMBINE_DATA(&val);
- /* 0x07fe is used for synchronization as well.
- * This address however will not trigger an interrupt
- */
+ /* 0x07fe is used for synchronization as well.
+ * This address however will not trigger an interrupt
+ */
if (offset == 0x0fff/2 && ACCESSING_BITS_8_15)
{
@@ -246,7 +246,7 @@ static WRITE8_HANDLER( m72_mcu_data_w )
static READ8_HANDLER(m72_mcu_data_r )
{
UINT8 ret;
-
+
if (offset&1) ret = (protection_ram[offset/2] & 0xff00)>>8;
else ret = (protection_ram[offset/2] & 0x00ff);
@@ -323,7 +323,7 @@ INLINE DRIVER_INIT( loht_mcu )
{
int cpunum = mame_find_cpu_index(machine, "main");
int sndnum = mame_find_cpu_index(machine, "sound");
-
+
protection_ram = auto_malloc(0x10000);
memory_install_read16_handler(machine, cpunum, ADDRESS_SPACE_PROGRAM, 0xb0000, 0xbffff, 0, 0, SMH_BANK1);
memory_install_write16_handler(machine, cpunum, ADDRESS_SPACE_PROGRAM, 0xb0000, 0xb0fff, 0, 0, m72_main_mcu_w);
@@ -1065,7 +1065,7 @@ static ADDRESS_MAP_START( mcu_io_map, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x0002, 0x0002) AM_READWRITE(m72_mcu_snd_r, m72_mcu_ack_w)
/* shared at b0000 - b0fff on the main cpu */
AM_RANGE(0xc000, 0xcfff) AM_RAM AM_READWRITE(m72_mcu_data_r,m72_mcu_data_w )
-
+
/* Ports */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(m72_mcu_port_r, m72_mcu_port_w)
ADDRESS_MAP_END
@@ -1866,10 +1866,10 @@ MACHINE_DRIVER_END
static MACHINE_DRIVER_START( m72_8751 )
MDRV_IMPORT_FROM(m72_base)
-
+
MDRV_CPU_ADD("mcu",I8751, MASTER_CLOCK/2)
/* internal - MDRV_CPU_PROGRAM_MAP(mcu_map,0) */
- //MDRV_CPU_DATA_MAP(mcu_data_map,0)
+ //MDRV_CPU_DATA_MAP(mcu_data_map,0)
MDRV_CPU_IO_MAP(mcu_io_map,0)
MDRV_CPU_VBLANK_INT("main", m72_mcu_int)
//MDRV_INTERLEAVE(1000)
diff --git a/src/mame/drivers/magictg.c b/src/mame/drivers/magictg.c
index 4b31063f586..1ea3d40e07b 100644
--- a/src/mame/drivers/magictg.c
+++ b/src/mame/drivers/magictg.c
@@ -5,58 +5,58 @@
Magic the Gathereing: Armageddon by Acclaim
TOP Board
-.20u 27c4001 stickered U20
- #1537 V1.0 a 1 was hadwritten over the 0
-
-.u7 stamped (c) 1997
- ACCLAIM COINOP
- ARMAGEDDON
- SND3 P/N 1605
- 9806 D
-
-
-.u8 stamped (c) 1997 11/25/97
- ACCLAIM COINOP
- ARMAGEDDON
- 1534 SND0
- 9752 D
-
-.u13 stamped (c) 1997 11/25/97
- ACCLAIM COINOP
- ARMAGEDDON
- 1536 SND2
- 9752 D
-
-.u14 stamped (c) 1997 11/25/97
- ACCLAIM COINOP
- ARMAGEDDON
- 1535 SND1
- 9752 D
-
-Analog devices ADSP 2181
-Xilinx XC5202
+.20u 27c4001 stickered U20
+ #1537 V1.0 a 1 was hadwritten over the 0
+
+.u7 stamped (c) 1997
+ ACCLAIM COINOP
+ ARMAGEDDON
+ SND3 P/N 1605
+ 9806 D
+
+
+.u8 stamped (c) 1997 11/25/97
+ ACCLAIM COINOP
+ ARMAGEDDON
+ 1534 SND0
+ 9752 D
+
+.u13 stamped (c) 1997 11/25/97
+ ACCLAIM COINOP
+ ARMAGEDDON
+ 1536 SND2
+ 9752 D
+
+.u14 stamped (c) 1997 11/25/97
+ ACCLAIM COINOP
+ ARMAGEDDON
+ 1535 SND1
+ 9752 D
+
+Analog devices ADSP 2181
+Xilinx XC5202
dt71256 x2
-Analog Devices AD1866R
+Analog Devices AD1866R
Bottom board
-.u32 27c801 stickered 4
-.u33 27c801 stickered 3
-.u34 27c801 stickered 2
-.u35 27c801 stickered 1
-.u58 AT17C128 stickered CC3E
-.u66 GAL16V8D
-
-Xilinx XC4005E
-Xilinx XC95108 stickered ACCLAIM COIN-OP
- CSC2_10.JED
- B710/0B84
- U40 p/N 1611
-
-3dFX 500-0003-03 x2
- BF1684.1
-TI TVP3409
- V53C16258HK40 x24
- V53C511816500K60 x4
+.u32 27c801 stickered 4
+.u33 27c801 stickered 3
+.u34 27c801 stickered 2
+.u35 27c801 stickered 1
+.u58 AT17C128 stickered CC3E
+.u66 GAL16V8D
+
+Xilinx XC4005E
+Xilinx XC95108 stickered ACCLAIM COIN-OP
+ CSC2_10.JED
+ B710/0B84
+ U40 p/N 1611
+
+3dFX 500-0003-03 x2
+ BF1684.1
+TI TVP3409
+ V53C16258HK40 x24
+ V53C511816500K60 x4
2 big chips with heat sinks on them, one by each 3dFX part
2 big chips with heat sinks on them, by the EPROMS
14.31818 Oscillator by the TI part
@@ -66,44 +66,44 @@ KM622560LG-7 by Battery
Bottom daughter board
All read as 29F800B
-.u9 stamped (c) 1997
- ACCLAIM COINOP
- ARMAGEDDON S0
- 1514 11/25/97
- 9803 D
-
-
-.u10 stamped (c) 1997
- ACCLAIM COINOP
- ARMAGEDDON S1
- 1515 11/25/97
- 9803 D
-
-.u11 stamped (c) 1997
- ACCLAIM COINOP
- ARMAGEDDON S3
- 1517 11/25/97
- 9803 D
-
-.u12 stamped (c) 1997
- ACCLAIM COINOP
- ARMAGEDDON S2
- 1516 11/25/97
- 9803 D
-
-.u20 stamped (c) 1997
- ACCLAIM COINOP
- ARMAGEDDON K0
- 1543 11/25/97
- 9752 D
-
-Xilinx XC4010E
-Zoran ZR36120PQC
-Zoran ZR36016PQC
-Xilinx XC3120A
- DT72811
- DT71256 x2
- DT72271
+.u9 stamped (c) 1997
+ ACCLAIM COINOP
+ ARMAGEDDON S0
+ 1514 11/25/97
+ 9803 D
+
+
+.u10 stamped (c) 1997
+ ACCLAIM COINOP
+ ARMAGEDDON S1
+ 1515 11/25/97
+ 9803 D
+
+.u11 stamped (c) 1997
+ ACCLAIM COINOP
+ ARMAGEDDON S3
+ 1517 11/25/97
+ 9803 D
+
+.u12 stamped (c) 1997
+ ACCLAIM COINOP
+ ARMAGEDDON S2
+ 1516 11/25/97
+ 9803 D
+
+.u20 stamped (c) 1997
+ ACCLAIM COINOP
+ ARMAGEDDON K0
+ 1543 11/25/97
+ 9752 D
+
+Xilinx XC4010E
+Zoran ZR36120PQC
+Zoran ZR36016PQC
+Xilinx XC3120A
+ DT72811
+ DT71256 x2
+ DT72271
29.500000 osciallator by ZR36120PQC
Medium size chip with heat sink on it
diff --git a/src/mame/drivers/megadriv.c b/src/mame/drivers/megadriv.c
index c96858d10c5..437eed87487 100644
--- a/src/mame/drivers/megadriv.c
+++ b/src/mame/drivers/megadriv.c
@@ -5524,16 +5524,16 @@ static WRITE16_HANDLER( _32x_68k_palette_w )
// returns MARS, the system ID of the 32x
static READ16_HANDLER( _32x_68k_MARS_r )
{
- switch (offset)
- {
- case 0:
- return 0x4d41;
+ switch (offset)
+ {
+ case 0:
+ return 0x4d41;
- case 1:
- return 0x5253;
- }
+ case 1:
+ return 0x5253;
+ }
- return 0x0000;
+ return 0x0000;
}
*/
@@ -5548,9 +5548,9 @@ DRIVER_INIT( _32x )
memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0900000, 0x09fffff, 0, 0, SMH_BANK12, SMH_BANK12); // 'bankable' 1024kb rom bank
memory_set_bankptr( 12, memory_region(machine, "gamecart") );
-// memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0000000, 0x00000ff, 0, 0, SMH_BANK10, SMH_BANK10);
-// memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0000100, 0x03fffff, 0, 0, SMH_NOP, SMH_NOP );
-// memory_set_bankptr( 10, memory_region(machine, "32x_68k_bios") );
+// memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0000000, 0x00000ff, 0, 0, SMH_BANK10, SMH_BANK10);
+// memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0000100, 0x03fffff, 0, 0, SMH_NOP, SMH_NOP );
+// memory_set_bankptr( 10, memory_region(machine, "32x_68k_bios") );
_32x_dram0 = auto_malloc(0x20000);
_32x_dram1 = auto_malloc(0x20000);
@@ -5575,7 +5575,7 @@ DRIVER_INIT( _32x )
_32x_a1518a_reg = 0x00; // inital value
memory_install_readwrite16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0a1518a, 0x0a1518b, 0, 0, _32x_68k_fbcontrol_r, _32x_68k_fbcontrol_w); // framebuffer control regs
-// memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0a130ec, 0x0a151ef, 0, 0, _32x_68k_MARS_r); // system ID
+// memory_install_read16_handler(machine, 0, ADDRESS_SPACE_PROGRAM, 0x0a130ec, 0x0a151ef, 0, 0, _32x_68k_MARS_r); // system ID
DRIVER_INIT_CALL(megadriv);
@@ -5588,9 +5588,9 @@ ROM_START( 32x_bios )
ROM_REGION16_BE( 0x400000, "gamecart", 0 ) /* 68000 Code */
ROM_LOAD( "32xquin.rom", 0x000000, 0x005d124, CRC(93d4b0a3) SHA1(128bd0b6e048c749da1a2f4c3abd6a867539a293))
-// ROM_LOAD( "32x_babe.rom", 0x000000, 0x14f80, CRC(816b0cb4) SHA1(dc16d3170d5809b57192e03864b7136935eada64) )
-// ROM_LOAD( "32xhot.rom", 0x000000, 0x01235c, CRC(da9c93c9) SHA1(a62652eb8ad8c62b36f6b1ffb96922d045c4e3ac))
-// ROM_LOAD( "knux.rom", 0x000000, 0x300000, CRC(d0b0b842) SHA1(0c2fff7bc79ed26507c08ac47464c3af19f7ced7) )
+// ROM_LOAD( "32x_babe.rom", 0x000000, 0x14f80, CRC(816b0cb4) SHA1(dc16d3170d5809b57192e03864b7136935eada64) )
+// ROM_LOAD( "32xhot.rom", 0x000000, 0x01235c, CRC(da9c93c9) SHA1(a62652eb8ad8c62b36f6b1ffb96922d045c4e3ac))
+// ROM_LOAD( "knux.rom", 0x000000, 0x300000, CRC(d0b0b842) SHA1(0c2fff7bc79ed26507c08ac47464c3af19f7ced7) )
ROM_REGION16_BE( 0x400000, "32x_68k_bios", 0 ) /* 68000 Code */
ROM_LOAD( "32x_g_bios.bin", 0x000000, 0x000100, CRC(5c12eae8) SHA1(dbebd76a448447cb6e524ac3cb0fd19fc065d944) )
diff --git a/src/mame/drivers/megasys1.c b/src/mame/drivers/megasys1.c
index 041f8c0da5e..af9081a2ec0 100644
--- a/src/mame/drivers/megasys1.c
+++ b/src/mame/drivers/megasys1.c
@@ -1303,7 +1303,7 @@ ROM_START( monkelf )
ROM_LOAD( "2", 0x000000, 0x040000, CRC(05bc04d9) SHA1(b903edf39393cad2b4b6b58b10651304793aaa3e) )
ROM_REGION( 0x0200, "proms", 0 ) /* Priority PROM */
-// ROM_LOAD( "ph.bin", 0x0000, 0x0200, CRC(8359650a) SHA1(97d0105f06c64340fb19a541db03481a7e0b5e05) )
+// ROM_LOAD( "ph.bin", 0x0000, 0x0200, CRC(8359650a) SHA1(97d0105f06c64340fb19a541db03481a7e0b5e05) )
// the bootleg prom is a different format, i don't know how to use it
ROM_LOAD( "82s147", 0x0000, 0x0200, CRC(547eccc0) SHA1(44dd92e899a7852d2fd937b7d45519315b8b4d4f) )
ROM_END
diff --git a/src/mame/drivers/merit.c b/src/mame/drivers/merit.c
index a80e8f313fe..83f2bd4e1aa 100644
--- a/src/mame/drivers/merit.c
+++ b/src/mame/drivers/merit.c
@@ -316,7 +316,7 @@ static ADDRESS_MAP_START( bigappg_map, ADDRESS_SPACE_PROGRAM, 8 )
ADDRESS_MAP_END
/* Address decoding is done by prom u13 on crt200a hardware. It decodes
- * the following addr lines: 2,3,9,13,14,15 ==> E20C
+ * the following addr lines: 2,3,9,13,14,15 ==> E20C
* ==> mirror 1DF3 & ~effective_addr_lines
* */
diff --git a/src/mame/drivers/micro3d.c b/src/mame/drivers/micro3d.c
index 0e3c1e746ce..631687faedb 100644
--- a/src/mame/drivers/micro3d.c
+++ b/src/mame/drivers/micro3d.c
@@ -803,9 +803,9 @@ static WRITE8_HANDLER(sound_io_w)
port_latch[offset] = data;
switch(offset)
{
- case 0x01:
+ case 0x01:
break;
- case 0x03:
+ case 0x03:
upd7759_set_bank_base(0, (data & 0x4) ? 0x20000 : 0);
upd7759_0_reset_w(machine,0,(data & 0x10) ? 0 : 1);
}
diff --git a/src/mame/drivers/mirage.c b/src/mame/drivers/mirage.c
index d45c3e16cb7..d56a4f021f7 100644
--- a/src/mame/drivers/mirage.c
+++ b/src/mame/drivers/mirage.c
@@ -207,12 +207,12 @@ static ADDRESS_MAP_START( mirage_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x140000, 0x140001) AM_READWRITE(okim6295_status_1_lsb_r, okim6295_data_1_lsb_w)
AM_RANGE(0x140002, 0x140003) AM_READWRITE(okim6295_status_1_lsb_r, okim6295_data_1_lsb_w)
-// AM_RANGE(0x140008, 0x140009) AM_WRITE(okim1_rombank_w)
+// AM_RANGE(0x140008, 0x140009) AM_WRITE(okim1_rombank_w)
AM_RANGE(0x150000, 0x150001) AM_READWRITE(okim6295_status_0_lsb_r, okim6295_data_0_lsb_w)
AM_RANGE(0x150002, 0x150003) AM_READWRITE(okim6295_status_0_lsb_r, okim6295_data_0_lsb_w)
-// AM_RANGE(0x150008, 0x150009) AM_WRITE(okim0_rombank_w)
+// AM_RANGE(0x150008, 0x150009) AM_WRITE(okim0_rombank_w)
AM_RANGE(0x160000, 0x160001) AM_WRITE(SMH_NOP)
diff --git a/src/mame/drivers/plygonet.c b/src/mame/drivers/plygonet.c
index 7ded9ca7261..f755e94e359 100644
--- a/src/mame/drivers/plygonet.c
+++ b/src/mame/drivers/plygonet.c
@@ -66,10 +66,10 @@ static UINT32* shared_ram;
static UINT16* dsp56k_p_mirror;
static UINT16* dsp56k_p_8000;
static const UINT16 dsp56k_bank00_size = 0x1000; static UINT16* dsp56k_bank00_ram;
-static const UINT16 dsp56k_bank01_size = 0x1000; static UINT16* dsp56k_bank01_ram;
-static const UINT16 dsp56k_bank02_size = 0x4000; static UINT16* dsp56k_bank02_ram;
-static const UINT16 dsp56k_shared_ram_16_size = 0x2000; static UINT16* dsp56k_shared_ram_16;
-static const UINT16 dsp56k_bank04_size = 0x1fc0; static UINT16* dsp56k_bank04_ram;
+static const UINT16 dsp56k_bank01_size = 0x1000; static UINT16* dsp56k_bank01_ram;
+static const UINT16 dsp56k_bank02_size = 0x4000; static UINT16* dsp56k_bank02_ram;
+static const UINT16 dsp56k_shared_ram_16_size = 0x2000; static UINT16* dsp56k_shared_ram_16;
+static const UINT16 dsp56k_bank04_size = 0x1fc0; static UINT16* dsp56k_bank04_ram;
static const eeprom_interface eeprom_intf =
{
@@ -315,7 +315,7 @@ static OPBASE_HANDLER( plygonet_dsp56k_opbase_handler )
001c banking is fairly easy - it happens in a loop and writes from 8000 to bfff
0181 banking is very weird - it happens in a nested loop and writes from 6000-6fff, 7000-7fff, and 8000-ffbf
- bit 0002 turns on *just* before this happens.
+ bit 0002 turns on *just* before this happens.
*/
enum { BANK_GROUP_A, BANK_GROUP_B, INVALID_BANK_GROUP };
@@ -481,7 +481,7 @@ static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x580000, 0x5807ff) AM_RAM
AM_RANGE(0x580800, 0x580803) AM_READWRITE(network_r, SMH_NOP)
AM_RANGE(0x580800, 0x580803) AM_RAM /* network RAM | registers? */
-// AM_RANGE(0x600000, 0x600000)
+// AM_RANGE(0x600000, 0x600000)
AM_RANGE(0x600004, 0x600007) AM_WRITE(sound_w)
AM_RANGE(0x600008, 0x60000b) AM_READ(sound_r)
AM_RANGE(0x640000, 0x640003) AM_WRITE(sound_irq_w)
@@ -574,8 +574,8 @@ static MACHINE_START(polygonet)
/* Set the dsp56k lines */
/* It's presumed the hardware has hard-wired operating mode 1 (MODA = 1, MODB = 0) */
- /* TODO: This should work, but the MAME core appears to do something funny.
- Not a big deal - it's hacked in dsp_w_lines. */
+ /* TODO: This should work, but the MAME core appears to do something funny.
+ Not a big deal - it's hacked in dsp_w_lines. */
//cpunum_set_input_line(machine, mame_find_cpu_index(machine, "dsp"), INPUT_LINE_RESET, ASSERT_LINE);
//cpunum_set_input_line(machine, mame_find_cpu_index(machine, "dsp"), DSP56K_IRQ_MODA, ASSERT_LINE);
//cpunum_set_input_line(machine, mame_find_cpu_index(machine, "dsp"), DSP56K_IRQ_MODB, CLEAR_LINE);
diff --git a/src/mame/drivers/psattack.c b/src/mame/drivers/psattack.c
index 5e9c008c5db..7aced086f27 100644
--- a/src/mame/drivers/psattack.c
+++ b/src/mame/drivers/psattack.c
@@ -2,9 +2,9 @@
P's Attack
using VRender0 System on a Chip
- This is basically the same hardware as Crystal System, but with a CF card for the game
+ This is basically the same hardware as Crystal System, but with a CF card for the game
- Skeleton driver only
+ Skeleton driver only
P's Attack (c) 2004 Uniana Co., Ltd
diff --git a/src/mame/drivers/shangha3.c b/src/mame/drivers/shangha3.c
index 63f5db1e970..55576730fd7 100644
--- a/src/mame/drivers/shangha3.c
+++ b/src/mame/drivers/shangha3.c
@@ -105,7 +105,7 @@ static WRITE16_HANDLER( blocken_coinctrl_w )
{
/* the sound ROM bank is selected by the main CPU! */
okim6295_set_bank_base(0, ((data >> 4) & 3) * 0x40000);
-
+
coin_lockout_w(0,~data & 0x04);
coin_lockout_w(1,~data & 0x04);
coin_counter_w(0,data & 0x01);
@@ -691,7 +691,7 @@ ROM_START( blocken )
ROM_COPY( "samples", 0x000000, 0x080000, 0x020000)
ROM_COPY( "samples", 0x040000, 0x0a0000, 0x020000)
ROM_COPY( "samples", 0x000000, 0x0c0000, 0x020000)
- ROM_COPY( "samples", 0x060000, 0x0e0000, 0x020000)
+ ROM_COPY( "samples", 0x060000, 0x0e0000, 0x020000)
ROM_END
diff --git a/src/mame/drivers/tnzs.c b/src/mame/drivers/tnzs.c
index 10f9995867a..2ea989f3a78 100644
--- a/src/mame/drivers/tnzs.c
+++ b/src/mame/drivers/tnzs.c
@@ -215,7 +215,7 @@ Stephh's notes (based on the games Z80 code and some tests) :
- Code and data differences :
* CPU0 to be looked at carefully
* 0x9fff (CPU1 - bank = 0x03) : 0x01 instead of 0x02 (value for region tests)
-
+
5c) 'kagekih'
- Region stored at 0x9fff.b (CPU1 - bank = 0x03) then 0xe000 (shared RAM)
@@ -241,7 +241,7 @@ Stephh's notes (based on the games Z80 code and some tests) :
- Code and data differences :
* CPU0 to be looked at carefully
* 0x9fff (CPU1 - bank = 0x03) : 0x01 instead of 0x02 (value for region tests)
-
+
6) 'chukatai' and clones
diff --git a/src/mame/drivers/yumefuda.c b/src/mame/drivers/yumefuda.c
index 85ba1090fb1..fc0faf6400f 100644
--- a/src/mame/drivers/yumefuda.c
+++ b/src/mame/drivers/yumefuda.c
@@ -146,7 +146,7 @@ static WRITE8_HANDLER( eeprom_w )
static WRITE8_HANDLER( port_c0_w )
{
-// logerror("PC %04x (Port $c0) value written %02x\n",activecpu_get_pc(),data);
+// logerror("PC %04x (Port $c0) value written %02x\n",activecpu_get_pc(),data);
}
diff --git a/src/mame/video/itech8.c b/src/mame/video/itech8.c
index b99d47d8629..6cb4f1d115e 100644
--- a/src/mame/video/itech8.c
+++ b/src/mame/video/itech8.c
@@ -598,7 +598,7 @@ TIMER_DEVICE_CALLBACK( grmatch_palette_update )
/* the TMS34070s latch at the start of the frame, based on the first few bytes */
UINT32 page_offset = (tms_state.dispstart & 0x0ffff) | grmatch_xscroll;
int page, x;
-
+
/* iterate over both pages */
for (page = 0; page < 2; page++)
{
@@ -688,12 +688,12 @@ VIDEO_UPDATE( itech8_grmatch )
{
UINT8 pix0 = base0[x / 2];
UINT8 pix2 = base2[x / 2];
-
+
if ((pix0 & 0xf0) != 0)
dest[x] = grmatch_palette[0][pix0 >> 4];
else
dest[x] = grmatch_palette[1][pix2 >> 4];
-
+
if ((pix0 & 0x0f) != 0)
dest[x + 1] = grmatch_palette[0][pix0 & 0x0f];
else
diff --git a/src/mame/video/taito_f3.c b/src/mame/video/taito_f3.c
index 98748330857..686cb78424d 100644
--- a/src/mame/video/taito_f3.c
+++ b/src/mame/video/taito_f3.c
@@ -2411,8 +2411,8 @@ static void scanline_draw(running_machine *machine, bitmap_t *bitmap, const rect
if(alpha_type==1)
{
/* if (f3_alpha_level_2as==0 && f3_alpha_level_2ad==255)
- * alpha_mode[i]=3; alpha_mode_flag[i] |= 0x80;}
- * will display continue screen in gseeker (mt 00026) */
+ * alpha_mode[i]=3; alpha_mode_flag[i] |= 0x80;}
+ * will display continue screen in gseeker (mt 00026) */
if (f3_alpha_level_2as==0 && f3_alpha_level_2ad==255) alpha_mode[i]=0;
else if(f3_alpha_level_2as==255 && f3_alpha_level_2ad==0 ) alpha_mode[i]=1;
}
diff --git a/src/version.c b/src/version.c
index 3846016ea4a..318ca35c004 100644
--- a/src/version.c
+++ b/src/version.c
@@ -9,4 +9,4 @@
***************************************************************************/
-const char build_version[] = "0.128 ("__DATE__")";
+const char build_version[] = "0.128u1 ("__DATE__")";