set=UTF-8
Last-Modified: Sat, 03 May 2025 18:56:29 GMT
Expires: Tue, 01 May 2035 18:56:29 GMT
mame - MAME - Multiple Arcade Machine Emulator
62 files changed, 1257 insertions, 1258 deletions
@@ -3,7 +3,7 @@ /********************************************************************* gizmo.cpp - HAL Labs Gizmo digital joystick adapter - Used by Vindicator and Super Taxman 2. + Used by Vindicator and Super Taxman 2. *********************************************************************/ @@ -55,7 +55,7 @@ void apple2_gizmo_device::device_start() READ_LINE_MEMBER(apple2_gizmo_device::sw0_r) { - static const int gizmo_bits[8] = { 1,3,2,0,4,5,5,5 }; + static const int gizmo_bits[8] = { 1,3,2,0,4,5,5,5 }; return BIT(m_player1->read(),gizmo_bits[m_an0+(m_an1<<1)+(m_an2<<2)]); } @@ -3,7 +3,7 @@ /********************************************************************* gizmo.h - HAL Labs Gizmo digital joystick adapter - Used by Vindicator and Super Taxman 2. + Used by Vindicator and Super Taxman 2. *********************************************************************/ @@ -106,8 +106,8 @@ Notes: 0704: rr a 0706: call $073F - There is an alternate format function in the controller firmware that allows to set a secret byte which is stored in the sector header. - Copy protected software checks the secret byte read from the sector header and refuses to start if the disk has not been appropriately formatted. + There is an alternate format function in the controller firmware that allows to set a secret byte which is stored in the sector header. + Copy protected software checks the secret byte read from the sector header and refuses to start if the disk has not been appropriately formatted. */ @@ -41,7 +41,7 @@ Notes: TODO - - sector length error in read check after format + - sector length error in read check after format */ @@ -57,9 +57,9 @@ Notes: //************************************************************************** #define SASIBUS_TAG "sasi" -#define DMA_O1 BIT(m_dma, 0) -#define DMA_O2 BIT(m_dma, 1) -#define DMA_O3 BIT(m_dma, 2) +#define DMA_O1 BIT(m_dma, 0) +#define DMA_O2 BIT(m_dma, 1) +#define DMA_O3 BIT(m_dma, 2) //************************************************************************** @@ -228,16 +228,16 @@ void luxor_4105_device::write_dma_register(uint8_t data) { /* - bit description + bit description - 0 - 1 - 2 - 3 - 4 - 5 byte interrupt enable? - 6 DMA/CPU mode (1=DMA, 0=CPU)? - 7 error interrupt enable? + 0 + 1 + 2 + 3 + 4 + 5 byte interrupt enable? + 6 DMA/CPU mode (1=DMA, 0=CPU)? + 7 error interrupt enable? */ @@ -255,7 +255,7 @@ void luxor_4105_device::write_sasi_data(uint8_t data) { m_data_out = data; - if (!m_sasi->io_r()) + if (!m_sasi->io_r()) { m_sasi->write(data); } @@ -355,9 +355,9 @@ uint8_t luxor_4105_device::abcbus_stat() 2 BSY 3 I/O 4 0 - 5 DMA !O3 + 5 DMA !O3 6 PREN - 7 DMA request + 7 DMA request */ @@ -365,7 +365,7 @@ uint8_t luxor_4105_device::abcbus_stat() data |= !m_sasi->cd_r() << 1; data |= m_sasi->bsy_r() << 2; data |= !m_sasi->io_r() << 3; - + data |= !DMA_O3 << 5; data |= !m_pren << 6; data |= !m_drq << 7; @@ -470,7 +470,7 @@ uint8_t luxor_4105_device::abcbus_tren() m_req = m_sasi->req_r(); update_ack(); update_dma(); - + return data; } @@ -89,10 +89,10 @@ void gigatron_cpu_device::reset_cpu() m_inReg = 0xff; m_outx = 0; m_out = 0; - + m_out_cb(0, 0); m_outx_cb(0, 0); - + for(uint16_t i = 0; i < m_ramMask; i++) gigatron_writemem8(i, floor(machine().rand() & 0xff)); } @@ -39,7 +39,7 @@ public: DECLARE_WRITE_LINE_MEMBER( centronics_input_data6 ) { if (state) m_centronics_data |= 0x40; else m_centronics_data &= ~0x40; } DECLARE_WRITE_LINE_MEMBER( centronics_input_data7 ) { if (state) m_centronics_data |= 0x80; else m_centronics_data &= ~0x80; } - int ready_led() { return !m_centronics_busy; } + int ready_led() { return !m_centronics_busy; } protected: // device-level overrides @@ -201,7 +201,7 @@ void pit_counter_device::device_reset() inline void pit_counter_device::adjust_timer(attotime target) { -// if (target != m_next_update) +// if (target != m_next_update) { m_next_update = target; m_updatetimer->adjust(target - machine().time()); @@ -84,7 +84,7 @@ private: // internal state int m_index; // index number of the timer double m_clockin; // input clock frequency in Hz - attotime m_clock_period; // precomputed input clock period + attotime m_clock_period; // precomputed input clock period int m_clock_signal; // clock signal when clockin is 0 attotime m_last_updated; // time when last updated @@ -241,7 +241,7 @@ int8_t sp0250_device::next() // DAC 62 -> 33,32,33,32 // DAC 63 -> 33,33,33,32 m_pwm_counts = (((dac + 68 + 3) >> 2) << 0) + - (((dac + 68 + 1) >> 2) << 8) + + (((dac + 68 + 1) >> 2) << 8) + (((dac + 68 + 2) >> 2) << 16) + (((dac + 68 + 0) >> 2) << 24); @@ -141,21 +141,21 @@ inline u16 epic12_device::COPY_NEXT_WORD(address_space &space, offs_t *addr) } /* - Upload command - This command uploads gfx data to VRAM, from Main CPU RAM. - - Offset Bits Description - fedcba98 76543210 - 00 0010---- -------- 0x2 for upload - ----0000 00000000 Fixed for upload? - 02 00000000 00000000 "" - 04 10011001 10011001 "" - 06 10011001 10011001 "" - 08 ---xxxxx xxxxxxxx Destination X start position - 0a ----xxxx xxxxxxxx Destination Y start position - 0c ---xxxxx xxxxxxxx Source Width - 0e ----xxxx xxxxxxxx Source Height - 10...10 + (Width * Height * 2) Source GFX data (ARGB1555 format) + Upload command + This command uploads gfx data to VRAM, from Main CPU RAM. + + Offset Bits Description + fedcba98 76543210 + 00 0010---- -------- 0x2 for upload + ----0000 00000000 Fixed for upload? + 02 00000000 00000000 "" + 04 10011001 10011001 "" + 06 10011001 10011001 "" + 08 ---xxxxx xxxxxxxx Destination X start position + 0a ----xxxx xxxxxxxx Destination Y start position + 0c ---xxxxx xxxxxxxx Source Width + 0e ----xxxx xxxxxxxx Source Height + 10...10 + (Width * Height * 2) Source GFX data (ARGB1555 format) */ inline void epic12_device::gfx_upload_shadow_copy(address_space &space, offs_t *addr) @@ -319,38 +319,38 @@ const epic12_device::blitfunction epic12_device::f1_ti0_tr0_blit_funcs[64] = /* - Draw command - This command draws gfx data. - - Offset Bits Description - fedcba98 76543210 - 00 0001---- -------- 0x1 for draw - ----x--- -------- Flip X - -----x-- -------- Flip Y - ------x- -------- Enable Blending - -------x -------- Enable Transparent - -------- -xxx---- Source Blending mode - -------- -----xxx Destination Blending mode - 02 xxxxxxxx -------- Source Alpha value - -------- xxxxxxxx Destination Alpha value - 04 ---xxxxx xxxxxxxx Source X start position - 06 ----xxxx xxxxxxxx Source Y start position - 08 sxxxxxxx xxxxxxxx Destination X start position - 0a sxxxxxxx xxxxxxxx Destination Y start position - 0c ---xxxxx xxxxxxxx Source Width - 0e ----xxxx xxxxxxxx Source Height - 10 -------- xxxxxxxx Source Red multiplication (0x80 = 100%) - 12 xxxxxxxx -------- Source Green multiplication (0x80 = 100%) - -------- xxxxxxxx Source Blue multiplication (0x80 = 100%) - - Blending mode (description from ibara test mode) - 000 +alpha - 001 +source - 010 +destination - 100 -alpha - 101 -source - 110 -destination - others are reserved/disable? + Draw command + This command draws gfx data. + + Offset Bits Description + fedcba98 76543210 + 00 0001---- -------- 0x1 for draw + ----x--- -------- Flip X + -----x-- -------- Flip Y + ------x- -------- Enable Blending + -------x -------- Enable Transparent + -------- -xxx---- Source Blending mode + -------- -----xxx Destination Blending mode + 02 xxxxxxxx -------- Source Alpha value + -------- xxxxxxxx Destination Alpha value + 04 ---xxxxx xxxxxxxx Source X start position + 06 ----xxxx xxxxxxxx Source Y start position + 08 sxxxxxxx xxxxxxxx Destination X start position + 0a sxxxxxxx xxxxxxxx Destination Y start position + 0c ---xxxxx xxxxxxxx Source Width + 0e ----xxxx xxxxxxxx Source Height + 10 -------- xxxxxxxx Source Red multiplication (0x80 = 100%) + 12 xxxxxxxx -------- Source Green multiplication (0x80 = 100%) + -------- xxxxxxxx Source Blue multiplication (0x80 = 100%) + + Blending mode (description from ibara test mode) + 000 +alpha + 001 +source + 010 +destination + 100 -alpha + 101 -source + 110 -destination + others are reserved/disable? */ inline void epic12_device::gfx_draw_shadow_copy(address_space &space, offs_t *addr) @@ -570,8 +570,7 @@ void input_class::remap_device_index(int oldindex, int newindex) if (nullptr != m_device[newindex].get()) m_device[newindex]->set_devindex(newindex); - // update the maximum index found, since newindex may - // exceed current m_maxindex + // update the maximum index found, since newindex may exceed current m_maxindex m_maxindex = std::max(m_maxindex, newindex); } @@ -83,9 +83,9 @@ protected: // internal state static constexpr int BUCKETS_PER_SECOND = 10; - std::vector<s32> m_max_sample; - s32 m_current_max; - u32 m_samples_this_bucket; + std::vector<s32> m_max_sample; + s32 m_current_max; + u32 m_samples_this_bucket; }; @@ -70,7 +70,7 @@ static NETLIST_START(CD4006_DIP) A.D3, /* D3 |5 10| D3+4 */ A.D3P4, A.D4, /* D4 |6 9| D4+5 */ A.D4P5, A.VSS, /* VSS |7 8| D4+4 */ A.D4P4 - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -95,15 +95,15 @@ NETLIST_END() //- +---+---++---+ //- static NETLIST_START(CD4011_DIP) - CD4011_GATE(A) - CD4011_GATE(B) - CD4011_GATE(C) - CD4011_GATE(D) + CD4011_GATE(A) + CD4011_GATE(B) + CD4011_GATE(C) + CD4011_GATE(D) - NET_C(A.VDD, B.VDD, C.VDD, D.VDD) - NET_C(A.VSS, B.VSS, C.VSS, D.VSS) + NET_C(A.VDD, B.VDD, C.VDD, D.VDD) + NET_C(A.VSS, B.VSS, C.VSS, D.VSS) - DIPPINS( /* +--------------+ */ + DIPPINS( /* +--------------+ */ A.A, /* A |1 ++ 14| VDD */ A.VDD, A.B, /* B |2 13| H */ D.B, A.Q, /* J |3 12| G */ D.A, @@ -147,14 +147,14 @@ static NETLIST_START(CD4013_DIP) NET_C(A.VSS, B.VSS) DIPPINS( /* +--------------+ */ - A.Q, /* Q1 |1 ++ 14| VDD */ A.VDD, + A.Q, /* Q1 |1 ++ 14| VDD */ A.VDD, A.QQ, /* Q1Q |2 13| Q2 */ B.Q, A.CLOCK, /* CLOCK1 |3 12| Q2Q */ B.QQ, A.RESET, /* RESET1 |4 4013 11| CLOCK2 */ B.CLOCK, A.DATA, /* DATA1 |5 10| RESET2 */ B.RESET, A.SET, /* SET1 |6 9| DATA2 */ B.DATA, A.VSS, /* VSS |7 8| SET2 */ B.SET - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -547,7 +547,7 @@ static NETLIST_START(CD4538_DIP) A.Q, /* 3S |6 11| 3Y */ B.B, A.QQ, /* EQ |7 10| 3Z */ B.Q, A.VSS, /* GND |8 9| VEE */ B.QQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -312,7 +312,7 @@ static NETLIST_START(TTL_82S16_DIP) A.DOUTQ, /* DOUTQ |6 11| A7 */ A.A7, A.A4, /* A4 |7 10| A6 */ A.A6, A.GND, /* GND |8 9| A5 */ A.A5 - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -909,7 +909,7 @@ static NETLIST_START(TTL_7473_DIP) B.CLK, /* CLK2 |5 10| K2 */ B.K, B.CLRQ, /* CLR2 |6 9| Q2 */ B.Q, B.J, /* J2 |7 8| QQ2 */ B.QQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -952,7 +952,7 @@ static NETLIST_START(TTL_7473A_DIP) B.CLK, /* CLK2 |5 10| K2 */ B.K, B.CLRQ, /* CLR2 |6 9| Q2 */ B.Q, B.J, /* J2 |7 8| QQ2 */ B.QQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -995,7 +995,7 @@ static NETLIST_START(TTL_7474_DIP) A.Q, /* Q1 |5 10| PR2 */ B.PREQ, A.QQ, /* QQ1 |6 9| Q2 */ B.Q, A.GND, /* GND |7 8| QQ2 */ B.QQ - /* +-------------+ */ + /* +-------------+ */ ) NETLIST_END() @@ -1179,7 +1179,7 @@ static NETLIST_START(TTL_7485_DIP) A.EQOUT, /* EQOUT |6 11| B1 */ A.B1, A.LTOUT, /* LTOUT |7 10| A0 */ A.A0, A.GND, /* GND |8 9| B0 */ A.B0 - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -1416,7 +1416,7 @@ NETLIST_END() A.VCC, /* VCC |5 10| GND */ A.GND, NC.I, /* NC |6 9| QB */ A.QB, NC.I, /* NC |7 8| QC */ A.QC - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -1437,15 +1437,15 @@ static NETLIST_START(TTL_7497_DIP) TTL_7497(A) DIPPINS( /* +--------------+ */ - A.B1, /* S1 |1 ++ 16| VCC */ A.VCC, - A.B4, /* S4 |2 15| S3 */ A.B3, - A.B5, /* S5 |3 14| S2 */ A.B2, - A.B0, /* S0 |4 7497 13| MR */ A.CLR, - A.ZQ, /* ZQ |5 12| EY */ A.UNITYQ, - A.Y, /* Y |6 11| CEQ */ A.ENQ, + A.B1, /* S1 |1 ++ 16| VCC */ A.VCC, + A.B4, /* S4 |2 15| S3 */ A.B3, + A.B5, /* S5 |3 14| S2 */ A.B2, + A.B0, /* S0 |4 7497 13| MR */ A.CLR, + A.ZQ, /* ZQ |5 12| EY */ A.UNITYQ, + A.Y, /* Y |6 11| CEQ */ A.ENQ, A.ENOUTQ, /* TCQ |7 10| EZQ */ A.STRBQ, A.GND, /* GND |8 9| CP */ A.CLK - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -1572,7 +1572,7 @@ static NETLIST_START(TTL_74113_DIP) A.Q, /* Q1 |5 10| PRQ2 */ B.SETQ, A.QQ, /* QQ1 |6 9| Q2 */ B.Q, A.GND, /* GND |7 8| QQ2 */ B.QQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -1615,7 +1615,7 @@ static NETLIST_START(TTL_74113A_DIP) A.Q, /* Q1 |5 10| PRQ2 */ B.SETQ, A.QQ, /* QQ1 |6 9| Q2 */ B.Q, A.GND, /* GND |7 8| QQ2 */ B.QQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -1663,7 +1663,7 @@ static NETLIST_START(TTL_74121_DIP) A.B, /* B |5 10| CEXT */ A.C, A.Q, /* Q |6 9| RINT */ RINT.1, A.GND, /* GND |7 8| NC */ NC.I - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -1702,15 +1702,15 @@ static NETLIST_START(TTL_74123_DIP) NET_C(A.GND, B.GND) DIPPINS( /* +--------------+ */ - A.A, /* A1 |1 ++ 16| VCC */ A.VCC, - A.B, /* B1 |2 15| RC1 */ A.RC, + A.A, /* A1 |1 ++ 16| VCC */ A.VCC, + A.B, /* B1 |2 15| RC1 */ A.RC, A.CLRQ, /* CLRQ1 |3 14| C1 */ A.C, - A.QQ, /* QQ1 |4 74123 13| Q1 */ A.Q, - B.Q, /* Q2 |5 12| QQ2 */ B.QQ, - B.C, /* C2 |6 11| CLRQ */ B.CLRQ, - B.RC, /* RC2 |7 10| B2 */ B.B, + A.QQ, /* QQ1 |4 74123 13| Q1 */ A.Q, + B.Q, /* Q2 |5 12| QQ2 */ B.QQ, + B.C, /* C2 |6 11| CLRQ */ B.CLRQ, + B.RC, /* RC2 |7 10| B2 */ B.B, A.GND, /* GND |8 9| A2 */ B.A - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -2124,7 +2124,7 @@ static NETLIST_START(TTL_74161_DIP) A.D, /* D |6 11| QD */ A.QD, A.ENP, /* Enable P |7 10| Enable T */ A.ENT, A.GND, /* GND |8 9| /LOAD */ A.LOADQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -2166,7 +2166,7 @@ static NETLIST_START(TTL_74163_DIP) A.D, /* D |6 11| QD */ A.QD, A.ENP, /* Enable P |7 10| Enable T */ A.ENT, A.GND, /* GND |8 9| /LOAD */ A.LOADQ - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -2205,7 +2205,7 @@ static NETLIST_START(TTL_74164_DIP) A.QC, /* QC |5 10| QE */ A.QE, A.QD, /* QD |6 9| CLRQ */ A.CLRQ, A.GND, /* GND |7 8| CLK */ A.CLK - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -2237,13 +2237,13 @@ static NETLIST_START(TTL_74165_DIP) DIPPINS( /* +--------------+ */ A.SH_LDQ, /* PLQ |1 ++ 16| VCC */ A.VCC, A.CLK, /* CP1 |2 15| CP2 */ A.CLKINH, - A.E, /* P4 |3 14| P3 */ A.D, - A.F, /* P5 |4 74165 13| P2 */ A.C, - A.G, /* P6 |5 12| P1 */ A.B, - A.H, /* P7 |6 11| P0 */ A.A, + A.E, /* P4 |3 14| P3 */ A.D, + A.F, /* P5 |4 74165 13| P2 */ A.C, + A.G, /* P6 |5 12| P1 */ A.B, + A.H, /* P7 |6 11| P0 */ A.A, A.QHQ, /* QQ7 |7 10| DS */ A.SER, A.GND, /* GND |8 9| Q7 */ A.QH - /* +--------------+ */ + /* +--------------+ */ ) NETLIST_END() @@ -2282,14 +2282,14 @@ static NETLIST_START(TTL_74166_DIP) DIPPINS( /* +--------------+ */ A.SER, /* SER |1 ++ 16| VCC */ A.VCC, - A.A, /* A |2 15| SH/LDQ */ A.SH_LDQ, - A.B, /* B |3 14| H */ A.H, - A.C, /* C |4 74166 13| QH */ A.QH, - A.D, /* D |5 12| G */ A.G, + A.A, /* A |2 15| SH/LDQ */ A.SH_LDQ, + A.B, /* B |3 14| H */ A.H, + A.C, /* C |4 74166 13| QH */ A.QH, + A.D, /* D |5 12| G */ A.G, A.CLKINH, /* CLKINH |6 11| F */ A.F, A.CLK, /* CLK |7 10| E */ A.E, A.GND, /* GND |8 9| CLRQ */ A.CLRQ - /* +--------------+ */ + /* +--------------+ */ ) |
iv> A.GND, /* GND |8 9| CLK */ A.CLK
- /* +--------------+ */
+ /* +--------------+ */
)
NETLIST_END()
@@ -2341,15 +2341,15 @@ static NETLIST_START(TTL_74175_DIP)
TTL_74175(A)
DIPPINS( /* +--------------+ */
- A.CLRQ, /* CLRQ |1 ++ 16| VCC */ A.VCC,
- A.Q1, /* Q1 |2 15| Q4 */ A.Q4,
- A.Q1Q, /* Q1Q |3 14| Q4Q */ A.Q4Q,
- A.D1, /* D1 |4 74175 13| D4 */ A.D4,
- A.D2, /* D2 |5 12| D3 */ A.D3,
- A.Q2Q, /* Q2Q |6 11| Q3Q */ A.Q3Q,
- A.Q2, /* Q2 |7 10| Q3 */ A.Q3,
- A.GND, /* GND |8 9| CLK */ A.CLK
- /* +--------------+ */
+ A.CLRQ, /* CLRQ |1 ++ 16| VCC */ A.VCC,
+ A.Q1, /* Q1 |2 15| Q4 */ A.Q4,
+ A.Q1Q, /* Q1Q |3 14| Q4Q */ A.Q4Q,
+ A.D1, /* D1 |4 74175 13| D4 */ A.D4,
+ A.D2, /* D2 |5 12| D3 */ A.D3,
+ A.Q2Q, /* Q2Q |6 11| Q3Q */ A.Q3Q,
+ A.Q2, /* Q2 |7 10| Q3 */ A.Q3,
+ A.GND, /* GND |8 9| CLK */ A.CLK
+ /* +--------------+ */
)
NETLIST_END()
@@ -2358,15 +2358,15 @@ static NETLIST_START(TTL_74192_DIP)
TTL_74192(A)
DIPPINS( /* +--------------+ */
- A.B, /* B |1 ++ 16| VCC */ A.VCC,
- A.QB, /* QB |2 15| A */ A.A,
- A.QA, /* QA |3 14| CLEAR */ A.CLEAR,
- A.CD, /* CD |4 74192 13| BORROWQ*/ A.BORROWQ,
- A.CU, /* CU |5 12| CARRYQ */ A.CARRYQ,
- A.QC, /* QC |6 11| LOADQ */ A.LOADQ,
- A.QD, /* QD |7 10| C */ A.C,
- A.GND, /* GND |8 9| D */ A.D
- /* +--------------+ */
+ A.B, /* B |1 ++ 16| VCC */ A.VCC,
+ A.QB, /* QB |2 15| A */ A.A,
+ A.QA, /* QA |3 14| CLEAR */ A.CLEAR,
+ A.CD, /* CD |4 74192 13| BORROWQ*/ A.BORROWQ,
+ A.CU, /* CU |5 12| CARRYQ */ A.CARRYQ,
+ A.QC, /* QC |6 11| LOADQ */ A.LOADQ,
+ A.QD, /* QD |7 10| C */ A.C,
+ A.GND, /* GND |8 9| D */ A.D
+ /* +--------------+ */
)
NETLIST_END()
@@ -2375,15 +2375,15 @@ static NETLIST_START(TTL_74193_DIP)
TTL_74193(A)
DIPPINS( /* +--------------+ */
- A.B, /* B |1 ++ 16| VCC */ A.VCC,
- A.QB, /* QB |2 15| A */ A.A,
- A.QA, /* QA |3 14| CLEAR */ A.CLEAR,
- A.CD, /* CD |4 74192 13| BORROWQ*/ A.BORROWQ,
- A.CU, /* CU |5 12| CARRYQ */ A.CARRYQ,
- A.QC, /* QC |6 11| LOADQ */ A.LOADQ,
- A.QD, /* QD |7 10| C */ A.C,
- A.GND, /* GND |8 9| D */ A.D
- /* +--------------+ */
+ A.B, /* B |1 ++ 16| VCC */ A.VCC,
+ A.QB, /* QB |2 15| A */ A.A,
+ A.QA, /* QA |3 14| CLEAR */ A.CLEAR,
+ A.CD, /* CD |4 74192 13| BORROWQ*/ A.BORROWQ,
+ A.CU, /* CU |5 12| CARRYQ */ A.CARRYQ,
+ A.QC, /* QC |6 11| LOADQ */ A.LOADQ,
+ A.QD, /* QD |7 10| C */ A.C,
+ A.GND, /* GND |8 9| D */ A.D
+ /* +--------------+ */
)
NETLIST_END()
@@ -2392,15 +2392,15 @@ static NETLIST_START(TTL_74194_DIP)
TTL_74194(A)
DIPPINS( /* +--------------+ */
- A.CLRQ, /* CLRQ |1 ++ 16| VCC */ A.VCC,
- A.SRIN, /* SRIN |2 15| QA */ A.QA,
- A.A, /* A |3 14| QB */ A.QB,
- A.B, /* B |4 74194 13| QC */ A.QC,
- A.C, /* C |5 12| QD */ A.QD,
- A.D, /* D |6 11| CLK */ A.CLK,
- A.SLIN, /* SLIN |7 10| S1 */ A.S1,
- A.GND, /* GND |8 9| S0 */ A.S0
- /* +--------------+ */
+ A.CLRQ, /* CLRQ |1 ++ 16| VCC */ A.VCC,
+ A.SRIN, /* SRIN |2 15| QA */ A.QA,
+ A.A, /* A |3 14| QB */ A.QB,
+ A.B, /* B |4 74194 13| QC */ A.QC,
+ A.C, /* C |5 12| QD */ A.QD,
+ A.D, /* D |6 11| CLK */ A.CLK,
+ A.SLIN, /* SLIN |7 10| S1 */ A.S1,
+ A.GND, /* GND |8 9| S0 */ A.S0
+ /* +--------------+ */
)
NETLIST_END()
@@ -2506,15 +2506,15 @@ static NETLIST_START(TTL_74365_DIP)
TTL_74365(A)
DIPPINS( /* +--------------+ */
- A.G1Q, /* G1Q |1 ++ 16| VCC */ A.VCC,
- A.A1, /* A1 |2 15| G2Q */ A.G2Q,
- A.Y1, /* Y1 |3 14| A6 */ A.A6,
- A.A2, /* A2 |4 74365 13| Y6 */ A.Y6,
- A.Y2, /* Y2 |5 12| A5 */ A.A5,
- A.A3, /* A3 |6 11| Y5 */ A.Y5,
- A.Y3, /* Y3 |7 10| A4 */ A.A4,
- A.GND, /* GND |8 9| Y4 */ A.Y4
- /* +--------------+ */
+ A.G1Q, /* G1Q |1 ++ 16| VCC */ A.VCC,
+ A.A1, /* A1 |2 15| G2Q */ A.G2Q,
+ A.Y1, /* Y1 |3 14| A6 */ A.A6,
+ A.A2, /* A2 |4 74365 13| Y6 */ A.Y6,
+ A.Y2, /* Y2 |5 12| A5 */ A.A5,
+ A.A3, /* A3 |6 11| Y5 */ A.Y5,
+ A.Y3, /* Y3 |7 10| A4 */ A.A4,
+ A.GND, /* GND |8 9| Y4 */ A.Y4
+ /* +--------------+ */
)
NETLIST_END()
@@ -2801,7 +2801,7 @@ static NETLIST_START(TTL_9310_DIP)
A.D, /* D |6 11| QD */ A.QD,
A.ENP, /* Enable P |7 10| Enable T */ A.ENT,
A.GND, /* GND |8 9| /LOAD */ A.LOADQ
- /* +--------------+ */
+ /* +--------------+ */
)
NETLIST_END()
@@ -2912,7 +2912,7 @@ static NETLIST_START(TTL_9316_DIP)
A.D, /* D |6 11| QD */ A.QD,
A.ENP, /* Enable P |7 10| Enable T */ A.ENT,
A.GND, /* GND |8 9| LOADQ */ A.LOADQ
- /* +--------------+ */
+ /* +--------------+ */
)
NETLIST_END()
@@ -2935,14 +2935,14 @@ static NETLIST_START(TTL_9322_DIP)
DIPPINS( /* +--------------+ */
A.SELECT, /* SELECT |1 ++ 16| VCC */ A.VCC,
- A.A1, /* A1 |2 15| STROBE */ A.STROBE,
- A.B1, /* B1 |3 14| A4 */ A.A4,
- A.Y1, /* Y1 |4 9322 13| B4 */ A.B4,
- A.A2, /* A2 |5 12| Y4 */ A.Y4,
- A.B2, /* B2 |6 11| A3 */ A.A3,
- A.Y2, /* Y2 |7 10| B3 */ A.B3,
- A.GND, /* GND |8 9| Y3 */ A.Y3
- /* +--------------+ */
+ A.A1, /* A1 |2 15| STROBE */ A.STROBE,
+ A.B1, /* B1 |3 14| A4 */ A.A4,
+ A.Y1, /* Y1 |4 9322 13| B4 */ A.B4,
+ A.A2, /* A2 |5 12| Y4 */ A.Y4,
+ A.B2, /* B2 |6 11| A3 */ A.A3,
+ A.Y2, /* Y2 |7 10| B3 */ A.B3,
+ A.GND, /* GND |8 9| Y3 */ A.Y3
+ /* +--------------+ */
)
NETLIST_END()
@@ -2960,15 +2960,15 @@ static NETLIST_START(TTL_9321_DIP)
NET_C(A.GND, B.GND)
DIPPINS( /* +--------------+ */
- A.E, /* /E |1 ++ 16| VCC */ A.VCC,
- A.A0, /* A0 |2 15| /E */ B.E,
- A.A1, /* A1 |3 14| A0 */ B.A0,
- A.D0, /* /D0 |4 9321 13| A1 */ B.A1,
- A.D1, /* /D1 |5 12| /D0 */ B.D0,
- A.D2, /* /D2 |6 11| /D1 */ B.D1,
- A.D3, /* /D3 |7 10| /D2 */ B.D2,
+ A.E, /* /E |1 ++ 16| VCC */ A.VCC,
+ A.A0, /* A0 |2 15| /E */ B.E,
+ A.A1, /* A1 |3 14| A0 */ B.A0,
+ A.D0, /* /D0 |4 9321 13| A1 */ B.A1,
+ A.D1, /* /D1 |5 12| /D0 */ B.D0,
+ A.D2, /* /D2 |6 11| /D1 */ B.D1,
+ A.D3, /* /D3 |7 10| /D2 */ B.D2,
A.GND, /* GND |8 9| /D3 */ B.D3
- /* +--------------+ */
+ /* +--------------+ */
)
NETLIST_END()
@@ -3017,7 +3017,7 @@ static NETLIST_START(TTL_9602_DIP)
A.Q, /* Q1 |6 11| A2 */ B.A,
A.QQ, /* QQ1 |7 10| Q2 */ B.Q,
A.GND, /* GND |8 9| QQ2 */ B.QQ
- /* +--------------+ */
+ /* +--------------+ */
)
NETLIST_END()
@@ -519,7 +519,7 @@ namespace plib {
error("#elif without #if");
//if ((m_if_flag & (1 << m_if_level)) == 0)
- // m_if_flag ^= (1 << m_if_level);
+ // m_if_flag ^= (1 << m_if_level);
if (m_elif & (1 << m_if_level)) // elif disabled
m_if_flag |= (1 << m_if_level);
else
@@ -3737,24 +3737,24 @@ void zzzap_common_audio_device::device_add_mconfig(machine_config &config)
.add_route(ALL_OUTPUTS, "mono", 1.0);
NETLIST_LOGIC_INPUT(config, "sound_nl:pedal_bit0",
- "I_PEDAL_BIT0", 0);
+ "I_PEDAL_BIT0", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:pedal_bit1",
- "I_PEDAL_BIT1", 0);
+ "I_PEDAL_BIT1", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:pedal_bit2",
- "I_PEDAL_BIT2", 0);
+ "I_PEDAL_BIT2", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:pedal_bit3",
- "I_PEDAL_BIT3", 0);
+ "I_PEDAL_BIT3", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:hi_shift",
- "I_HI_SHIFT", 0);
+ "I_HI_SHIFT", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:lo_shift",
- "I_LO_SHIFT", 0);
+ "I_LO_SHIFT", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:boom", "I_BOOM", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:engine_sound_off",
- "I_ENGINE_SOUND_OFF", 0);
+ "I_ENGINE_SOUND_OFF", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:noise_cr_1",
- "I_NOISE_CR_1", 0);
+ "I_NOISE_CR_1", 0);
NETLIST_LOGIC_INPUT(config, "sound_nl:noise_cr_2",
- "I_NOISE_CR_2", 0);
+ "I_NOISE_CR_2", 0);
// The audio output is taken from an LM3900 op-amp whose
// output has a peak-to-peak range of about 5 volts, centered
@@ -3786,13 +3786,13 @@ void zzzap_common_audio_device::device_start()
zzzap_audio_device::zzzap_audio_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock) :
- zzzap_common_audio_device(mconfig, ZZZAP_AUDIO, tag, owner, clock, NETLIST_NAME(280zzzap))
+ zzzap_common_audio_device(mconfig, ZZZAP_AUDIO, tag, owner, clock, NETLIST_NAME(280zzzap))
{
}
lagunar_audio_device::lagunar_audio_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock) :
- zzzap_common_audio_device(mconfig, LAGUNAR_AUDIO, tag, owner, clock, NETLIST_NAME(lagunar))
+ zzzap_common_audio_device(mconfig, LAGUNAR_AUDIO, tag, owner, clock, NETLIST_NAME(lagunar))
{
}
@@ -74,9 +74,9 @@ NETLIST_START(astrob)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 4e-5)
#if (SIMPLIFY_SONAR)
- PARAM(Solver.Solver_54.DYNAMIC_MIN_TIMESTEP, 7e-6) // gets rid of NR loops failure
+ PARAM(Solver.Solver_54.DYNAMIC_MIN_TIMESTEP, 7e-6) // gets rid of NR loops failure
#else
- PARAM(Solver.Solver_40.DYNAMIC_MIN_TIMESTEP, 7e-6) // gets rid of NR loops failure
+ PARAM(Solver.Solver_40.DYNAMIC_MIN_TIMESTEP, 7e-6) // gets rid of NR loops failure
#endif
#else
SOLVER(Solver, 48000)
@@ -171,7 +171,7 @@ NETLIST_START(astrob)
RES(R16, RES_K(10))
RES(R17, RES_K(10))
RES(R18, RES_M(2.7))
-// RES(R19, RES_K(1))
+// RES(R19, RES_K(1))
RES(R20, RES_M(1))
RES(R21, RES_K(100))
RES(R22, RES_K(470))
@@ -188,11 +188,11 @@ NETLIST_START(astrob)
RES(R33, RES_K(39))
RES(R34, RES_K(4.7))
RES(R35, RES_K(4.7))
- RES(R36, RES_K(100.1)) // part of SONAR circuit that relies on subtle part differences
- RES(R37, RES_K(1.51)) // part of SONAR circuit that relies on subtle part differences
- RES(R38, RES_K(330.1)) // part of SONAR circuit that relies on subtle part differences
- RES(R39, RES_K(10.1)) // part of SONAR circuit that relies on subtle part differences
- RES(R40, RES_K(68.1)) // part of SONAR circuit that relies on subtle part differences
+ RES(R36, RES_K(100.1)) // part of SONAR circuit that relies on subtle part differences
+ RES(R37, RES_K(1.51)) // part of SONAR circuit that relies on subtle part differences
+ RES(R38, RES_K(330.1)) // part of SONAR circuit that relies on subtle part differences
+ RES(R39, RES_K(10.1)) // part of SONAR circuit that relies on subtle part differences
+ RES(R40, RES_K(68.1)) // part of SONAR circuit that relies on subtle part differences
RES(R41, RES_K(10))
RES(R42, RES_K(100))
RES(R43, RES_K(470))
@@ -214,11 +214,11 @@ NETLIST_START(astrob)
RES(R59, RES_K(100))
RES(R60, RES_K(10))
RES(R61, RES_K(100))
- RES(R62, RES_K(99.9)) // part of SONAR circuit that relies on subtle part differences
- RES(R63, RES_K(1.49)) // part of SONAR circuit that relies on subtle part differences
- RES(R64, RES_K(329.9)) // part of SONAR circuit that relies on subtle part differences
- RES(R65, RES_K(9.9)) // part of SONAR circuit that relies on subtle part differences
- RES(R66, RES_K(67.9)) // part of SONAR circuit that relies on subtle part differences
+ RES(R62, RES_K(99.9)) // part of SONAR circuit that relies on subtle part differences
+ RES(R63, RES_K(1.49)) // part of SONAR circuit that relies on subtle part differences
+ RES(R64, RES_K(329.9)) // part of SONAR circuit that relies on subtle part differences
+ RES(R65, RES_K(9.9)) // part of SONAR circuit that relies on subtle part differences
+ RES(R66, RES_K(67.9)) // part of SONAR circuit that relies on subtle part differences
RES(R67, RES_K(10))
RES(R68, RES_K(82))
RES(R69, RES_K(470))
@@ -243,11 +243,11 @@ NETLIST_START(astrob)
RES(R88, RES_K(100))
RES(R89, RES_K(10))
RES(R90, RES_K(100))
- RES(R91, RES_K(100.2)) // part of SONAR circuit that relies on subtle part differences
- RES(R92, RES_K(1.52)) // part of SONAR circuit that relies on subtle part differences
- RES(R93, RES_K(330.2)) // part of SONAR circuit that relies on subtle part differences
- RES(R94, RES_K(10.2)) // part of SONAR circuit that relies on subtle part differences
- RES(R95, RES_K(68.2)) // part of SONAR circuit that relies on subtle part differences
+ RES(R91, RES_K(100.2)) // part of SONAR circuit that relies on subtle part differences
+ RES(R92, RES_K(1.52)) // part of SONAR circuit that relies on subtle part differences
+ RES(R93, RES_K(330.2)) // part of SONAR circuit that relies on subtle part differences
+ RES(R94, RES_K(10.2)) // part of SONAR circuit that relies on subtle part differences
+ RES(R95, RES_K(68.2)) // part of SONAR circuit that relies on subtle part differences
RES(R96, RES_K(10))
RES(R97, RES_K(4.7))
RES(R98, RES_M(1))
@@ -267,16 +267,16 @@ NETLIST_START(astrob)
RES(R112, RES_K(10))
RES(R113, RES_K(10))
RES(R114, 100)
-// RES(R115, RES_K(100)) -- part of final amp (not emulated)
-// RES(R116, RES_K(470)) -- part of final amp (not emulated)
+// RES(R115, RES_K(100)) -- part of final amp (not emulated)
+// RES(R116, RES_K(470)) -- part of final amp (not emulated)
RES(R117, RES_K(1))
RES(R118, RES_K(470))
RES(R119, RES_K(470))
RES(R120, RES_K(220))
RES(R121, RES_K(10))
RES(R122, RES_K(4.7))
-// RES(R123, RES_K(1)) -- part of final amp (not emulated)
-// RES(R124, RES_K(100)) -- part of final amp (not emulated)
+// RES(R123, RES_K(1)) -- part of final amp (not emulated)
+// RES(R124, RES_K(100)) -- part of final amp (not emulated)
RES(R125, RES_K(82))
RES(R126, RES_K(39))
RES(R127, RES_K(10))
@@ -287,16 +287,16 @@ NETLIST_START(astrob)
RES(R132, RES_K(82))
RES(R133, RES_K(100))
RES(R134, RES_M(2.7))
-// RES(R135, RES_K(22)) -- part of final amp (not emulated)
+// RES(R135, RES_K(22)) -- part of final amp (not emulated)
RES(R136, RES_K(1))
RES(R137, RES_K(4.7))
RES(R138, RES_M(2.2))
RES(R139, RES_K(4.7))
RES(R140, RES_K(4.7))
-// RES(R141, RES_K(22))
-// RES(R142, RES_M(1)) -- part of final amp (not emulated)
-// RES(R143, RES_K(22)) -- part of final amp (not emulated)
-// RES(R144, RES_K(22)) -- part of final amp (not emulated)
+// RES(R141, RES_K(22))
+// RES(R142, RES_M(1)) -- part of final amp (not emulated)
+// RES(R143, RES_K(22)) -- part of final amp (not emulated)
+// RES(R144, RES_K(22)) -- part of final amp (not emulated)
RES(R145, RES_K(4.7))
RES(R146, RES_K(100))
RES(R147, RES_M(2.2))
@@ -349,11 +349,11 @@ NETLIST_START(astrob)
CAP(C7, CAP_U(0.1))
CAP(C8, CAP_U(0.1))
CAP(C9, CAP_U(0.1))
-// CAP(C10, CAP_U(0.05))
-// CAP(C11, CAP_U(0.05))
+// CAP(C10, CAP_U(0.05))
+// CAP(C11, CAP_U(0.05))
CAP(C12, CAP_U(10))
-// CAP(C13, CAP_U(0.05))
-// CAP(C14, CAP_U(0.05))
+// CAP(C13, CAP_U(0.05))
+// CAP(C14, CAP_U(0.05))
CAP(C15, CAP_U(10))
CAP(C16, CAP_U(0.01))
CAP(C17, CAP_U(0.01))
@@ -368,8 +368,8 @@ NETLIST_START(astrob)
CAP(C26, CAP_U(0.022))
CAP(C27, CAP_U(10))
CAP(C28, CAP_U(0.05))
-// CAP(C29, CAP_U(0.05))
-// CAP(C30, CAP_U(0.05))
+// CAP(C29, CAP_U(0.05))
+// CAP(C30, CAP_U(0.05))
CAP(C31, CAP_U(0.0047))
CAP(C32, CAP_U(0.05))
CAP(C33, CAP_U(10))
@@ -381,23 +381,23 @@ NETLIST_START(astrob)
CAP(C39, CAP_U(0.1))
CAP(C40, CAP_U(0.01))
CAP(C41, CAP_U(0.01))
-// CAP(C42, CAP_U(0.001))
-// CAP(C43, CAP_U(10))
-// CAP(C44, CAP_U(0.001))
-// CAP(C45, CAP_U(0.001))
-// CAP(C46, CAP_U(10))
+// CAP(C42, CAP_U(0.001))
+// CAP(C43, CAP_U(10))
+// CAP(C44, CAP_U(0.001))
+// CAP(C45, CAP_U(0.001))
+// CAP(C46, CAP_U(10))
CAP(C47, CAP_U(4.7))
-// CAP(C48, CAP_U(22)) -- part of final amp (not emulated)
+// CAP(C48, CAP_U(22)) -- part of final amp (not emulated)
CAP(C49, CAP_U(0.05))
CAP(C50, CAP_U(0.05))
CAP(C51, CAP_U(0.05))
CAP(C52, CAP_U(0.05))
CAP(C53, CAP_U(0.1))
-// CAP(C54, CAP_U(0.05))
+// CAP(C54, CAP_U(0.05))
CAP(C55, CAP_U(0.05))
CAP(C56, CAP_U(10))
CAP(C57, CAP_U(0.1))
-// CAP(C58, CAP_U(4.7)) -- part of final amp (not emulated)
+// CAP(C58, CAP_U(4.7)) -- part of final amp (not emulated)
CAP(C59, CAP_U(0.33))
CAP(C60, CAP_U(4.7))
CAP(C61, CAP_U(4.7))
@@ -405,20 +405,20 @@ NETLIST_START(astrob)
CAP(C63, CAP_U(0.1))
CAP(C64, CAP_U(0.1))
CAP(C65, CAP_U(0.01))
-// CAP(C66, CAP_U(0.05))
+// CAP(C66, CAP_U(0.05))
CAP(C67, CAP_U(0.05))
CAP(C68, CAP_U(0.0047))
CAP(C69, CAP_U(4.7))
CAP(C70, CAP_U(0.1))
CAP(C71, CAP_U(0.022))
CAP(C72, CAP_U(0.05))
-// CAP(C73, CAP_U(0.05))
+// CAP(C73, CAP_U(0.05))
CAP(C74, CAP_U(0.05))
CAP(C75, CAP_U(0.05))
CAP(C76, CAP_U(0.022))
CAP(C77, CAP_U(0.0047))
CAP(C78, CAP_U(0.1))
-// CAP(C79, CAP_U(0.05))
+// CAP(C79, CAP_U(0.05))
CAP(C80, CAP_U(4.7))
CAP(C81, CAP_U(0.05))
CAP(C82, CAP_U(0.1))
@@ -435,7 +435,7 @@ NETLIST_START(astrob)
D_1N5231(D10)
D_1N914(D11)
D_1N914(D12)
-// D_1N914(D13) -- part of final amp (not emulated)
+// D_1N914(D13) -- part of final amp (not emulated)
D_1N914(D14)
D_1N914(D15)
D_1N914(D16)
@@ -466,138 +466,138 @@ NETLIST_START(astrob)
Q_2N4403(Q9)
Q_2N4403(Q10)
- TL084_DIP(U1) // Op. Amp.
+ TL084_DIP(U1) // Op. Amp.
NET_C(U1.4, I_V12)
NET_C(U1.11, I_VM12)
- TL084_DIP(U2) // Op. Amp.
+ TL084_DIP(U2) // Op. Amp.
NET_C(U2.4, I_V12)
NET_C(U2.11, I_VM12)
- CD4017_DIP(U3) // Decade Counter/Divider
+ CD4017_DIP(U3) // Decade Counter/Divider
NET_C(U3.8, GND)
NET_C(U3.16, I_V12)
- NE555_DIP(U4) // Timer
+ NE555_DIP(U4) // Timer
- NE555_DIP(U5) // Timer
+ NE555_DIP(U5) // Timer
- NE555_DIP(U6) // Timer
+ NE555_DIP(U6) // Timer
- TL084_DIP(U7) // Op. Amp.
+ TL084_DIP(U7) // Op. Amp.
NET_C(U7.4, I_V12)
NET_C(U7.11, I_VM12)
- MM5837_DIP(U8) // Noise Generator
+ MM5837_DIP(U8) // Noise Generator
#if (UNDERCLOCK_NOISE_GEN)
// officially runs at 48-112kHz, but little noticeable difference
// in exchange for a big performance boost
PARAM(U8.FREQ, 12000)
#endif
- CD4011_DIP(U9) // Quad 2-Input NAND Gates
+ CD4011_DIP(U9) // Quad 2-Input NAND Gates
NET_C(U9.7, GND)
NET_C(U9.14, I_V12)
- CD4011_DIP(U10) // Quad 2-Input NAND Gates
+ CD4011_DIP(U10) // Quad 2-Input NAND Gates
NET_C(U10.7, GND)
NET_C(U10.14, I_V12)
- CD4011_DIP(U11) // Quad 2-Input NAND Gates
+ CD4011_DIP(U11) // Quad 2-Input NAND Gates
NET_C(U11.7, GND)
NET_C(U11.14, I_V12)
- CD4024_DIP(U12) // 7-Stage Ripple Binary Counter
+ CD4024_DIP(U12) // 7-Stage Ripple Binary Counter
NET_C(U12.7, GND)
NET_C(U12.14, I_V12)
- NE555_DIP(U13) // Timer
+ NE555_DIP(U13) // Timer
- CD4024_DIP(U14) // 7-Stage Ripple Binary Counter
+ CD4024_DIP(U14) // 7-Stage Ripple Binary Counter
NET_C(U14.7, GND)
NET_C(U14.14, I_V12)
- CD4017_DIP(U15) // Decade Counter/Divider
+ CD4017_DIP(U15) // Decade Counter/Divider
NET_C(U15.8, GND)
NET_C(U15.16, I_V12)
- TL084_DIP(U16) // Op. Amp.
+ TL084_DIP(U16) // Op. Amp.
NET_C(U16.4, I_V12)
NET_C(U16.11, I_VM12)
- NE555_DIP(U17) // Timer
+ NE555_DIP(U17) // Timer
- NE555_DIP(U18) // Timer
+ NE555_DIP(U18) // Timer
- CD4024_DIP(U19) // 7-Stage Ripple Binary Counter
+ CD4024_DIP(U19) // 7-Stage Ripple Binary Counter
NET_C(U19.7, GND)
NET_C(U19.14, I_V12)
- NE555_DIP(U20) // Timer
+ NE555_DIP(U20) // Timer
- CD4011_DIP(U21) // Quad 2-Input NAND Gates
+ CD4011_DIP(U21) // Quad 2-Input NAND Gates
NET_C(U21.7, GND)
NET_C(U21.14, I_V12)
- TL084_DIP(U22) // Op. Amp.
+ TL084_DIP(U22) // Op. Amp.
NET_C(U22.4, I_V12)
NET_C(U22.11, I_VM12)
- NE555_DIP(U23) // Timer
+ NE555_DIP(U23) // Timer
- NE555_DIP(U24) // Timer
+ NE555_DIP(U24) // Timer
- CD4011_DIP(U25) // Quad 2-Input NAND Gates
+ CD4011_DIP(U25) // Quad 2-Input NAND Gates
NET_C(U25.7, GND)
NET_C(U25.14, I_V12)
- TTL_7407_DIP(U26) // Hex Buffers with High Votage Open-Collector Outputs
- NET_C(U26.7, GND)
- NET_C(U26.14, I_V5)
+ TTL_7407_DIP(U26) // Hex Buffers with High Votage Open-Collector Outputs
+ NET_C(U26.7, GND)
+ NET_C(U26.14, I_V5)
- CD4011_DIP(U27) // Quad 2-Input NAND Gates
+ CD4011_DIP(U27) // Quad 2-Input NAND Gates
NET_C(U27.7, GND)
NET_C(U27.14, I_V12)
- CD4024_DIP(U28) // 7-Stage Ripple Binary Counter
+ CD4024_DIP(U28) // 7-Stage Ripple Binary Counter
NET_C(U28.7, GND)
NET_C(U28.14, I_V12)
- TTL_7407_DIP(U29) // Hex Buffers with High Votage Open-Collector Outputs
- NET_C(U29.7, GND)
- NET_C(U29.14, I_V5)
+ TTL_7407_DIP(U29) // Hex Buffers with High Votage Open-Collector Outputs
+ NET_C(U29.7, GND)
+ NET_C(U29.14, I_V5)
- TTL_7406_DIP(U30) // Hex inverter -- currently using a clone of 7416, no open collector behavior
+ TTL_7406_DIP(U30) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(U30.7, GND)
NET_C(U30.14, I_V5)
- TTL_7406_DIP(U31) // Hex inverter -- currently using a clone of 7416, no open collector behavior
+ TTL_7406_DIP(U31) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(U31.7, GND)
NET_C(U31.14, I_V5)
-// TTL_74LS374_DIP(U32) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
-// NET_C(U32.10, GND)
-// NET_C(U32.20, I_V5)
+// TTL_74LS374_DIP(U32) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
+// NET_C(U32.10, GND)
+// NET_C(U32.20, I_V5)
-// TTL_74LS374_DIP(U33) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
-// NET_C(U33.10, GND)
-// NET_C(U33.20, I_V5)
+// TTL_74LS374_DIP(U33) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
+// NET_C(U33.10, GND)
+// NET_C(U33.20, I_V5)
-// TTL_74LS00_DIP(U34) // Quad 4-Input NAND Gate
+// TTL_74LS00_DIP(U34) // Quad 4-Input NAND Gate
// NET_C(U34.7, GND)
// NET_C(U34.14, I_V5)
-// TTL_74LS30_DIP(U35) // 8-Input NAND Gate
-// NET_C(U35.7, GND)
-// NET_C(U35.14, I_V5)
+// TTL_74LS30_DIP(U35) // 8-Input NAND Gate
+// NET_C(U35.7, GND)
+// NET_C(U35.14, I_V5)
-// TTL_74LS04_DIP(U36) // Hex Inverting Gates
-// NET_C(U36.7, GND)
-// NET_C(U36.14, I_V5)
+// TTL_74LS04_DIP(U36) // Hex Inverting Gates
+// NET_C(U36.7, GND)
+// NET_C(U36.14, I_V5)
- NE555_DIP(U37) // Timer
+ NE555_DIP(U37) // Timer
- NE555_DIP(U38) // Timer
+ NE555_DIP(U38) // Timer
//
// Sheet 7, top-left (SONAR)
@@ -722,8 +722,8 @@ NETLIST_START(astrob)
VARCLOCK(LASER1CLK, 1, "max(0.000001,min(0.1,(0.0000000343262*A0*A0*A0*A0*A0) - (0.00000096054*A0*A0*A0*A0) + (0.0000105481*A0*A0*A0) - (0.0000561978*A0*A0) + (0.000148191*A0) - 0.000131018))")
NET_C(LASER1CLK.GND, GND)
NET_C(LASER1CLK.VCC, I_V12)
- NET_C(LASER1CLK.A0, Q10.E)
- NET_C(LASER1CLK.Q, LASER1ENV.A1)
+ NET_C(LASER1CLK.A0, Q10.E)
+ NET_C(LASER1CLK.Q, LASER1ENV.A1)
AFUNC(LASER1ENV, 2, "if(A0>6,A1,0)")
NET_C(LASER1ENV.A0, U25.10)
NET_C(LASER1ENV.Q, U19.1)
@@ -774,8 +774,8 @@ NETLIST_START(astrob)
VARCLOCK(LASER2CLK, 1, "max(0.000001,min(0.1,(0.0000000153499*A0*A0*A0*A0*A0) - (0.000000433800*A0*A0*A0*A0) + (0.00000480504*A0*A0*A0) - (0.0000257871*A0*A0) + (0.000068467*A0) - 0.0000608574))")
NET_C(LASER2CLK.GND, GND)
NET_C(LASER2CLK.VCC, I_V12)
- NET_C(LASER2CLK.A0, Q9.E)
- NET_C(LASER2CLK.Q, LASER2ENV.A1)
+ NET_C(LASER2CLK.A0, Q9.E)
+ NET_C(LASER2CLK.Q, LASER2ENV.A1)
AFUNC(LASER2ENV, 2, "if(A0>6,A1,0)")
NET_C(LASER2ENV.A0, U25.11)
NET_C(LASER2ENV.Q, U14.1)
@@ -916,7 +916,7 @@ NETLIST_START(astrob)
NET_C(C80.2, GND)
NET_C(R180.2, U16.9, R179.1)
NET_C(R179.2, U16.8, R177.1)
- NET_C(R181.2, U16.10, Q6.D, D26.K) // D and S swapped on schematics???
+ NET_C(R181.2, U16.10, Q6.D, D26.K) // D and S swapped on schematics???
NET_C(Q6.G, C72.2, R151.2, Q5.G)
NET_C(R151.1, GND)
NET_C(C72.1, U8.3)
@@ -960,7 +960,7 @@ NETLIST_START(astrob)
NET_C(I_ASTROIDS, R97.1, R174.1, R175.1)
NET_C(R97.2, I_V12)
NET_C(R174.2, U16.13, R173.1)
- NET_C(R175.2, U16.12, Q5.D, D25.K) // D and S swapped on schematics???
+ NET_C(R175.2, U16.12, Q5.D, D25.K) // D and S swapped on schematics???
NET_C(D25.A, Q5.S, GND)
NET_C(R173.2, U16.14, R172.1)
NET_C(R172.2, R150.1, C70.1)
@@ -992,7 +992,7 @@ NETLIST_START(astrob)
NET_C(MUTEFUNC.A0, I_MUTE)
NET_C(MUTEFUNC.A1, R121.2)
ALIAS(OUTPUT, MUTEFUNC.Q)
-// ALIAS(OUTPUT, C55.2)
+// ALIAS(OUTPUT, C55.2)
//
// Sheet 8, middle-top (INVADER_1)
@@ -1154,7 +1154,7 @@ NETLIST_START(astrob)
OPTIMIZE_FRONTIER(INVADER_4, RES_M(1), RXX)
OPTIMIZE_FRONTIER(C50.1, RES_M(10), RXX)
- OPTIMIZE_FRONTIER(C60.1, RES_M(10), RXX) // this is a big one
+ OPTIMIZE_FRONTIER(C60.1, RES_M(10), RXX) // this is a big one
OPTIMIZE_FRONTIER(C61.1, RES_M(10), RXX)
#endif
@@ -81,10 +81,10 @@ NETLIST_START(carpolo)
ANALOG_INPUT(V5, 5)
ALIAS(VCC, V5)
- TTL_INPUT(PL1_CRASH, 1) // active high
- TTL_INPUT(PL2_CRASH, 0) // active high
- TTL_INPUT(PL3_CRASH, 0) // active high
- TTL_INPUT(PL4_CRASH, 0) // active high
+ TTL_INPUT(PL1_CRASH, 1) // active high
+ TTL_INPUT(PL2_CRASH, 0) // active high
+ TTL_INPUT(PL3_CRASH, 0) // active high
+ TTL_INPUT(PL4_CRASH, 0) // active high
LOCAL_SOURCE(PLAYER_CRASH)
@@ -96,14 +96,14 @@ NETLIST_END()
// once for Zektor
//
-#define VARIANT_ELIMINATOR 0
-#define VARIANT_ZEKTOR 1
+#define VARIANT_ELIMINATOR 0
+#define VARIANT_ZEKTOR 1
-#define SOUND_VARIANT (VARIANT_ELIMINATOR)
+#define SOUND_VARIANT (VARIANT_ELIMINATOR)
#include "nl_elim.cpp"
#undef SOUND_VARIANT
-#define SOUND_VARIANT (VARIANT_ZEKTOR)
+#define SOUND_VARIANT (VARIANT_ZEKTOR)
#include "nl_elim.cpp"
@@ -131,7 +131,7 @@ NETLIST_START(zektor)
LOCAL_SOURCE(_CA3080_FAST_DIP)
-// TTL_INPUT(I_LO_D0, 0)
+// TTL_INPUT(I_LO_D0, 0)
TTL_INPUT(I_LO_D1, 0)
ALIAS(I_FIREBALL, I_LO_D1)
TTL_INPUT(I_LO_D2, 0)
@@ -193,14 +193,14 @@ NETLIST_START(zektor)
// C46 0.022uF 0.047uF
//
-// RES(R1, RES_K(100)) -- part of final amp (not emulated)
-// RES(R2, RES_M(1)) -- part of final amp (not emulated)
-// RES(R3, RES_K(22)) -- part of final amp (not emulated)
-// RES(R4, RES_K(2.2)) -- part of final amp (not emulated)
+// RES(R1, RES_K(100)) -- part of final amp (not emulated)
+// RES(R2, RES_M(1)) -- part of final amp (not emulated)
+// RES(R3, RES_K(22)) -- part of final amp (not emulated)
+// RES(R4, RES_K(2.2)) -- part of final amp (not emulated)
#if (SOUND_VARIANT == VARIANT_ELIMINATOR)
-// RES(R5, RES_K(10)) -- part of final amp (not emulated)
+// RES(R5, RES_K(10)) -- part of final amp (not emulated)
#else // (SOUND_VARIANT == VARIANT_ZEKTOR)
-// RES(R5, RES_K(4.7)) -- part of final amp (not emulated)
+// RES(R5, RES_K(4.7)) -- part of final amp (not emulated)
#endif
RES(R6, RES_K(220))
RES(R7, RES_K(220))
@@ -211,9 +211,9 @@ NETLIST_START(zektor)
RES(R9, RES_K(12))
#endif
RES(R10, RES_K(10))
-// RES(R11, RES_K(2.2)) -- part of final amp (not emulated)
-// RES(R12, RES_M(1)) -- part of final amp (not emulated)
-// RES(R13, RES_K(330)) -- part of final amp (not emulated)
+// RES(R11, RES_K(2.2)) -- part of final amp (not emulated)
+// RES(R12, RES_M(1)) -- part of final amp (not emulated)
+// RES(R13, RES_K(330)) -- part of final amp (not emulated)
RES(R14, RES_K(470))
RES(R15, RES_K(100))
RES(R16, RES_K(100))
@@ -363,10 +363,10 @@ NETLIST_START(zektor)
RES(R146, RES_K(22))
RES(R147, RES_K(2.2))
-// CAP(C1, CAP_U(4.7)) -- part of final amp (not emulated)
-// CAP(C2, CAP_U(0.1))
-// CAP(C3, CAP_U(0.1))
-// CAP(C4, CAP_U(10)) -- part of final amp (not emulated)
+// CAP(C1, CAP_U(4.7)) -- part of final amp (not emulated)
+// CAP(C2, CAP_U(0.1))
+// CAP(C3, CAP_U(0.1))
+// CAP(C4, CAP_U(10)) -- part of final amp (not emulated)
CAP(C5, CAP_U(0.1))
CAP(C6, CAP_U(0.1))
CAP(C7, CAP_U(0.001))
@@ -388,17 +388,17 @@ NETLIST_START(zektor)
CAP(C19, CAP_U(0.068))
CAP(C20, CAP_U(0.068))
CAP(C21, CAP_U(2.2))
-// CAP(C22, CAP_U(0.1))
-// CAP(C23, CAP_U(0.1))
-// CAP(C24, CAP_U(0.1))
-// CAP(C25, CAP_U(0.1))
-// CAP(C26, CAP_U(0.1))
-// CAP(C27, CAP_U(0.1))
+// CAP(C22, CAP_U(0.1))
+// CAP(C23, CAP_U(0.1))
+// CAP(C24, CAP_U(0.1))
+// CAP(C25, CAP_U(0.1))
+// CAP(C26, CAP_U(0.1))
+// CAP(C27, CAP_U(0.1))
CAP(C28, CAP_U(0.1))
CAP(C29, CAP_U(0.1))
CAP(C30, CAP_U(0.022))
-// CAP(C31, CAP_U(0.1))
-// CAP(C32, CAP_U(0.1))
+// CAP(C31, CAP_U(0.1))
+// CAP(C32, CAP_U(0.1))
CAP(C33, CAP_U(0.1))
CAP(C34, CAP_U(0.1))
CAP(C35, CAP_U(1))
@@ -406,8 +406,8 @@ NETLIST_START(zektor)
CAP(C37, CAP_U(10))
CAP(C38, CAP_U(4.7))
CAP(C39, CAP_U(0.1))
-// CAP(C40, CAP_U(0.1))
-// CAP(C41, CAP_U(0.1))
+// CAP(C40, CAP_U(0.1))
+// CAP(C41, CAP_U(0.1))
// C42??
CAP(C43, CAP_U(0.033))
CAP(C44, CAP_U(0.1))
@@ -432,7 +432,7 @@ NETLIST_START(zektor)
CAP(C59, CAP_U(0.1))
CAP(C60, CAP_U(0.001))
CAP(C61, CAP_U(0.068))
-// CAP(C62, CAP_U(0.1))
+// CAP(C62, CAP_U(0.1))
CAP(C63, CAP_P(100))
CAP(C64, CAP_U(0.1))
CAP(C65, CAP_U(0.01))
@@ -440,11 +440,11 @@ NETLIST_START(zektor)
CAP(C67, CAP_U(0.047))
CAP(C68, CAP_U(0.01))
CAP(C69, CAP_U(0.1))
-// CAP(C70, CAP_U(0.1))
-// CAP(C71, CAP_U(0.1))
-// CAP(C72, CAP_U(0.1))
-// CAP(C73, CAP_U(10))
-// CAP(C74, CAP_U(0.1))
+// CAP(C70, CAP_U(0.1))
+// CAP(C71, CAP_U(0.1))
+// CAP(C72, CAP_U(0.1))
+// CAP(C73, CAP_U(10))
+// CAP(C74, CAP_U(0.1))
CAP(C75, CAP_U(0.1))
CAP(C76, CAP_U(0.1))
CAP(C77, CAP_U(0.1))
@@ -458,7 +458,7 @@ NETLIST_START(zektor)
D_1N914(D7)
D_1N4002(D8)
-// Q_2N4093(Q1) -- part of final amp (not emulated)
+// Q_2N4093(Q1) -- part of final amp (not emulated)
Q_2N4403(Q2)
Q_2N4403(Q3)
Q_2N4403(Q4)
@@ -470,164 +470,164 @@ NETLIST_START(zektor)
Q_2N4403(Q10)
Q_2N4403(Q11)
- TL081_DIP(U1) // Op. Amp.
+ TL081_DIP(U1) // Op. Amp.
NET_C(U1.7, I_V12)
NET_C(U1.4, I_VM12)
-// TL082_DIP(U2) // Op. Amp. -- part of final amp (not emulated)
-// NET_C(U2.8, I_V12)
-// NET_C(U2.4, I_VM12)
+// TL082_DIP(U2) // Op. Amp. -- part of final amp (not emulated)
+// NET_C(U2.8, I_V12)
+// NET_C(U2.4, I_VM12)
- TL081_DIP(U3) // Op. Amp.
+ TL081_DIP(U3) // Op. Amp.
NET_C(U3.7, I_V12)
NET_C(U3.4, I_VM12)
- MM5837_DIP(U4) // Noise Generator
+ MM5837_DIP(U4) // Noise Generator
#if (UNDERCLOCK_NOISE_GEN)
PARAM(U4.FREQ, 24000)
#endif
- LM555_DIP(U5) // Timer
+ LM555_DIP(U5) // Timer
- CA3080_DIP(U6) // Op. Amp.
+ CA3080_DIP(U6) // Op. Amp.
NET_C(U6.4, I_VM12)
NET_C(U6.7, I_V12)
- CA3080_DIP(U7) // Op. Amp.
+ CA3080_DIP(U7) // Op. Amp.
NET_C(U7.4, I_VM12)
NET_C(U7.7, I_V12)
- CA3080_DIP(U8) // Op. Amp.
+ CA3080_DIP(U8) // Op. Amp.
NET_C(U8.4, I_VM12)
NET_C(U8.7, I_V12)
- CA3080_DIP(U9) // Op. Amp.
+ CA3080_DIP(U9) // Op. Amp.
NET_C(U9.4, I_VM12)
NET_C(U9.7, I_V12)
- CA3080_DIP(U10) // Op. Amp.
+ CA3080_DIP(U10) // Op. Amp.
NET_C(U10.4, I_VM12)
NET_C(U10.7, I_V12)
- CA3080_DIP(U11) // Op. Amp.
+ CA3080_DIP(U11) // Op. Amp.
NET_C(U11.4, I_VM12)
NET_C(U11.7, I_V12)
- TL081_DIP(U12) // Op. Amp.
+ TL081_DIP(U12) // Op. Amp.
NET_C(U12.7, I_V12)
NET_C(U12.4, I_VM12)
- LM555_DIP(U13) // Timer
+ LM555_DIP(U13) // Timer
- CA3080_DIP(U14) // Op. Amp.
+ CA3080_DIP(U14) // Op. Amp.
NET_C(U14.4, I_VM12)
NET_C(U14.7, I_V12)
- CA3080_DIP(U15) // Op. Amp.
+ CA3080_DIP(U15) // Op. Amp.
NET_C(U15.4, I_VM12)
NET_C(U15.7, I_V12)
- TL082_DIP(U16) // Op. Amp.
+ TL082_DIP(U16) // Op. Amp.
NET_C(U16.8, I_V12)
NET_C(U16.4, I_VM12)
- CD4011_DIP(U17) // Quad 2-Input NAND Gates
+ CD4011_DIP(U17) // Quad 2-Input NAND Gates
NET_C(U17.7, GND)
NET_C(U17.14, I_V12)
- CD4011_DIP(U18) // Quad 2-Input NAND Gates
+ CD4011_DIP(U18) // Quad 2-Input NAND Gates
NET_C(U18.7, GND)
NET_C(U18.14, I_V12)
- CD4011_DIP(U19) // Quad 2-Input NAND Gates
+ CD4011_DIP(U19) // Quad 2-Input NAND Gates
NET_C(U19.7, GND)
NET_C(U19.14, I_V12)
- TL082_DIP(U20) // Op. Amp.
+ TL082_DIP(U20) // Op. Amp.
NET_C(U20.8, I_V12)
NET_C(U20.4, I_VM12)
- CD4024_DIP(U21) // 7-Stage Ripple Binary Counter
+ CD4024_DIP(U21) // 7-Stage Ripple Binary Counter
NET_C(U21.7, GND)
NET_C(U21.14, I_V12)
- CD4011_DIP(U22) // Quad 2-Input NAND Gates
+ CD4011_DIP(U22) // Quad 2-Input NAND Gates
NET_C(U22.7, GND)
NET_C(U22.14, I_V12)
- CD4024_DIP(U23) // 7-Stage Ripple Binary Counter
+ CD4024_DIP(U23) // 7-Stage Ripple Binary Counter
NET_C(U23.7, GND)
NET_C(U23.14, I_V12)
- TTL_7406_DIP(U24) // Hex inverter -- currently using a clone of 7416, no open collector behavior
+ TTL_7406_DIP(U24) // Hex inverter -- currently using a clone of 7416, no open collector behavior
NET_C(U24.7, GND)
NET_C(U24.14, I_V5)
#if (!HLE_BACKGROUND_VCO)
- LM566_DIP(U25) // Voltage-Controlled Oscillator
+ LM566_DIP(U25) // Voltage-Controlled Oscillator
#endif
- TTL_74LS00_DIP(U26) // Quad 4-Input NAND Gate
- NET_C(U26.7, GND)
- NET_C(U26.14, I_V5)
+ TTL_74LS00_DIP(U26) // Quad 4-Input NAND Gate
+ NET_C(U26.7, GND)
+ NET_C(U26.14, I_V5)
- TTL_7407_DIP(U27) // Hex Buffers with High Votage Open-Collector Outputs
- NET_C(U27.7, GND)
- NET_C(U27.14, I_V5)
+ TTL_7407_DIP(U27) // Hex Buffers with High Votage Open-Collector Outputs
+ NET_C(U27.7, GND)
+ NET_C(U27.14, I_V5)
- TTL_7407_DIP(U28) // Hex Buffers with High Votage Open-Collector Outputs
- NET_C(U28.7, GND)
- NET_C(U28.14, I_V5)
+ TTL_7407_DIP(U28) // Hex Buffers with High Votage Open-Collector Outputs
+ NET_C(U28.7, GND)
+ NET_C(U28.14, I_V5)
- TL081_DIP(U29) // Op. Amp.
+ TL081_DIP(U29) // Op. Amp.
NET_C(U29.7, I_V12)
NET_C(U29.4, I_VM12)
-// AY_3_8912_DIP(U30) // PSG -- emulated by MAME
+// AY_3_8912_DIP(U30) // PSG -- emulated by MAME
- CD4069_DIP(U31) // Hex Inverter
+ CD4069_DIP(U31) // Hex Inverter
NET_C(U31.7, GND)
NET_C(U31.14, I_V12)
- CD4069_DIP(U32) // Hex Inverter
+ CD4069_DIP(U32) // Hex Inverter
NET_C(U32.7, GND)
NET_C(U32.14, I_V12)
-// TTL_74LS125_DIP(U33) // Quad 3-state buffer
-// NET_C(U33.7, GND)
-// NET_C(U33.14, I_V5)
+// TTL_74LS125_DIP(U33) // Quad 3-state buffer
+// NET_C(U33.7, GND)
+// NET_C(U33.14, I_V5)
-// TTL_74LS374_DIP(U34) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
-// NET_C(U34.10, GND)
-// NET_C(U34.20, I_V5)
+// TTL_74LS374_DIP(U34) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
+// NET_C(U34.10, GND)
+// NET_C(U34.20, I_V5)
//
-// TTL_74LS374_DIP(U35) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
-// NET_C(U34.10, GND)
-// NET_C(U34.20, I_V5)
+// TTL_74LS374_DIP(U35) // Octal D-Type Transparent Latches And Edge-Triggered Flip-Flop
+// NET_C(U34.10, GND)
+// NET_C(U34.20, I_V5)
// TTL_74LS74_DIP(U36) // Dual D Flip Flop
// NET_C(U36.7, GND)
// NET_C(U36.14, I_V5)
-// TTL_74LS10_DIP(U37) // Triple 3-Input NAND Gate
-// NET_C(U37.7, GND)
-// NET_C(U37.14, I_V5)
+// TTL_74LS10_DIP(U37) // Triple 3-Input NAND Gate
+// NET_C(U37.7, GND)
+// NET_C(U37.14, I_V5)
-// TTL_74LS14_DIP(U38)
-// NET_C(U38.7, GND)
-// NET_C(U38.14, I_V5)
+// TTL_74LS14_DIP(U38)
+// NET_C(U38.7, GND)
+// NET_C(U38.14, I_V5)
-// TTL_74LS08_DIP(U39) // Quad 2-Input AND Gates
-// NET_C(U39.7, GND)
-// NET_C(U39.14, I_V5)
+// TTL_74LS08_DIP(U39) // Quad 2-Input AND Gates
+// NET_C(U39.7, GND)
+// NET_C(U39.14, I_V5)
-// TTL_74LS30_DIP(U40) // 8-Input NAND Gate
-// NET_C(U40.7, GND)
-// NET_C(U40.14, I_V5)
+// TTL_74LS30_DIP(U40) // 8-Input NAND Gate
+// NET_C(U40.7, GND)
+// NET_C(U40.14, I_V5)
-// TTL_74LS14_DIP(U41)
-// NET_C(U41.7, GND)
-// NET_C(U41.14, I_V5)
+// TTL_74LS14_DIP(U41)
+// NET_C(U41.7, GND)
+// NET_C(U41.14, I_V5)
//
// Sheet 7, top-left/middle (Thrust)
@@ -817,9 +817,9 @@ NETLIST_START(zektor)
VARCLOCK(BGCLK, 1, "max(0.000001,min(0.1,(0.00000748879*A0*A0*A0*A0) - (0.000189174*A0*A0*A0) + (0.00180942*A0*A0) - (0.00759439*A0) + 0.0124560))")
NET_C(BGCLK.GND, GND)
NET_C(BGCLK.VCC, I_V5)
- NET_C(BGCLK.A0, U16.1)
- NET_C(BGCLK.Q, BGENV.A0)
- NET_C(GND, C57.1, C57.2, C58.1, C58.2)
+ NET_C(BGCLK.A0, U16.1)
+ NET_C(BGCLK.Q, BGENV.A0)
+ NET_C(GND, C57.1, C57.2, C58.1, C58.2)
AFUNC(BGENV, 1, "if(A0>2.5,2.5,-2.5)")
NET_C(BGENV.Q, R106.1)
#else
@@ -867,7 +867,7 @@ NETLIST_START(zektor)
HINT(U32.6, NC)
HINT(U32.8, NC)
- CLOCK(_200HZBCLK, 217.98) // tweak frequency so this is out of phase
+ CLOCK(_200HZBCLK, 217.98) // tweak frequency so this is out of phase
NET_C(_200HZBCLK.VCC, I_V12)
NET_C(_200HZBCLK.GND, GND)
NET_C(_200HZB, _200HZBCLK.Q)
@@ -1100,14 +1100,14 @@ NETLIST_START(zektor)
VARCLOCK(TORP1CLK, 1, "max(0.000001,min(0.1,(0.00000342725*A0*A0*A0) + (0.000000183693*A0*A0) + (0.000079091*A0) + 0.0000157375))")
NET_C(TORP1CLK.GND, GND)
NET_C(TORP1CLK.VCC, I_V5)
- NET_C(TORP1CLK.A0, D2.K)
- NET_C(TORP1CLK.Q, T1ENV.A0)
+ NET_C(TORP1CLK.A0, D2.K)
+ NET_C(TORP1CLK.Q, T1ENV.A0)
AFUNC(T1ENV, 1, "if(A0>2.5,11.1,-11.1)")
NET_C(T1ENV.Q, U23.1)
NET_C(D2.A, D3.K, R91.1)
NET_C(C46.2, R90.1)
NET_C(R90.2, R91.2, R146.1)
- NET_C(GND, U20.3, U20.2)
+ NET_C(GND, U20.3, U20.2)
#else
NET_C(D2.A, D3.K, R91.1, U20.3)
NET_C(U20.2, C46.2, R90.1)
@@ -1129,9 +1129,9 @@ NETLIST_START(zektor)
NET_C(WBN, R36.1)
#if (DISABLE_TORPEDO2_NOISE)
- NET_C(R36.2, GND) // noise source
+ NET_C(R36.2, GND) // noise source
#else
- NET_C(R36.2, D6.A) // noise source
+ NET_C(R36.2, D6.A) // noise source
#endif
#if (HLE_TORPEDO2_VCO)
@@ -1145,14 +1145,14 @@ NETLIST_START(zektor)
VARCLOCK(TORP2CLK, 1, "max(0.000001,min(0.1,(0.0000104419*A0*A0*A0) - (0.00000603211*A0*A0) + (0.000109865*A0) + 0.0000082421))")
NET_C(TORP2CLK.GND, GND)
NET_C(TORP2CLK.VCC, I_V5)
- NET_C(TORP2CLK.A0, D6.K)
- NET_C(TORP2CLK.Q, T2ENV.A0)
+ NET_C(TORP2CLK.A0, D6.K)
+ NET_C(TORP2CLK.Q, T2ENV.A0)
AFUNC(T2ENV, 1, "if(A0>2.5,11.1,-11.1)")
NET_C(T2ENV.Q, U21.1)
NET_C(D6.A, D7.K, R93.1)
NET_C(C43.2, R94.1)
NET_C(R94.2, R93.2, R92.2)
- NET_C(GND, U20.6, U20.5)
+ NET_C(GND, U20.6, U20.5)
#else
NET_C(D6.A, U20.5, D7.K, R93.1)
NET_C(U20.6, C43.2, R94.1)
@@ -41,56 +41,56 @@ NETLIST_END()
//
static NETLIST_START(ICL8038_DIP)
- VCVS(VI, 1)
- CCCS(CI1, -1)
- CCCS(CI2, 2)
- SYS_COMPD(COMP)
- SYS_DSW2(SW)
- VCVS(VO, 1)
- RES(R_SHUNT, RES_R(50))
-
- PARAM(VO.RO, 50)
- PARAM(COMP.MODEL, "FAMILY(TYPE=CUSTOM IVL=0.16 IVH=0.4 OVL=0.01 OVH=0.01 ORL=50 ORH=50)")
- PARAM(SW.GOFF, 0) // This has to be zero to block current sources
-
- NET_C(VI.OP, CI1.IN, CI2.IN)
- NET_C(CI1.OP, VO.IP)
- NET_C(COMP.Q, SW.I)
- NET_C(CI2.OP, SW.2)
- NET_C(COMP.VCC, R_SHUNT.1)
- NET_C(SW.1, R_SHUNT.2)
- NET_C(SW.3, VO.IP)
- NET_C(VO.OP, COMP.IN)
-
- // Avoid singular Matrix due to G=0 switch
- RES(RX1, 1e10)
- RES(RX2, 1e10)
- NET_C(RX1.1, SW.1)
- NET_C(RX2.1, SW.3)
-
- NET_C(COMP.GND, RX1.2, RX2.2)
-
- RES(R1, 5000)
- RES(R2, 5000)
- RES(R3, 5000)
-
- // Square output wave
- VCVS(V_SQR, 1)
- NET_C(COMP.Q, V_SQR.IP)
-
- NET_C(COMP.GND, SW.GND, VI.ON, VI.IN, CI1.ON, CI2.ON, VO.IN, VO.ON, R2.2, V_SQR.IN, V_SQR.ON)
- NET_C(COMP.VCC, SW.VCC, R1.2)
- NET_C(COMP.IP, R1.1, R2.1, R3.1)
- NET_C(COMP.Q, R3.2)
-
- ALIAS(11, VI.ON) // GND
- ALIAS(9, V_SQR.OP) // Square out
- ALIAS(3, VO.OP) // Triag out
- ALIAS(8, VI.IP) // VC
- ALIAS(4, CI1.IP) // R1
- ALIAS(5, CI2.IP) // R2
- ALIAS(10, VO.IP) // C1
- ALIAS(6, COMP.VCC) // V+
+ VCVS(VI, 1)
+ CCCS(CI1, -1)
+ CCCS(CI2, 2)
+ SYS_COMPD(COMP)
+ SYS_DSW2(SW)
+ VCVS(VO, 1)
+ RES(R_SHUNT, RES_R(50))
+
+ PARAM(VO.RO, 50)
+ PARAM(COMP.MODEL, "FAMILY(TYPE=CUSTOM IVL=0.16 IVH=0.4 OVL=0.01 OVH=0.01 ORL=50 ORH=50)")
+ PARAM(SW.GOFF, 0) // This has to be zero to block current sources
+
+ NET_C(VI.OP, CI1.IN, CI2.IN)
+ NET_C(CI1.OP, VO.IP)
+ NET_C(COMP.Q, SW.I)
+ NET_C(CI2.OP, SW.2)
+ NET_C(COMP.VCC, R_SHUNT.1)
+ NET_C(SW.1, R_SHUNT.2)
+ NET_C(SW.3, VO.IP)
+ NET_C(VO.OP, COMP.IN)
+
+ // Avoid singular Matrix due to G=0 switch
+ RES(RX1, 1e10)
+ RES(RX2, 1e10)
+ NET_C(RX1.1, SW.1)
+ NET_C(RX2.1, SW.3)
+
+ NET_C(COMP.GND, RX1.2, RX2.2)
+
+ RES(R1, 5000)
+ RES(R2, 5000)
+ RES(R3, 5000)
+
+ // Square output wave
+ VCVS(V_SQR, 1)
+ NET_C(COMP.Q, V_SQR.IP)
+
+ NET_C(COMP.GND, SW.GND, VI.ON, VI.IN, CI1.ON, CI2.ON, VO.IN, VO.ON, R2.2, V_SQR.IN, V_SQR.ON)
+ NET_C(COMP.VCC, SW.VCC, R1.2)
+ NET_C(COMP.IP, R1.1, R2.1, R3.1)
+ NET_C(COMP.Q, R3.2)
+
+ ALIAS(11, VI.ON) // GND
+ ALIAS(9, V_SQR.OP) // Square out
+ ALIAS(3, VO.OP) // Triag out
+ ALIAS(8, VI.IP) // VC
+ ALIAS(4, CI1.IP) // R1
+ ALIAS(5, CI2.IP) // R2
+ ALIAS(10, VO.IP) // C1
+ ALIAS(6, COMP.VCC) // V+
NETLIST_END()
//
@@ -109,19 +109,19 @@ NETLIST_START(fireone)
NET_MODEL("PIT8253PORT FAMILY(TYPE=NMOS OVL=0.05 OVH=0.05 ORL=100.0 ORH=0.5k)")
- TTL_INPUT(LTORP, 0) // active high
- TTL_INPUT(LSHPHT, 0) // active high
- TTL_INPUT(LBOOM, 0) // active high
- TTL_INPUT(SOUND_OFF_L, 0) // active high
- TTL_INPUT(SOUND_OFF_R, 0) // active high
- TTL_INPUT(RTORP, 0) // active high
- TTL_INPUT(RSHPHT, 0) // active high
- TTL_INPUT(RBOOM, 0) // active high
- TTL_INPUT(TORPCOLL, 0) // active high
- TTL_INPUT(SUBENG, 0) // active high
- TTL_INPUT(ALERT, 0) // active high
- //TTL_INPUT(SONAR_ENABLE, 0) // active high
- TTL_INPUT(SONAR_SYNC, 0) // active low
+ TTL_INPUT(LTORP, 0) // active high
+ TTL_INPUT(LSHPHT, 0) // active high
+ TTL_INPUT(LBOOM, 0) // active high
+ TTL_INPUT(SOUND_OFF_L, 0) // active high
+ TTL_INPUT(SOUND_OFF_R, 0) // active high
+ TTL_INPUT(RTORP, 0) // active high
+ TTL_INPUT(RSHPHT, 0) // active high
+ TTL_INPUT(RBOOM, 0) // active high
+ TTL_INPUT(TORPCOLL, 0) // active high
+ TTL_INPUT(SUBENG, 0) // active high
+ TTL_INPUT(ALERT, 0) // active high
+ //TTL_INPUT(SONAR_ENABLE, 0) // active high
+ TTL_INPUT(SONAR_SYNC, 0) // active low
LOGIC_INPUT(MUSIC_A, 0, "PIT8253PORT")
LOGIC_INPUT(MUSIC_B, 0, "PIT8253PORT")
@@ -45,7 +45,7 @@ NETLIST_START(segaspeech)
// There are two schematic drawings of the speech board
// that show fairly different outputs from the SP0250.
// Both have their problems.
- //
+ //
// The simpler one is included in the Astro Blaster and
// Space Fury manuals. This is largely correct, except
// that it is believed (not verified) that R20 should be
@@ -89,14 +89,14 @@ NETLIST_START(segaspeech)
RES(R17, RES_K(10))
RES(R18, RES_K(22))
RES(R19, RES_K(250))
- RES(R20, RES_K(4.7)) // schematic shows 470Ohm, but a real PCB had 4.7k here
+ RES(R20, RES_K(4.7)) // schematic shows 470Ohm, but a real PCB had 4.7k here
RES(R21, RES_K(10))
CAP(C9, CAP_U(0.1))
CAP(C10, CAP_U(0.047))
CAP(C50, CAP_U(0.003))
- TL081_DIP(U8) // Op. Amp.
+ TL081_DIP(U8) // Op. Amp.
NET_C(U8.7, I_V5)
NET_C(U8.4, I_VM5)
@@ -42,33 +42,33 @@ NETLIST_START(segausb)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5)
- ANALOG_INPUT(I_U12_DAC, 0) // AD7524
- ANALOG_INPUT(I_U13_DAC, 0) // AD7524
- ANALOG_INPUT(I_U14_DAC, 0) // AD7524
- TTL_INPUT(I_U2B_SEL, 0) // 74LS74
+ ANALOG_INPUT(I_U12_DAC, 0) // AD7524
+ ANALOG_INPUT(I_U13_DAC, 0) // AD7524
+ ANALOG_INPUT(I_U14_DAC, 0) // AD7524
+ TTL_INPUT(I_U2B_SEL, 0) // 74LS74
- ANALOG_INPUT(I_U24_DAC, 0) // AD7524
- ANALOG_INPUT(I_U25_DAC, 0) // AD7524
- ANALOG_INPUT(I_U26_DAC, 0) // AD7524
- TTL_INPUT(I_U38B_SEL, 0) // 74LS74
+ ANALOG_INPUT(I_U24_DAC, 0) // AD7524
+ ANALOG_INPUT(I_U25_DAC, 0) // AD7524
+ ANALOG_INPUT(I_U26_DAC, 0) // AD7524