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path: root/src/mess/drivers/vector06.c
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/***************************************************************************

        Vector06c driver by Miodrag Milanovic

        10/07/2008 Preliminary driver.

****************************************************************************/

#include "includes/vector06.h"


/* Address maps */
static ADDRESS_MAP_START(vector06_mem, AS_PROGRAM, 8, vector06_state)
	AM_RANGE( 0x0000, 0x7fff ) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
	AM_RANGE( 0x8000, 0xffff ) AM_READ_BANK("bank3") AM_WRITE_BANK("bank4")
ADDRESS_MAP_END

static ADDRESS_MAP_START(vector06_io, AS_IO, 8, vector06_state)
	ADDRESS_MAP_GLOBAL_MASK(0xff)
	ADDRESS_MAP_UNMAP_HIGH
	AM_RANGE( 0x00, 0x03) AM_READWRITE(vector06_8255_1_r, vector06_8255_1_w )
	AM_RANGE( 0x04, 0x07) AM_READWRITE(vector06_8255_2_r, vector06_8255_2_w )
	AM_RANGE( 0x0C, 0x0C) AM_WRITE(vector06_color_set)
	AM_RANGE( 0x18, 0x18) AM_DEVREADWRITE_LEGACY("wd1793", wd17xx_data_r,wd17xx_data_w)
	AM_RANGE( 0x19, 0x19) AM_DEVREADWRITE_LEGACY("wd1793", wd17xx_sector_r,wd17xx_sector_w)
	AM_RANGE( 0x1A, 0x1A) AM_DEVREADWRITE_LEGACY("wd1793", wd17xx_track_r,wd17xx_track_w)
	AM_RANGE( 0x1B, 0x1B) AM_DEVREADWRITE_LEGACY("wd1793", wd17xx_status_r,wd17xx_command_w)
	AM_RANGE( 0x1C, 0x1C) AM_WRITE(vector06_disc_w)
ADDRESS_MAP_END

/* Input ports */
static INPUT_PORTS_START( vector06 )
	PORT_START("LINE0")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Tab") PORT_CODE(KEYCODE_TAB)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Del") PORT_CODE(KEYCODE_DEL)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Enter") PORT_CODE(KEYCODE_ENTER)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BkSp") PORT_CODE(KEYCODE_BACKSPACE)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Left") PORT_CODE(KEYCODE_LEFT)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Up") PORT_CODE(KEYCODE_UP)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Right") PORT_CODE(KEYCODE_RIGHT)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Down") PORT_CODE(KEYCODE_DOWN)
	PORT_START("LINE1")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Home") PORT_CODE(KEYCODE_HOME)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("PgUp") PORT_CODE(KEYCODE_PGUP)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F1") PORT_CODE(KEYCODE_F1)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F2") PORT_CODE(KEYCODE_F2)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F3") PORT_CODE(KEYCODE_F3)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F4") PORT_CODE(KEYCODE_F4)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F5") PORT_CODE(KEYCODE_F5)
	PORT_START("LINE2")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0") PORT_CODE(KEYCODE_0)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4") PORT_CODE(KEYCODE_4)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("5") PORT_CODE(KEYCODE_5)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("6") PORT_CODE(KEYCODE_6)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("7") PORT_CODE(KEYCODE_7)
	PORT_START("LINE3")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("8") PORT_CODE(KEYCODE_8)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("9") PORT_CODE(KEYCODE_9)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("'") PORT_CODE(KEYCODE_INSERT)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(",") PORT_CODE(KEYCODE_COMMA)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("=") PORT_CODE(KEYCODE_EQUALS)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(".") PORT_CODE(KEYCODE_STOP)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
	PORT_START("LINE4")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("@") PORT_CODE(KEYCODE_QUOTE)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("C") PORT_CODE(KEYCODE_C)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("E") PORT_CODE(KEYCODE_E)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F") PORT_CODE(KEYCODE_F)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("G") PORT_CODE(KEYCODE_G)
	PORT_START("LINE5")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("H") PORT_CODE(KEYCODE_H)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O)
	PORT_START("LINE6")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("P") PORT_CODE(KEYCODE_P)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("R") PORT_CODE(KEYCODE_R)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("V") PORT_CODE(KEYCODE_V)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("W") PORT_CODE(KEYCODE_W)
	PORT_START("LINE7")
		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("X") PORT_CODE(KEYCODE_X)
		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y)
		PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Z") PORT_CODE(KEYCODE_Z)
		PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("[") PORT_CODE(KEYCODE_OPENBRACE)
		PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("\\") PORT_CODE(KEYCODE_BACKSLASH)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("]") PORT_CODE(KEYCODE_CLOSEBRACE)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("~") PORT_CODE(KEYCODE_TILDE)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Space") PORT_CODE(KEYCODE_SPACE)
	PORT_START("LINE8")
		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_UNUSED)
		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_UNUSED)
		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_UNUSED)
		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
		PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT)
		PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL)
		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Rus/Lat") PORT_CODE(KEYCODE_LALT)
	PORT_START("RESET")
		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Reset") PORT_CODE(KEYCODE_F11)
		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Reset 2") PORT_CODE(KEYCODE_F12)

INPUT_PORTS_END

static const cassette_interface vector_cassette_interface =
{
	cassette_default_formats,
	NULL,
	(cassette_state)(CASSETTE_STOPPED | CASSETTE_MOTOR_ENABLED | CASSETTE_SPEAKER_ENABLED),
	NULL,
	NULL
};

static LEGACY_FLOPPY_OPTIONS_START(vector)
	LEGACY_FLOPPY_OPTION(vector, "fdd", "Vector disk image", basicdsk_identify_default, basicdsk_construct_default, NULL,
		HEADS([2])
		TRACKS([82])
		SECTORS([5])
		SECTOR_LENGTH([1024])
		FIRST_SECTOR_ID([1]))
LEGACY_FLOPPY_OPTIONS_END

static const floppy_interface vector_floppy_interface =
{
	DEVCB_NULL,
	DEVCB_NULL,
	DEVCB_NULL,
	DEVCB_NULL,
	DEVCB_NULL,
	FLOPPY_STANDARD_5_25_DSHD,
	LEGACY_FLOPPY_OPTIONS_NAME(vector),
	NULL,
	NULL
};

const wd17xx_interface vector06_wd17xx_interface =
{
	DEVCB_LINE_VCC,
	DEVCB_NULL,
	DEVCB_NULL,
	{ FLOPPY_0, FLOPPY_1, NULL, NULL}
};

/* Machine driver */
static MACHINE_CONFIG_START( vector06, vector06_state )
	/* basic machine hardware */
	MCFG_CPU_ADD("maincpu", I8080, 3000000)
//  MCFG_CPU_ADD("maincpu", Z80, 3000000)
	MCFG_CPU_PROGRAM_MAP(vector06_mem)
	MCFG_CPU_IO_MAP(vector06_io)
	MCFG_CPU_VBLANK_INT_DRIVER("screen", vector06_state,  vector06_interrupt)


	/* video hardware */
	MCFG_SCREEN_ADD("screen", RASTER)
	MCFG_SCREEN_REFRESH_RATE(50)
	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
	MCFG_SCREEN_SIZE(256+64, 256+64)
	MCFG_SCREEN_VISIBLE_AREA(0, 256+64-1, 0, 256+64-1)
	MCFG_SCREEN_UPDATE_DRIVER(vector06_state, screen_update_vector06)
	MCFG_PALETTE_LENGTH(16)

	MCFG_SPEAKER_STANDARD_MONO("mono")
	MCFG_SOUND_WAVE_ADD(WAVE_TAG, CASSETTE_TAG)
	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)

	/* Devices */
	MCFG_I8255_ADD("ppi8255", vector06_ppi8255_interface)
	MCFG_I8255_ADD("ppi8255_2", vector06_ppi8255_2_interface)
	MCFG_CASSETTE_ADD(CASSETTE_TAG, vector_cassette_interface)
	MCFG_FD1793_ADD("wd1793", vector06_wd17xx_interface)
	MCFG_LEGACY_FLOPPY_2_DRIVES_ADD(vector_floppy_interface)

	/* cartridge */
	MCFG_CARTSLOT_ADD("cart")
	MCFG_CARTSLOT_EXTENSION_LIST("emr")
	MCFG_CARTSLOT_NOT_MANDATORY

	/* internal ram */
	MCFG_RAM_ADD(RAM_TAG)
	MCFG_RAM_DEFAULT_SIZE("64K")
	MCFG_RAM_DEFAULT_VALUE(0)
MACHINE_CONFIG_END

/* ROM definition */

ROM_START( vector06 )
	ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASEFF )
	ROM_SYSTEM_BIOS(0, "unboot32k", "Universal Boot 32K")
	ROMX_LOAD( "unboot32k.rt", 0x10000, 0x8000, CRC(28c9b5cd) SHA1(8cd7fb658896a7066ae93b10eaafa0f12139ad81), ROM_BIOS(1))
	ROM_SYSTEM_BIOS(1, "unboot2k", "Universal Boot 2K")
	ROMX_LOAD( "unboot2k.rt",  0x10000, 0x0800, CRC(4c80dc31) SHA1(7e5e3acfdbea2e52b0d64c5868821deaec383815), ROM_BIOS(2))
	ROM_SYSTEM_BIOS(2, "coman", "Boot Coman")
	ROMX_LOAD( "coman.rt",     0x10000, 0x0800, CRC(f8c4a85a) SHA1(47fa8b02f09a1d06aa63a2b90b2597b1d93d976f), ROM_BIOS(3))
	ROM_SYSTEM_BIOS(3, "bootbyte", "Boot Byte")
	ROMX_LOAD( "bootbyte.rt",  0x10000, 0x0800, CRC(3b42fd9d) SHA1(a112f4fe519bc3dbee85b09040d4804a17c9eda2), ROM_BIOS(4))
	ROM_SYSTEM_BIOS(4, "bootos", "Boot OS")
	ROMX_LOAD( "bootos.rt",    0x10000, 0x0200, CRC(46bef038) SHA1(6732f4a360cd38112c53c458842d31f5b035cf59), ROM_BIOS(5))
	ROM_SYSTEM_BIOS(5, "boot512", "Boot 512")
	ROMX_LOAD( "boot512.rt",   0x10000, 0x0200, CRC(a0b1c6b2) SHA1(f6fe15cb0974aed30f9b7aa72133324a66d1ed3f), ROM_BIOS(6))
	ROM_CART_LOAD("cart", 0x18000, 0x8000, ROM_OPTIONAL)
ROM_END

ROM_START( vec1200 )
	ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASEFF )
	ROM_LOAD( "vec1200.bin", 0x10000, 0x2000, CRC(37349224) SHA1(060fbb2c1a89040c929521cfd58cb6f1431a8b75))
	ROM_CART_LOAD("cart", 0x18000, 0x8000, ROM_OPTIONAL)

	ROM_REGION( 0x0200, "palette", 0 )
	ROM_LOAD( "palette.bin", 0x0000, 0x0200, CRC(74b7376b) SHA1(fb56b60babd7e6ed68e5f4e791ad2800d7ef6729))
ROM_END

ROM_START( pk6128c )
	ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASEFF )
	ROM_LOAD( "6128.bin", 0x10000, 0x4000, CRC(d4f68433) SHA1(ef5ac75f9240ca8996689c23642d4e47e5e774d8))
	ROM_CART_LOAD("cart", 0x18000, 0x8000, ROM_OPTIONAL)
ROM_END

ROM_START( krista2 )
	ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASEFF )
	ROM_LOAD( "krista2.epr", 0x10000, 0x0200, CRC(df5440b0) SHA1(bcbbb3cc10aeb17c1262b45111d20279266b9ba4))
	ROM_CART_LOAD("cart", 0x18000, 0x8000, ROM_OPTIONAL)
	ROM_LOAD( "krista2.pal", 0x0000, 0x0200, CRC(b243da33) SHA1(9af7873e6f8bf452c8d831833ffb02dce833c095))
ROM_END
/* Driver */

/*    YEAR  NAME         PARENT    COMPAT  MACHINE     INPUT       INIT     COMPANY    FULLNAME      FLAGS */
COMP( 1987, vector06,    0,        0,      vector06,   vector06, driver_device,   0,    "<unknown>", "Vector 06c",  GAME_NOT_WORKING)
COMP( 1987, vec1200,     vector06, 0,      vector06,   vector06, driver_device,   0,    "<unknown>", "Vector 1200", GAME_NOT_WORKING)
COMP( 1987, pk6128c,     vector06, 0,      vector06,   vector06, driver_device,   0,    "<unknown>", "PK-6128c",    GAME_NOT_WORKING)
COMP( 1987, krista2,     vector06, 0,      vector06,   vector06, driver_device,   0,    "<unknown>", "Krista-2",    GAME_NOT_WORKING)
dma_targets[slot]; sprintf(buf, "<%02x>", slot); return buf; } void next_state::dma_drq_w(int slot, bool state) { // fprintf(stderr, "DMA drq_w %d, %d\n", slot, state); dma_slot &ds = dma_slots[slot]; ds.drq = state; if(state && (ds.state & DMA_ENABLE)) { address_space &space = maincpu->space(AS_PROGRAM); if(ds.state & DMA_READ) { while(ds.drq) { dma_check_update(slot); UINT8 val; bool eof; bool err; dma_read(slot, val, eof, err); if(err) { ds.state = (ds.state & ~DMA_ENABLE) | DMA_BUSEXC; logerror("DMA: bus error on read slot %d\n", slot); return; } space.write_byte(ds.current++, val); dma_check_end(slot, eof); if(!(ds.state & DMA_ENABLE)) return; } } else { while(ds.drq) { dma_check_update(slot); UINT8 val = space.read_byte(ds.current++); bool eof = ds.current == (ds.limit & 0x7fffffff) && (ds.limit & 0x80000000); bool err; dma_write(slot, val, eof, err); if(err) { ds.state = (ds.state & ~DMA_ENABLE) | DMA_BUSEXC; logerror("DMA: bus error on write slot %d\n", slot); return; } dma_check_end(slot, false); if(!(ds.state & DMA_ENABLE)) return; } } } } void next_state::dma_read(int slot, UINT8 &val, bool &eof, bool &err) { err = false; eof = false; switch(slot) { case 1: if(fdc && fdc->get_drq()) val = fdc->dma_r(); else val = scsi->dma_r(); break; case 5: val = mo->dma_r(); break; case 21: net->rx_dma_r(val, eof); break; default: err = true; val = 0; break; } } void next_state::dma_write(int slot, UINT8 data, bool eof, bool &err) { err = false; switch(slot) { case 1: scsi->dma_w(data); break; case 4: break; case 5: mo->dma_w(data); break; case 17: net->tx_dma_w(data, eof); break; default: err = true; break; } } void next_state::dma_check_update(int slot) { dma_slot &ds = dma_slots[slot]; if(ds.restart) { ds.current = ds.start; ds.restart = false; } } void next_state::dma_end(int slot) { dma_slot &ds = dma_slots[slot]; if(dma_has_saved[slot]) { dma_slot &ds1 = dma_slots[(slot-1) & 31]; ds1.current = ds.start; ds1.limit = ds.current; } if(!ds.supdate) ds.state &= ~DMA_ENABLE; else { ds.start = ds.chain_start; ds.limit = ds.chain_limit; ds.restart = true; ds.supdate = false; ds.state &= ~DMA_SUPDATE; } ds.state |= DMA_COMPLETE; if(dma_irqs[slot] >= 0) irq_set(dma_irqs[slot], true); } void next_state::dma_check_end(int slot, bool eof) { dma_slot &ds = dma_slots[slot]; if(eof || ds.current == (ds.limit & 0x7fffffff)) dma_end(slot); } READ32_MEMBER( next_state::dma_regs_r) { int slot = offset >> 2; int reg = offset & 3; UINT32 res; switch(reg) { case 0: res = dma_slots[slot].current; break; case 1: res = dma_slots[slot].limit; break; case 2: res = dma_slots[slot].chain_start; break; case 3: default: res = dma_slots[slot].chain_limit; break; } const char *name = dma_name(slot); logerror("dma_regs_r %s:%d %08x (%08x)\n", name, reg, res, space.device().safe_pc()); return res; } WRITE32_MEMBER( next_state::dma_regs_w) { int slot = offset >> 2; int reg = offset & 3; const char *name = dma_name(slot); logerror("dma_regs_w %s:%d %08x (%08x)\n", name, reg, data, space.device().safe_pc()); switch(reg) { case 0: dma_slots[slot].start = data; dma_slots[slot].current = data; break; case 1: dma_slots[slot].limit = data; break; case 2: dma_slots[slot].chain_start = data; break; case 3: dma_slots[slot].chain_limit = data; break; } } READ32_MEMBER( next_state::dma_ctrl_r) { int slot = offset >> 2; int reg = offset & 3; const char *name = dma_name(slot); if(space.device().safe_pc() != 0x409bb4e) logerror("dma_ctrl_r %s:%d %02x (%08x)\n", name, reg, dma_slots[slot].state, space.device().safe_pc()); return reg ? 0 : dma_slots[slot].state << 24; } WRITE32_MEMBER( next_state::dma_ctrl_w) { int slot = offset >> 2; int reg = offset & 3; const char *name = dma_name(slot); logerror("dma_ctrl_w %s:%d %08x @ %08x (%08x)\n", name, reg, data, mem_mask, space.device().safe_pc()); if(!reg) { if(ACCESSING_BITS_16_23) dma_do_ctrl_w(slot, data >> 16); else if(ACCESSING_BITS_24_31) dma_do_ctrl_w(slot, data >> 24); } } void next_state::dma_do_ctrl_w(int slot, UINT8 data) { const char *name = dma_name(slot); #if 0 fprintf(stderr, "dma_ctrl_w %s %02x (%08x)\n", name, data, maincpu->safe_pc()); fprintf(stderr, " ->%s%s%s%s%s%s%s\n", data & DMA_SETENABLE ? " enable" : "", data & DMA_SETSUPDATE ? " supdate" : "", data & DMA_SETREAD ? " read" : "", data & DMA_CLRCOMPLETE ? " complete" : "", data & DMA_RESET ? " reset" : "", data & DMA_INITBUF ? " initbuf" : "", data & DMA_INITBUFTURBO ? " initbufturbo" : ""); #endif if(data & DMA_SETENABLE) logerror("dma enable %s %s %08x (%08x)\n", name, data & DMA_SETREAD ? "read" : "write", (dma_slots[slot].limit-dma_slots[slot].start) & 0x7fffffff, maincpu->pc()); dma_slot &ds = dma_slots[slot]; if(data & (DMA_RESET|DMA_INITBUF|DMA_INITBUFTURBO)) { ds.state = 0; if(dma_irqs[slot] >= 0) irq_set(dma_irqs[slot], false); } if(data & DMA_SETSUPDATE) { ds.state |= DMA_SUPDATE; ds.supdate = true; } if(data & DMA_SETREAD) ds.state |= DMA_READ; if(data & DMA_CLRCOMPLETE) { ds.state &= ~DMA_COMPLETE; if(dma_irqs[slot] >= 0) irq_set(dma_irqs[slot], false); } if(data & DMA_SETENABLE) { ds.state |= DMA_ENABLE; // fprintf(stderr, "dma slot %d drq=%s\n", slot, ds.drq ? "on" : "off"); if(ds.drq) dma_drq_w(slot, ds.drq); } } const int next_state::scsi_clocks[4] = { 10000000, 12000000, 20000000, 16000000 }; READ32_MEMBER( next_state::scsictrl_r ) { UINT32 res = (scsictrl << 24) | (scsistat << 16); logerror("scsictrl_read %08x @ %08x (%08x)\n", res, mem_mask, space.device().safe_pc()); return res; } WRITE32_MEMBER( next_state::scsictrl_w ) { if(ACCESSING_BITS_24_31) { scsictrl = data >> 24; if(scsictrl & 0x02) scsi->reset(); device_t::static_set_clock(*scsi, scsi_clocks[scsictrl >> 6]); logerror("SCSIctrl %dMHz int=%s dma=%s dmadir=%s%s%s dest=%s (%08x)\n", scsi_clocks[scsictrl >> 6]/1000000, scsictrl & 0x20 ? "on" : "off", scsictrl & 0x10 ? "on" : "off", scsictrl & 0x08 ? "read" : "write", scsictrl & 0x04 ? " flush" : "", scsictrl & 0x02 ? " reset" : "", scsictrl & 0x01 ? "wd3392" : "ncr5390", space.device().safe_pc()); } if(ACCESSING_BITS_16_23) { scsistat = data >> 16; logerror("SCSIstat %02x (%08x)\n", data, space.device().safe_pc()); } } READ32_MEMBER( next_state::event_counter_r) { // Event counters, around that time, are usually fixed-frequency counters. // This one being 1MHz seems to make sense // The v74 rom seems pretty convinced that it's 20 bits only. if(ACCESSING_BITS_24_31) eventc_latch = machine().time().as_ticks(1000000) & 0xfffff; return eventc_latch; } READ32_MEMBER( next_state::dsp_r) { return 0x7fffffff; } WRITE32_MEMBER( next_state::fdc_control_w ) { logerror("FDC write %02x (%08x)\n", data >> 24, space.device().safe_pc()); } READ32_MEMBER( next_state::fdc_control_r ) { // Type of floppy present // 0 = no floppy in drive // 1 = ed // 2 = hd // 3 = dd // The rom strangely can't boot on anything else than ED, it has // code for the other densities but forces ED for some mysterious // reason. The kernel otoh behaves as expected. if(fdc) { floppy_image_device *fdev = machine().device<floppy_connector>(":fdc:0")->get_device(); if(fdev->exists()) { UINT32 variant = fdev->get_variant(); switch(variant) { case floppy_image::SSSD: case floppy_image::SSDD: case floppy_image::DSDD: return 3 << 24; case floppy_image::DSHD: return 2 << 24; case floppy_image::DSED: return 1 << 24; } } } return 0 << 24; } READ32_MEMBER( next_state::phy_r ) { logerror("phy_r %d %08x (%08x)\n", offset, phy[offset], space.device().safe_pc()); return phy[offset] | (0 << 24); } WRITE32_MEMBER( next_state::phy_w ) { COMBINE_DATA(phy+offset); logerror("phy_w %d %08x (%08x)\n", offset, phy[offset], space.device().safe_pc()); } void next_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) { irq_set(29, true); timer_data = timer_next_data; if(timer_ctrl & 0x40000000) timer_start(); else timer_ctrl &= 0x7fffffff; } READ32_MEMBER( next_state::timer_data_r ) { if(timer_ctrl & 0x80000000) timer_update(); return timer_data; } WRITE32_MEMBER( next_state::timer_data_w ) { if(timer_ctrl & 0x80000000) { COMBINE_DATA(&timer_next_data); timer_next_data &= 0xffff0000; } else { COMBINE_DATA(&timer_data); timer_data &= 0xffff0000; } } READ32_MEMBER( next_state::timer_ctrl_r ) { irq_set(29, false); return timer_ctrl; } WRITE32_MEMBER( next_state::timer_ctrl_w ) { bool oldact = timer_ctrl & 0x80000000; COMBINE_DATA(&timer_ctrl); bool newact = timer_ctrl & 0x80000000; if(oldact != newact) { if(oldact) { timer_update(); irq_set(29, false); } else { timer_next_data = timer_data; timer_start(); } } } void next_state::timer_update() { int delta = timer_vbase - (machine().time() - timer_tbase).as_ticks(1000000); if(delta < 0) delta = 0; timer_data = delta << 16; } void next_state::timer_start() { timer_tbase = machine().time(); timer_vbase = timer_data >> 16; timer_tm->adjust(attotime::from_usec(timer_vbase)); } void next_state::scc_irq(bool state) { irq_set(17, state); } void next_state::keyboard_irq(bool state) { irq_set(3, state); } void next_state::power_irq(bool state) { irq_set(2, state); } void next_state::nmi_irq(bool state) { irq_set(31, state); } void next_state::fdc_irq(bool state) { irq_set(7, state); } void next_state::fdc_drq(bool state) { dma_drq_w(1, state); } void next_state::net_tx_irq(bool state) { irq_set(10, state); } void next_state::net_rx_irq(bool state) { irq_set(9, state); } void next_state::net_tx_drq(bool state) { dma_drq_w(17, state); } void next_state::net_rx_drq(bool state) { dma_drq_w(21, state); } void next_state::mo_irq(bool state) { irq_set(13, state); } void next_state::mo_drq(bool state) { dma_drq_w(5, state); } WRITE_LINE_MEMBER(next_state::scsi_irq) { irq_set(12, state); } WRITE_LINE_MEMBER(next_state::scsi_drq) { dma_drq_w(1, state); } void next_state::setup(UINT32 _scr1, int size_x, int size_y, int skip, bool color) { scr1 = _scr1; screen_sx = size_x; screen_sy = size_y; screen_skip = skip; screen_color = color; } void next_state::machine_start() { save_item(NAME(scr2)); save_item(NAME(irq_status)); save_item(NAME(irq_mask)); save_item(NAME(irq_level)); save_item(NAME(phy)); save_item(NAME(scsictrl)); save_item(NAME(timer_tbase)); save_item(NAME(timer_vbase)); save_item(NAME(timer_data)); save_item(NAME(timer_ctrl)); save_item(NAME(eventc_latch)); timer_tm = timer_alloc(0); if(fdc) { fdc->setup_intrq_cb(n82077aa_device::line_cb(FUNC(next_state::fdc_irq), this)); fdc->setup_drq_cb(n82077aa_device::line_cb(FUNC(next_state::fdc_drq), this)); } } void next_state::machine_reset() { scr2 = 0; irq_status = 0; irq_mask = 0; irq_level = 0; esp = 0; scsictrl = 0; phy[0] = phy[1] = 0; eventc_latch = 0; timer_vbase = 0; timer_data = 0; timer_next_data = 0; timer_ctrl = 0; dma_drq_w(4, true); // soundout } static ADDRESS_MAP_START( next_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("user1", 0) AM_RANGE(0x01000000, 0x0101ffff) AM_ROM AM_REGION("user1", 0) AM_RANGE(0x02000000, 0x020001ff) AM_MIRROR(0x300200) AM_READWRITE(dma_ctrl_r, dma_ctrl_w) AM_RANGE(0x02004000, 0x020041ff) AM_MIRROR(0x300200) AM_READWRITE(dma_regs_r, dma_regs_w) AM_RANGE(0x02006000, 0x0200600f) AM_MIRROR(0x300000) AM_DEVICE8("net", mb8795_device, map, 0xffffffff) // AM_RANGE(0x02006010, 0x02006013) AM_MIRROR(0x300000) memory timing AM_RANGE(0x02007000, 0x02007003) AM_MIRROR(0x300000) AM_READ(irq_status_r) AM_RANGE(0x02007800, 0x02007803) AM_MIRROR(0x300000) AM_READWRITE(irq_mask_r,irq_mask_w) AM_RANGE(0x02008000, 0x02008003) AM_MIRROR(0x300000) AM_READ(dsp_r) AM_RANGE(0x0200c000, 0x0200c003) AM_MIRROR(0x300000) AM_READ(scr1_r) AM_RANGE(0x0200c800, 0x0200c803) AM_MIRROR(0x300000) AM_READ(rom_map_r) AM_RANGE(0x0200d000, 0x0200d003) AM_MIRROR(0x300000) AM_READWRITE(scr2_r,scr2_w) // AM_RANGE(0x0200d800, 0x0200d803) AM_MIRROR(0x300000) RMTINT AM_RANGE(0x0200e000, 0x0200e00b) AM_MIRROR(0x300000) AM_DEVICE("keyboard", nextkbd_device, amap) // AM_RANGE(0x0200f000, 0x0200f003) AM_MIRROR(0x300000) printer // AM_RANGE(0x02010000, 0x02010003) AM_MIRROR(0x300000) brightness AM_RANGE(0x02012000, 0x0201201f) AM_MIRROR(0x300000) AM_DEVICE8("mo", nextmo_device, map, 0xffffffff) AM_RANGE(0x02014000, 0x0201400f) AM_MIRROR(0x300000) AM_DEVICE8("scsibus:7:ncr5390", ncr5390_device, map, 0xffffffff) AM_RANGE(0x02014020, 0x02014023) AM_MIRROR(0x300000) AM_READWRITE(scsictrl_r, scsictrl_w) AM_RANGE(0x02016000, 0x02016003) AM_MIRROR(0x300000) AM_READWRITE(timer_data_r, timer_data_w) AM_RANGE(0x02016004, 0x02016007) AM_MIRROR(0x300000) AM_READWRITE(timer_ctrl_r, timer_ctrl_w) AM_RANGE(0x02018000, 0x02018003) AM_MIRROR(0x300000) AM_DEVREADWRITE8("scc", scc8530_t, reg_r, reg_w, 0xffffffff) // AM_RANGE(0x02018004, 0x02018007) AM_MIRROR(0x300000) SCC CLK // AM_RANGE(0x02018100, 0x02018103) AM_MIRROR(0x300000) Color RAMDAC // AM_RANGE(0x02018104, 0x02018107) AM_MIRROR(0x300000) Color CSR // AM_RANGE(0x02018190, 0x02018197) AM_MIRROR(0x300000) warp 9c DRAM timing // AM_RANGE(0x02018198, 0x0201819f) AM_MIRROR(0x300000) warp 9c VRAM timing AM_RANGE(0x0201a000, 0x0201a003) AM_MIRROR(0x300000) AM_READ(event_counter_r) // EVENTC // AM_RANGE(0x020c0000, 0x020c0004) AM_MIRROR(0x300000) BMAP AM_RANGE(0x020c0030, 0x020c0037) AM_MIRROR(0x300000) AM_READWRITE(phy_r, phy_w) AM_RANGE(0x04000000, 0x07ffffff) AM_RAM //work ram // AM_RANGE(0x0c000000, 0x0c03ffff) video RAM w A+B-AB function // AM_RANGE(0x0d000000, 0x0d03ffff) video RAM w (1-A)B function // AM_RANGE(0x0e000000, 0x0e03ffff) video RAM w ceil(A+B) function // AM_RANGE(0x0f000000, 0x0f03ffff) video RAM w AB function // AM_RANGE(0x10000000, 0x1003ffff) main RAM w A+B-AB function // AM_RANGE(0x14000000, 0x1403ffff) main RAM w (1-A)B function // AM_RANGE(0x18000000, 0x1803ffff) main RAM w ceil(A+B) function // AM_RANGE(0x1c000000, 0x1c03ffff) main RAM w AB function ADDRESS_MAP_END static ADDRESS_MAP_START( next_0b_nofdc_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x0b000000, 0x0b03ffff) AM_RAM AM_SHARE("vram") AM_IMPORT_FROM(next_mem) ADDRESS_MAP_END static ADDRESS_MAP_START( next_fdc_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x02014100, 0x02014107) AM_MIRROR(0x300000) AM_DEVICE8("fdc", n82077aa_device, map, 0xffffffff) AM_RANGE(0x02014108, 0x0201410b) AM_MIRROR(0x300000) AM_READWRITE(fdc_control_r, fdc_control_w) AM_IMPORT_FROM(next_mem) ADDRESS_MAP_END static ADDRESS_MAP_START( next_0b_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x0b000000, 0x0b03ffff) AM_RAM AM_SHARE("vram") AM_IMPORT_FROM(next_fdc_mem) ADDRESS_MAP_END static ADDRESS_MAP_START( next_0c_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x0c000000, 0x0c1fffff) AM_RAM AM_SHARE("vram") AM_IMPORT_FROM(next_fdc_mem) ADDRESS_MAP_END static ADDRESS_MAP_START( next_2c_mem, AS_PROGRAM, 32, next_state ) AM_RANGE(0x2c000000, 0x2c1fffff) AM_RAM AM_SHARE("vram") AM_IMPORT_FROM(next_fdc_mem) ADDRESS_MAP_END /* Input ports */ static INPUT_PORTS_START( next ) INPUT_PORTS_END FLOPPY_FORMATS_MEMBER( next_state::floppy_formats ) FLOPPY_PC_FORMAT FLOPPY_FORMATS_END static SLOT_INTERFACE_START( next_floppies ) SLOT_INTERFACE( "35ed", FLOPPY_35_ED ) SLOT_INTERFACE_END static SLOT_INTERFACE_START( next_scsi_devices ) SLOT_INTERFACE("cdrom", NSCSI_CDROM) SLOT_INTERFACE("harddisk", NSCSI_HARDDISK) SLOT_INTERFACE_INTERNAL("ncr5390", NCR5390) SLOT_INTERFACE_END static const ncr5390_interface next_ncr5390_interface = { DEVCB_DRIVER_LINE_MEMBER(next_state, scsi_irq), DEVCB_DRIVER_LINE_MEMBER(next_state, scsi_drq) }; static MACHINE_CONFIG_START( next_base, next_state ) /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_REFRESH_RATE(60) MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */ MCFG_SCREEN_UPDATE_DRIVER(next_state, screen_update) MCFG_SCREEN_SIZE(1120, 900) MCFG_SCREEN_VISIBLE_AREA(0, 1120-1, 0, 832-1) // devices MCFG_NSCSI_BUS_ADD("scsibus") MCFG_MCCS1850_ADD("rtc", XTAL_32_768kHz, line_cb_t(), line_cb_t(), line_cb_t()) MCFG_SCC8530_ADD("scc", XTAL_25MHz, line_cb_t(FUNC(next_state::scc_irq), static_cast<next_state *>(owner))) MCFG_NEXTKBD_ADD("keyboard", line_cb_t(FUNC(next_state::keyboard_irq), static_cast<next_state *>(owner)), line_cb_t(FUNC(next_state::power_irq), static_cast<next_state *>(owner)), line_cb_t(FUNC(next_state::nmi_irq), static_cast<next_state *>(owner))) MCFG_NSCSI_ADD("scsibus:0", next_scsi_devices, "cdrom", 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:1", next_scsi_devices, "harddisk", 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:2", next_scsi_devices, 0, 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:3", next_scsi_devices, 0, 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:4", next_scsi_devices, 0, 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:5", next_scsi_devices, 0, 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:6", next_scsi_devices, 0, 0, 0, 0, false) MCFG_NSCSI_ADD("scsibus:7", next_scsi_devices, "ncr5390", 0, &next_ncr5390_interface, 10000000, true) MCFG_MB8795_ADD("net", line_cb_t(FUNC(next_state::net_tx_irq), static_cast<next_state *>(owner)), line_cb_t(FUNC(next_state::net_rx_irq), static_cast<next_state *>(owner)), line_cb_t(FUNC(next_state::net_tx_drq), static_cast<next_state *>(owner)), line_cb_t(FUNC(next_state::net_rx_drq), static_cast<next_state *>(owner))) MCFG_NEXTMO_ADD("mo", line_cb_t(FUNC(next_state::mo_irq), static_cast<next_state *>(owner)), line_cb_t(FUNC(next_state::mo_drq), static_cast<next_state *>(owner))) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( next, next_base ) MCFG_CPU_ADD("maincpu", M68030, XTAL_25MHz) MCFG_CPU_PROGRAM_MAP(next_0b_nofdc_mem) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( next_fdc_base, next_base ) MCFG_N82077AA_ADD("fdc", n82077aa_device::MODE_PS2) MCFG_FLOPPY_DRIVE_ADD("fdc:0", next_floppies, "35ed", 0, next_state::floppy_formats) // software list MCFG_SOFTWARE_LIST_ADD("flop_list", "next") MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nexts, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_25MHz) MCFG_CPU_PROGRAM_MAP(next_0b_mem) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nexts2, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_25MHz) MCFG_CPU_PROGRAM_MAP(next_0b_mem) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nextsc, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_25MHz) MCFG_CPU_PROGRAM_MAP(next_2c_mem) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nextst, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz) MCFG_CPU_PROGRAM_MAP(next_0b_mem) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nextstc, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz) MCFG_CPU_PROGRAM_MAP(next_0c_mem) MCFG_SCREEN_MODIFY("screen") MCFG_SCREEN_VISIBLE_AREA(0, 832-1, 0, 624-1) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nextct, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz) MCFG_CPU_PROGRAM_MAP(next_0c_mem) MACHINE_CONFIG_END static MACHINE_CONFIG_DERIVED( nextctc, next_fdc_base ) MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz) MCFG_CPU_PROGRAM_MAP(next_0c_mem) MCFG_SCREEN_MODIFY("screen") MCFG_SCREEN_VISIBLE_AREA(0, 832-1, 0, 624-1) MACHINE_CONFIG_END /* ROM definition */ #define ROM_NEXT_V1 \ ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \ ROM_SYSTEM_BIOS( 0, "v12", "v1.2" ) /* MAC address/serial number word at 0xC: 005AD0 */ \ ROMX_LOAD( "rev_1.2.bin", 0x0000, 0x10000, CRC(7070bd78) SHA1(e34418423da61545157e36b084e2068ad41c9e24), ROM_BIOS(1)) /* Label: "(C) 1990 NeXT, Inc. // All Rights Reserved. // Release 1.2 // 1142.02", underlabel exists but unknown */ \ ROM_SYSTEM_BIOS( 1, "v10", "v1.0 v41" ) /* MAC address/serial number word at 0xC: 003090 */ \ ROMX_LOAD( "rev_1.0_v41.bin", 0x0000, 0x10000, CRC(54df32b9) SHA1(06e3ecf09ab67a571186efd870e6b44028612371), ROM_BIOS(2)) /* Label: "(C) 1989 NeXT, Inc. // All Rights Reserved. // Release 1.0 // 1142.00", underlabel: "MYF // 1.0.41 // 0D5C" */ \ ROM_SYSTEM_BIOS( 2, "v10p", "v1.0 v41 alternate" ) /* MAC address/serial number word at 0xC: 0023D9 */ \ ROMX_LOAD( "rev_1.0_proto.bin", 0x0000, 0x10000, CRC(F44974F9) SHA1(09EAF9F5D47E379CFA0E4DC377758A97D2869DDC), ROM_BIOS(3)) /* Label: "(C) 1989 NeXT, Inc. // All Rights Reserved. // Release 1.0 // 1142.00", no underlabel */ #define ROM_NEXT_V2 \ ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \ ROM_SYSTEM_BIOS( 0, "v25", "v2.5 v66" ) /* MAC address/serial number word at 0xC: 00F302 */ \ ROMX_LOAD( "rev_2.5_v66.bin", 0x0000, 0x20000, CRC(f47e0bfe) SHA1(b3534796abae238a0111299fc406a9349f7fee24), ROM_BIOS(1)) \ ROM_SYSTEM_BIOS( 1, "v24", "v2.4 v65" ) /* MAC address/serial number word at 0xC: 00A634 */ \ ROMX_LOAD( "rev_2.4_v65.bin", 0x0000, 0x20000, CRC(74e9e541) SHA1(67d195351288e90818336c3a84d55e6a070960d2), ROM_BIOS(2)) \ ROM_SYSTEM_BIOS( 2, "v22", "v2.2 v63" ) /* MAC address/serial number word at 0xC: 00894C */ \ ROMX_LOAD( "rev_2.2_v63.bin", 0x0000, 0x20000, CRC(739D7C07) SHA1(48FFE54CF2038782A92A0850337C5C6213C98571), ROM_BIOS(3)) /* Label: "(C) 1990 NeXT Computer, Inc. // All Rights Reserved. // Release 2.1 // 2918.AB" */ \ ROM_SYSTEM_BIOS( 3, "v21", "v2.1 v59" ) /* MAC address/serial number word at 0xC: 0072FE */ \ ROMX_LOAD( "rev_2.1_v59.bin", 0x0000, 0x20000, CRC(f20ef956) SHA1(09586c6de1ca73995f8c9b99870ee3cc9990933a), ROM_BIOS(4)) \ ROM_SYSTEM_BIOS( 4, "v12", "v1.2 v58" ) /* MAC address/serial number word at 0xC: 006372 */ \ ROMX_LOAD( "rev_1.2_v58.bin", 0x0000, 0x20000, CRC(B815B6A4) SHA1(97D8B09D03616E1487E69D26609487486DB28090), ROM_BIOS(5)) /* Label: "V58 // (C) 1990 NeXT, Inc. // All Rights Reserved // Release 1.2 // 1142.02" */ #define ROM_NEXT_V3 \ ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \ ROM_SYSTEM_BIOS( 0, "v33", "v3.3 v74" ) /* MAC address/serial number word at 0xC: 123456 */ \ ROMX_LOAD( "rev_3.3_v74.bin", 0x0000, 0x20000, CRC(fbc3a2cd) SHA1(a9bef655f26f97562de366e4a33bb462e764c929), ROM_BIOS(1)) \ ROM_SYSTEM_BIOS( 1, "v32", "v3.2 v72" ) /* MAC address/serial number word at 0xC: 012f31 */ \ ROMX_LOAD( "rev_3.2_v72.bin", 0x0000, 0x20000, CRC(e750184f) SHA1(ccebf03ed090a79c36f761265ead6cd66fb04329), ROM_BIOS(2)) \ ROM_SYSTEM_BIOS( 2, "v30", "v3.0 v70" ) /* MAC address/serial number word at 0xC: 0106e8 */ \ ROMX_LOAD( "rev_3.0_v70.bin", 0x0000, 0x20000, CRC(37250453) SHA1(a7e42bd6a25c61903c8ca113d0b9a624325ee6cf), ROM_BIOS(3)) ROM_START(next) ROM_NEXT_V1 ROM_END ROM_START(nexts) ROM_NEXT_V2 ROM_END ROM_START(nexts2) ROM_NEXT_V2 ROM_END ROM_START(nextsc) ROM_NEXT_V2 ROM_END ROM_START(nextst) ROM_NEXT_V3 ROM_END ROM_START(nextstc) ROM_NEXT_V3 ROM_END ROM_START(nextct) ROM_NEXT_V3 ROM_END ROM_START(nextctc) ROM_NEXT_V3 ROM_END DRIVER_INIT_MEMBER(next_state,next) { setup(0x00010002, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nexts) { setup(0x00011002, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nexts2) { setup(0x00012102, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nextsc) { setup(0x00013102, 1120, 832, 16, true); } DRIVER_INIT_MEMBER(next_state,nextst) { setup(0x00014103, 1120, 832, 2, false); } DRIVER_INIT_MEMBER(next_state,nextstc) { setup(0x00015103, 832, 624, 0, true); } DRIVER_INIT_MEMBER(next_state,nextct) { setup(0x00018103, 1120, 832, 0, false); } DRIVER_INIT_MEMBER(next_state,nextctc) { setup(0x00019103, 832, 624, 0, true); } /* Driver */ /* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */ COMP( 1987, next, 0, 0, next, next, next_state, next, "Next Software Inc", "NeXT Cube", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( 1990, nexts, 0, 0, nexts, next, next_state, nexts, "Next Software Inc", "NeXTstation", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( 1990, nexts2, nexts, 0, nexts2, next, next_state, nexts2, "Next Software Inc", "NeXTstation (X15 variant)", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( 1990, nextsc, nexts, 0, nextsc, next, next_state, nextsc, "Next Software Inc", "NeXTstation color", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( 1990, nextst, 0, 0, nextst, next, next_state, nextst, "Next Software Inc", "NeXTstation turbo", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( 1990, nextstc, nextst, 0, nextstc, next, next_state, nextstc, "Next Software Inc", "NeXTstation turbo color", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( ????, nextct, nextst, 0, nextct, next, next_state, nextct, "Next Software Inc", "NeXT Cube turbo", GAME_NOT_WORKING | GAME_NO_SOUND) COMP( ????, nextctc, nextst, 0, nextctc, next, next_state, nextctc, "Next Software Inc", "NeXT Cube turbo color", GAME_NOT_WORKING | GAME_NO_SOUND)