1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
|
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_system.h
*
* netlist devices defined in the core
*/
#ifndef NLD_SYSTEM_H_
#define NLD_SYSTEM_H_
#include "../nl_setup.h"
#include "../nl_base.h"
#include "../analog/nld_twoterm.h"
// -----------------------------------------------------------------------------
// Macros
// -----------------------------------------------------------------------------
#define TTL_INPUT(_name, _v) \
NET_REGISTER_DEV(ttl_input, _name) \
PARAM(_name.IN, _v)
#define ANALOG_INPUT(_name, _v) \
NET_REGISTER_DEV(analog_input, _name) \
PARAM(_name.IN, _v)
#define MAINCLOCK(_name, _freq) \
NET_REGISTER_DEV(mainclock, _name) \
PARAM(_name.FREQ, _freq)
#define CLOCK(_name, _freq) \
NET_REGISTER_DEV(clock, _name) \
PARAM(_name.FREQ, _freq)
#define GNDA() \
NET_REGISTER_DEV(gnd, GND)
#define DUMMY_INPUT(_name) \
NET_REGISTER_DEV(dummy_input, _name)
#define FRONTIER(_name, _IN, _OUT) \
NET_REGISTER_DEV(frontier, _name) \
NET_C(_IN, _name.I) \
NET_C(_OUT, _name.Q)
// -----------------------------------------------------------------------------
// mainclock
// -----------------------------------------------------------------------------
NETLIB_DEVICE_WITH_PARAMS(mainclock,
public:
netlist_ttl_output_t m_Q;
netlist_param_double_t m_freq;
netlist_time m_inc;
ATTR_HOT inline static void mc_update(netlist_logic_net_t &net);
);
// -----------------------------------------------------------------------------
// clock
// -----------------------------------------------------------------------------
NETLIB_DEVICE_WITH_PARAMS(clock,
netlist_ttl_input_t m_feedback;
netlist_ttl_output_t m_Q;
netlist_param_double_t m_freq;
netlist_time m_inc;
);
// -----------------------------------------------------------------------------
// Special support devices ...
// -----------------------------------------------------------------------------
NETLIB_DEVICE_WITH_PARAMS(ttl_input,
netlist_ttl_output_t m_Q;
netlist_param_logic_t m_IN;
);
NETLIB_DEVICE_WITH_PARAMS(analog_input,
netlist_analog_output_t m_Q;
netlist_param_double_t m_IN;
);
// -----------------------------------------------------------------------------
// nld_gnd
// -----------------------------------------------------------------------------
class NETLIB_NAME(gnd) : public netlist_device_t
{
public:
ATTR_COLD NETLIB_NAME(gnd)()
: netlist_device_t(GND) { }
ATTR_COLD virtual ~NETLIB_NAME(gnd)() {}
protected:
ATTR_COLD void start()
{
register_output("Q", m_Q);
}
ATTR_COLD void reset()
{
}
ATTR_HOT ATTR_ALIGN void update()
{
OUTANALOG(m_Q, 0.0);
}
private:
netlist_analog_output_t m_Q;
};
// -----------------------------------------------------------------------------
// nld_dummy_input
// -----------------------------------------------------------------------------
class NETLIB_NAME(dummy_input) : public netlist_device_t
{
public:
ATTR_COLD NETLIB_NAME(dummy_input)()
: netlist_device_t(DUMMY) { }
ATTR_COLD virtual ~NETLIB_NAME(dummy_input)() {}
protected:
ATTR_COLD void start()
{
register_input("I", m_I);
}
ATTR_COLD void reset()
{
}
ATTR_HOT ATTR_ALIGN void update()
{
}
private:
netlist_analog_input_t m_I;
};
// -----------------------------------------------------------------------------
// nld_frontier
// -----------------------------------------------------------------------------
class NETLIB_NAME(frontier) : public netlist_device_t
{
public:
ATTR_COLD NETLIB_NAME(frontier)()
: netlist_device_t(DUMMY) { }
ATTR_COLD virtual ~NETLIB_NAME(frontier)() {}
protected:
ATTR_COLD void start()
{
register_input("I", m_I);
register_output("Q", m_Q);
}
ATTR_COLD void reset()
{
}
ATTR_HOT ATTR_ALIGN void update()
{
OUTANALOG(m_Q, INPANALOG(m_I));
}
private:
netlist_analog_input_t m_I;
netlist_analog_output_t m_Q;
};
// -----------------------------------------------------------------------------
// netdev_a_to_d
// -----------------------------------------------------------------------------
class nld_a_to_d_proxy : public netlist_device_t
{
public:
ATTR_COLD nld_a_to_d_proxy(netlist_input_t &in_proxied)
: netlist_device_t()
{
nl_assert(in_proxied.family() == LOGIC);
m_I.m_logic_family = in_proxied.m_logic_family;
}
ATTR_COLD virtual ~nld_a_to_d_proxy() {}
netlist_analog_input_t m_I;
netlist_ttl_output_t m_Q;
protected:
ATTR_COLD void start()
{
register_input("I", m_I);
register_output("Q", m_Q);
}
ATTR_COLD void reset()
{
}
ATTR_HOT ATTR_ALIGN void update()
{
if (m_I.Q_Analog() > m_I.m_logic_family->m_high_thresh_V)
OUTLOGIC(m_Q, 1, NLTIME_FROM_NS(1));
else if (m_I.Q_Analog() < m_I.m_logic_family->m_low_thresh_V)
OUTLOGIC(m_Q, 0, NLTIME_FROM_NS(1));
//else
// OUTLOGIC(m_Q, m_Q.net().last_Q(), NLTIME_FROM_NS(1));
}
};
// -----------------------------------------------------------------------------
// nld_base_d_to_a_proxy
// -----------------------------------------------------------------------------
class nld_base_d_to_a_proxy : public netlist_device_t
{
public:
ATTR_COLD nld_base_d_to_a_proxy(netlist_output_t &out_proxied)
: netlist_device_t()
{
nl_assert(out_proxied.family() == LOGIC);
m_logic_family = out_proxied.m_logic_family;
}
ATTR_COLD virtual ~nld_base_d_to_a_proxy() {}
ATTR_COLD virtual netlist_core_terminal_t &out() = 0;
netlist_ttl_input_t m_I;
protected:
ATTR_COLD void start()
{
register_input("I", m_I);
}
ATTR_COLD virtual const netlist_logic_family_desc_t *logic_family()
{
return m_logic_family;
}
const netlist_logic_family_desc_t *m_logic_family;
private:
};
#if 0
class nld_d_to_a_proxy : public nld_base_d_to_a_proxy
{
public:
ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
: nld_base_d_to_a_proxy(out_proxied)
{
}
ATTR_COLD virtual ~nld_d_to_a_proxy() {}
protected:
ATTR_COLD void start()
{
nld_base_d_to_a_proxy::start();
register_output("Q", m_Q);
}
ATTR_COLD void reset()
{
//m_Q.initial(0);
}
ATTR_COLD virtual netlist_core_terminal_t &out()
{
return m_Q;
}
ATTR_HOT ATTR_ALIGN void update()
{
OUTANALOG(m_Q, INPLOGIC(m_I) ? m_logic_family->m_high_V : m_logic_family->m_low_V, NLTIME_FROM_NS(1));
}
private:
netlist_analog_output_t m_Q;
};
#else
class nld_d_to_a_proxy : public nld_base_d_to_a_proxy
{
public:
ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
: nld_base_d_to_a_proxy(out_proxied)
, m_RV(TWOTERM)
, m_last_state(-1)
{
}
ATTR_COLD virtual ~nld_d_to_a_proxy() {}
protected:
ATTR_COLD virtual void start();
ATTR_COLD virtual void reset();
ATTR_COLD virtual netlist_core_terminal_t &out();
ATTR_HOT ATTR_ALIGN void update();
private:
netlist_analog_output_t m_Q;
nld_twoterm m_RV;
int m_last_state;
};
#endif
#endif /* NLD_SYSTEM_H_ */
|