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// license:BSD-3-Clause
// copyright-holders:Carl, Miodrag Milanovic, Vas Crabb
#pragma once

#ifndef __EMU_H__
#error Dont include this file directly; include emu.h instead.
#endif

#ifndef MAME_EMU_DISERIAL_H
#define MAME_EMU_DISERIAL_H

// Windows headers are crap, let me count the ways
#undef PARITY_NONE
#undef PARITY_ODD
#undef PARITY_EVEN
#undef PARITY_MARK
#undef PARITY_SPACE

// ======================> device_serial_interface
class device_serial_interface : public device_interface
{
public:
	enum
	{
		/* receive is waiting for start bit. The transition from high-low indicates
		start of start bit. This is used to synchronise with the data being transferred */
		RECEIVE_REGISTER_WAITING_FOR_START_BIT = 0x01,

		/* receive is synchronised with data, data bits will be clocked in */
		RECEIVE_REGISTER_SYNCHRONISED = 0x02,

		/* set if receive register has been filled */
		RECEIVE_REGISTER_FULL = 0x04
	};

	enum
	{
		/* register is empty and ready to be filled with data */
		TRANSMIT_REGISTER_EMPTY = 0x0001
	};

	/* parity selections */
	/* if all the bits are added in a byte, if the result is:
	   even -> parity is even
	   odd -> parity is odd
	*/

	enum parity_t
	{
		PARITY_NONE,     /* no parity. a parity bit will not be in the transmitted/received data */
		PARITY_ODD,      /* odd parity */
		PARITY_EVEN,     /* even parity */
		PARITY_MARK,     /* one parity */
		PARITY_SPACE     /* zero parity */
	};

	enum stop_bits_t
	{
		STOP_BITS_0,
		STOP_BITS_1 = 1,
		STOP_BITS_1_5 = 2,
		STOP_BITS_2 = 3
	};

	/* Communication lines.  Beware, everything is active high */
	enum
	{
		CTS = 0x0001, /* Clear to Send.       (INPUT)  Other end of connection is ready to accept data */
		RTS = 0x0002, /* Request to Send.     (OUTPUT) This end is ready to send data, and requests if the other */
						/*                               end is ready to accept it */
		DSR = 0x0004, /* Data Set ready.      (INPUT)  Other end of connection has data */
		DTR = 0x0008, /* Data terminal Ready. (OUTPUT) TX contains new data. */
		RX  = 0x0010, /* Receive data.        (INPUT)  */
		TX  = 0x0020  /* TX = Transmit data.  (OUTPUT) */
	};

	// construction/destruction
	device_serial_interface(const machine_config &mconfig, device_t &device);
	virtual ~device_serial_interface();

	DECLARE_WRITE_LINE_MEMBER(rx_w);
	DECLARE_WRITE_LINE_MEMBER(tx_clock_w);
	DECLARE_WRITE_LINE_MEMBER(rx_clock_w);
	DECLARE_WRITE_LINE_MEMBER(clock_w);

protected:
	void set_data_frame(int start_bit_count, int data_bit_count, parity_t parity, stop_bits_t stop_bits);

	void receive_register_reset();
	void receive_register_update_bit(int bit);
	void receive_register_extract();

	void set_rcv_rate(const attotime &rate);
	void set_tra_rate(const attotime &rate);
	void set_rcv_rate(u32 clock, int div) { set_rcv_rate((clock && div) ? (attotime::from_hz(clock) * div) : attotime::never); }
	void set_tra_rate(u32 clock, int div) { set_tra_rate((clock && div) ? (attotime::from_hz(clock) * div) : attotime::never); }
	void set_rcv_rate(int baud) { set_rcv_rate(baud ? attotime::from_hz(baud) : attotime::never); }
	void set_tra_rate(int baud) { set_tra_rate(baud ? attotime::from_hz(baud) : attotime::never); }
	void set_rate(const attotime &rate) { set_rcv_rate(rate); set_tra_rate(rate); }
	void set_rate(u32 clock, int div) { set_rcv_rate(clock, div); set_tra_rate(clock, div); }
	void set_rate(int baud) { set_rcv_rate(baud); set_tra_rate(baud); }

	void transmit_register_reset();
	void transmit_register_add_bit(int bit);
	void transmit_register_setup(u8 data_byte);
	u8 transmit_register_get_data_bit();

	u8 serial_helper_get_parity(u8 data) { return m_serial_parity_table[data]; }

	bool is_receive_register_full();
	bool is_transmit_register_empty();
	bool is_receive_register_synchronized() const { return m_rcv_flags & RECEIVE_REGISTER_SYNCHRONISED; }
	bool is_receive_register_shifting() const { return m_rcv_bit_count_received > 0; }
	bool is_receive_framing_error() const { return m_rcv_framing_error; }
	bool is_receive_parity_error() const { return m_rcv_parity_error; }

	u8 get_received_char() const { return m_rcv_byte_received; }

	virtual void tra_callback() { }
	virtual void rcv_callback() { receive_register_update_bit(m_rcv_line); }
	virtual void tra_complete() { }
	virtual void rcv_complete() { }

	// interface-level overrides
	virtual void interface_pre_start() override;
	virtual void interface_post_start() override;

	bool m_start_bit_hack_for_external_clocks;

	const char *parity_tostring(parity_t stop_bits);
	const char *stop_bits_tostring(stop_bits_t stop_bits);

private:
	TIMER_CALLBACK_MEMBER(rcv_clock) { rx_clock_w(!m_rcv_clock_state); }
	TIMER_CALLBACK_MEMBER(tra_clock) { tx_clock_w(!m_tra_clock_state); }

	u8 m_serial_parity_table[256];

	// Data frame
	// number of start bits
	int m_df_start_bit_count;
	// length of word in bits
	u8 m_df_word_length;
	// parity state
	u8 m_df_parity;
	// number of stop bits
	u8 m_df_stop_bit_count;

	// Receive register
	/* data */
	u16 m_rcv_register_data;
	/* flags */
	u8 m_rcv_flags;
	/* bit count received */
	u8 m_rcv_bit_count_received;
	/* length of data to receive - includes data bits, parity bit and stop bit */
	u8 m_rcv_bit_count;
	/* the byte of data received */
	u8 m_rcv_byte_received;

	bool m_rcv_framing_error;
	bool m_rcv_parity_error;

	// Transmit register
	/* data */
	u16 m_tra_register_data;
	/* flags */
	u8 m_tra_flags;
	/* number of bits transmitted */
	u8 m_tra_bit_count_transmitted;
	/* length of data to send */
	u8 m_tra_bit_count;

	emu_timer *m_rcv_clock;
	emu_timer *m_tra_clock;
	attotime m_rcv_rate;
	attotime m_tra_rate;
	u8 m_rcv_line;

	int m_tra_clock_state, m_rcv_clock_state;

	void tra_edge();
	void rcv_edge();
};


template <u32 FIFO_LENGTH>
class device_buffered_serial_interface : public device_serial_interface
{
protected:
	using device_serial_interface::device_serial_interface;

	virtual void tra_complete() override
	{
		assert(!m_empty || (m_head == m_tail));
		assert(m_head < ARRAY_LENGTH(m_fifo));
		assert(m_tail < ARRAY_LENGTH(m_fifo));

		if (!m_empty)
		{
			transmit_register_setup(m_fifo[m_head]);
			m_head = (m_head + 1U) % FIFO_LENGTH;
			m_empty = (m_head == m_tail) ? 1U : 0U;
		}
	}

	virtual void rcv_complete() override
	{
		receive_register_extract();
		received_byte(get_received_char());
	}

	void clear_fifo()
	{
		m_head = m_tail = 0U;
		m_empty = 1U;
	}

	void transmit_byte(u8 byte)
	{
		assert(!m_empty || (m_head == m_tail));
		assert(m_head < ARRAY_LENGTH(m_fifo));
		assert(m_tail < ARRAY_LENGTH(m_fifo));

		if (m_empty && is_transmit_register_empty())
		{
			transmit_register_setup(byte);
		}
		else if (m_empty || (m_head != m_tail))
		{
			m_fifo[m_tail] = byte;
			m_tail = (m_tail + 1U) % FIFO_LENGTH;
			m_empty = 0U;
		}
		else
		{
			device().logerror("FIFO overrun (byte = 0x%02x)", byte);
		}
	}

	bool fifo_full() const
	{
		return !m_empty && (m_head == m_tail);
	}

protected:
	void interface_post_start() override
	{
		device_serial_interface::interface_post_start();

		device().save_item(NAME(m_fifo));
		device().save_item(NAME(m_head));
		device().save_item(NAME(m_tail));
		device().save_item(NAME(m_empty));
	}

private:
	virtual void received_byte(u8 byte) = 0;

	u8  m_fifo[FIFO_LENGTH];
	u32 m_head = 0U, m_tail = 0U;
	u8  m_empty = 1U;
};

#endif  // MAME_EMU_DISERIAL_H
vice).m_xf1_cb.set_callback(object); } template<class _Object> static devcb_base &set_iack_callback(device_t &device, _Object object) { return downcast<tms3203x_device &>(device).m_iack_cb.set_callback(object); } // public interfaces static float fp_to_float(UINT32 floatdata); static double fp_to_double(UINT32 floatdata); static UINT32 float_to_fp(float fval); static UINT32 double_to_fp(double dval); protected: // device-level overrides virtual void device_start(); virtual void device_reset(); virtual const rom_entry *device_rom_region() const; // device_execute_interface overrides virtual UINT32 execute_min_cycles() const; virtual UINT32 execute_max_cycles() const; virtual UINT32 execute_input_lines() const; virtual void execute_run(); virtual void execute_set_input(int inputnum, int state); // device_memory_interface overrides virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; // device_state_interface overrides virtual void state_import(const device_state_entry &entry); virtual void state_export(const device_state_entry &entry); virtual void state_string_export(const device_state_entry &entry, std::string &str); // device_disasm_interface overrides virtual UINT32 disasm_min_opcode_bytes() const; virtual UINT32 disasm_max_opcode_bytes() const; virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); // memory helpers DECLARE_DIRECT_UPDATE_MEMBER(direct_handler); UINT32 ROPCODE(offs_t pc); UINT32 RMEM(offs_t addr); void WMEM(offs_t addr, UINT32 data); // misc helpers void check_irqs(); void execute_one(); void update_special(int dreg); bool condition(int which); // floating point helpers void double_to_dsp_with_flags(double val, tmsreg &result); void int2float(tmsreg &srcdst); void float2int(tmsreg &srcdst, bool setflags); void negf(tmsreg &dst, tmsreg &src); void addf(tmsreg &dst, tmsreg &src1, tmsreg &src2); void subf(tmsreg &dst, tmsreg &src1, tmsreg &src2); void mpyf(tmsreg &dst, tmsreg &src1, tmsreg &src2); void norm(tmsreg &dst, tmsreg &src); // memory addressing UINT32 mod00_d(UINT32 op, UINT8 ar); UINT32 mod01_d(UINT32 op, UINT8 ar); UINT32 mod02_d(UINT32 op, UINT8 ar); UINT32 mod03_d(UINT32 op, UINT8 ar); UINT32 mod04_d(UINT32 op, UINT8 ar); UINT32 mod05_d(UINT32 op, UINT8 ar); UINT32 mod06_d(UINT32 op, UINT8 ar); UINT32 mod07_d(UINT32 op, UINT8 ar); UINT32 mod00_1(UINT32 op, UINT8 ar); UINT32 mod01_1(UINT32 op, UINT8 ar); UINT32 mod02_1(UINT32 op, UINT8 ar); UINT32 mod03_1(UINT32 op, UINT8 ar); UINT32 mod04_1(UINT32 op, UINT8 ar); UINT32 mod05_1(UINT32 op, UINT8 ar); UINT32 mod06_1(UINT32 op, UINT8 ar); UINT32 mod07_1(UINT32 op, UINT8 ar); UINT32 mod08(UINT32 op, UINT8 ar); UINT32 mod09(UINT32 op, UINT8 ar); UINT32 mod0a(UINT32 op, UINT8 ar); UINT32 mod0b(UINT32 op, UINT8 ar); UINT32 mod0c(UINT32 op, UINT8 ar); UINT32 mod0d(UINT32 op, UINT8 ar); UINT32 mod0e(UINT32 op, UINT8 ar); UINT32 mod0f(UINT32 op, UINT8 ar); UINT32 mod10(UINT32 op, UINT8 ar); UINT32 mod11(UINT32 op, UINT8 ar); UINT32 mod12(UINT32 op, UINT8 ar); UINT32 mod13(UINT32 op, UINT8 ar); UINT32 mod14(UINT32 op, UINT8 ar); UINT32 mod15(UINT32 op, UINT8 ar); UINT32 mod16(UINT32 op, UINT8 ar); UINT32 mod17(UINT32 op, UINT8 ar); UINT32 mod18(UINT32 op, UINT8 ar); UINT32 mod19(UINT32 op, UINT8 ar); UINT32 modillegal(UINT32 op, UINT8 ar); UINT32 mod00_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod01_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod02_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod03_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod04_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod05_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod06_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod07_1_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod08_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod09_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod0a_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod0b_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod0c_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod0d_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod0e_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod0f_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod10_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod11_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod12_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod13_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod14_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod15_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod16_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod17_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod18_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 mod19_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); UINT32 modillegal_def(UINT32 op, UINT8 ar, UINT32 *&defptrptr); // instructions void illegal(UINT32 op); void unimplemented(UINT32 op); void absf_reg(UINT32 op); void absf_dir(UINT32 op); void absf_ind(UINT32 op); void absf_imm(UINT32 op); void absi_reg(UINT32 op); void absi_dir(UINT32 op); void absi_ind(UINT32 op); void absi_imm(UINT32 op); void addc_reg(UINT32 op); void addc_dir(UINT32 op); void addc_ind(UINT32 op); void addc_imm(UINT32 op); void addf_reg(UINT32 op); void addf_dir(UINT32 op); void addf_ind(UINT32 op); void addf_imm(UINT32 op); void addi_reg(UINT32 op); void addi_dir(UINT32 op); void addi_ind(UINT32 op); void addi_imm(UINT32 op); void and_reg(UINT32 op); void and_dir(UINT32 op); void and_ind(UINT32 op); void and_imm(UINT32 op); void andn_reg(UINT32 op); void andn_dir(UINT32 op); void andn_ind(UINT32 op); void andn_imm(UINT32 op); void ash_reg(UINT32 op); void ash_dir(UINT32 op); void ash_ind(UINT32 op); void ash_imm(UINT32 op); void cmpf_reg(UINT32 op); void cmpf_dir(UINT32 op); void cmpf_ind(UINT32 op); void cmpf_imm(UINT32 op); void cmpi_reg(UINT32 op); void cmpi_dir(UINT32 op); void cmpi_ind(UINT32 op); void cmpi_imm(UINT32 op); void fix_reg(UINT32 op); void fix_dir(UINT32 op); void fix_ind(UINT32 op); void fix_imm(UINT32 op); void float_reg(UINT32 op); void float_dir(UINT32 op); void float_ind(UINT32 op); void float_imm(UINT32 op); void idle(UINT32 op); void lde_reg(UINT32 op); void lde_dir(UINT32 op); void lde_ind(UINT32 op); void lde_imm(UINT32 op); void ldf_reg(UINT32 op); void ldf_dir(UINT32 op); void ldf_ind(UINT32 op); void ldf_imm(UINT32 op); void ldfi_dir(UINT32 op); void ldfi_ind(UINT32 op); void ldi_reg(UINT32 op); void ldi_dir(UINT32 op); void ldi_ind(UINT32 op); void ldi_imm(UINT32 op); void ldii_dir(UINT32 op); void ldii_ind(UINT32 op); void ldm_reg(UINT32 op); void ldm_dir(UINT32 op); void ldm_ind(UINT32 op); void ldm_imm(UINT32 op); void lsh_reg(UINT32 op); void lsh_dir(UINT32 op); void lsh_ind(UINT32 op); void lsh_imm(UINT32 op); void mpyf_reg(UINT32 op); void mpyf_dir(UINT32 op); void mpyf_ind(UINT32 op); void mpyf_imm(UINT32 op); void mpyi_reg(UINT32 op); void mpyi_dir(UINT32 op); void mpyi_ind(UINT32 op); void mpyi_imm(UINT32 op); void negb_reg(UINT32 op); void negb_dir(UINT32 op); void negb_ind(UINT32 op); void negb_imm(UINT32 op); void negf_reg(UINT32 op); void negf_dir(UINT32 op); void negf_ind(UINT32 op); void negf_imm(UINT32 op); void negi_reg(UINT32 op); void negi_dir(UINT32 op); void negi_ind(UINT32 op); void negi_imm(UINT32 op); void nop_reg(UINT32 op); void nop_ind(UINT32 op); void norm_reg(UINT32 op); void norm_dir(UINT32 op); void norm_ind(UINT32 op); void norm_imm(UINT32 op); void not_reg(UINT32 op); void not_dir(UINT32 op); void not_ind(UINT32 op); void not_imm(UINT32 op); void pop(UINT32 op); void popf(UINT32 op); void push(UINT32 op); void pushf(UINT32 op); void or_reg(UINT32 op); void or_dir(UINT32 op); void or_ind(UINT32 op); void or_imm(UINT32 op); void maxspeed(UINT32 op); void rnd_reg(UINT32 op); void rnd_dir(UINT32 op); void rnd_ind(UINT32 op); void rnd_imm(UINT32 op); void rol(UINT32 op); void rolc(UINT32 op); void ror(UINT32 op); void rorc(UINT32 op); void rtps_reg(UINT32 op); void rtps_dir(UINT32 op); void rtps_ind(UINT32 op); void rtps_imm(UINT32 op); void stf_dir(UINT32 op); void stf_ind(UINT32 op); void stfi_dir(UINT32 op); void stfi_ind(UINT32 op); void sti_dir(UINT32 op); void sti_ind(UINT32 op); void stii_dir(UINT32 op); void stii_ind(UINT32 op); void sigi(UINT32 op); void subb_reg(UINT32 op); void subb_dir(UINT32 op); void subb_ind(UINT32 op); void subb_imm(UINT32 op); void subc_reg(UINT32 op); void subc_dir(UINT32 op); void subc_ind(UINT32 op); void subc_imm(UINT32 op); void subf_reg(UINT32 op); void subf_dir(UINT32 op); void subf_ind(UINT32 op); void subf_imm(UINT32 op); void subi_reg(UINT32 op); void subi_dir(UINT32 op); void subi_ind(UINT32 op); void subi_imm(UINT32 op); void subrb_reg(UINT32 op); void subrb_dir(UINT32 op); void subrb_ind(UINT32 op); void subrb_imm(UINT32 op); void subrf_reg(UINT32 op); void subrf_dir(UINT32 op); void subrf_ind(UINT32 op); void subrf_imm(UINT32 op); void subri_reg(UINT32 op); void subri_dir(UINT32 op); void subri_ind(UINT32 op); void subri_imm(UINT32 op); void tstb_reg(UINT32 op); void tstb_dir(UINT32 op); void tstb_ind(UINT32 op); void tstb_imm(UINT32 op); void xor_reg(UINT32 op); void xor_dir(UINT32 op); void xor_ind(UINT32 op); void xor_imm(UINT32 op); void iack_dir(UINT32 op); void iack_ind(UINT32 op); void addc3_regreg(UINT32 op); void addc3_indreg(UINT32 op); void addc3_regind(UINT32 op); void addc3_indind(UINT32 op); void addf3_regreg(UINT32 op); void addf3_indreg(UINT32 op); void addf3_regind(UINT32 op); void addf3_indind(UINT32 op); void addi3_regreg(UINT32 op); void addi3_indreg(UINT32 op); void addi3_regind(UINT32 op); void addi3_indind(UINT32 op); void and3_regreg(UINT32 op); void and3_indreg(UINT32 op); void and3_regind(UINT32 op); void and3_indind(UINT32 op); void andn3_regreg(UINT32 op); void andn3_indreg(UINT32 op); void andn3_regind(UINT32 op); void andn3_indind(UINT32 op); void ash3_regreg(UINT32 op); void ash3_indreg(UINT32 op); void ash3_regind(UINT32 op); void ash3_indind(UINT32 op); void cmpf3_regreg(UINT32 op); void cmpf3_indreg(UINT32 op); void cmpf3_regind(UINT32 op); void cmpf3_indind(UINT32 op); void cmpi3_regreg(UINT32 op); void cmpi3_indreg(UINT32 op); void cmpi3_regind(UINT32 op); void cmpi3_indind(UINT32 op); void lsh3_regreg(UINT32 op); void lsh3_indreg(UINT32 op); void lsh3_regind(UINT32 op); void lsh3_indind(UINT32 op); void mpyf3_regreg(UINT32 op); void mpyf3_indreg(UINT32 op); void mpyf3_regind(UINT32 op); void mpyf3_indind(UINT32 op); void mpyi3_regreg(UINT32 op); void mpyi3_indreg(UINT32 op); void mpyi3_regind(UINT32 op); void mpyi3_indind(UINT32 op); void or3_regreg(UINT32 op); void or3_indreg(UINT32 op); void or3_regind(UINT32 op); void or3_indind(UINT32 op); void subb3_regreg(UINT32 op); void subb3_indreg(UINT32 op); void subb3_regind(UINT32 op); void subb3_indind(UINT32 op); void subf3_regreg(UINT32 op); void subf3_indreg(UINT32 op); void subf3_regind(UINT32 op); void subf3_indind(UINT32 op); void subi3_regreg(UINT32 op); void subi3_indreg(UINT32 op); void subi3_regind(UINT32 op); void subi3_indind(UINT32 op); void tstb3_regreg(UINT32 op); void tstb3_indreg(UINT32 op); void tstb3_regind(UINT32 op); void tstb3_indind(UINT32 op); void xor3_regreg(UINT32 op); void xor3_indreg(UINT32 op); void xor3_regind(UINT32 op); void xor3_indind(UINT32 op); void ldfu_reg(UINT32 op); void ldfu_dir(UINT32 op); void ldfu_ind(UINT32 op); void ldfu_imm(UINT32 op); void ldflo_reg(UINT32 op); void ldflo_dir(UINT32 op); void ldflo_ind(UINT32 op); void ldflo_imm(UINT32 op); void ldfls_reg(UINT32 op); void ldfls_dir(UINT32 op); void ldfls_ind(UINT32 op); void ldfls_imm(UINT32 op); void ldfhi_reg(UINT32 op); void ldfhi_dir(UINT32 op); void ldfhi_ind(UINT32 op); void ldfhi_imm(UINT32 op); void ldfhs_reg(UINT32 op); void ldfhs_dir(UINT32 op); void ldfhs_ind(UINT32 op); void ldfhs_imm(UINT32 op); void ldfeq_reg(UINT32 op); void ldfeq_dir(UINT32 op); void ldfeq_ind(UINT32 op); void ldfeq_imm(UINT32 op); void ldfne_reg(UINT32 op); void ldfne_dir(UINT32 op); void ldfne_ind(UINT32 op); void ldfne_imm(UINT32 op); void ldflt_reg(UINT32 op); void ldflt_dir(UINT32 op); void ldflt_ind(UINT32 op); void ldflt_imm(UINT32 op); void ldfle_reg(UINT32 op); void ldfle_dir(UINT32 op); void ldfle_ind(UINT32 op); void ldfle_imm(UINT32 op); void ldfgt_reg(UINT32 op); void ldfgt_dir(UINT32 op); void ldfgt_ind(UINT32 op); void ldfgt_imm(UINT32 op); void ldfge_reg(UINT32 op); void ldfge_dir(UINT32 op); void ldfge_ind(UINT32 op); void ldfge_imm(UINT32 op); void ldfnv_reg(UINT32 op); void ldfnv_dir(UINT32 op); void ldfnv_ind(UINT32 op); void ldfnv_imm(UINT32 op); void ldfv_reg(UINT32 op); void ldfv_dir(UINT32 op); void ldfv_ind(UINT32 op); void ldfv_imm(UINT32 op); void ldfnuf_reg(UINT32 op); void ldfnuf_dir(UINT32 op); void ldfnuf_ind(UINT32 op); void ldfnuf_imm(UINT32 op); void ldfuf_reg(UINT32 op); void ldfuf_dir(UINT32 op); void ldfuf_ind(UINT32 op); void ldfuf_imm(UINT32 op); void ldfnlv_reg(UINT32 op); void ldfnlv_dir(UINT32 op); void ldfnlv_ind(UINT32 op); void ldfnlv_imm(UINT32 op); void ldflv_reg(UINT32 op); void ldflv_dir(UINT32 op); void ldflv_ind(UINT32 op); void ldflv_imm(UINT32 op); void ldfnluf_reg(UINT32 op); void ldfnluf_dir(UINT32 op); void ldfnluf_ind(UINT32 op); void ldfnluf_imm(UINT32 op); void ldfluf_reg(UINT32 op); void ldfluf_dir(UINT32 op); void ldfluf_ind(UINT32 op); void ldfluf_imm(UINT32 op); void ldfzuf_reg(UINT32 op); void ldfzuf_dir(UINT32 op); void ldfzuf_ind(UINT32 op); void ldfzuf_imm(UINT32 op); void ldiu_reg(UINT32 op); void ldiu_dir(UINT32 op); void ldiu_ind(UINT32 op); void ldiu_imm(UINT32 op); void ldilo_reg(UINT32 op); void ldilo_dir(UINT32 op); void ldilo_ind(UINT32 op); void ldilo_imm(UINT32 op); void ldils_reg(UINT32 op); void ldils_dir(UINT32 op); void ldils_ind(UINT32 op); void ldils_imm(UINT32 op); void ldihi_reg(UINT32 op); void ldihi_dir(UINT32 op); void ldihi_ind(UINT32 op); void ldihi_imm(UINT32 op); void ldihs_reg(UINT32 op); void ldihs_dir(UINT32 op); void ldihs_ind(UINT32 op); void ldihs_imm(UINT32 op); void ldieq_reg(UINT32 op); void ldieq_dir(UINT32 op); void ldieq_ind(UINT32 op); void ldieq_imm(UINT32 op); void ldine_reg(UINT32 op); void ldine_dir(UINT32 op); void ldine_ind(UINT32 op); void ldine_imm(UINT32 op); void ldilt_reg(UINT32 op); void ldilt_dir(UINT32 op); void ldilt_ind(UINT32 op); void ldilt_imm(UINT32 op); void ldile_reg(UINT32 op); void ldile_dir(UINT32 op); void ldile_ind(UINT32 op); void ldile_imm(UINT32 op); void ldigt_reg(UINT32 op); void ldigt_dir(UINT32 op); void ldigt_ind(UINT32 op); void ldigt_imm(UINT32 op); void ldige_reg(UINT32 op); void ldige_dir(UINT32 op); void ldige_ind(UINT32 op); void ldige_imm(UINT32 op); void ldinv_reg(UINT32 op); void ldinv_dir(UINT32 op); void ldinv_ind(UINT32 op); void ldinv_imm(UINT32 op); void ldiuf_reg(UINT32 op); void ldiuf_dir(UINT32 op); void ldiuf_ind(UINT32 op); void ldiuf_imm(UINT32 op); void ldinuf_reg(UINT32 op); void ldinuf_dir(UINT32 op); void ldinuf_ind(UINT32 op); void ldinuf_imm(UINT32 op); void ldiv_reg(UINT32 op); void ldiv_dir(UINT32 op); void ldiv_ind(UINT32 op); void ldiv_imm(UINT32 op); void ldinlv_reg(UINT32 op); void ldinlv_dir(UINT32 op); void ldinlv_ind(UINT32 op); void ldinlv_imm(UINT32 op); void ldilv_reg(UINT32 op); void ldilv_dir(UINT32 op); void ldilv_ind(UINT32 op); void ldilv_imm(UINT32 op); void ldinluf_reg(UINT32 op); void ldinluf_dir(UINT32 op); void ldinluf_ind(UINT32 op); void ldinluf_imm(UINT32 op); void ldiluf_reg(UINT32 op); void ldiluf_dir(UINT32 op); void ldiluf_ind(UINT32 op); void ldiluf_imm(UINT32 op); void ldizuf_reg(UINT32 op); void ldizuf_dir(UINT32 op); void ldizuf_ind(UINT32 op); void ldizuf_imm(UINT32 op); void execute_delayed(UINT32 newpc); void br_imm(UINT32 op); void brd_imm(UINT32 op); void call_imm(UINT32 op); void rptb_imm(UINT32 op); void swi(UINT32 op); void brc_reg(UINT32 op); void brcd_reg(UINT32 op); void brc_imm(UINT32 op); void brcd_imm(UINT32 op); void dbc_reg(UINT32 op); void dbcd_reg(UINT32 op); void dbc_imm(UINT32 op); void dbcd_imm(UINT32 op); void callc_reg(UINT32 op); void callc_imm(UINT32 op); void trap(int trapnum); void trapc(UINT32 op); void retic_reg(UINT32 op); void retsc_reg(UINT32 op); void mpyaddf_0(UINT32 op); void mpyaddf_1(UINT32 op); void mpyaddf_2(UINT32 op); void mpyaddf_3(UINT32 op); void mpysubf_0(UINT32 op); void mpysubf_1(UINT32 op); void mpysubf_2(UINT32 op); void mpysubf_3(UINT32 op); void mpyaddi_0(UINT32 op); void mpyaddi_1(UINT32 op); void mpyaddi_2(UINT32 op); void mpyaddi_3(UINT32 op); void mpysubi_0(UINT32 op); void mpysubi_1(UINT32 op); void mpysubi_2(UINT32 op); void mpysubi_3(UINT32 op); void stfstf(UINT32 op); void stisti(UINT32 op); void ldfldf(UINT32 op); void ldildi(UINT32 op); void absfstf(UINT32 op); void absisti(UINT32 op); void addf3stf(UINT32 op); void addi3sti(UINT32 op); void and3sti(UINT32 op); void ash3sti(UINT32 op); void fixsti(UINT32 op); void floatstf(UINT32 op); void ldfstf(UINT32 op); void ldisti(UINT32 op); void lsh3sti(UINT32 op); void mpyf3stf(UINT32 op); void mpyi3sti(UINT32 op); void negfstf(UINT32 op); void negisti(UINT32 op); void notsti(UINT32 op); void or3sti(UINT32 op); void subf3stf(UINT32 op); void subi3sti(UINT32 op); void xor3sti(UINT32 op); // configuration const address_space_config m_program_config; UINT32 m_chip_type; union int_double { double d; float f[2]; UINT32 i[2]; }; // core registers UINT32 m_pc; tmsreg m_r[36]; UINT32 m_bkmask; // internal stuff UINT16 m_irq_state; bool m_delayed; bool m_irq_pending; bool m_is_idling; int m_icount; UINT32 m_iotemp; address_space * m_program; direct_read_data * m_direct; UINT32 * m_bootrom; bool m_mcbl_mode; devcb_write8 m_xf0_cb; devcb_write8 m_xf1_cb; devcb_write8 m_iack_cb; // tables static void (tms3203x_device::*const s_tms32031ops[])(UINT32 op); static UINT32 (tms3203x_device::*const s_indirect_d[0x20])(UINT32, UINT8); static UINT32 (tms3203x_device::*const s_indirect_1[0x20])(UINT32, UINT8); static UINT32 (tms3203x_device::*const s_indirect_1_def[0x20])(UINT32, UINT8, UINT32 *&); #if (TMS_3203X_LOG_OPCODE_USAGE) UINT32 m_hits[0x200*4]; #endif }; // ======================> tms32031_device class tms32031_device : public tms3203x_device { public: // construction/destruction tms32031_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; // ======================> tms32032_device class tms32032_device : public tms3203x_device { public: // construction/destruction tms32032_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; // device type definition extern const device_type TMS32031; extern const device_type TMS32032; #endif /* __TMS32031_H__ */