1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
|
/***************************************************************************
420ops.c
National Semiconductor COP420 Emulator.
Copyright Nicola Salmoria and the MAME Team.
Visit http://mamedev.org for licensing and usage restrictions.
***************************************************************************/
#define SC R.SC
#define IL R.IL
#define PUSH(addr) { SC = SB; SB = SA; SA = addr; }
#define POP() { PC = SA; SA = SB; SB = SC; }
#include "410ops.c"
#define IN_IN() (R.IN_mask ? IN(COP400_PORT_IN) : 0)
/* Arithmetic Instructions */
/*
Mnemonic: ADT
Hex Code: 4A
Binary: 0 1 0 0 1 0 1 0
Data Flow: A + 10 -> A
Description: Add Ten to A
*/
INSTRUCTION(adt)
{
A = (A + 10) & 0x0F;
}
/*
Mnemonic: CASC
Hex Code: 10
Binary: 0 0 0 1 0 0 0 0
Data Flow: ~A + RAM(B) + C -> A
Carry -> C
Skip Conditions: Carry
Description: Complement and Add with Carry, Skip on Carry
*/
INSTRUCTION(casc)
{
A = (A ^ 0xF) + RAM_R(B) + C;
if (A > 0xF)
{
C = 1;
skip = 1;
A &= 0xF;
}
else
{
C = 0;
}
}
/* Transfer-of-Control Instructions */
/*
Mnemonic: RET
Hex Code: 48
Binary: 0 1 0 0 1 0 0 0
Data Flow: SC -> SB -> SA -> PC
Description: Return from Subroutine, restore Skip logic
*/
INSTRUCTION(cop420_ret)
{
POP();
skip = R.last_skip;
}
/* Memory Reference Instructions */
/*
Mnemonic: CQMA
Hex Code: 33 2C
Binary: 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0
Data Flow: Q7:4 -> RAM(B)
Q3:0 -> A
Description: Copy Q to RAM, A
*/
INSTRUCTION(cqma)
{
RAM_W(B, Q >> 4);
A = Q & 0xF;
}
/*
Mnemonic: LDD
Operand: r, d
Hex Code: 23 --
Binary: 0 0 1 0 0 0 1 1 0 0 r1 r0 d3 d2 d1 d0
Data Flow: RAM(r,d) -> A
Description: Load A with RAM pointed to directly by r,d
*/
INSTRUCTION(ldd)
{
UINT8 rd = opcode & 0x3f;
A = RAM_R(rd);
}
/* Register Reference Instructions */
/*
Mnemonic: XABR
Hex Code: 12
Binary: 0 0 0 1 0 0 1 0
Data Flow: A <-> Br(0,0 -> A3,A2)
Description: Exchange A with Br
*/
INSTRUCTION(xabr)
{
UINT8 Br = A & 0x03;
UINT8 Bd = B & 0x0f;
A = B >> 4;
B = (Br << 4) + Bd;
}
/* Test Instructions */
/*
Mnemonic: SKT
Hex Code: 41
Binary: 0 1 0 0 0 0 0 1
Skip Conditions: A time-base counter carry has occurred since last test
Description: Skip on Timer
*/
INSTRUCTION(skt)
{
if (R.timerlatch)
{
R.timerlatch = 0;
skip = 1;
}
}
/* Input/Output Instructions */
/*
Mnemonic: ININ
Hex Code: 33 28
Binary:
Data Flow: IN -> A
Description: Input IN Inputs to A
*/
INSTRUCTION(inin)
{
A = IN_IN();
}
/*
Processor: COP402M
Mnemonic: ININ
Hex Code: 33 28
Binary:
Data Flow: IN -> A, A1 = "1"
Description: Input IN Inputs to A
*/
INSTRUCTION(cop402m_inin)
{
A = IN_IN() | 0x02;
}
/*
Mnemonic: INIL
Hex Code: 33 29
Binary:
Data Flow: IL3,CKO,"0",IL0 -> A
Description: Input IL Latches to A
*/
INSTRUCTION(inil)
{
A = (IL & 0x09) | IN_CKO() << 2;
IL = 0;
}
/*
Mnemonic: OGI
Operand: y
Hex Code: 33 5-
Binary: 0 0 1 1 0 0 1 1 0 1 0 1 y3 y2 y1 y0
Data Flow: y -> G
Description: Output to G Ports Immediate
*/
INSTRUCTION(ogi)
{
UINT4 y = opcode & 0x0f;
WRITE_G(y);
}
|