1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
|
// license:BSD-3-Clause
// copyright-holders:Curt Coder
/**********************************************************************
SMC CRT9007 CRT Video Processor and Controller (VPAC) emulation
**********************************************************************
_____ _____
VA2 1 |* \_/ | 40 GND
VA10 2 | | 39 VA9
VA3 3 | | 38 VA1
VA11 4 | | 37 VA8
VA12 5 | | 36 VA0
VA4 6 | | 35 CBLANK
VA13 7 | | 34 CURS
VA5 8 | | 33 ACK/_TSC
VA6 9 | | 32 _CSYNC/LPSTB
VA7 10 | CRT9007 | 31 SLD/SL0
VLT 11 | | 30 _SLG/SL1
_VS 12 | | 29 WBEN/SL2/_CSYNC
_HS 13 | | 28 DMAR/SL3/VBLANK
_CCLK 14 | | 27 INT
_DRB 15 | | 26 _RST
VD7 16 | | 25 _CS
VD6 17 | | 24 VD0
VD5 18 | | 23 VD1
VD4 19 | | 22 VD2
VD3 20 |_____________| 21 +5V
**********************************************************************/
#ifndef MAME_VIDEO_CRT9007_H
#define MAME_VIDEO_CRT9007_H
#pragma once
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
//**************************************************************************
#define MCFG_CRT9007_CHARACTER_WIDTH(_value) \
downcast<crt9007_device &>(*device).config_set_character_width(_value);
#define MCFG_CRT9007_INT_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_int_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_DMAR_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_dmar_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_VS_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_vs_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_HS_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_hs_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_VLT_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_vlt_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_CURS_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_curs_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_DRB_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_drb_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_WBEN_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_wben_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_CBLANK_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_cblank_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_SLG_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_slg_wr_callback(DEVCB_##_write);
#define MCFG_CRT9007_SLD_CALLBACK(_write) \
devcb = &downcast<crt9007_device &>(*device).set_sld_wr_callback(DEVCB_##_write);
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
// ======================> crt9007_device
class crt9007_device : public device_t,
public device_memory_interface,
public device_video_interface
{
public:
// construction/destruction
crt9007_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void config_set_character_width(int value) { m_hpixels_per_column = value; }
template <class Object> devcb_base &set_int_wr_callback(Object &&cb) { return m_write_int.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_dmar_wr_callback(Object &&cb) { return m_write_dmar.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_vs_wr_callback(Object &&cb) { return m_write_vs.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_hs_wr_callback(Object &&cb) { return m_write_hs.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_vlt_wr_callback(Object &&cb) { return m_write_vlt.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_curs_wr_callback(Object &&cb) { return m_write_curs.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_drb_wr_callback(Object &&cb) { return m_write_drb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_wben_wr_callback(Object &&cb) { return m_write_wben.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_cblank_wr_callback(Object &&cb) { return m_write_cblank.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_slg_wr_callback(Object &&cb) { return m_write_slg.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_sld_wr_callback(Object &&cb) { return m_write_sld.set_callback(std::forward<Object>(cb)); }
DECLARE_READ8_MEMBER( read );
DECLARE_WRITE8_MEMBER( write );
void set_character_width(int value);
DECLARE_WRITE_LINE_MEMBER( ack_w );
DECLARE_WRITE_LINE_MEMBER( lpstb_w );
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_clock_changed() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
// device_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
private:
enum
{
TIMER_HSYNC,
TIMER_VSYNC,
TIMER_VLT,
TIMER_CURS,
TIMER_DRB,
TIMER_DMA
};
void crt9007(address_map &map);
inline uint8_t readbyte(offs_t address);
inline void trigger_interrupt(int line);
inline void update_cblank_line();
inline void update_hsync_timer(int state);
inline void update_vsync_timer(int state);
inline void update_vlt_timer(int state);
inline void update_curs_timer(int state);
inline void update_drb_timer(int state);
inline void update_dma_timer();
inline void recompute_parameters();
// address space configurations
const address_space_config m_space_config;
devcb_write_line m_write_int;
devcb_write_line m_write_dmar;
devcb_write_line m_write_hs;
devcb_write_line m_write_vs;
devcb_write_line m_write_vlt;
devcb_write_line m_write_curs;
devcb_write_line m_write_drb;
devcb_write_line m_write_wben;
devcb_write_line m_write_cblank;
devcb_write_line m_write_slg;
devcb_write_line m_write_sld;
// registers
uint8_t m_reg[0x3d];
uint8_t m_status;
int m_disp;
int m_hpixels_per_column;
// runtime variables, do not state save
int m_vsync_start;
int m_vsync_end;
int m_hsync_start;
int m_hsync_end;
int m_vlt_start;
int m_vlt_end;
int m_vlt_bottom;
int m_drb_bottom;
int m_hs;
int m_vs;
int m_cblank;
int m_vlt;
int m_drb;
//int m_wben;
//int m_slg;
//int m_sld;
int m_lpstb;
// DMA
int m_dmar;
int m_ack;
int m_dma_count;
int m_dma_burst;
int m_dma_delay;
// timers
emu_timer *m_vsync_timer;
emu_timer *m_hsync_timer;
emu_timer *m_vlt_timer;
emu_timer *m_curs_timer;
emu_timer *m_drb_timer;
emu_timer *m_dma_timer;
};
// device type definition
DECLARE_DEVICE_TYPE(CRT9007, crt9007_device)
#endif // MAME_VIDEO_CRT9007_H
|