1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
|
// license:BSD-3-Clause
// copyright-holders:Patrick Mackinlay
/*
* This device emulates the Sun-1 memory management unit.
*
* Sources:
* - Sun-1 System Reference Manual, Draft Version 1.0, July 27, 1982, Sun Microsystems, Inc.
* - Sun 68000 Board User's Manual, Revision B, February 1983, Sun Microsystems Inc.
*
* TODO:
* - everything
*/
#include "emu.h"
#include "sun1_mmu.h"
//#define VERBOSE (LOG_GENERAL)
#include "logmacro.h"
enum segment_mask : u16
{
SEGMENT_PPTR = 0x003f,
SEGMENT_PROT = 0x0f00,
SEGMENT_CTXT = 0xf000,
};
enum page_mask : u16
{
PAGE_ADDR = 0x0fff,
PAGE_TYPE = 0x3000, // 0=on-board memory, 1=nonexistent, 2=multibus memory, 3=multibus i/o
PAGE_MOD = 0x4000,
PAGE_ACC = 0x8000,
};
enum mode_mask : unsigned
{
P_R = 0x04, // read
P_W = 0x02, // write
P_X = 0x01, // execute
P_RX = P_R | P_X,
P_RW = P_R | P_W,
P_RWX = P_R | P_W | P_X,
};
DEFINE_DEVICE_TYPE(SUN1_MMU, sun1_mmu_device, "sun1_mmu", "Sun-1 MMU")
sun1_mmu_device::sun1_mmu_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
: device_t(mconfig, SUN1_MMU, tag, owner, clock)
, m_space{
{*this, finder_base::DUMMY_TAG, 0},
{*this, finder_base::DUMMY_TAG, 1},
{*this, finder_base::DUMMY_TAG, 2},
{*this, finder_base::DUMMY_TAG, 3},
}
, m_error(*this)
, m_context(0)
, m_segment{}
, m_page{}
, m_super(true)
{
}
void sun1_mmu_device::device_start()
{
save_item(NAME(m_context));
save_item(NAME(m_segment));
save_item(NAME(m_page));
save_item(NAME(m_stall));
save_item(NAME(m_super));
m_space[0]->specific(m_cpu_mem);
m_space[1]->specific(m_cpu_spc);
m_space[2]->specific(m_bus_mem);
m_space[3]->specific(m_bus_pio);
}
void sun1_mmu_device::device_reset()
{
m_stall = false;
}
static bool access(bool const super, unsigned const code, unsigned const mode)
{
static constexpr unsigned protection[2][16] =
{
// user mode
{
0 , 0 , 0 , 0 , 0 , 0 , P_R , P_R ,
P_RW , P_RW , P_RX , P_RWX, P_RX , P_RX , P_X , P_RWX,
},
// supervisor mode
{
0 , P_X , P_R , P_RX , P_RW , P_RWX, P_R , P_RW ,
P_R , P_RW , P_RW , P_RW , P_RX , P_RWX, P_RWX, P_RWX,
},
};
return protection[super][code] & mode;
}
void sun1_mmu_device::context_w(u16 data)
{
LOG("context 0x%04x (%s)\n", data, machine().describe_context());
m_context = data & 0xf000U;
}
u16 sun1_mmu_device::segment_r(offs_t offset)
{
return m_context | m_segment[m_context >> 12][BIT(offset, 14, 6)];
}
void sun1_mmu_device::segment_w(offs_t offset, u16 data, u16 mem_mask)
{
LOG("segment[0x%x][0x%02x] 0x%04x (%s)\n", m_context >> 12, BIT(offset, 14, 6), data, machine().describe_context());
m_segment[m_context >> 12][BIT(offset, 14, 6)] = data & 0x0fffU;
}
u16 sun1_mmu_device::page_r(offs_t offset)
{
u16 const segment = m_segment[m_context >> 12][BIT(offset, 14, 6)];
return m_page[(segment & SEGMENT_PPTR) << 4 | BIT(offset, 10, 4)];
}
void sun1_mmu_device::page_w(offs_t offset, u16 data, u16 mem_mask)
{
u16 const segment = m_segment[m_context >> 12][BIT(offset, 14, 6)];
LOG("page[0x%03x] 0x%04x (%s)\n", (segment & SEGMENT_PPTR) << 4 | BIT(offset, 10, 4), data, machine().describe_context());
m_page[(segment & SEGMENT_PPTR) << 4 | BIT(offset, 10, 4)] = data;
}
std::optional<std::pair<unsigned, offs_t>> sun1_mmu_device::translate(offs_t const logical, unsigned const mode)
{
// check for mapped address
if (logical < 0x20'0000)
{
u16 const segment = m_segment[m_context >> 12][BIT(logical, 15, 6)];
// check segment map error
if (access(m_super, BIT(segment, 8, 4), mode) || machine().side_effects_disabled())
{
u16 &page = m_page[(segment & SEGMENT_PPTR) << 4 | BIT(logical, 11, 4)];
// update reference and modify bits
if (!machine().side_effects_disabled())
{
if (mode & P_W)
page |= PAGE_ACC | PAGE_MOD;
else
page |= PAGE_ACC;
}
return std::pair<unsigned, offs_t>(BIT(page, 12, 2), (page & PAGE_ADDR) << 11 | BIT(logical, 0, 11));
}
else
LOG("segment map error 0x%08x context %d segment 0x%04x mode %c (%s)\n",
logical, m_context, segment, (mode == P_R) ? 'R' : (mode == P_W) ? 'W' : 'X', machine().describe_context());
}
else if (m_super || machine().side_effects_disabled())
// unmapped supervisor access
return std::pair<unsigned, offs_t>(0, logical);
else
LOG("system space error 0x%08x (%s)\n", logical, machine().describe_context());
// protection error
return std::nullopt;
}
template <bool Execute> u16 sun1_mmu_device::mmu_read(offs_t logical, u16 mem_mask)
{
u16 data = 0;
if (m_stall)
{
m_error(MMU_DEFER);
return data;
}
auto const t = translate(logical, Execute ? P_X : P_R);
if (t.has_value())
{
auto const [type, physical] = t.value();
u16 flags = 0;
switch (type)
{
case 0:
// on-board memory
data = m_cpu_mem.read_word(physical, mem_mask);
break;
case 1:
// nonexistent
LOG("nonexistent_r 0x%08x translated 0x%08x (%s)\n", logical, physical, machine().describe_context());
m_error(MMU_ERROR);
break;
case 2:
// multibus memory
std::tie(data, flags) = m_bus_mem.read_word_flags(physical, mem_mask);
if (flags)
{
LOG("multibus_r mem 0x%08x translated 0x%08x (%s)\n", logical, physical, machine().describe_context());
m_stall = true;
m_error(MMU_DEFER);
}
break;
case 3:
// mutibus i/o
std::tie(data, flags) = m_bus_pio.read_word_flags(physical, mem_mask);
if (flags)
{
LOG("multibus_r i/o 0x%08x translated 0x%08x (%s)\n", logical, physical, machine().describe_context());
m_stall = true;
m_error(MMU_DEFER);
}
break;
}
}
else
m_error(MMU_ERROR);
return data;
}
void sun1_mmu_device::mmu_write(offs_t logical, u16 data, u16 mem_mask)
{
if (m_stall)
{
m_error(MMU_DEFER);
return;
}
auto const t = translate(logical, P_W);
if (t.has_value())
{
auto const [type, physical] = t.value();
switch (type)
{
case 0:
// on-board memory
m_cpu_mem.write_word(physical, data, mem_mask);
break;
case 1:
// nonexistent
LOG("nonexistent write 0x%08x translated 0x%08x (%s)\n", logical, physical, machine().describe_context());
m_error(MMU_ERROR);
break;
case 2:
// multibus memory
if (m_bus_mem.write_word_flags(physical, data, mem_mask))
{
LOG("multibus_w mem 0x%08x translated 0x%08x (%s)\n", logical, physical, machine().describe_context());
m_stall = true;
m_error(MMU_DEFER);
}
break;
case 3:
// mutibus i/o
if (m_bus_pio.write_word_flags(physical, data, mem_mask))
{
LOG("multibus_w i/o 0x%08x translated 0x%08x (%s)\n", logical, physical, machine().describe_context());
m_stall = true;
m_error(MMU_DEFER);
}
break;
}
}
else
m_error(MMU_ERROR);
}
u16 sun1_mmu_device::read_program(offs_t logical, u16 mem_mask)
{
return mmu_read<true>(logical, mem_mask);
}
void sun1_mmu_device::write_program(offs_t logical, u16 data, u16 mem_mask)
{
mmu_write(logical, data, mem_mask);
}
u16 sun1_mmu_device::read_data(offs_t logical, u16 mem_mask)
{
return mmu_read<false>(logical, mem_mask);
}
void sun1_mmu_device::write_data(offs_t logical, u16 data, u16 mem_mask)
{
mmu_write(logical, data, mem_mask);
}
u16 sun1_mmu_device::read_cpu(offs_t logical, u16 mem_mask)
{
return m_cpu_spc.read_word(logical, mem_mask);
}
void sun1_mmu_device::set_super(bool super)
{
m_super = super;
}
|