summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/machine/dimm_spd.cpp
blob: b6736e71ade31d3ad3f201081e2be31328129e6e (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
// license:BSD-3-Clause
// copyright-holders:R. Belmont
/*
    DIMM serial presence detect (SPD) readback device
    by R. Belmont

    Each DIMM contains a small EEPROM with information about the capacity and
    timings of the module.  The EEPROM speaks a version of I2C called SMBus.

    This does not attempt to be a generalized I2C/SMBus solution.
*/


#include "emu.h"
#include "dimm_spd.h"

#define LOG_DATAOUT (1U << 1)

#define VERBOSE (0)
#include "logmacro.h"

//**************************************************************************
//  DEVICE DEFINITIONS
//**************************************************************************

DEFINE_DEVICE_TYPE(DIMM_SPD, dimm_spd_device, "dimm_spd", "DIMM Serial Presence Detect")

constexpr int STATE_IDLE = 0;
constexpr int STATE_GET_ADDRESS = 1;
constexpr int STATE_GET_SUBADDRESS = 2;
constexpr int STATE_READ_DATA = 3;
constexpr int STATE_WAIT_ACK = 4;

//**************************************************************************
//  LIVE DEVICE
//**************************************************************************

//-------------------------------------------------
//  dimm_spd_device - constructor
//-------------------------------------------------

dimm_spd_device::dimm_spd_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
	device_t(mconfig, DIMM_SPD, tag, owner, clock),
	write_sda(*this)
{
	m_data_offset = 0;
	m_sda = m_scl = 1;
	m_state = m_state_next = STATE_IDLE;
	m_last_address = 0;
	m_just_acked = false;
}

//-------------------------------------------------
//  device_start - device-specific startup
//-------------------------------------------------

void dimm_spd_device::device_start()
{
	std::fill(std::begin(m_data), std::end(m_data), 0);

	m_data[0] = 128;    // # of bytes in EEPROM
	m_data[1] = 8;      // log2 of EEPROM size
	m_data[2] = 4;      // 4 is SDRAM, 7 is DDR SDRAM, 8 is DDR2, 11 is DDR3, 12 is DDR4
	m_data[3] = 12;     // # of rows
	m_data[4] = 8;      // # of columns
	m_data[5] = 1;      // # of banks (12/8/1 = 32 MiB)
	m_data[6] = 64;     // data bus width low byte
	m_data[7] = 0;      // data bus width high byte
	m_data[11] = 0;     // non-ECC (1=parity, 2=ECC)
	m_data[62] = 0x12;  // SPD version 1.2

	m_latch = m_bit = 0;
	m_state = STATE_IDLE;
	m_sda = m_scl = 1;
	m_last_address = 0;
	m_data_offset = 0;

	save_item(NAME(m_latch));
	save_item(NAME(m_bit));
	save_item(NAME(m_state));
	save_item(NAME(m_state_next));
	save_item(NAME(m_data_offset));
	save_item(NAME(m_just_acked));

	write_sda(1);
}

void dimm_spd_device::set_dimm_size(dimm_size_t size)
{
	m_size = size;

	switch (size)
	{
		case SIZE_4_MIB:
			m_data[3] = 12; // # of rows
			m_data[4] = 5;  // # of columns
			m_data[5] = 1;  // # of banks
			break;

		case SIZE_8_MIB:
			m_data[3] = 12;
			m_data[4] = 6;
			m_data[5] = 1;
			break;

		case SIZE_16_MIB:
			m_data[3] = 12;
			m_data[4] = 7;
			m_data[5] = 1;
			break;

		case SIZE_32_MIB:
			m_data[3] = 12;
			m_data[4] = 8;
			m_data[5] = 1;
			break;

		case SIZE_64_MIB:
			m_data[3] = 12;
			m_data[4] = 9;
			m_data[5] = 1;
			break;

		case SIZE_128_MIB:
			m_data[3] = 12;
			m_data[4] = 10;
			m_data[5] = 1;
			break;

		case SIZE_256_MIB:
			m_data[3] = 12;
			m_data[4] = 10;
			m_data[5] = 2;
			break;

		case SIZE_SLOT_EMPTY:
			break;
	}
}

//-------------------------------------------------
//  device_reset - device-specific reset
//-------------------------------------------------

void dimm_spd_device::device_reset()
{
}

void dimm_spd_device::sda_write(int state)
{
	if (m_size == SIZE_SLOT_EMPTY)
	{
		return;
	}

	if (m_sda != state)
	{
		m_sda = state & 1;

		if (m_scl)
		{
			if (m_sda)
			{
				LOG("%s: stop\n", tag());
				m_state = STATE_IDLE;
				m_last_address = 0;
				m_just_acked = false;
				m_data_offset = 0;
			}
			else
			{
				LOG("%s: start\n", tag());
				m_state = STATE_GET_ADDRESS;
				m_bit = 0;
				m_latch = 0;
				m_just_acked = false;
			}
		}
	}
}

void dimm_spd_device::scl_write(int state)
{
	if (m_size == SIZE_SLOT_EMPTY)
	{
		return;
	}

	if (m_scl != state)
	{
		m_scl = state & 1;

		switch (m_state)
		{
			case STATE_IDLE:
				// just ignore everything until a START
				break;

			case STATE_GET_ADDRESS:
			case STATE_GET_SUBADDRESS:
				if (m_bit < 8)
				{
					if (m_scl)
					{
						m_latch <<= 1;
						m_latch |= m_sda;
						m_bit++;
					}
				}
				else
				{
					if (m_scl)
					{
						m_bit++;
					}
					else
					{
						if (m_bit == 8)
						{
							if (m_state == STATE_GET_ADDRESS)
							{
								LOG("%s: Got address %02x (ours is %02x r/w %d)\n", tag(), m_latch >> 1, m_address, m_latch & 1);
								// check if reading
								if (m_latch & 1)
								{
									if ((m_latch >> 1) == m_address)
									{
										LOG("%s: address matches, ACKing\n", tag());
										write_sda(0);
										m_bit = 0;
										m_latch = 0;
										m_state_next = STATE_READ_DATA;
										m_state = STATE_WAIT_ACK;
									}
									else
									{
										LOG("%s: address doesn't match, ignoring\n", tag());
										m_state = STATE_IDLE;
										write_sda(1);
									}
								}
								else
								{
									LOGMASKED(LOG_DATAOUT, "%s: write: getting subaddress\n", tag());
									m_last_address = m_latch >> 1;
									write_sda(0);
									m_bit = 0;
									m_latch = 0;
									m_state_next = STATE_GET_SUBADDRESS;
									m_state = STATE_WAIT_ACK;
								}
							}
							else if (m_state == STATE_GET_SUBADDRESS)
							{
								LOGMASKED(LOG_DATAOUT, "%s: subaddress is %02x\n", tag(), m_latch);
								m_data_offset = m_latch;
								write_sda(0);
								m_bit = 0;
								m_latch = 0;
								m_state_next = STATE_IDLE;  // is this correct?
								m_state = STATE_WAIT_ACK;
							}
						}
					}
				}
				break;

			case STATE_WAIT_ACK:
				if (!m_scl)
				{
					m_state = m_state_next;
					write_sda(1);
				}
				break;

			case STATE_READ_DATA:
				if (m_bit < 8)
				{
					if (!m_scl)
					{
						m_bit++;
						write_sda(1);
					}
					else
					{
						if (m_bit == 0)
						{
							m_latch = m_data[m_data_offset++];
							m_data_offset &= 0xff;
							LOGMASKED(LOG_DATAOUT, "%s: outputting byte %02x\n", tag(), m_latch);
						}

						write_sda(BIT(m_latch, 7));
						m_latch <<= 1;
					}
				}
				else
				{
					if (m_scl)
					{
						// did the master ACK or NACK?
						if (m_sda)
						{
							LOGMASKED(LOG_DATAOUT, "%s: master NACK\n", tag());
							m_state = STATE_IDLE;
							write_sda(1);
						}
						else
						{
							LOGMASKED(LOG_DATAOUT, "%s: master ACK\n", tag());
							m_just_acked = true;
						}
					}
					else
					{
						write_sda(1);
						if (m_just_acked)
						{
							m_bit = 0;
							m_just_acked = false;
						}
					}
				}
				break;
		}

	}
}