1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
|
// license:BSD-3-Clause
// copyright-holders:hap, Igor
// SM500 shared opcode handlers
#include "emu.h"
#include "sm500.h"
// internal helpers
void sm500_device::shift_w()
{
// shifts internal W' latches
for (int i = 0; i < (m_o_pins-1); i++)
m_ox[i] = m_ox[i + 1];
}
u8 sm500_device::get_digit()
{
// default digit segments PLA
static const u8 lut_digits[0x20] =
{
0xe, 0x0, 0xc, 0x8, 0x2, 0xa, 0xe, 0x2, 0xe, 0xa, 0x0, 0x0, 0x2, 0xa, 0x2, 0x2,
0xb, 0x9, 0x7, 0xf, 0xd, 0xe, 0xe, 0xb, 0xf, 0xf, 0x4, 0x0, 0xd, 0xe, 0x4, 0x0
};
return lut_digits[m_cn << 4 | m_acc] | (~m_cn & m_mx);
}
// instruction set
// RAM address instructions
void sm500_device::op_lb()
{
// LB x: load BM/BL with 4-bit immediate value (partial)
m_bm = m_op & 3;
m_bl = (m_op >> 2 & 3) | ((m_op & 0xc) ? 8 : 0);
}
void sm500_device::op_incb()
{
// INCB: increment BL, but overflow on 3rd bit!
sm510_base_device::op_incb();
m_skip = (m_bl == 8);
}
void sm500_device::op_sbm()
{
// SBM: set RAM address high bit
m_bm |= 4;
}
void sm500_device::op_rbm()
{
// RBM: reset RAM address high bit
m_bm &= ~4;
}
// ROM address instructions
void sm500_device::op_comcb()
{
// COMCB: complement CB
m_cb ^= 1;
}
void sm500_device::op_rtn0()
{
// RTN0(RTN): return from subroutine
sm510_base_device::op_rtn0();
m_rsub = false;
}
void sm500_device::op_ssr()
{
// SSR x: set stack upper bits, also sets E flag for next opcode
set_su(m_op & 0xf);
}
void sm500_device::op_tr()
{
// TR x: jump (long or short)
m_pc = (m_pc & ~0x3f) | (m_op & 0x3f);
if (!m_rsub)
do_branch(m_cb, get_su(), m_pc & 0x3f);
}
void sm500_device::op_trs()
{
// TRS x: call subroutine
if (!m_rsub)
{
m_rsub = true;
u8 su = get_su();
push_stack();
do_branch(get_trs_field(), 0, m_op & 0x3f);
// E flag was set?
if ((m_prev_op & 0xf0) == 0x70)
do_branch(m_cb, su, m_pc & 0x3f);
}
else
m_pc = (m_pc & ~0xff) | (m_op << 2 & 0xc0) | (m_op & 0xf);
}
// Data transfer instructions
void sm500_device::op_atbp()
{
// ATBP: same as SM510, and set CN with ACC3
sm510_base_device::op_atbp();
m_cn = m_acc >> 3 & 1;
}
void sm500_device::op_ptw()
{
// PTW: partial transfer W' to W
m_o[m_o_pins-1] = m_ox[m_o_pins-1];
m_o[m_o_pins-2] = m_ox[m_o_pins-2];
}
void sm500_device::op_tw()
{
// TW: transfer W' to W
for (int i = 0; i < m_o_pins; i++)
m_o[i] = m_ox[i];
}
void sm500_device::op_pdtw()
{
// PDTW: partial shift digit into W'
m_ox[m_o_pins-2] = m_ox[m_o_pins-1];
m_ox[m_o_pins-1] = get_digit();
}
void sm500_device::op_dtw()
{
// DTW: shift digit into W'
shift_w();
m_ox[m_o_pins-1] = get_digit();
}
void sm500_device::op_wr()
{
// WR: shift ACC into W', reset last bit
shift_w();
m_ox[m_o_pins-1] = m_acc & 7;
}
void sm500_device::op_ws()
{
// WR: shift ACC into W', set last bit
shift_w();
m_ox[m_o_pins-1] = m_acc | 8;
}
// I/O instructions
void sm500_device::op_ats()
{
// ATS: transfer ACC to S
m_s = m_acc;
}
void sm500_device::op_exksa()
{
// EXKSA: x
}
void sm500_device::op_exkfa()
{
// EXKFA: x
}
// Divider manipulation instructions
void sm500_device::op_idiv()
{
// IDIV: reset divider low 9 bits
m_div &= 0x3f;
}
// Bit manipulation instructions
void sm500_device::op_rmf()
{
// RMF: reset m' flag, also clears ACC
m_mx = 0;
m_acc = 0;
}
void sm500_device::op_smf()
{
// SMF: set m' flag
m_mx = 1;
}
void sm500_device::op_comcn()
{
// COMCN: complement CN flag
m_cn ^= 1;
}
|