summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/h8/c77.h
blob: 6c23c5b5c59645ea6c9fdd9b6d8348c5008b0b81 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
// license:BSD-3-Clause
// copyright-holders:smf, Olivier Galibert
/***************************************************************************

    Namco C77

    Custom H8 used on Cyberlead cabinet I/O boards

***************************************************************************/

#ifndef MAME_CPU_H8_C77_H
#define MAME_CPU_H8_C77_H

#pragma once

#include "h8.h"
#include "h8_intc.h"
//#include "h8_adc.h"
#include "h8_port.h"
#include "h8_timer8.h"
#include "h8_sci.h"

class namco_c77_device :
	public h8_device
{
public:
	namco_c77_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

	auto read_port1()  { return m_read_port [PORT_1].bind(); }
	auto write_port1() { return m_write_port[PORT_1].bind(); }
	auto read_port2()  { return m_read_port [PORT_2].bind(); }
	auto write_port2() { return m_write_port[PORT_2].bind(); }
	auto read_port3()  { return m_read_port [PORT_3].bind(); }
	auto write_port3() { return m_write_port[PORT_3].bind(); }
	auto read_port4()  { return m_read_port [PORT_4].bind(); }
	auto write_port4() { return m_write_port[PORT_4].bind(); }
	auto read_port5()  { return m_read_port [PORT_5].bind(); }
	auto write_port5() { return m_write_port[PORT_5].bind(); }
	auto read_port6()  { return m_read_port [PORT_6].bind(); }
	auto write_port6() { return m_write_port[PORT_6].bind(); }
	auto read_port7()  { return m_read_port [PORT_7].bind(); }
	auto read_port8()  { return m_read_port [PORT_8].bind(); }
	auto write_port8() { return m_write_port[PORT_8].bind(); }
	auto read_port9()  { return m_read_port [PORT_9].bind(); }
	auto write_port9() { return m_write_port[PORT_9].bind(); }

	uint8_t wscr_r();
	void wscr_w(uint8_t data);
	uint8_t stcr_r();
	void stcr_w(uint8_t data);
	uint8_t syscr_r();
	void syscr_w(uint8_t data);
	uint8_t mdcr_r();
	void mdcr_w(uint8_t data);

protected:
	namco_c77_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t start);

	// device_t
	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
	virtual void device_start() override ATTR_COLD;
	virtual void device_reset() override;

	// device_execute_interface
	virtual void execute_set_input(int inputnum, int state) override;

	// h8_device
	virtual void irq_setup() override;
	virtual void update_irq_filter() override;
	virtual void interrupt_taken() override;
	virtual void internal_update(uint64_t current_time) override;
	virtual void notify_standby(int state) override;

	void map(address_map &map) ATTR_COLD;

	required_device<h8_intc_device> m_intc;
	required_device<h8_port_device> m_port1;
	required_device<h8_port_device> m_port2;
	required_device<h8_port_device> m_port3;
	required_device<h8_port_device> m_port4;
	required_device<h8_port_device> m_port5;
	required_device<h8_port_device> m_port6;
	required_device<h8_port_device> m_port7;
	required_device<h8_port_device> m_port8;
	required_device<h8_port_device> m_port9;
	required_device<h8_timer8_channel_device> m_timer8_0;
	//required_device<h8_timer8_channel_device> m_timer8_1;

	uint8_t m_syscr;
	uint32_t m_ram_start;
};

DECLARE_DEVICE_TYPE(NAMCO_C77, namco_c77_device)

#endif // MAME_CPU_H8_C77_H