1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
// license:BSD-3-Clause
// copyright-holders:Sandro Ronco
/*********************************************************************
Decision Mate V expansion slot
*********************************************************************/
#ifndef MAME_BUS_DMV_DMVBUS_H
#define MAME_BUS_DMV_DMVBUS_H
#pragma once
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
// ======================> device_dmvslot_interface
class device_dmvslot_interface : public device_slot_card_interface
{
public:
// construction/destruction
virtual ~device_dmvslot_interface();
virtual bool read(offs_t offset, uint8_t &data) { return false; }
virtual bool write(offs_t offset, uint8_t data) { return false; }
virtual void io_read(address_space &space, int ifsel, offs_t offset, uint8_t &data) { }
virtual void io_write(address_space &space, int ifsel, offs_t offset, uint8_t data) { }
// slot 1
virtual void ram_read(uint8_t cas, offs_t offset, uint8_t &data) { }
virtual void ram_write(uint8_t cas, offs_t offset, uint8_t data) { }
// slot 7 and 7A
virtual bool av16bit() { return false; }
virtual void hold_w(int state) { }
virtual void switch16_w(int state) { }
virtual void timint_w(int state) { }
virtual void keyint_w(int state) { }
virtual void busint_w(int state) { }
virtual void flexint_w(int state) { }
virtual void irq2_w(int state) { }
virtual void irq2a_w(int state) { }
virtual void irq3_w(int state) { }
virtual void irq4_w(int state) { }
virtual void irq5_w(int state) { }
virtual void irq6_w(int state) { }
protected:
device_dmvslot_interface(const machine_config &mconfig, device_t &device);
};
// ======================> dmvcart_slot_device
class dmvcart_slot_device : public device_t,
public device_slot_interface
{
public:
// construction/destruction
dmvcart_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual ~dmvcart_slot_device();
template <class Object> devcb_base &set_prog_read_callback(Object &&cb) { return m_prog_read_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_prog_write_callback(Object &&cb) { return m_prog_write_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_out_int_callback(Object &&cb) { return m_out_int_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_out_irq_callback(Object &&cb) { return m_out_irq_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_out_thold_callback(Object &&cb) { return m_out_thold_cb.set_callback(std::forward<Object>(cb)); }
// device-level overrides
virtual void device_start() override;
// reading and writing
virtual bool read(offs_t offset, uint8_t &data);
virtual bool write(offs_t offset, uint8_t data);
virtual void ram_read(uint8_t cas, offs_t offset, uint8_t &data);
virtual void ram_write(uint8_t cas, offs_t offset, uint8_t data);
virtual void io_read(address_space &space, int ifsel, offs_t offset, uint8_t &data);
virtual void io_write(address_space &space, int ifsel, offs_t offset, uint8_t data);
virtual void hold_w(int state);
virtual void switch16_w(int state);
virtual void timint_w(int state);
virtual void keyint_w(int state);
virtual void busint_w(int state);
virtual void flexint_w(int state);
virtual void irq2_w(int state);
virtual void irq2a_w(int state);
virtual void irq3_w(int state);
virtual void irq4_w(int state);
virtual void irq5_w(int state);
virtual void irq6_w(int state);
virtual bool av16bit();
// internal state
devcb_read8 m_prog_read_cb;
devcb_write8 m_prog_write_cb;
devcb_write_line m_out_int_cb;
devcb_write_line m_out_irq_cb;
devcb_write_line m_out_thold_cb;
device_dmvslot_interface* m_cart;
};
// device type definition
DECLARE_DEVICE_TYPE(DMVCART_SLOT, dmvcart_slot_device)
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_DMVCART_SLOT_PROGRAM_READWRITE_CB(_read_devcb, _write_devcb) \
downcast<dmvcart_slot_device &>(*device).set_prog_read_callback(DEVCB_##_read_devcb); \
downcast<dmvcart_slot_device &>(*device).set_prog_write_callback(DEVCB_##_write_devcb);
#define MCFG_DMVCART_SLOT_OUT_INT_CB(_devcb) \
downcast<dmvcart_slot_device &>(*device).set_out_int_callback(DEVCB_##_devcb);
#define MCFG_DMVCART_SLOT_OUT_IRQ_CB(_devcb) \
downcast<dmvcart_slot_device &>(*device).set_out_irq_callback(DEVCB_##_devcb);
#define MCFG_DMVCART_SLOT_OUT_THOLD_CB(_devcb) \
downcast<dmvcart_slot_device &>(*device).set_out_thold_callback(DEVCB_##_devcb);
#endif // MAME_BUS_DMV_DMVBUS_H
|