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* cpu/e132xs: Moved interrupt check to the beginning of instruction execution. Vas Crabb2025-03-265-328/+271
| | | | | | | * Fixes interrupts not being serviced while tracing. * Further improves recompiler performance. * Fixes recompiler interrupt check function calling itself recursively. * Also added debugger exception hook calls to interpreter and recompiler.
* machine/i82371sb.cpp: rectify ↵ angelosa2025-03-254-0/+5
| | | | https://github.com/mamedev/mame/commit/377e9d6d7dd2f04427b21387f14dc0e9b30970e3
* -cpu/e132xs: Fixes and optimisations: Vas Crabb2025-03-266-670/+380
| | | | | | | | | | | | | | | | | | | * Fixed XM (index move) instructions failing to update the destination register on range error for interpreter and recompiler. * Fixed double-word stores when the source indicates SR (both stored words are zero) for interpreter and recompiler. * Fixed recompiler failing to set ILC and P on range error and frame error exceptions. * Optimised recompiled code for word size shifts. * Pushed more recompiler logic from run-time to code generation time and simplified delay slot PC check and trace check logic. * Use MOV rather than LOAD where possible in recompiler to improve code generation performance and symbolic memory locatin names in disassembled UML. * Updated TODO list in header comment, reduced copy/paste some more. -cpu/drcbex64.cpp: Avoid some more unnecessary register copies for ROLAND.
* cpu/e132xs: Optimised recompiled FRAME instruction. Vas Crabb2025-03-254-197/+181
| | | | Also added some more constants so there are a few less magic literals.
* i960: Fix disassembly of ADD<cc>, SUB<cc> & SEL<cc> for cc = l, ne, le, o AJR2025-03-241-1/+1
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* cpu/e132xs: Removed leftover block end from a function that no longer ↵ Vas Crabb2025-03-251-2/+0
| | | | generates a standalone block.
* cpu/e132xs, cpu/drcbex64.cpp: More fixes and optimisation: Vas Crabb2025-03-257-406/+397
| | | | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs: Implemented supervisor and trace modes as recompiler modes. This eliminates or simplifies a lot of run-time checks. In particular, the trace checks on every instruction are not generated when not tracing, and simplified to just checking the P bit when tracing. cpu/e132xs: Optimised code generation for RET, avoid a redundant load when checking for an overflow trap, use the exception parameter for exception codes rather than generating one function for each possible code. Also simplified interpreter code for RET. cpu/e132xs: Implemented SUMS for the recompiler. cpu/e132xs: Implemented privilege check for setting L (interrupt lockout) for recompiler. Not implemented for interpreter. cpu/e132xs: Partially fixed tracing. P flag should be set by all instructions except RET. Trace exceptions are not triggered for branches when using the recompiler. cpu/e132xs: Fixed ILC being set incorrectly for RET. cpu/drcbex64.cpp: Avoid unnecessary expensive operations when a shift operation request the zero and/or sign flags but not the carry flag.
* cpu/e132xs: Don't generate code to handle a delayed branch inline. Vas Crabb2025-03-243-85/+49
| | | | | | | * Also avoid an redundant load when checking if trace is active. * Reduces generated native instruction count by about 24% on x86-64 and gives an overall performance improvement of about 3.5% in -bench scores.
* mn10300: Fix disassembly of ADD Dm, Dn AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of even more move instruction modes AJR2025-03-221-1/+1
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* mn10300: Re-add missing LSR and ASR modes AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of yet another move instruction mode AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of another move instruction mode AJR2025-03-221-1/+1
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* mn10300: Fix disassembly of some move instruction modes AJR2025-03-221-5/+5
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* unidasm: Add Panasonic MN10300 disassembler AJR2025-03-222-0/+971
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* srcclean the tree. Vas Crabb2025-03-2310-50/+50
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* cpu/e132xs: Fixed IO2 interrupt check in recompiler. Vas Crabb2025-03-231-33/+33
| | | | | Also further reduced conditional branches and logic operations in interrupt check.
* cpu/e132xs: More recompiler optimisation: Vas Crabb2025-03-233-198/+126
| | | | | | | | * Made interrupt check function generate far more compact code (about 85% reduction in number of native instructions on x86-64). * Optimised out-of-cycles check. * Applied prior optimisation for trap/interrupt checks to static exception checks as well (code is still copy/pasted).
* machine/psion_ssd.cpp: Don't save state of removable media. Nigel Barnes2025-03-211-10/+2
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* machine/psion_asic9.cpp: Improved ASIC9MX RAM configuration to detect 2MB. Nigel Barnes2025-03-212-19/+62
| | | | | | | | | | psion/psion3a.cpp: Improved LCD palette contrast. - Series 3mx now uses ASIC9MX to correctly detect 2MB RAM. psion/siena.cpp: Improved LCD palette contrast. psion/workabout.cpp: Improved LCD palette contrast. - Workabout mx now uses ASIC9MX to correctly detect 2MB RAM.
* Revert "i960: don't preserve sign bit when shifting integer left (#13507)" AJR2025-03-211-1/+1
| | | | | | This reverts commit 5954767b0b4da0c43f7194c7def4c162fbc8ef78. This was merged way too hastily based on incomplete information.
* i960: don't preserve sign bit when shifting integer left (#13507) Matthew Daniels2025-03-211-1/+1
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* cpu/e132xs: More recompiler fixes: Vas Crabb2025-03-224-177/+169
| | | | | | | | | * Cleaned up and commented code for generating an exception, reducing about nine memory accesses to update SR to two. * Implemented NEGS, and fixed ADDS and SUBS not setting excption handler address. * Optimised code to update Z flag on logic operations to avoid branches. * Reduced copy/paste a bit more.
* v60: implement correct rounding mode when converting float to integer (#13506) Matthew Daniels2025-03-211-1/+7
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* z80/z80dasm.cpp: Switched *R (LDIR, OTIR, etc) debugger flag to STEP_OVER ↵ holub2025-03-211-3/+3
| | | | (#13451)
* cpu/e132xs, cpu/drcbex64.cpp: Recompiler fixes and optimisations: Vas Crabb2025-03-214-1500/+753
| | | | | | | | | | | | | | | | | | | | | | | | cpu/e132xs.cpp: Refactored code generation to improve performance and fixed some issues: * Moved a considerable amound of logic from execution time to code generation time. * Fixed some cases where add/subtract carry was being interpreted incorrectly. * Fixed a case where a load double intruction was incorrectly writing the same register twice. * Use UML flags to generate condition codes for addition/subtraction. * Use UML carry flag for carry-/borrow-in. * Reduced UML register pressure (improves performance for hosts with fewer callee-saved CPU registers). * Moved more logic to helper functions to simplify maintenance. cpu/drcbex64.cpp: Fixed upper bits of UML registers being cleared when used as address offset for LOAD/STORE. cpu/drcbex64.cpp: Don't do expensive zero/sign flag update for shift operations if only carry flag will be used. cpu/drcbex64.cpp: Reduced copy/paste in READ[M]/WRITE[M] generators.
* Write the results of an ALU operation before writing to register/memory (#13486) Matthew Daniels2025-03-202-19/+19
| | | | | Sega Rally has an instruction that calculates d += p and loads a value into d at the same time; it is the loaded value that should be used, not the result of the ALU operation Also only test the d register when performing an ALU operation
* fixing cpu for missing opcode (#13502) ffxx682025-03-203-11/+18
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* [heathzenith/h8.cpp] Update interrupt handling to not use ↵ Mark Garlanger2025-03-204-5/+5
| | | | | | | set_input_line_and_vector (#13492) * [heathzenith/h8.cpp] Update interrupt handling to not use set_input_line_and_vector * Fix include guards for moved header file
* mips/mips1: remove embedded syscall logging Patrick Mackinlay2025-03-202-233/+4
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* Some relatively simple recompiler optimisations: Vas Crabb2025-03-203-25/+44
| | | | | | | | | | | | | | | | cpu/drcbex64.cpp: Avoid a lot of unnecessary flag manipulation on shift/rotate operations. Don't calculate flags when not requested. Don't preserve carry in for operations that don't use it as an input. cpu/drcbex64.cpp: Avoid loading CL when ECX can be used. Loading CL doesn't clear the upper bits, so it depends on the previous value of RCX, causing pipeline dependencies. Loading ECX can grab a fresh rename register. cpu/drcbearm64.cpp: Attempt more optimisation on one more load immediate operation. cpu/e132xs: Get rid of a redundant TEST - ROLAND can set the Z flag.
* m16c: Fix disassembly syntax for adjnz/sbjnz AJR2025-03-191-0/+1
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* -More DRC fixes/improvements: Vas Crabb2025-03-207-378/+789
| | | | | | | | | | | | | | | | | | | * cpu/uml.cpp: Handle some more cases where ROLAND can be turned into AND in the simplifier. * cpu/drcbearm.cpp, cpu/drcbex64.cpp: Fixed a number of cases where 4-byte operations wouldn't clear the upper half of the destination (there are plenty more of these caused by the simplifier that will be harder to fix). * cpu/drcbearm64.cpp: Fixed some cases where a conditional MOV could unexpectedly clear the upper bits of the destination. * cpu/drcbex64.cpp: Improved code generation for various arithmetic and logical operations. More AND/OR/XOR/ADD/ADDC operand combinations are optimised. Special cases of ROLAND/ROLINS are optimised. * cpu/drcbex64.cpp: Don't treat operands to FADD/FMUL as commutative. This isn't true when one is a NaN. -cpu/e132xs: Use osd_printf_error for diagnositc output, and make more local variables const.
* tea1002: fix compile hap2025-03-191-1/+1
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* video/tea1002.cpp: fix misspelled amplitude variable angelosa2025-03-192-6/+6
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* bus/nes/disksys.cpp, sound/rp2c33_snd.cpp: Updates (#13496) cam9002025-03-193-12/+20
| | | | | | | | * bus/nes/disksys.cpp: Updates - Fix dead link - Implement readable nametable mirroring status - Fix save state support, Fix initializing function * sound/rp2c33_snd.cpp: Fix dead link
* -cpu/drcbe*.cpp: Print an error message and abort when running off the end ↵ Vas Crabb2025-03-183-22/+140
| | | | | | | | | of a generated code block. -cpu/drcbearm64.cpp: Don't emit code for UML NOP - the simplifier litters the code with these for elided operations. -frontend/mame/clifront.cpp: Added newline at end of -version output.
* v60: improve CVTSW flags and fix issue with float-to-u32 cast hap2025-03-172-5/+3
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* Miscellaneous minor stuff: Vas Crabb2025-03-171-6/+6
| | | | | | | | * scripts/minimaws: Set option strict for JavaScript code. * util/mfpresolve.h: Be explicit about turning nullptr into a pointer to data. * cpu/drcbearm64.cpp: Reduced number of temporary registers used for AND with some operand combinations.
* cpu/drcbearm64.cpp: Optimised conditional operations using carry flag. (#13484) Vas Crabb2025-03-172-207/+468
| | | | | | | | | | | | | | | | | | | | | | | | | | Track the state of the native carry flag to avoid unnecessarily manipulating the native NZCV register. If the native carry flag does not correspond to the UML carry flag, test the bit in the flags register for the C and NC conditions. Use condition select instructions to implement conditional forms of MOV and FMOV when advantageous. Fixed EXIT with C/NC/A/BE condition not working properly if it doesn't immediately follow a CMP or SUB. Extended reach of conditional EXIT to +/-128MiB (was +/-1MiB for conditions other than U/NU). Moved code to set up skipping conditional instructions to a common function. Use TBZ/TBNZ for short backward jumps with U/NU/C/NC conditions to save one instruction and a temporary register. Simplified/optimised ADD[C]/SUB[B] code generation - avoids an unnecessary register copy when one operand is in memory and the other is a small immediate value. Also fixed another unnecessary register copy for SUB[B] when an operand is kept in a host register. Slightly optimised generated code for AND immediate.
* machine/i82371sb.cpp: lift cargo cult 0xe0-0xef noprw angelosa2025-03-154-4/+5
| | | | machine/mediagx_cs5530_bridge, machine/sis85c496.cpp, machine/sis950_lpc.cpp: as above
* pci/virge_pci.cpp: hookup Leadtek WinFast 3D S600DX BIOS alt to virgedx_pci ↵ angelosa2025-03-151-1/+13
| | | | [Devin Acker]
* video/s3virge.cpp: add stub Serial Port implementation, retire ↵ angelosa2025-03-152-43/+41
| | | | s3virgedx_rev1_vga_device
* cpu/drcbearm64.cpp: Minor fixes and optimisations: Vas Crabb2025-03-161-19/+81
| | | | | | | | | | | | | | | | | | | | | Clear V/Z/S bits in flags register after SETFLGS or RESTORE. These flags are kept in the native NZCV register, and SAVE assumes the corresponding bits in the flags register are clear. Don't use an extra temporary register for SETFMOD with operand loaded from memory. It doesn't allow additional parallelism anyway. Slightly optimised generated code for GETFLGS. Avoid a redundant TST when flags are requested for the non-optimised ROLAND case. Also avoid unnecessarily updating flags when not requested. Don't update flags for ADD/ADDC/SUB/SUBB/AND if not requested. Slightly reduces pressure on the NZCV register. Added TODO notes for opportunities to use CSEL/FCSEL rather than conditional branches.
* cpu/drcbearm64.cpp: General cleanup, no functional changes. Vas Crabb2025-03-166-195/+193
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* vax: Minor disassembly refinements AJR2025-03-141-2/+2
| | | | * xtal.cpp: Add value for later use
* cpu/drcbearm64.cpp: Fixed issues with and optimise ADD[C]/SUB[B] code ↵ Vas Crabb2025-03-151-38/+149
| | | | | | generation. (#13476) * Fixed potential crash on generating code for UML ADDC or SUBB with immediate operands (GitHub #13475). * Optimised generated code for various degenerate cases and cases where register loads can be avoided.
* z80scc: reassert interrupt if conditions persist (fixes MT#9141) Patrick Mackinlay2025-03-142-16/+25
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* -cpu/drcbearm64.cpp: More fixes and optimisations: Vas Crabb2025-03-144-66/+80
| | | | | | | | | | | | | | | * Correctly identify valid immediate constants for add/sub/cmp (it was too conservative). * Don't unnecessarily copy UML register values kept in host registers for CMP. * Fixed detection of TST against immediate zero and optimised generated code. * Optimised TST against immediate with all bits set. -cpu/alto2: Follow the same pattern as the other things that have been altered to avoid problematic memsets in this device. -cpu/powerpc: Realigned some comments that had drifted.
* New systems marked not working Ivan Vangelista2025-03-132-1/+12
| | | | | | | | | | | | | | | | ------------------------------ Flower World 3 (V118CN) [little0, XingXing] New clones marked not working ----------------------------- Super Star 97 / Ming Xing 97 Jianan Ban [little0] Tumble Pop (Electronic Devices bootleg) [Hammy] - neogeo/neogeo.cpp: updated documentation [JacKc] - various drivers: identified manufacturers for some bootlegs [Hammy] - devices/cpu/alto2/a2disp.cpp: removed use of memset on non-trivial object