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* mcs96d: Location 0 is just 0 (nw) AJR2020-04-041-2/+2
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* st62xx: Add to unidasm AJR2018-10-261-1/+1
| | | | mcs96d.cpp: Minor spacing fix (nw)
* Improve MCS-96 (i8x9x) disassembly AJR2018-10-251-110/+223
| | | | | | | - Properly decode names of directly addressed SFRs. This involves a major refactoring of the instruction execution/description unit to keep track of operand sizes and write-only destinations (since 8X9X maps numerous write-only SFRs to the same addresses as read-only SFRs). - Correct operand size for immediate modes of ADDCB and SUBCB and indexed mode of MULB. - Correct destination register for execution of the indexed mode of 2-argument ANDB. - Correct assembler syntax of JBC and JBS (the bit specifier follows the register).
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-0/+278
Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.