| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | emumem: A little more speedup. cache and specific change syntax, and are ↵ | 2020-05-25 | 1 | -12/+12 | |
| | | | | | | | | | | | | | | | | | not pointers anymore [O. Galibert] The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer). | ||||
| * | r65c19: Add bank registers to debug state (nw) | 2019-12-16 | 1 | -0/+3 | |
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| * | r65c19: (IND), X rather than (IND, X); give L2800 more internal RAM (nw) | 2019-12-02 | 1 | -9/+6 | |
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| * | r65c19: Add banking for C39 subfamily (nw) | 2019-12-01 | 1 | -0/+184 | |
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| * | New machines marked as NOT_WORKING | 2019-11-25 | 1 | -0/+106 | |
| ---------------------------------- Speedcom VD56SP [ClawGrip] Add disassembler and basic execution core for Rockwell R65C19 [AJR] | |||||
