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* i960: Further disassembly fixes AJR2025-03-251-3/+3
| | | | | - Enable decoding of a few more reg-type instructions - Add 0x prefix to unary branch destinations
* i960: Fix disassembly of ADD<cc>, SUB<cc> & SEL<cc> for cc = l, ne, le, o AJR2025-03-241-1/+1
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* cpu/i960: Corrected disassembly of dcinva instruction. (#11378) Joshua Scoggins2023-06-291-2/+2
| | | 0xad should be disassembled as dcinva, not 0xac.
* coretmpl.h: Add utility function for sign-extending values of arbitrary width AJR2022-11-011-2/+2
| | | | | * cpu/ccpu: Simplify code for right-shifting 12-bit values arithmetically * konami/3dom2_te.cpp: Fix probable copy-and-paste error
* Debugger feature improvements AJR2022-03-271-0/+2
| | | | | | | | - Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected. - Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions. - Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse. - Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx) - Don't pass over delay slots for debugging in ASAP core
* srcclean and cleanup (nw) Vas Crabb2020-06-211-3/+3
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* i960dasm: rewrote disassembler [SailorSat] Ariane Fugmann2020-05-041-262/+484
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* i960dasm: add missing opcodes [SailorSat] Ariane Fugmann2020-04-291-19/+77
| | | i960dasm: add missing opcodes [SailorSat]
* fix #6207 (nw) MetalliC2020-01-231-3/+3
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* i960: Wasn't supposed to break this (nw) AJR2018-02-081-1/+1
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* i960: Fix disassembly of REG instructions AJR2018-02-081-2/+2
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* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-84/+75
| | | | | | | | Disassemblers are now independant classes. Not only the code is cleaner, but unidasm has access to all the cpu cores again. The interface to the disassembly method has changed from byte buffers to objects that give a result to read methods. This also adds support for lfsr and/or paged PCs.
* i960: Preliminary support for CALLS instruction and WIP on FAULTx ↵ arbee2016-12-221-1/+1
| | | | instructions. [R. Belmont]
* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-201-11/+1
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* Changed 'std::ostream *' in disassemble_t to be 'std::ostream &' Nathan Woods2016-11-161-27/+23
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* Changed the i960 disassembler to use 'std::ostream &' internally Nathan Woods2016-11-151-26/+37
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* Rename *.c -> *.cpp in our source (nw) Miodrag Milanovic2015-11-081-0/+306