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path: root/src/devices/cpu/i960/i960dis.cpp
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* i960: Further disassembly fixes AJR2025-03-251-3/+3
* i960: Fix disassembly of ADD<cc>, SUB<cc> & SEL<cc> for cc = l, ne, le, o AJR2025-03-241-1/+1
* cpu/i960: Corrected disassembly of dcinva instruction. (#11378) Joshua Scoggins2023-06-291-2/+2
* coretmpl.h: Add utility function for sign-extending values of arbitrary width AJR2022-11-011-2/+2
* Debugger feature improvements AJR2022-03-271-0/+2
* srcclean and cleanup (nw) Vas Crabb2020-06-211-3/+3
* i960dasm: rewrote disassembler [SailorSat] Ariane Fugmann2020-05-041-262/+484
* i960dasm: add missing opcodes [SailorSat] Ariane Fugmann2020-04-291-19/+77
* fix #6207 (nw) MetalliC2020-01-231-3/+3
* i960: Wasn't supposed to break this (nw) AJR2018-02-081-1/+1
* i960: Fix disassembly of REG instructions AJR2018-02-081-2/+2
* dvdisasm: Overhaul [O. Galibert] Olivier Galibert2017-11-261-84/+75
* i960: Preliminary support for CALLS instruction and WIP on FAULTx instruction... arbee2016-12-221-1/+1
* Changed disassembler infrastructure to not use char buffers internally Nathan Woods2016-11-201-11/+1
* Changed 'std::ostream *' in disassemble_t to be 'std::ostream &' Nathan Woods2016-11-161-27/+23
* Changed the i960 disassembler to use 'std::ostream &' internally Nathan Woods2016-11-151-26/+37
* Rename *.c -> *.cpp in our source (nw) Miodrag Milanovic2015-11-081-0/+306