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* cpu/m68000: Updated 680x0 FPU to Softfloat 3 from 2. (MT5411 and MT8793). ↵ arbee2024-05-272-15/+38
| | | | | | | | | | | | | | | | | | [R. Belmont] - Update to Softloat 3 from 2 - FREM and FMOD now generate the quotient bits in FPSR, required by Apple's SANE to do sin/cos/tan properly. - FMOVE of a float to a Dx integer register generates the exception status bits, fixing square roots in SANE - Rewrote how FMOVEM instructions are decoded and executed, fixing issues including skipping too few or too many opcode bytes and causing serious weird behavior. - FPU instructions all now have more realistic cycle timings for a 68881. - All FPU instructions now generate exception bits in FPSR. 3rdparty/softfloat3: Updates [R. Belmont] - Softfloat3 was always being built for a big-endian host, causing incorrect math on LE x64 and AArch64 machines. - Fixed up Softfloat3 to build properly as part of MAME and up-ported the Bochs extensions. In latest Bochs, they were only partially up-ported and Softfloat3 had been hacked up to be more like 2; here they're fixed to work with stock Softfloat3.
* Initial import of SoftFloat release 3E [R. Belmont] arbee2018-05-13427-0/+40985
This is a pre-usage import so everyone can get things in line for various compilers. GCC/Clang should be OK on most targets as-is; MSVC may need to edit 3rdparty/softfloat3/build/MAME/build.h to conform. Please report failure/success with various compilers.