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-rw-r--r--src/mess/machine/6883sam.h2
-rw-r--r--src/mess/machine/a7800.c8
-rw-r--r--src/mess/machine/amstrad.c2
-rw-r--r--src/mess/machine/apollo.c24
-rw-r--r--src/mess/machine/apollo_kbd.c2
-rw-r--r--src/mess/machine/apple2.c20
-rw-r--r--src/mess/machine/apple2gs.c10
-rw-r--r--src/mess/machine/apple3.c153
-rw-r--r--src/mess/machine/apricotkb.c18
-rw-r--r--src/mess/machine/apricotkb.h2
-rw-r--r--src/mess/machine/atarifdc.c2
-rw-r--r--src/mess/machine/atarifdc.h2
-rw-r--r--src/mess/machine/bbc.c12
-rw-r--r--src/mess/machine/beta.h10
-rw-r--r--src/mess/machine/dec_lk201.c147
-rw-r--r--src/mess/machine/dgn_beta.c2
-rw-r--r--src/mess/machine/hp48.c12
-rw-r--r--src/mess/machine/mac.c8
-rw-r--r--src/mess/machine/mackbd.h6
-rw-r--r--src/mess/machine/mega32x.c6
-rw-r--r--src/mess/machine/mega32x.h8
-rw-r--r--src/mess/machine/megacd.h4
-rw-r--r--src/mess/machine/micropolis.h2
-rw-r--r--src/mess/machine/nes.c2
-rw-r--r--src/mess/machine/oric.c2
-rw-r--r--src/mess/machine/partner.c2
-rw-r--r--src/mess/machine/pecom.c2
-rw-r--r--src/mess/machine/sgi.c2
-rw-r--r--src/mess/machine/sgi.h2
-rw-r--r--src/mess/machine/smartmed.c4
-rw-r--r--src/mess/machine/sms.c14
-rw-r--r--src/mess/machine/svi318.c4
-rw-r--r--src/mess/machine/swtpc09.c624
-rw-r--r--src/mess/machine/thomson.c46
-rw-r--r--src/mess/machine/ti99/990_hd.h4
-rw-r--r--src/mess/machine/ti99/grom.c2
-rw-r--r--src/mess/machine/ti99/grom.h4
-rw-r--r--src/mess/machine/ti99/gromport.c14
-rw-r--r--src/mess/machine/ti99/speech8.h2
-rw-r--r--src/mess/machine/x68k_kbd.c6
-rw-r--r--src/mess/machine/zx8302.h12
41 files changed, 604 insertions, 606 deletions
diff --git a/src/mess/machine/6883sam.h b/src/mess/machine/6883sam.h
index 395585e59ec..ca637c5fa72 100644
--- a/src/mess/machine/6883sam.h
+++ b/src/mess/machine/6883sam.h
@@ -170,7 +170,7 @@ private:
// incidentals
address_space * m_cpu_space;
- devcb2_read8 m_read_res;
+ devcb2_read8 m_read_res;
sam_bank m_banks[8];
sam_space<0x0000, 0x7FFF> m_space_0000;
sam_space<0x8000, 0x9FFF> m_space_8000;
diff --git a/src/mess/machine/a7800.c b/src/mess/machine/a7800.c
index 82af304b259..45e7db18a1b 100644
--- a/src/mess/machine/a7800.c
+++ b/src/mess/machine/a7800.c
@@ -19,8 +19,8 @@
added Activision bank select type
19-Feb-2010 DanB Added return values for TIA collision registers
- 04-Apr-2014 Mike Saarna Fix to controller button RIOT behavior and
- expanded cart handling (bit 05).
+ 04-Apr-2014 Mike Saarna Fix to controller button RIOT behavior and
+ expanded cart handling (bit 05).
***************************************************************************/
#include "emu.h"
@@ -406,7 +406,7 @@ WRITE8_MEMBER(a7800_state::a7800_cart_w)
if(m_cart_type & 0x04)
{
//adjust write location if supercart bankram is in use
- if(m_cart_type & 0x20)
+ if(m_cart_type & 0x20)
{
UINT8 *currentbank1 = (UINT8 *)m_bank1->base();
currentbank1[offset] = data;
@@ -435,7 +435,7 @@ WRITE8_MEMBER(a7800_state::a7800_cart_w)
if( m_cart_size == 0x10000 )
{
data &= 0x03;
- }
+ }
else if( m_cart_size == 0x40000 )
{
data &= 0x0f;
diff --git a/src/mess/machine/amstrad.c b/src/mess/machine/amstrad.c
index c9e19eed4a5..36dd1fe3de2 100644
--- a/src/mess/machine/amstrad.c
+++ b/src/mess/machine/amstrad.c
@@ -2669,7 +2669,7 @@ READ8_MEMBER(amstrad_state::amstrad_psg_porta_read)
return (keyrow[m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F]->read_safe(0) & 0x80) | 0x7f;
}
}
-
+
return keyrow[m_ppi_port_outputs[amstrad_ppi_PortC] & 0x0F]->read_safe(0) & 0xFF;
}
return 0xFF;
diff --git a/src/mess/machine/apollo.c b/src/mess/machine/apollo.c
index f30bee58d07..47168890569 100644
--- a/src/mess/machine/apollo.c
+++ b/src/mess/machine/apollo.c
@@ -23,8 +23,8 @@
* - http://www.freescale.com/files/32bit/doc/inactive/MC68681UM.pdf
*
* SIO usage:
- * SIO: ch A keyboard, ch B serial console
- * SIO2: modem/printer?
+ * SIO: ch A keyboard, ch B serial console
+ * SIO2: modem/printer?
*
*/
@@ -190,7 +190,7 @@ static UINT16 cpu_control_register = 0x0000;
/*static int apollo_csr_get_servicemode()
{
- return cpu_status_register & APOLLO_CSR_SR_SERVICE ? 0 : 1;
+ return cpu_status_register & APOLLO_CSR_SR_SERVICE ? 0 : 1;
}*/
static void apollo_csr_set_servicemode(int mode)
@@ -569,7 +569,7 @@ void apollo_state::select_dma_channel(int channel, bool state)
#undef VERBOSE
#define VERBOSE 0
-void apollo_state::apollo_pic_set_irq_line(int irq, int state)
+void apollo_state::apollo_pic_set_irq_line(int irq, int state)
{
switch (irq) {
case 0: m_pic8259_master->ir0_w(state); break;
@@ -665,7 +665,7 @@ WRITE_LINE_MEMBER(apollo_state::apollo_ptm_timer_tick)
{
if ((state) && (m_ptm->started()))
{
- ptm_counter++;
+ ptm_counter++;
m_ptm->set_c1( 1);
m_ptm->set_c1( 0);
m_ptm->set_c2(ptm_counter & 1);
@@ -751,7 +751,7 @@ WRITE_LINE_MEMBER(apollo_state::sio_irq_handler)
WRITE8_MEMBER(apollo_state::sio_output)
{
- if ((data & 0x80) != (sio_output_data & 0x80))
+ if ((data & 0x80) != (sio_output_data & 0x80))
{
apollo_pic_set_irq_line(APOLLO_IRQ_DIAG, (data & 0x80) ? 1 : 0);
sio_output_data = data;
@@ -762,7 +762,7 @@ WRITE8_MEMBER(apollo_state::sio_output)
// The period of the output is 15 microseconds.
// toggle memory refresh counter
-// sio_input_data ^= 0x01;
+// sio_input_data ^= 0x01;
//##########################################################################
// machine/apollo_sio2.c - APOLLO DS3500 SIO2
@@ -808,9 +808,9 @@ static const isa16bus_interface isabus_intf =
};
static SLOT_INTERFACE_START(apollo_isa_cards)
- SLOT_INTERFACE("wdc", ISA16_OMTI8621) // Combo ESDI/AT floppy controller
- SLOT_INTERFACE("ctape", ISA8_SC499) // Archive SC499 cartridge tape
- SLOT_INTERFACE("3c505", ISA16_3C505) // 3Com 3C505 Ethernet card
+ SLOT_INTERFACE("wdc", ISA16_OMTI8621) // Combo ESDI/AT floppy controller
+ SLOT_INTERFACE("ctape", ISA8_SC499) // Archive SC499 cartridge tape
+ SLOT_INTERFACE("3c505", ISA16_3C505) // 3Com 3C505 Ethernet card
SLOT_INTERFACE_END
MACHINE_CONFIG_FRAGMENT( common )
@@ -849,7 +849,7 @@ MACHINE_CONFIG_FRAGMENT( apollo )
MCFG_MC68681_ADD( APOLLO_SIO_TAG, XTAL_3_6864MHz )
MCFG_MC68681_IRQ_CALLBACK(WRITELINE(apollo_state, sio_irq_handler))
- MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
+ MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
MCFG_MC68681_A_TX_CALLBACK(DEVWRITELINE(APOLLO_KBD_TAG, apollo_kbd_device, rx_w))
MACHINE_CONFIG_END
@@ -868,7 +868,7 @@ MACHINE_CONFIG_FRAGMENT( apollo_terminal )
MCFG_MC68681_ADD( APOLLO_SIO_TAG, XTAL_3_6864MHz )
MCFG_MC68681_IRQ_CALLBACK(WRITELINE(apollo_state, sio_irq_handler))
- MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
+ MCFG_MC68681_OUTPORT_CALLBACK(WRITE8(apollo_state, sio_output))
MCFG_MC68681_B_TX_CALLBACK(DEVWRITELINE("rs232", rs232_port_device, write_txd))
MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "serial_terminal")
diff --git a/src/mess/machine/apollo_kbd.c b/src/mess/machine/apollo_kbd.c
index 07b5a150da4..4c6c7501b66 100644
--- a/src/mess/machine/apollo_kbd.c
+++ b/src/mess/machine/apollo_kbd.c
@@ -201,7 +201,7 @@ void apollo_kbd_device::beeper::on()
int apollo_kbd_device::beeper::keyboard_has_beeper()
{
- return true; // driver has no facility to return false here, so go with it
+ return true; // driver has no facility to return false here, so go with it
}
void apollo_kbd_device::beeper::beeper_callback()
diff --git a/src/mess/machine/apple2.c b/src/mess/machine/apple2.c
index 7128a80da32..22e6db8fec0 100644
--- a/src/mess/machine/apple2.c
+++ b/src/mess/machine/apple2.c
@@ -2374,7 +2374,7 @@ READ_LINE_MEMBER(apple2_state::ay3600_control_r)
static const UINT8 a2_key_remap[0x32][4] =
{
-/* norm shft ctrl both */
+/* norm shft ctrl both */
{ 0x33,0x23,0x33,0x23 }, /* 3 # 00 */
{ 0x34,0x24,0x34,0x24 }, /* 4 $ 01 */
{ 0x35,0x25,0x35,0x25 }, /* 5 % 02 */
@@ -2432,7 +2432,7 @@ WRITE_LINE_MEMBER(apple2_state::ay3600_data_ready_w)
if (state == ASSERT_LINE)
{
int mod = 0;
- m_lastchar = m_ay3600->b_r();
+ m_lastchar = m_ay3600->b_r();
mod = (m_kbspecial->read() & 0x06) ? 0x01 : 0x00;
mod |= (m_kbspecial->read() & 0x08) ? 0x02 : 0x00;
@@ -2442,7 +2442,7 @@ WRITE_LINE_MEMBER(apple2_state::ay3600_data_ready_w)
if (m_transchar != 0)
{
m_strobe = 0x80;
-// printf("new char = %04x (%02x)\n", m_lastchar&0x3f, m_transchar);
+// printf("new char = %04x (%02x)\n", m_lastchar&0x3f, m_transchar);
}
}
}
@@ -2456,16 +2456,16 @@ WRITE_LINE_MEMBER(apple2_state::ay3600_iie_data_ready_w)
m_lastchar = m_ay3600->b_r();
- trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
- trans |= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
- trans <<= 2; // 4 entries per key
- trans |= (m_kbspecial->read() & 0x06) ? 0x00 : 0x01; // shift is bit 1 (active low)
- trans |= (m_kbspecial->read() & 0x08) ? 0x00 : 0x02; // control is bit 2 (active low)
- trans |= (m_kbspecial->read() & 0x01) ? 0x0000 : 0x0200; // caps lock is bit 9 (active low)
+ trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
+ trans |= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
+ trans <<= 2; // 4 entries per key
+ trans |= (m_kbspecial->read() & 0x06) ? 0x00 : 0x01; // shift is bit 1 (active low)
+ trans |= (m_kbspecial->read() & 0x08) ? 0x00 : 0x02; // control is bit 2 (active low)
+ trans |= (m_kbspecial->read() & 0x01) ? 0x0000 : 0x0200; // caps lock is bit 9 (active low)
m_transchar = decode[trans];
m_strobe = 0x80;
-// printf("new char = %04x (%02x)\n", m_lastchar, m_transchar);
+// printf("new char = %04x (%02x)\n", m_lastchar, m_transchar);
}
}
diff --git a/src/mess/machine/apple2gs.c b/src/mess/machine/apple2gs.c
index 28d77ef9808..2b051dc4a65 100644
--- a/src/mess/machine/apple2gs.c
+++ b/src/mess/machine/apple2gs.c
@@ -946,23 +946,23 @@ READ8_MEMBER( apple2gs_state::apple2gs_c0xx_r )
result = 0;
{
UINT8 temp = m_kbspecial->read();
- if (temp & 1) // capslock
+ if (temp & 1) // capslock
{
result |= 4;
}
- if (temp & 6) // shift
+ if (temp & 6) // shift
{
result |= 1;
}
- if (temp & 8) // control
+ if (temp & 8) // control
{
result |= 2;
}
- if (temp & 0x10) // open apple/command
+ if (temp & 0x10) // open apple/command
{
result |= 0x40;
}
- if (temp & 0x20) // option
+ if (temp & 0x20) // option
{
result |= 0x80;
}
diff --git a/src/mess/machine/apple3.c b/src/mess/machine/apple3.c
index 2a77176e220..e169a9788cf 100644
--- a/src/mess/machine/apple3.c
+++ b/src/mess/machine/apple3.c
@@ -3,43 +3,43 @@
machine/apple3.c
Apple ///
-
+
VIA #0 (D VIA)
- CA1: IRQ from the MM58167 RTC
- CA2: 1 if key pressed, 0 otherwise
- CB1/CB2: connected to VBL
-
- Port A: Environment register (all bits out)
- bit 7: 1 for 1 MHz, 0 for 2 MHz
- bit 6: 1 for I/O at C000-CFFF
- bit 5: 1 to enable video
- bit 4: 1 to enable NMI/Reset
- bit 3: 1 to write-protect RAM in system bank C000-FFFF
- bit 2: 1 to force primary stack at 0100-01FF
- bit 1: 1 for primary ROM, 0 for secondary (Apple III doesn't have a secondary ROM, so this should always be '1' when bit 0 is)
- bit 0: 1 to enable ROM in F000-FFFF
-
- Port B: Zero page high 8 address bits, also MM58167 RTC register select (all bits out)
-
+ CA1: IRQ from the MM58167 RTC
+ CA2: 1 if key pressed, 0 otherwise
+ CB1/CB2: connected to VBL
+
+ Port A: Environment register (all bits out)
+ bit 7: 1 for 1 MHz, 0 for 2 MHz
+ bit 6: 1 for I/O at C000-CFFF
+ bit 5: 1 to enable video
+ bit 4: 1 to enable NMI/Reset
+ bit 3: 1 to write-protect RAM in system bank C000-FFFF
+ bit 2: 1 to force primary stack at 0100-01FF
+ bit 1: 1 for primary ROM, 0 for secondary (Apple III doesn't have a secondary ROM, so this should always be '1' when bit 0 is)
+ bit 0: 1 to enable ROM in F000-FFFF
+
+ Port B: Zero page high 8 address bits, also MM58167 RTC register select (all bits out)
+
VIA #1 (E VIA)
- CA1: OR of all 4 slots' IRQ status
- CA2: SW1 (Open Apple key?)
- CB1: SW3/SCO
- CB2: SER
-
- Port A:
- bits 0-2: bank select for $2000-$9FFF range
- bit 3: n/c
- bit 4: slot 4 IRQ (in)
- bit 5: slot 3 IRQ (in)
- bit 6: Apple II mode trap output (out)
- bit 7: IRQ status (in) (0 = IRQ, 1 = no IRQ)
-
- Port B:
- bits 0-5: 6-bit audio DAC output
- bit 6: screen blank
- bit 7: OR of NMI from slots
-
+ CA1: OR of all 4 slots' IRQ status
+ CA2: SW1 (Open Apple key?)
+ CB1: SW3/SCO
+ CB2: SER
+
+ Port A:
+ bits 0-2: bank select for $2000-$9FFF range
+ bit 3: n/c
+ bit 4: slot 4 IRQ (in)
+ bit 5: slot 3 IRQ (in)
+ bit 6: Apple II mode trap output (out)
+ bit 7: IRQ status (in) (0 = IRQ, 1 = no IRQ)
+
+ Port B:
+ bits 0-5: 6-bit audio DAC output
+ bit 6: screen blank
+ bit 7: OR of NMI from slots
+
***************************************************************************/
#include "emu.h"
@@ -53,14 +53,14 @@ static void apple3_update_drives(device_t *device);
#define LOG_MEMORY 1
#define LOG_INDXADDR 1
-#define ENV_SLOWSPEED (0x80)
-#define ENV_IOENABLE (0x40)
-#define ENV_VIDENABLE (0x20)
-#define ENV_NMIENABLE (0x10)
-#define ENV_WRITEPROT (0x08)
-#define ENV_STACK1XX (0x04)
-#define ENV_PRIMARYROM (0x02)
-#define ENV_ROMENABLE (0x01)
+#define ENV_SLOWSPEED (0x80)
+#define ENV_IOENABLE (0x40)
+#define ENV_VIDENABLE (0x20)
+#define ENV_NMIENABLE (0x10)
+#define ENV_WRITEPROT (0x08)
+#define ENV_STACK1XX (0x04)
+#define ENV_PRIMARYROM (0x02)
+#define ENV_ROMENABLE (0x01)
READ8_MEMBER(apple3_state::apple3_c0xx_r)
{
@@ -109,7 +109,7 @@ READ8_MEMBER(apple3_state::apple3_c0xx_r)
result &= ~0x20;
}
}
-// printf("modifier = %02x\n", result);
+// printf("modifier = %02x\n", result);
break;
case 0x10: case 0x11: case 0x12: case 0x13:
@@ -174,7 +174,7 @@ READ8_MEMBER(apple3_state::apple3_c0xx_r)
{
result = slotdevice->read_c0nx(space, offset&0xf);
}
- break;
+ break;
case 0xa0: case 0xa1: case 0xa2: case 0xa3:
case 0xa4: case 0xa5: case 0xa6: case 0xa7:
@@ -185,7 +185,7 @@ READ8_MEMBER(apple3_state::apple3_c0xx_r)
{
result = slotdevice->read_c0nx(space, offset&0xf);
}
- break;
+ break;
case 0xb0: case 0xb1: case 0xb2: case 0xb3:
case 0xb4: case 0xb5: case 0xb6: case 0xb7:
@@ -196,7 +196,7 @@ READ8_MEMBER(apple3_state::apple3_c0xx_r)
{
result = slotdevice->read_c0nx(space, offset&0xf);
}
- break;
+ break;
case 0xc0: case 0xc1: case 0xc2: case 0xc3:
case 0xc4: case 0xc5: case 0xc6: case 0xc7:
@@ -207,7 +207,7 @@ READ8_MEMBER(apple3_state::apple3_c0xx_r)
{
result = slotdevice->read_c0nx(space, offset&0xf);
}
- break;
+ break;
case 0xD0: case 0xD1: case 0xD2: case 0xD3:
case 0xD4: case 0xD5: case 0xD6: case 0xD7:
@@ -305,7 +305,7 @@ WRITE8_MEMBER(apple3_state::apple3_c0xx_w)
{
slotdevice->write_c0nx(space, offset&0xf, data);
}
- break;
+ break;
case 0xa0: case 0xa1: case 0xa2: case 0xa3:
case 0xa4: case 0xa5: case 0xa6: case 0xa7:
@@ -316,7 +316,7 @@ WRITE8_MEMBER(apple3_state::apple3_c0xx_w)
{
slotdevice->write_c0nx(space, offset&0xf, data);
}
- break;
+ break;
case 0xb0: case 0xb1: case 0xb2: case 0xb3:
case 0xb4: case 0xb5: case 0xb6: case 0xb7:
@@ -327,7 +327,7 @@ WRITE8_MEMBER(apple3_state::apple3_c0xx_w)
{
slotdevice->write_c0nx(space, offset&0xf, data);
}
- break;
+ break;
case 0xc0: case 0xc1: case 0xc2: case 0xc3:
case 0xc4: case 0xc5: case 0xc6: case 0xc7:
@@ -338,7 +338,7 @@ WRITE8_MEMBER(apple3_state::apple3_c0xx_w)
{
slotdevice->write_c0nx(space, offset&0xf, data);
}
- break;
+ break;
case 0xD0: case 0xD1: case 0xD2: case 0xD3:
case 0xD4: case 0xD5: case 0xD6: case 0xD7:
@@ -372,7 +372,7 @@ WRITE8_MEMBER(apple3_state::apple3_c0xx_w)
TIMER_DEVICE_CALLBACK_MEMBER(apple3_state::apple3_interrupt)
{
- m_via_1->write_cb1(machine().first_screen()->vblank());
+ m_via_1->write_cb1(machine().first_screen()->vblank());
m_via_1->write_cb2(machine().first_screen()->vblank());
}
@@ -437,31 +437,31 @@ void apple3_state::apple3_update_memory()
bank = ~0;
page = 0x01;
}
- m_bank2 = apple3_bankaddr(bank, ((offs_t) page) * 0x100);
+ m_bank2 = apple3_bankaddr(bank, ((offs_t) page) * 0x100);
/* bank 3 (0200-1FFF) */
- m_bank3 = apple3_bankaddr(~0, 0x0200);
+ m_bank3 = apple3_bankaddr(~0, 0x0200);
/* bank 4 (2000-9FFF) */
- m_bank4 = apple3_bankaddr(m_via_1_a, 0x0000);
+ m_bank4 = apple3_bankaddr(m_via_1_a, 0x0000);
/* bank 5 (A000-BFFF) */
- m_bank5 = apple3_bankaddr(~0, 0x2000);
+ m_bank5 = apple3_bankaddr(~0, 0x2000);
/* bank 8 (C000-C0FF) */
if (!(m_via_0_a & ENV_IOENABLE))
{
- m_bank8 = apple3_bankaddr(~0, 0x4000);
+ m_bank8 = apple3_bankaddr(~0, 0x4000);
}
/* bank 9 (C100-C4FF) */
if (!(m_via_0_a & ENV_IOENABLE))
{
- m_bank9 = apple3_bankaddr(~0, 0x4100);
+ m_bank9 = apple3_bankaddr(~0, 0x4100);
}
/* bank 10 (C500-C7FF) */
- m_bank10 = apple3_bankaddr(~0, 0x4500);
+ m_bank10 = apple3_bankaddr(~0, 0x4500);
/* bank 11 (C800-CFFF) */
if (!(m_via_0_a & ENV_IOENABLE))
@@ -507,7 +507,7 @@ WRITE8_MEMBER(apple3_state::apple3_via_0_out_a)
WRITE8_MEMBER(apple3_state::apple3_via_0_out_b)
{
-// printf("ZP to %02x\n", data);
+// printf("ZP to %02x\n", data);
apple3_via_out(&m_via_0_b, data);
}
@@ -529,7 +529,7 @@ void apple3_state::apple3_irq_update()
// HACK: SOS floppy driver enables ROM at Fxxx *before* trying to
// suppress IRQs. IRQ hits at inopportune time -> bad vector -> system crash.
// This breaks the Confidence Test, but the Confidence Test
- // never disables the ROM so checking for that gets us
+ // never disables the ROM so checking for that gets us
// working in all cases.
// Bonus points: for some reason this isn't a problem with -debug.
// m6502 heisenbug maybe?
@@ -537,13 +537,13 @@ void apple3_state::apple3_irq_update()
{
return;
}
-// printf(" setting IRQ\n");
+// printf(" setting IRQ\n");
m_maincpu->set_input_line(M6502_IRQ_LINE, ASSERT_LINE);
- m_via_1->write_pa7(0); // this is active low
+ m_via_1->write_pa7(0); // this is active low
}
else
{
-// printf(" clearing IRQ\n");
+// printf(" clearing IRQ\n");
m_maincpu->set_input_line(M6502_IRQ_LINE, CLEAR_LINE);
m_via_1->write_pa7(1);
}
@@ -551,14 +551,14 @@ void apple3_state::apple3_irq_update()
WRITE_LINE_MEMBER(apple3_state::apple3_acia_irq_func)
{
-// printf("acia IRQ: %d\n", state);
+// printf("acia IRQ: %d\n", state);
m_acia_irq = state;
apple3_irq_update();
}
WRITE_LINE_MEMBER(apple3_state::apple3_via_1_irq_func)
{
-// printf("via 1 IRQ: %d\n", state);
+// printf("via 1 IRQ: %d\n", state);
m_via_1_irq = state;
apple3_irq_update();
}
@@ -566,7 +566,7 @@ WRITE_LINE_MEMBER(apple3_state::apple3_via_1_irq_func)
WRITE_LINE_MEMBER(apple3_state::apple3_via_0_irq_func)
{
-// printf("via 0 IRQ: %d\n", state);
+// printf("via 0 IRQ: %d\n", state);
m_via_0_irq = state;
apple3_irq_update();
}
@@ -745,7 +745,7 @@ READ8_MEMBER(apple3_state::apple3_memory_r)
if (offset < 0x100)
{
- rv = *apple3_get_zpa_addr(offset);
+ rv = *apple3_get_zpa_addr(offset);
if ((!m_sync) && (m_via_0_b >= 0x18) && (m_via_0_b <= 0x1F))
{
@@ -849,7 +849,7 @@ READ8_MEMBER(apple3_state::apple3_memory_r)
}
else
{
- rv = m_bank7rd[offset - 0xf000];
+ rv = m_bank7rd[offset - 0xf000];
}
}
@@ -1002,7 +1002,7 @@ WRITE8_MEMBER(apple3_state::apple3_memory_w)
WRITE_LINE_MEMBER(apple3_state::apple3_sync_w)
{
-// printf("sync: %d\n", state);
+// printf("sync: %d\n", state);
m_sync = (state == ASSERT_LINE) ? true : false;
if (m_sync)
@@ -1044,7 +1044,7 @@ READ_LINE_MEMBER(apple3_state::ay3600_control_r)
static const UINT8 key_remap[0x50][4] =
{
-/* norm shft ctrl both */
+/* norm shft ctrl both */
{ 0x9b,0x9b,0x9b,0x9b }, /* Escape 00 */
{ 0x31,0x21,0x31,0x31 }, /* 1 ! 01 */
{ 0x32,0x40,0x32,0x00 }, /* 2 @ 02 */
@@ -1135,10 +1135,10 @@ WRITE_LINE_MEMBER(apple3_state::ay3600_data_ready_w)
{
UINT16 trans;
int mod = 0;
- m_lastchar = m_ay3600->b_r();
+ m_lastchar = m_ay3600->b_r();
- trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
- trans |= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
+ trans = m_lastchar & ~(0x1c0); // clear the 3600's control/shift stuff
+ trans |= (m_lastchar & 0x100)>>2; // bring the 0x100 bit down to the 0x40 place
mod = (m_kbspecial->read() & 0x06) ? 0x01 : 0x00;
mod |= (m_kbspecial->read() & 0x08) ? 0x02 : 0x00;
@@ -1148,8 +1148,7 @@ WRITE_LINE_MEMBER(apple3_state::ay3600_data_ready_w)
if (m_transchar != 0)
{
m_strobe = 0x80;
-// printf("new char = %04x (%02x)\n", trans, m_transchar);
+// printf("new char = %04x (%02x)\n", trans, m_transchar);
}
}
}
-
diff --git a/src/mess/machine/apricotkb.c b/src/mess/machine/apricotkb.c
index d8b538ec836..683a7ce3b53 100644
--- a/src/mess/machine/apricotkb.c
+++ b/src/mess/machine/apricotkb.c
@@ -52,13 +52,13 @@ const rom_entry *apricot_keyboard_device::device_rom_region() const
#ifdef UPD7507_EMULATED
static ADDRESS_MAP_START( apricot_keyboard_io, AS_IO, 8, apricot_keyboard_device )
- AM_RANGE(0x00, 0x00) AM_READ(kb_lo_r)
- AM_RANGE(0x01, 0x01) AM_READ(kb_hi_r)
- AM_RANGE(0x03, 0x03) AM_WRITE(kb_p3_w)
- AM_RANGE(0x04, 0x04) AM_WRITE(kb_y0_w)
- AM_RANGE(0x05, 0x05) AM_WRITE(kb_y4_w)
- AM_RANGE(0x06, 0x06) AM_READWRITE(kb_p6_r, kb_yc_w)
- AM_RANGE(0x07, 0x07) AM_WRITE(kb_y8_w)
+ AM_RANGE(0x00, 0x00) AM_READ(kb_lo_r)
+ AM_RANGE(0x01, 0x01) AM_READ(kb_hi_r)
+ AM_RANGE(0x03, 0x03) AM_WRITE(kb_p3_w)
+ AM_RANGE(0x04, 0x04) AM_WRITE(kb_y0_w)
+ AM_RANGE(0x05, 0x05) AM_WRITE(kb_y4_w)
+ AM_RANGE(0x06, 0x06) AM_READWRITE(kb_p6_r, kb_yc_w)
+ AM_RANGE(0x07, 0x07) AM_WRITE(kb_y8_w)
ADDRESS_MAP_END
#endif
@@ -69,8 +69,8 @@ ADDRESS_MAP_END
static MACHINE_CONFIG_FRAGMENT( apricot_keyboard )
#ifdef UPD7507_EMULATED
- MCFG_CPU_ADD(UPD7507C_TAG, UPD7507, XTAL_32_768kHz)
- MCFG_CPU_IO_MAP(apricot_keyboard_io)
+ MCFG_CPU_ADD(UPD7507C_TAG, UPD7507, XTAL_32_768kHz)
+ MCFG_CPU_IO_MAP(apricot_keyboard_io)
#endif
MACHINE_CONFIG_END
diff --git a/src/mess/machine/apricotkb.h b/src/mess/machine/apricotkb.h
index db781b788bd..bf12f70c664 100644
--- a/src/mess/machine/apricotkb.h
+++ b/src/mess/machine/apricotkb.h
@@ -46,7 +46,7 @@ public:
apricot_keyboard_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
template<class _Object> static devcb2_base &set_txd_wr_callback(device_t &device, _Object object) { return downcast<apricot_keyboard_device &>(device).m_write_txd.set_callback(object); }
-
+
// optional information overrides
virtual const rom_entry *device_rom_region() const;
virtual machine_config_constructor device_mconfig_additions() const;
diff --git a/src/mess/machine/atarifdc.c b/src/mess/machine/atarifdc.c
index 4e2cee018fb..9b07cd20e5e 100644
--- a/src/mess/machine/atarifdc.c
+++ b/src/mess/machine/atarifdc.c
@@ -763,7 +763,7 @@ atari_fdc_device::atari_fdc_device(const machine_config &mconfig, const char *ta
m_serout_count(0),
m_serout_offs(0),
m_serout_chksum(0),
-// m_serout_delay(0),
+// m_serout_delay(0),
m_serin_count(0),
m_serin_offs(0),
m_serin_chksum(0),
diff --git a/src/mess/machine/atarifdc.h b/src/mess/machine/atarifdc.h
index a6bb687de25..4d1f544a129 100644
--- a/src/mess/machine/atarifdc.h
+++ b/src/mess/machine/atarifdc.h
@@ -51,7 +51,7 @@ private:
int m_serout_offs;
UINT8 m_serout_buff[512];
UINT8 m_serout_chksum;
-// int m_serout_delay;
+// int m_serout_delay;
int m_serin_count;
int m_serin_offs;
diff --git a/src/mess/machine/bbc.c b/src/mess/machine/bbc.c
index 27b342d9a95..87c392cb6df 100644
--- a/src/mess/machine/bbc.c
+++ b/src/mess/machine/bbc.c
@@ -1445,7 +1445,7 @@ WRITE8_MEMBER(bbc_state::bbc_SerialULA_w)
WRITE_LINE_MEMBER(bbc_state::write_acia_clock)
{
m_acia->write_txc(state);
-
+
if (m_serproc_data & 0x40)
m_acia->write_rxc(state);
}
@@ -1965,12 +1965,12 @@ int bbc_state::exp_rom_load(device_image_interface &image, int index)
UINT8 *RAM = m_region_user1->base();
int size, read_;
int addr = 0x8000 + (0x4000 * index);
-
+
if (image.software_entry() == NULL)
{
size = image.length();
logerror("loading rom %s, at %.4x size:%.4x\n", image.filename(), addr, size);
-
+
switch (size)
{
case 0x2000:
@@ -1988,7 +1988,7 @@ int bbc_state::exp_rom_load(device_image_interface &image, int index)
logerror("bad rom file size of %.4x\n", size);
break;
}
-
+
if (read_ != size)
return IMAGE_INIT_FAIL;
}
@@ -2005,7 +2005,7 @@ DEVICE_IMAGE_LOAD_MEMBER( bbc_state, bbc_exp_rom )
if (strcmp(image.device().tag(),":exp_rom3") == 0)
return exp_rom_load(image, 2);
-
+
if (strcmp(image.device().tag(),":exp_rom4") == 0)
return exp_rom_load(image, 3);
@@ -2038,7 +2038,7 @@ DEVICE_IMAGE_LOAD_MEMBER( bbc_state, bbcm_cart )
image.seterror(IMAGE_ERROR_UNSUPPORTED, "Invalid rom file size");
return IMAGE_INIT_FAIL;
}
-
+
image.fread(RAM + addr, size);
}
else
diff --git a/src/mess/machine/beta.h b/src/mess/machine/beta.h
index 5ffe06f822d..fa82244eb11 100644
--- a/src/mess/machine/beta.h
+++ b/src/mess/machine/beta.h
@@ -20,7 +20,7 @@ class beta_disk_device : public device_t
public:
beta_disk_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
~beta_disk_device() {}
-
+
DECLARE_READ8_MEMBER(status_r);
DECLARE_READ8_MEMBER(track_r);
DECLARE_READ8_MEMBER(sector_r);
@@ -32,18 +32,18 @@ public:
DECLARE_WRITE8_MEMBER(track_w);
DECLARE_WRITE8_MEMBER(sector_w);
DECLARE_WRITE8_MEMBER(data_w);
-
+
DECLARE_WRITE_LINE_MEMBER(wd179x_intrq_w);
DECLARE_WRITE_LINE_MEMBER(wd179x_drq_w);
-
+
int is_active();
void enable();
void disable();
void clear_status();
-
+
UINT8 m_betadisk_status;
UINT8 m_betadisk_active;
-
+
protected:
// device-level overrides
virtual void device_start();
diff --git a/src/mess/machine/dec_lk201.c b/src/mess/machine/dec_lk201.c
index af94303dcc7..aa0b98e1a7e 100644
--- a/src/mess/machine/dec_lk201.c
+++ b/src/mess/machine/dec_lk201.c
@@ -116,58 +116,58 @@ ________|D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0
// SERIAL COMMUNICATIONS INTERFACE
//-------------------------------------------------
-#define SCI_BAUD 0 // Baud rate register
-#define BAUD_SCR 0x07 // SCI baud rate select
-#define BAUD_SCP 0x30 // SCI prescaler select
-
-#define SCI_SCCR1 1 // Control register 1
-#define SCCR1_WAKE 0x08 // Wakeup method
-#define SCCR1_M 0x10 // Character length
-#define SCCR1_T8 0x40 // Transmit bit 8
-#define SCCR1_R8 0x80 // Receive bit 8
-
-#define SCI_SCCR2 2 // Control register 2
-#define SCCR2_SBK 0x01 // Send break
-#define SCCR2_RWU 0x02 // Receiver wakeup enable
-#define SCCR2_RE 0x04 // Receiver enable
-#define SCCR2_TE 0x08 // Transmitter enable
-#define SCCR2_ILIE 0x10 // Idle line interrupt enable
-#define SCCR2_RIE 0x20 // Receiver interrupt enable
-#define SCCR2_TCIE 0x40 // Transmit complete interrupt enable
-#define SCCR2_TIE 0x80 // Transmit interrupt enable
-
-#define SCI_SCSR 3 // Status register
-#define SCSR_FE 0x02 // Receiver framing error
-#define SCSR_NF 0x04 // Receiver noise
-#define SCSR_OR 0x08 // Receiver overrun
-#define SCSR_IDLE 0x10 // Receiver idle
-#define SCSR_RDRF 0x20 // Receive data register full
-#define SCSR_TC 0x40 // Transmit complete
-#define SCSR_TDRE 0x80 // Transmit data register empty
-#define SCSR_INT (SCSR_IDLE | SCSR_RDRF| \
- SCSR_TC | SCSR_TDRE) // Interrupt sources
-
-#define SCI_SCDR 4 // Data register
+#define SCI_BAUD 0 // Baud rate register
+#define BAUD_SCR 0x07 // SCI baud rate select
+#define BAUD_SCP 0x30 // SCI prescaler select
+
+#define SCI_SCCR1 1 // Control register 1
+#define SCCR1_WAKE 0x08 // Wakeup method
+#define SCCR1_M 0x10 // Character length
+#define SCCR1_T8 0x40 // Transmit bit 8
+#define SCCR1_R8 0x80 // Receive bit 8
+
+#define SCI_SCCR2 2 // Control register 2
+#define SCCR2_SBK 0x01 // Send break
+#define SCCR2_RWU 0x02 // Receiver wakeup enable
+#define SCCR2_RE 0x04 // Receiver enable
+#define SCCR2_TE 0x08 // Transmitter enable
+#define SCCR2_ILIE 0x10 // Idle line interrupt enable
+#define SCCR2_RIE 0x20 // Receiver interrupt enable
+#define SCCR2_TCIE 0x40 // Transmit complete interrupt enable
+#define SCCR2_TIE 0x80 // Transmit interrupt enable
+
+#define SCI_SCSR 3 // Status register
+#define SCSR_FE 0x02 // Receiver framing error
+#define SCSR_NF 0x04 // Receiver noise
+#define SCSR_OR 0x08 // Receiver overrun
+#define SCSR_IDLE 0x10 // Receiver idle
+#define SCSR_RDRF 0x20 // Receive data register full
+#define SCSR_TC 0x40 // Transmit complete
+#define SCSR_TDRE 0x80 // Transmit data register empty
+#define SCSR_INT (SCSR_IDLE | SCSR_RDRF| \
+ SCSR_TC | SCSR_TDRE) // Interrupt sources
+
+#define SCI_SCDR 4 // Data register
//-------------------------------------------------
// SERIAL PERIPHERAL INTERFACE
//-------------------------------------------------
-#define SPI_SPCR 0 // Control register
-#define SPCR_SPR 0x03 // SPI clock rate select
-#define SPCR_CPHA 0x04 // Clock phase
-#define SPCR_CPOL 0x08 // Clock polarity
-#define SPCR_MSTR 0x10 // Master mode select
-#define SPCR_DWOM 0x20 // Port D wire-or mode option
-#define SPCR_SPE 0x40 // Serial peripheral system enable
-#define SPCR_SPIE 0x80 // Serial peripheral interrupt enable
+#define SPI_SPCR 0 // Control register
+#define SPCR_SPR 0x03 // SPI clock rate select
+#define SPCR_CPHA 0x04 // Clock phase
+#define SPCR_CPOL 0x08 // Clock polarity
+#define SPCR_MSTR 0x10 // Master mode select
+#define SPCR_DWOM 0x20 // Port D wire-or mode option
+#define SPCR_SPE 0x40 // Serial peripheral system enable
+#define SPCR_SPIE 0x80 // Serial peripheral interrupt enable
-#define SPI_SPSR 1 // Status register
-#define SPSR_MODF 0x10 // Mode fault flag
-#define SPSR_WCOL 0x40 // Write collision
-#define SPSR_SPIF 0x80 // SPI transfer complete
+#define SPI_SPSR 1 // Status register
+#define SPSR_MODF 0x10 // Mode fault flag
+#define SPSR_WCOL 0x40 // Write collision
+#define SPSR_SPIF 0x80 // SPI transfer complete
-#define SPI_SPDR 2 // Data I/O Register
+#define SPI_SPDR 2 // Data I/O Register
//**************************************************************************
// DEVICE DEFINITIONS
@@ -338,8 +338,8 @@ INPUT_PORTS_START( lk201 )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
PORT_START("KBD11")
- PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
- PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/") PORT_CODE(KEYCODE_SLASH)
+ PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME(";") PORT_CODE(KEYCODE_COLON)
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_UNUSED ) // FIXME - duplicate "Return"
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("P") PORT_CODE(KEYCODE_P)
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("0") PORT_CODE(KEYCODE_0)
@@ -363,7 +363,7 @@ INPUT_PORTS_START( lk201 )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("'") PORT_CODE(KEYCODE_QUOTE)
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("[") PORT_CODE(KEYCODE_OPENBRACE)
PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Previous") PORT_CODE(KEYCODE_END)
- PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Do (F16)")
+ PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Do (F16)")
PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS)
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Insert Here") PORT_CODE(KEYCODE_HOME)
@@ -494,7 +494,7 @@ void lk201_device::rcv_complete()
sci_status |= SCSR_RDRF;
update_interrupts();
receive_register_extract();
-// printf("lk201 got %02x\n", get_received_char());
+// printf("lk201 got %02x\n", get_received_char());
}
void lk201_device::tra_complete()
@@ -527,7 +527,7 @@ READ8_MEMBER( lk201_device::ddr_r )
WRITE8_MEMBER( lk201_device::ddr_w )
{
-// printf("%02x to PORT %c DDR (PC=%x)\n", data, 'A' + offset, m_maincpu->pc());
+// printf("%02x to PORT %c DDR (PC=%x)\n", data, 'A' + offset, m_maincpu->pc());
send_port(space, offset, ports[offset] & data);
@@ -543,7 +543,7 @@ READ8_MEMBER( lk201_device::ports_r )
// add in ddr-masked version of port writes
incoming |= (ports[offset] & ddrs[offset]);
-// printf("PORT %c read = %02x (DDR = %02x latch = %02x) (PC=%x)\n", 'A' + offset, ports[offset], ddrs[offset], ports[offset], m_maincpu->pc());
+// printf("PORT %c read = %02x (DDR = %02x latch = %02x) (PC=%x)\n", 'A' + offset, ports[offset], ddrs[offset], ports[offset], m_maincpu->pc());
return incoming;
}
@@ -557,7 +557,7 @@ WRITE8_MEMBER( lk201_device::ports_w )
void lk201_device::send_port(address_space &space, UINT8 offset, UINT8 data)
{
-// printf("PORT %c write %02x (DDR = %02x) (PC=%x)\n", 'A' + offset, data, ddrs[offset], m_maincpu->pc());
+// printf("PORT %c write %02x (DDR = %02x) (PC=%x)\n", 'A' + offset, data, ddrs[offset], m_maincpu->pc());
switch (offset)
{
@@ -609,21 +609,21 @@ READ8_MEMBER( lk201_device::sci_r )
switch (offset)
{
- case SCI_BAUD: // Baud rate
+ case SCI_BAUD: // Baud rate
break;
- case SCI_SCCR1: // Control 1
+ case SCI_SCCR1: // Control 1
break;
- case SCI_SCCR2: // Control 2
+ case SCI_SCCR2: // Control 2
incoming = sci_ctl2;
break;
- case SCI_SCSR: // Status
+ case SCI_SCSR: // Status
incoming = sci_status;
break;
- case SCI_SCDR: // Data
+ case SCI_SCDR: // Data
incoming = get_received_char();
sci_status &= ~SCSR_RDRF;
m_maincpu->set_input_line(M68HC05EG_INT_CPI, 0);
@@ -631,7 +631,7 @@ READ8_MEMBER( lk201_device::sci_r )
break;
}
-// printf("SCI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
+// printf("SCI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
return incoming;
}
@@ -640,22 +640,22 @@ WRITE8_MEMBER( lk201_device::sci_w )
{
switch (offset)
{
- case SCI_BAUD: // Baud rate
+ case SCI_BAUD: // Baud rate
break;
- case SCI_SCCR1: // Control 1
+ case SCI_SCCR1: // Control 1
break;
- case SCI_SCCR2: // Control 2
+ case SCI_SCCR2: // Control 2
sci_ctl2 = data;
update_interrupts();
break;
- case SCI_SCSR: // Status
+ case SCI_SCSR: // Status
break;
- case SCI_SCDR: // Data
-// printf("LK201: sending %02x\n", data);
+ case SCI_SCDR: // Data
+// printf("LK201: sending %02x\n", data);
transmit_register_setup(data);
sci_status &= ~(SCSR_TC | SCSR_TDRE);
m_maincpu->set_input_line(M68HC05EG_INT_CPI, 0);
@@ -663,7 +663,7 @@ WRITE8_MEMBER( lk201_device::sci_w )
break;
}
-// printf("SCI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
+// printf("SCI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
}
READ8_MEMBER( lk201_device::spi_r )
@@ -672,20 +672,20 @@ READ8_MEMBER( lk201_device::spi_r )
switch (offset)
{
- case SPI_SPCR: // Control
+ case SPI_SPCR: // Control
break;
- case SPI_SPSR: // Status
+ case SPI_SPSR: // Status
incoming = spi_status;
spi_status &= ~SPSR_SPIF;
break;
- case SPI_SPDR: // Data I/O
+ case SPI_SPDR: // Data I/O
incoming = spi_data;
break;
}
-// printf("SPI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
+// printf("SPI read @ %x = %02x (PC=%x)\n", offset, incoming, m_maincpu->pc());
return incoming;
}
@@ -694,13 +694,13 @@ WRITE8_MEMBER( lk201_device::spi_w )
{
switch (offset)
{
- case SPI_SPCR: // Control
+ case SPI_SPCR: // Control
break;
- case SPI_SPSR: // Status (read only)
+ case SPI_SPSR: // Status (read only)
break;
- case SPI_SPDR: // Data I/O
+ case SPI_SPDR: // Data I/O
spi_data = data;
// Transfer only allowed if transfer complete flag has been acknowleged
@@ -718,6 +718,5 @@ WRITE8_MEMBER( lk201_device::spi_w )
break;
}
-// printf("SPI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
+// printf("SPI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
}
-
diff --git a/src/mess/machine/dgn_beta.c b/src/mess/machine/dgn_beta.c
index 6b2c4e9092b..aaf8fae22d0 100644
--- a/src/mess/machine/dgn_beta.c
+++ b/src/mess/machine/dgn_beta.c
@@ -931,7 +931,7 @@ void dgn_beta_state::dgn_beta_line_interrupt (int data)
/********************************* Machine/Driver Initialization ****************************************/
void dgn_beta_state::machine_reset()
-{
+{
wd2797_device *fdc = machine().device<wd2797_device>(FDC_TAG);
pia6821_device *pia_0 = machine().device<pia6821_device>( PIA_0_TAG );
pia6821_device *pia_1 = machine().device<pia6821_device>( PIA_1_TAG );
diff --git a/src/mess/machine/hp48.c b/src/mess/machine/hp48.c
index 9c3c4774ec5..8dbe6e01130 100644
--- a/src/mess/machine/hp48.c
+++ b/src/mess/machine/hp48.c
@@ -450,7 +450,7 @@ WRITE8_MEMBER(hp48_state::hp48_io_w)
bit 1: transmitting
bit 2: irq enable on buffer empty
bit 3: led on (direct mode)
- on HP49 G, flash ROM write enable
+ on HP49 G, flash ROM write enable
- 0x1d: I/R output buffer
*/
@@ -576,10 +576,10 @@ READ8_MEMBER(hp48_state::hp48_io_r)
READ8_MEMBER(hp48_state::hp48_bank_r)
{
- /* HP48 GX
+ /* HP48 GX
bit 0: ignored
bits 2-5: bank number
- bit 6: enable
+ bit 6: enable
*/
/* HP49 G
@@ -746,7 +746,7 @@ void hp48_state::hp48_apply_modules()
else
{
/* NCE3 */
- nce3_enable = m_bank_switch >> 6;
+ nce3_enable = m_bank_switch >> 6;
LOG(( "hp48_apply_modules: A19 disabled, NCE3 %s\n", nce3_enable ? "enabled" : "disabled" ));
space.install_read_bank( 0, 0x7ffff, 0, 0x80000, "bank5" );
}
@@ -1130,7 +1130,7 @@ void hp48_state::hp48_machine_start( hp48_models model )
m_model = model;
/* internal RAM */
- ram_size =
+ ram_size =
HP49_G_MODEL ? (512 * 1024) :
HP48_GX_MODEL ? (128 * 1024) : (32 * 1024);
@@ -1139,7 +1139,7 @@ void hp48_state::hp48_machine_start( hp48_models model )
/* ROM load */
- rom_size =
+ rom_size =
HP49_G_MODEL ? (2048 * 1024) :
HP48_S_SERIES ? (256 * 1024) : (512 * 1024);
m_rom = auto_alloc_array(machine(), UINT8, 2 * rom_size);
diff --git a/src/mess/machine/mac.c b/src/mess/machine/mac.c
index f02923073b4..1c144ec4b99 100644
--- a/src/mess/machine/mac.c
+++ b/src/mess/machine/mac.c
@@ -1242,7 +1242,7 @@ READ8_MEMBER(mac_state::mac_via_in_a_pmu)
// printf("VIA1 IN_A (PC %x)\n", m_maincpu->safe_pc());
#if LOG_ADB
-// printf("Read PM data %x\n", m_pm_data_recv);
+// printf("Read PM data %x\n", m_pm_data_recv);
#endif
return m_pm_data_recv;
}
@@ -1312,7 +1312,7 @@ READ8_MEMBER(mac_state::mac_via_in_b_via2pmu)
READ8_MEMBER(mac_state::mac_via_in_b_pmu)
{
int val = 0;
-// printf("Read VIA B: PM_ACK %x\n", m_pm_ack);
+// printf("Read VIA B: PM_ACK %x\n", m_pm_ack);
val = 0x80 | 0x04 | m_pm_ack; // SCC wait/request (bit 2 must be set at 900c1a or startup tests always fail)
// printf("VIA1 IN_B = %02x (PC %x)\n", val, m_maincpu->safe_pc());
@@ -1358,7 +1358,7 @@ WRITE8_MEMBER(mac_state::mac_via_out_a_pmu)
// printf("VIA1 OUT A: %02x (PC %x)\n", data, m_maincpu->safe_pc());
#if LOG_ADB
-// printf("%02x to PM\n", data);
+// printf("%02x to PM\n", data);
#endif
m_pm_data_send = data;
return;
@@ -1657,7 +1657,7 @@ WRITE8_MEMBER(mac_state::mac_via2_out_b)
WRITE8_MEMBER(mac_state::mac_via2_out_b_pmu)
{
-// logerror("VIA2 OUT B PMU: %02x (PC %x)\n", data, m_maincpu->pc());
+// logerror("VIA2 OUT B PMU: %02x (PC %x)\n", data, m_maincpu->pc());
if ((data & 4) && !(m_pm_req & 4))
{
diff --git a/src/mess/machine/mackbd.h b/src/mess/machine/mackbd.h
index d52363e59f5..feb0eac27e0 100644
--- a/src/mess/machine/mackbd.h
+++ b/src/mess/machine/mackbd.h
@@ -12,13 +12,13 @@
//**************************************************************************
#define MCFG_MACKBD_ADD(_tag) \
- MCFG_DEVICE_ADD(_tag, MACKBD, 0)
+ MCFG_DEVICE_ADD(_tag, MACKBD, 0)
#define MCFG_MACKBD_REPLACE(_tag) \
- MCFG_DEVICE_REPLACE(_tag, MACKBD, 0)
+ MCFG_DEVICE_REPLACE(_tag, MACKBD, 0)
#define MCFG_MACKBD_REMOVE(_tag) \
- MCFG_DEVICE_REMOVE(_tag)
+ MCFG_DEVICE_REMOVE(_tag)
#define MCFG_MACKBD_CLKOUT_HANDLER(_devcb) \
devcb = &mackbd_device::set_clkout_handler(*device, DEVCB2_##_devcb);
diff --git a/src/mess/machine/mega32x.c b/src/mess/machine/mega32x.c
index 6a3fe6efda5..52af206c90a 100644
--- a/src/mess/machine/mega32x.c
+++ b/src/mess/machine/mega32x.c
@@ -1582,14 +1582,14 @@ void sega_32x_device::_32x_interrupt_cb(int scanline, int irq6)
_32x_check_framebuffer_swap(scanline >= irq6);
m_32x_hcount_compare_val++;
-
+
if (m_32x_hcount_compare_val >= m_32x_hcount_reg)
{
m_32x_hcount_compare_val = -1;
-
+
if (scanline < 224 || m_sh2_hint_in_vbl)
{
- if (m_sh2_master_hint_enable)
+ if (m_sh2_master_hint_enable)
m_master_cpu->set_input_line(SH2_HINT_IRQ_LEVEL, ASSERT_LINE);
if (m_sh2_slave_hint_enable)
m_slave_cpu->set_input_line(SH2_HINT_IRQ_LEVEL, ASSERT_LINE);
diff --git a/src/mess/machine/mega32x.h b/src/mess/machine/mega32x.h
index cf877add84e..ad10677c403 100644
--- a/src/mess/machine/mega32x.h
+++ b/src/mess/machine/mega32x.h
@@ -41,9 +41,9 @@ public:
// set some variables at start, depending on region (shall be moved to a device interface?)
void set_framerate(int rate) { m_framerate = rate; }
void set_32x_pal(bool pal) { m_32x_pal = pal ? 1 : 0; }
- void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this get set at start only
- void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
-
+ void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this get set at start only
+ void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
+
// static configuration
static void static_set_palette_tag(device_t &device, const char *tag);
@@ -192,7 +192,7 @@ private:
UINT16 *m_32x_display_dram, *m_32x_access_dram;
UINT16* m_32x_palette;
UINT16* m_32x_palette_lookup;
-
+
required_device<palette_device> m_palette;
};
diff --git a/src/mess/machine/megacd.h b/src/mess/machine/megacd.h
index 8d53cb088fb..3d0d7ef18f4 100644
--- a/src/mess/machine/megacd.h
+++ b/src/mess/machine/megacd.h
@@ -111,8 +111,8 @@ public:
// set some variables at start, depending on region (shall be moved to a device interface?)
void set_framerate(int rate) { m_framerate = rate; }
- void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this gets set at start only
- void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
+ void set_total_scanlines(int total) { m_base_total_scanlines = total; } // this gets set at start only
+ void update_total_scanlines(bool mode3) { m_total_scanlines = mode3 ? (m_base_total_scanlines * 2) : m_base_total_scanlines; } // this gets set at each EOF
void SCD_GET_TILE_INFO_16x16_1x1( int& tile_region, int& tileno, int tile_index );
void SCD_GET_TILE_INFO_32x32_1x1( int& tile_region, int& tileno, int tile_index );
diff --git a/src/mess/machine/micropolis.h b/src/mess/machine/micropolis.h
index 8ac0325280f..9989c18a65e 100644
--- a/src/mess/machine/micropolis.h
+++ b/src/mess/machine/micropolis.h
@@ -38,7 +38,7 @@ struct micropolis_interface
***************************************************************************/
class micropolis_device : public device_t,
- public micropolis_interface
+ public micropolis_interface
{
public:
micropolis_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
diff --git a/src/mess/machine/nes.c b/src/mess/machine/nes.c
index eb66a84fc6f..382d8639855 100644
--- a/src/mess/machine/nes.c
+++ b/src/mess/machine/nes.c
@@ -159,7 +159,7 @@ void nes_state::machine_start()
// install additional handlers (read_h, read_ex, write_ex)
if (m_cartslot->get_pcb_id() == STD_NROM368 || m_cartslot->get_pcb_id() == GG_NROM || m_cartslot->get_pcb_id() == CAMERICA_ALADDIN || m_cartslot->get_pcb_id() == SUNSOFT_DCS
- || m_cartslot->get_pcb_id() == BANDAI_DATACH || m_cartslot->get_pcb_id() == BANDAI_KARAOKE || m_cartslot->get_pcb_id() == AVE_MAXI15
+ || m_cartslot->get_pcb_id() == BANDAI_DATACH || m_cartslot->get_pcb_id() == BANDAI_KARAOKE || m_cartslot->get_pcb_id() == AVE_MAXI15
|| m_cartslot->get_pcb_id() == KAISER_KS7022 || m_cartslot->get_pcb_id() == KAISER_KS7031 || m_cartslot->get_pcb_id() == BMC_VT5201
|| m_cartslot->get_pcb_id() == UNL_LH32 || m_cartslot->get_pcb_id() == UNL_LH10 || m_cartslot->get_pcb_id() == UNL_2708
|| m_cartslot->get_pcb_id() == UNL_43272 || m_cartslot->get_pcb_id() == BMC_G63IN1 || m_cartslot->get_pcb_id() == BMC_8157
diff --git a/src/mess/machine/oric.c b/src/mess/machine/oric.c
index ef9fe8165ab..9930f2a351d 100644
--- a/src/mess/machine/oric.c
+++ b/src/mess/machine/oric.c
@@ -55,7 +55,7 @@ void oric_state::oric_refresh_ints()
if (m_is_telestrat==0)
{
/* oric 1 or oric atmos */
-
+
/* if floppy disc hardware is disabled, do not allow interrupts from it */
if ((m_io_floppy->manager().safe_to_read()) && ((m_io_floppy->read() & 0x07) == ORIC_FLOPPY_INTERFACE_NONE))
{
diff --git a/src/mess/machine/partner.c b/src/mess/machine/partner.c
index d61bc9b3bef..9f07f149d23 100644
--- a/src/mess/machine/partner.c
+++ b/src/mess/machine/partner.c
@@ -77,7 +77,7 @@ void partner_state::partner_window_2(UINT8 bank_num, UINT16 offset,UINT8 *rom)
}
}
-READ8_MEMBER(partner_state::partner_floppy_r){
+READ8_MEMBER(partner_state::partner_floppy_r){
if (offset<0x100) {
switch(offset & 3) {
case 0x00 : return m_fdc->status_r(space, 0);
diff --git a/src/mess/machine/pecom.c b/src/mess/machine/pecom.c
index 5cc255a06b4..e9333b15bc0 100644
--- a/src/mess/machine/pecom.c
+++ b/src/mess/machine/pecom.c
@@ -170,7 +170,7 @@ WRITE8_MEMBER(pecom_state::sc_w )
// DMA acknowledge clears the DMAOUT request
m_cdp1802->set_input_line(COSMAC_INPUT_LINE_DMAOUT, CLEAR_LINE);
break;
-
+
case COSMAC_STATE_CODE_S3_INTERRUPT:
break;
}
diff --git a/src/mess/machine/sgi.c b/src/mess/machine/sgi.c
index 1240dd5d378..e45be40ecae 100644
--- a/src/mess/machine/sgi.c
+++ b/src/mess/machine/sgi.c
@@ -88,7 +88,7 @@ void sgi_mc_device::device_start()
}
timer_init();
-
+
save_item(NAME(m_nCPUControl0));
save_item(NAME(m_nCPUControl1));
save_item(NAME(m_nWatchdog));
diff --git a/src/mess/machine/sgi.h b/src/mess/machine/sgi.h
index 4109d7cebdf..d56c9ec5887 100644
--- a/src/mess/machine/sgi.h
+++ b/src/mess/machine/sgi.h
@@ -66,7 +66,7 @@ private:
UINT32 m_nDMAMode;
UINT32 m_nDMAZoomByteCnt;
UINT32 m_nDMARunning;
-
+
void update();
TIMER_CALLBACK_MEMBER(update_callback);
void timer_init();
diff --git a/src/mess/machine/smartmed.c b/src/mess/machine/smartmed.c
index fc5b38e8712..fc5fe8a22e3 100644
--- a/src/mess/machine/smartmed.c
+++ b/src/mess/machine/smartmed.c
@@ -76,12 +76,12 @@ const device_type NAND = &device_creator<nand_device>;
nand_device::nand_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, NAND, "NAND Flash Memory", tag, owner, clock, "nand", __FILE__),
- m_write_rnb(*this)
+ m_write_rnb(*this)
{
}
nand_device::nand_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
- m_write_rnb(*this)
+ m_write_rnb(*this)
{
}
diff --git a/src/mess/machine/sms.c b/src/mess/machine/sms.c
index 9a11d1de4ae..7a542265938 100644
--- a/src/mess/machine/sms.c
+++ b/src/mess/machine/sms.c
@@ -698,9 +698,9 @@ void sms_state::setup_media_slots()
// a bunch of SG1000 carts (compatible with SG1000 Mark III) use their own RAM...
// TODO: are BASIC and Music actually compatible with Mark III??
if (m_cartslot->get_type() == SEGA8_BASIC_L3 ||
- m_cartslot->get_type() == SEGA8_MUSIC_EDITOR ||
- m_cartslot->get_type() == SEGA8_DAHJEE_TYPEA ||
- m_cartslot->get_type() == SEGA8_DAHJEE_TYPEB)
+ m_cartslot->get_type() == SEGA8_MUSIC_EDITOR ||
+ m_cartslot->get_type() == SEGA8_DAHJEE_TYPEA ||
+ m_cartslot->get_type() == SEGA8_DAHJEE_TYPEB)
{
m_mem_device_enabled |= ENABLE_EXT_RAM;
}
@@ -773,10 +773,10 @@ MACHINE_START_MEMBER(sms_state,sms)
// the "call $4010" without a following RET statement. That is basically
// a bug in the program code. The only way this cartridge could have run
// successfully on a real unit is if the RAM would be initialized with
- // a F0 pattern on power up; F0 = RET P.
- // This initialization breaks the some Game Gear games though (e.g.
+ // a F0 pattern on power up; F0 = RET P.
+ // This initialization breaks the some Game Gear games though (e.g.
// tempojr), suggesting that not all systems had the same initialization.
- // For the moment we apply this to systems that have the Japanese SMS
+ // For the moment we apply this to systems that have the Japanese SMS
// cartridge slot.
if (m_has_jpn_sms_cart_slot)
{
@@ -888,7 +888,7 @@ WRITE8_MEMBER(smssdisp_state::sms_store_cart_select_w)
// - the one with 16 cart slots and 3 card slots;
// - the one with 16 cart slots and 16 card slots.
//
-// On front panel of both models there are only 16 game switches,
+// On front panel of both models there are only 16 game switches,
// that seems to change the active cart/card slot pair or, for the 4th
// game switch onward of the 16-3 model, the active cart slot only.
diff --git a/src/mess/machine/svi318.c b/src/mess/machine/svi318.c
index d9006355ab7..7467bd0e901 100644
--- a/src/mess/machine/svi318.c
+++ b/src/mess/machine/svi318.c
@@ -741,7 +741,7 @@ READ8_MEMBER(svi318_state::svi318_io_ext_r)
{
return 0xff;
}
-
+
fd1793_device *fdc = machine().device<fd1793_device>("wd179x");
switch( offset )
@@ -804,7 +804,7 @@ WRITE8_MEMBER(svi318_state::svi318_io_ext_w)
{
return;
}
-
+
fd1793_device *fdc = machine().device<fd1793_device>("wd179x");
switch( offset )
diff --git a/src/mess/machine/swtpc09.c b/src/mess/machine/swtpc09.c
index 8e27c2224c0..dd3b59a7688 100644
--- a/src/mess/machine/swtpc09.c
+++ b/src/mess/machine/swtpc09.c
@@ -1,6 +1,6 @@
/***************************************************************************
- swtpc09 machine file
- Robert Justice ,2009-2014
+ swtpc09 machine file
+ Robert Justice ,2009-2014
****************************************************************************/
@@ -21,7 +21,7 @@
#define VERBOSE 0
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
+#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
/******* MC6840 PTM on MPID Board *******/
@@ -41,7 +41,7 @@ WRITE8_MEMBER( swtpc09_state::ptm_o1_callback )
m_pia_counter++;
//pia_counter = pia_counter && 0xff;
- if (m_pia_counter & 0x80) pia->ca1_w(1);
+ if (m_pia_counter & 0x80) pia->ca1_w(1);
}
WRITE8_MEMBER( swtpc09_state::ptm_o3_callback )
@@ -54,9 +54,9 @@ WRITE8_MEMBER( swtpc09_state::ptm_o3_callback )
WRITE_LINE_MEMBER( swtpc09_state::ptm_irq )
{
if (state)
- swtpc09_irq_handler(PTM_IRQ, ASSERT_LINE);
+ swtpc09_irq_handler(PTM_IRQ, ASSERT_LINE);
else
- swtpc09_irq_handler(PTM_IRQ, CLEAR_LINE);
+ swtpc09_irq_handler(PTM_IRQ, CLEAR_LINE);
}
/******* MC6821 PIA on MPID Board *******/
@@ -64,7 +64,7 @@ WRITE_LINE_MEMBER( swtpc09_state::ptm_irq )
READ8_MEMBER( swtpc09_state::pia0_a_r )
{
- return m_pia_counter;
+ return m_pia_counter;
}
READ8_MEMBER( swtpc09_state::pia0_ca1_r )
@@ -74,12 +74,12 @@ READ8_MEMBER( swtpc09_state::pia0_ca1_r )
WRITE_LINE_MEMBER( swtpc09_state::pia0_irq_a )
{
- pia6821_device *pia = machine().device<pia6821_device>("pia");
+ pia6821_device *pia = machine().device<pia6821_device>("pia");
if ( pia->irq_a_state())
- swtpc09_irq_handler(PIA_IRQ, ASSERT_LINE);
+ swtpc09_irq_handler(PIA_IRQ, ASSERT_LINE);
else
- swtpc09_irq_handler(PIA_IRQ, CLEAR_LINE);
+ swtpc09_irq_handler(PIA_IRQ, CLEAR_LINE);
}
@@ -90,14 +90,14 @@ WRITE_LINE_MEMBER( swtpc09_state::acia_interrupt )
{
if (state)
{
- swtpc09_irq_handler(ACIA_IRQ, ASSERT_LINE);
+ swtpc09_irq_handler(ACIA_IRQ, ASSERT_LINE);
LOG(("swtpc09_acia_irq_assert\n"));
- }
+ }
else
{
- swtpc09_irq_handler(ACIA_IRQ, CLEAR_LINE);
+ swtpc09_irq_handler(ACIA_IRQ, CLEAR_LINE);
LOG(("swtpc09_acia_irq_clear\n"));
- }
+ }
}
/*********************************************************************/
@@ -107,17 +107,17 @@ WRITE_LINE_MEMBER( swtpc09_state::acia_interrupt )
/* DMF2 dma extended address register */
READ8_MEMBER ( swtpc09_state::dmf2_dma_address_reg_r )
{
- return m_fdc_dma_address_reg;
+ return m_fdc_dma_address_reg;
}
WRITE8_MEMBER ( swtpc09_state::dmf2_dma_address_reg_w )
{
- m_fdc_dma_address_reg = data;
-
+ m_fdc_dma_address_reg = data;
+
// bit 4 controls a gate enable/disable for DMF2 fdc irq line
if ((m_fdc_dma_address_reg & 0x10) && (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2))
- swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); //then clear the irq to cpu
-
+ swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE); //then clear the irq to cpu
+
LOG(("swtpc09_dmf2_dma_address_reg_w %02X\n", data));
}
@@ -134,31 +134,31 @@ WRITE8_MEMBER ( swtpc09_state::dmf2_control_reg_w )
switch (data & 0x0F)
{
- case 0x0e:
- m_fdc->set_drive(0);
- // need to set drive ready as sw checks before doing anything
- machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
+ case 0x0e:
+ m_fdc->set_drive(0);
+ // need to set drive ready as sw checks before doing anything
+ machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
break;
- case 0x0d:
- m_fdc->set_drive(1);
- machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
+ case 0x0d:
+ m_fdc->set_drive(1);
+ machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
break;
- case 0x0b:
- m_fdc->set_drive(2);
- machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
- break;
+ case 0x0b:
+ m_fdc->set_drive(2);
+ machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
+ break;
- case 0x07:
- m_fdc->set_drive(3);
- machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
- break;
+ case 0x07:
+ m_fdc->set_drive(3);
+ machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
+ break;
default:
break;
- }
+ }
- // ignore side select in emulation due to sector numbering
+ // ignore side select in emulation due to sector numbering
////side select
//if (!(data & 0x10)) {
// wd17xx_set_side(fdc, 1);
@@ -168,15 +168,15 @@ WRITE8_MEMBER ( swtpc09_state::dmf2_control_reg_w )
//}
- /* bit 5 dden select */
+ /* bit 5 dden select */
if (!(data & 0x20)) {
- m_fdc->dden_w(0);
- LOG(("Density single\n"));
+ m_fdc->dden_w(0);
+ LOG(("Density single\n"));
}
if (data & 0x20) {
- m_fdc->dden_w(1);
- LOG(("Density double\n"));
+ m_fdc->dden_w(1);
+ LOG(("Density double\n"));
}
}
@@ -184,10 +184,10 @@ WRITE8_MEMBER ( swtpc09_state::dmf2_control_reg_w )
void swtpc09_state::swtpc09_fdc_dma_transfer()
{
UINT8 *RAM = memregion("maincpu")->base();
- UINT32 offset;
+ UINT32 offset;
address_space &space = m_maincpu->space(AS_PROGRAM);
- offset = (m_fdc_dma_address_reg & 0x0f)<<16;
+ offset = (m_fdc_dma_address_reg & 0x0f)<<16;
if (m_m6844_channel[0].active == 1) //active dma transfer
{
@@ -211,12 +211,12 @@ void swtpc09_state::swtpc09_fdc_dma_transfer()
if (m_m6844_channel[0].counter == 0) // dma transfer has finished
{
- m_m6844_channel[0].control |= 0x80; // set dend flag
- if (m_m6844_interrupt & 0x01) // interrupt for channel 0 is enabled?
- {
- m_m6844_interrupt |= 0x80; // set bit 7 to indicate active interrupt
- swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
- }
+ m_m6844_channel[0].control |= 0x80; // set dend flag
+ if (m_m6844_interrupt & 0x01) // interrupt for channel 0 is enabled?
+ {
+ m_m6844_interrupt |= 0x80; // set bit 7 to indicate active interrupt
+ swtpc09_irq_handler(DMAC_IRQ, ASSERT_LINE);
+ }
}
}
@@ -230,26 +230,26 @@ void swtpc09_state::swtpc09_irq_handler(UINT8 peripheral, UINT8 state)
switch (state)
{
case ASSERT_LINE:
- m_interrupt |= peripheral;
- break;
+ m_interrupt |= peripheral;
+ break;
case CLEAR_LINE:
- m_interrupt &= (~peripheral & 0x3f);
- break;
- }
-
- if (!m_active_interrupt && m_interrupt) //no active interrupt and it needs to be asserted
- {
- m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
- m_active_interrupt=TRUE;
- LOG(("swtpc09_irq_assert %02X\n", peripheral));
- }
+ m_interrupt &= (~peripheral & 0x3f);
+ break;
+ }
+
+ if (!m_active_interrupt && m_interrupt) //no active interrupt and it needs to be asserted
+ {
+ m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
+ m_active_interrupt=TRUE;
+ LOG(("swtpc09_irq_assert %02X\n", peripheral));
+ }
else if (m_active_interrupt && !m_interrupt) //active interrupt and it needs to be cleared
{
m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
LOG(("swtpc09_irq_clear %02X\n", peripheral));
m_active_interrupt=FALSE;
- }
+ }
}
/******* WD1791 FDC *******/
@@ -258,61 +258,61 @@ const wd17xx_interface swtpc09_wd17xx_interface =
{
DEVCB_NULL,
DEVCB_DRIVER_LINE_MEMBER(swtpc09_state, fdc_intrq_w),
- DEVCB_DRIVER_LINE_MEMBER(swtpc09_state, fdc_drq_w),
+ DEVCB_DRIVER_LINE_MEMBER(swtpc09_state, fdc_drq_w),
{FLOPPY_0, FLOPPY_1, FLOPPY_2, FLOPPY_3 }
};
/* handlers for fdc */
WRITE_LINE_MEMBER( swtpc09_state::fdc_intrq_w )
{
- LOG(("swtpc09_fdc_intrq_w %02X\n", state));
+ LOG(("swtpc09_fdc_intrq_w %02X\n", state));
if ( m_system_type == UNIFLEX_DMF3 ) //IRQ from 1791 is connect into VIA ca2
{
- if (state)
- {
- m_fdc_status |= 0x40;
+ if (state)
+ {
+ m_fdc_status |= 0x40;
m_via->write_cb2(0); //fdc interrupt is connected to CA1
- m_dmf3_via_porta &= 0xfb; //clear pa3
+ m_dmf3_via_porta &= 0xfb; //clear pa3
//m_via->write_porta(m_dmf3_via_porta); //and connected to PA3
- //swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
+ //swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
}
else
{
- m_fdc_status &= ~0x40;
+ m_fdc_status &= ~0x40;
m_via->write_cb2(1);
m_dmf3_via_porta |= 0x04; //and connected to PA3
//m_via->write_porta(m_dmf3_via_porta); //and connected to PA3
- //swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
+ //swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
}
- }
+ }
else if ( m_system_type == FLEX_DC4_PIAIDE ) //for dc4 emulate irq jumper out
{
- if (state)
- {
- m_fdc_status |= 0x40;
+ if (state)
+ {
+ m_fdc_status |= 0x40;
}
else
{
- m_fdc_status &= ~0x40;
+ m_fdc_status &= ~0x40;
}
}
else //for dmf2 it is connected directly to cpu via a gate
{
- if (state)
- {
- m_fdc_status |= 0x40;
+ if (state)
+ {
+ m_fdc_status |= 0x40;
if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled
{
- LOG(("swtpc09_fdc_int ** assert\n"));
+ LOG(("swtpc09_fdc_int ** assert\n"));
swtpc09_irq_handler(FDC_IRQ, ASSERT_LINE);
}
}
else
{
- m_fdc_status &= ~0x40;
- if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled
+ m_fdc_status &= ~0x40;
+ if (!(m_fdc_dma_address_reg & 0x10)) // is dmf2 fdc irq enabled
{
- LOG(("swtpc09_fdc_int ** clear\n"));
+ LOG(("swtpc09_fdc_int ** clear\n"));
swtpc09_irq_handler(FDC_IRQ, CLEAR_LINE);
}
}
@@ -323,23 +323,23 @@ WRITE_LINE_MEMBER( swtpc09_state::fdc_drq_w )
{
if (m_system_type == FLEX_DC4_PIAIDE) //for dc4 no dma
{
- if (state)
- {
- m_fdc_status |= 0x80;
- }
- else
- m_fdc_status &= 0x7f;
- }
+ if (state)
+ {
+ m_fdc_status |= 0x80;
+ }
+ else
+ m_fdc_status &= 0x7f;
+ }
else
{
- if (state)
- {
- m_fdc_status |= 0x80;
- swtpc09_fdc_dma_transfer();
- }
- else
- m_fdc_status &= 0x7f;
- }
+ if (state)
+ {
+ m_fdc_status |= 0x80;
+ swtpc09_fdc_dma_transfer();
+ }
+ else
+ m_fdc_status &= 0x7f;
+ }
}
/*********************************************************************/
@@ -364,7 +364,7 @@ WRITE8_MEMBER( swtpc09_state::dmf3_via_write_porta )
//WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_write_ca1 )
//{
-// return m_via_ca1_input;
+// return m_via_ca1_input;
// LOG(("swtpc09_dmf3_via_write_ca1 %02X\n", state));
//}
@@ -372,21 +372,21 @@ WRITE8_MEMBER( swtpc09_state::dmf3_via_write_porta )
WRITE_LINE_MEMBER( swtpc09_state::dmf3_via_irq )
{
if (state)
- swtpc09_irq_handler(VIA_IRQ, ASSERT_LINE);
- else
- swtpc09_irq_handler(VIA_IRQ, CLEAR_LINE);
+ swtpc09_irq_handler(VIA_IRQ, ASSERT_LINE);
+ else
+ swtpc09_irq_handler(VIA_IRQ, CLEAR_LINE);
}
/* DMF3 dma extended address register */
READ8_MEMBER ( swtpc09_state::dmf3_dma_address_reg_r )
{
- return m_fdc_dma_address_reg;
+ return m_fdc_dma_address_reg;
}
WRITE8_MEMBER ( swtpc09_state::dmf3_dma_address_reg_w )
{
- m_fdc_dma_address_reg = data;
- LOG(("swtpc09_dmf3_dma_address_reg_w %02X\n", data));
+ m_fdc_dma_address_reg = data;
+ LOG(("swtpc09_dmf3_dma_address_reg_w %02X\n", data));
}
/* DMF3 fdc control register */
@@ -402,31 +402,31 @@ WRITE8_MEMBER ( swtpc09_state::dmf3_control_reg_w )
switch (data & 0x0F)
{
- case 0x01:
- m_fdc->set_drive(0);
- // need to set drive ready as sw checks before doing anything
- machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
+ case 0x01:
+ m_fdc->set_drive(0);
+ // need to set drive ready as sw checks before doing anything
+ machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
break;
- case 0x02:
- m_fdc->set_drive(1);
- machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
+ case 0x02:
+ m_fdc->set_drive(1);
+ machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
break;
- case 0x04:
- m_fdc->set_drive(2);
- machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
- break;
+ case 0x04:
+ m_fdc->set_drive(2);
+ machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
+ break;
- case 0x08:
- m_fdc->set_drive(3);
- machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
- break;
+ case 0x08:
+ m_fdc->set_drive(3);
+ machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
+ break;
default:
break;
- }
+ }
- // ignore side select in emulation due to sector numbering
+ // ignore side select in emulation due to sector numbering
////side select
//if (!(data & 0x10)) {
// wd17xx_set_side(fdc, 1);
@@ -436,15 +436,15 @@ WRITE8_MEMBER ( swtpc09_state::dmf3_control_reg_w )
//}
- /* bit 5 dden select */
+ /* bit 5 dden select */
if (data & 0x20) {
- m_fdc->dden_w(0);
- LOG(("Density single\n"));
+ m_fdc->dden_w(0);
+ LOG(("Density single\n"));
}
if (!(data & 0x20)) {
- m_fdc->dden_w(1);
- LOG(("Density double\n"));
+ m_fdc->dden_w(1);
+ LOG(("Density double\n"));
}
}
@@ -456,31 +456,31 @@ WRITE8_MEMBER ( swtpc09_state::dc4_control_reg_w )
switch (data & 0x03)
{
- case 0x00:
- m_fdc->set_drive(0);
- // need to set drive ready as sw checks before doing anything
- machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
+ case 0x00:
+ m_fdc->set_drive(0);
+ // need to set drive ready as sw checks before doing anything
+ machine().device<legacy_floppy_image_device>("floppy0")->floppy_drive_set_ready_state(1,0);
break;
- case 0x01:
- m_fdc->set_drive(1);
- machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
+ case 0x01:
+ m_fdc->set_drive(1);
+ machine().device<legacy_floppy_image_device>("floppy1")->floppy_drive_set_ready_state(1,0);
break;
- case 0x02:
- m_fdc->set_drive(2);
- machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
- break;
+ case 0x02:
+ m_fdc->set_drive(2);
+ machine().device<legacy_floppy_image_device>("floppy2")->floppy_drive_set_ready_state(1,0);
+ break;
- case 0x03:
- m_fdc->set_drive(3);
- machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
- break;
+ case 0x03:
+ m_fdc->set_drive(3);
+ machine().device<legacy_floppy_image_device>("floppy3")->floppy_drive_set_ready_state(1,0);
+ break;
default:
break;
- }
+ }
- // ignore side select in emulation due to sector numbering
+ // ignore side select in emulation due to sector numbering
}
@@ -490,7 +490,7 @@ WRITE8_MEMBER ( swtpc09_state::dc4_control_reg_w )
READ8_MEMBER( swtpc09_state::piaide_a_r )
{
- return m_piaide_porta;
+ return m_piaide_porta;
}
READ8_MEMBER( swtpc09_state::piaide_b_r )
@@ -500,43 +500,43 @@ READ8_MEMBER( swtpc09_state::piaide_b_r )
WRITE8_MEMBER( swtpc09_state::piaide_a_w )
{
- m_piaide_porta = data;
+ m_piaide_porta = data;
}
WRITE8_MEMBER( swtpc09_state::piaide_b_w )
{
- int tempidedata;
+ int tempidedata;
- m_piaide_portb = data;
+ m_piaide_portb = data;
- if ((data & 0x40)&&(!(data&0x20))) //cs0=0 cs1=1 bit 5&6
- {
- if (!(data & 0x02)) //rd line bit 1
- {
- tempidedata = m_ide->read_cs0(space, (data&0x1c)>>2, 0xffff);
- LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
- m_piaide_porta = tempidedata & 0x00ff;
- }
- else if (!(data & 0x01)) //wr line bit 0
+ if ((data & 0x40)&&(!(data&0x20))) //cs0=0 cs1=1 bit 5&6
+ {
+ if (!(data & 0x02)) //rd line bit 1
+ {
+ tempidedata = m_ide->read_cs0(space, (data&0x1c)>>2, 0xffff);
+ LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
+ m_piaide_porta = tempidedata & 0x00ff;
+ }
+ else if (!(data & 0x01)) //wr line bit 0
{
m_ide->write_cs0(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
- LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
- }
- }
- else if ((data & 0x20)&&(!(data&0x40))) //cs0=1 cs1=0 bit 5&6
- {
- if (!(data & 0x02)) //rd line bit 1
- {
- tempidedata = m_ide->read_cs1(space, (data&0x1c)>>2, 0xffff);
- LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
- m_piaide_porta = tempidedata & 0x00ff;
- }
- else if (!(data & 0x01)) //wr line bit 0
+ LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
+ }
+ }
+ else if ((data & 0x20)&&(!(data&0x40))) //cs0=1 cs1=0 bit 5&6
+ {
+ if (!(data & 0x02)) //rd line bit 1
+ {
+ tempidedata = m_ide->read_cs1(space, (data&0x1c)>>2, 0xffff);
+ LOG(("swtpc09_ide_bus_r: offset $%02X data %04X\n", (data&0x1c)>>2, tempidedata));
+ m_piaide_porta = tempidedata & 0x00ff;
+ }
+ else if (!(data & 0x01)) //wr line bit 0
{
m_ide->write_cs1(space, (data&0x1c)>>2, m_piaide_porta, 0xffff);
- LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
- }
- }
+ LOG(("swtpc09_ide_bus_w: offset $%02X data %04X\n", (data&0x1c)>>2, m_piaide_porta));
+ }
+ }
}
@@ -547,125 +547,125 @@ WRITE8_MEMBER( swtpc09_state::piaide_b_w )
WRITE8_MEMBER(swtpc09_state::dat_w)
{
- UINT8 a16_to_a19, a12_to_a15;
- UINT8 *RAM = memregion("maincpu")->base();
- UINT32 physical_address, logical_address;
+ UINT8 a16_to_a19, a12_to_a15;
+ UINT8 *RAM = memregion("maincpu")->base();
+ UINT32 physical_address, logical_address;
- address_space &mem = m_maincpu->space(AS_PROGRAM);
+ address_space &mem = m_maincpu->space(AS_PROGRAM);
fd1793_device *fdc = machine().device<fd1793_device>("fdc");
- pia6821_device *pia = machine().device<pia6821_device>("pia");
- ptm6840_device *ptm = machine().device<ptm6840_device>("ptm");
- acia6850_device *acia = machine().device<acia6850_device>("acia");
- via6522_device *via = machine().device<via6522_device>("via");
- pia6821_device *piaide = machine().device<pia6821_device>("piaide");
+ pia6821_device *pia = machine().device<pia6821_device>("pia");
+ ptm6840_device *ptm = machine().device<ptm6840_device>("ptm");
+ acia6850_device *acia = machine().device<acia6850_device>("acia");
+ via6522_device *via = machine().device<via6522_device>("via");
+ pia6821_device *piaide = machine().device<pia6821_device>("piaide");
- a16_to_a19 = data & 0xf0;
- a12_to_a15 = ~data & 0x0f; //lower 4 bits are inverted
- physical_address = ((a16_to_a19 + a12_to_a15) << 12);
- logical_address = offset << 12;
- LOG(("swtpc09_dat_bank_unmap Logical address:%04X\n", offset << 12 ));
- LOG(("swtpc09_dat_bank_set dat:%02X Logical address:%04X Physical address:%05X\n", data, offset << 12, physical_address ));
+ a16_to_a19 = data & 0xf0;
+ a12_to_a15 = ~data & 0x0f; //lower 4 bits are inverted
+ physical_address = ((a16_to_a19 + a12_to_a15) << 12);
+ logical_address = offset << 12;
+ LOG(("swtpc09_dat_bank_unmap Logical address:%04X\n", offset << 12 ));
+ LOG(("swtpc09_dat_bank_set dat:%02X Logical address:%04X Physical address:%05X\n", data, offset << 12, physical_address ));
- // unmap page to be changed
+ // unmap page to be changed
mem.unmap_readwrite(offset << 12, (offset << 12)+0x0fff);
- // map in new page
- if (a12_to_a15 == 0x0e) // 0xE000 address range to be mapped in at this page
- {
- if (m_system_type == FLEX_DMF2) // if flex/sbug, map in acia at 0xE004
- {
+ // map in new page
+ if (a12_to_a15 == 0x0e) // 0xE000 address range to be mapped in at this page
+ {
+ if (m_system_type == FLEX_DMF2) // if flex/sbug, map in acia at 0xE004
+ {
mem.nop_readwrite(logical_address+0x000, logical_address+0x003);
- mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
- mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
- mem.nop_readwrite(logical_address+0x006, logical_address+0x07f);
- mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
- mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
- mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
+ mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
+ mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
+ mem.nop_readwrite(logical_address+0x006, logical_address+0x07f);
+ mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
+ mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
+ mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
}
- else if (m_system_type == FLEX_DC4_PIAIDE) // if flex/sbug and dc4 and piaide
- {
+ else if (m_system_type == FLEX_DC4_PIAIDE) // if flex/sbug and dc4 and piaide
+ {
mem.nop_readwrite(logical_address+0x000, logical_address+0x003);
- mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
- mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
- mem.install_write_handler(logical_address+0x014, logical_address+0x014, write8_delegate(FUNC(swtpc09_state::dc4_control_reg_w),this));
- mem.install_readwrite_handler(logical_address+0x018, logical_address+0x01b, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
- //mem.nop_readwrite(logical_address+0x01c, logical_address+0x05f);
- mem.install_readwrite_handler(logical_address+0x060, logical_address+0x06f, read8_delegate(FUNC(pia6821_device::read), piaide), write8_delegate(FUNC(pia6821_device::write), piaide));
- //mem.nop_readwrite(logical_address+0x070, logical_address+0x07f);
- mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
- mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
- //mem.nop_readwrite(logical_address+0x0a0, logical_address+0x7ff);
- mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xe800]); //piaide rom
+ mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
+ mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
+ mem.install_write_handler(logical_address+0x014, logical_address+0x014, write8_delegate(FUNC(swtpc09_state::dc4_control_reg_w),this));
+ mem.install_readwrite_handler(logical_address+0x018, logical_address+0x01b, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
+ //mem.nop_readwrite(logical_address+0x01c, logical_address+0x05f);
+ mem.install_readwrite_handler(logical_address+0x060, logical_address+0x06f, read8_delegate(FUNC(pia6821_device::read), piaide), write8_delegate(FUNC(pia6821_device::write), piaide));
+ //mem.nop_readwrite(logical_address+0x070, logical_address+0x07f);
+ mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
+ mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
+ //mem.nop_readwrite(logical_address+0x0a0, logical_address+0x7ff);
+ mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xe800]); //piaide rom
}
else // assume unibug, map in acia at 0xE000
{
- mem.install_readwrite_handler(logical_address+0x000, logical_address+0x000, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w), acia));
- mem.install_readwrite_handler(logical_address+0x001, logical_address+0x001, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w), acia));
+ mem.install_readwrite_handler(logical_address+0x000, logical_address+0x000, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w), acia));
+ mem.install_readwrite_handler(logical_address+0x001, logical_address+0x001, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w), acia));
mem.nop_readwrite(logical_address+0x002, logical_address+0x07f);
- mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
- mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
- mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
- }
- }
- else if (a12_to_a15 == 0x0f) // 0xF000 address range to be mapped in at this page
- {
- if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 conroller this is the map
- {
- mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
- mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
- mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
- mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
- //mem.nop_readwrite(logical_address+0x042, logical_address+0x7ff);
- mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
- mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
- }
- else if (m_system_type == FLEX_DC4_PIAIDE) // 2k ram for piaide on s09 board
- {
- //mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
- //mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
- //mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
- //mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
- mem.install_ram(logical_address+0x000, logical_address+0x7ff, &RAM[0xf000]);
- mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
- mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
- }
- else // assume DMF3 controller
- {
+ mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
+ mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
+ mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
+ }
+ }
+ else if (a12_to_a15 == 0x0f) // 0xF000 address range to be mapped in at this page
+ {
+ if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 conroller this is the map
+ {
mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
- mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
- mem.install_readwrite_handler(logical_address+0x024, logical_address+0x024, read8_delegate(FUNC(swtpc09_state::dmf3_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_control_reg_w),this));
- mem.install_readwrite_handler(logical_address+0x025, logical_address+0x025, read8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_w),this));
- //mem.nop_readwrite(logical_address+0x030, logical_address+0x03f);
- mem.install_readwrite_handler(logical_address+0x040, logical_address+0x04f, read8_delegate(FUNC(via6522_device::read), via), write8_delegate(FUNC(via6522_device::write), via));
- //mem.nop_readwrite(logical_address+0x050, logical_address+0x7ff);
- mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
- mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
- }
- }
- else if (offset==0x0f) // then we need to leave in top part of ram and dat write
- {
- mem.install_ram(logical_address, logical_address+0x0eff, 0, 0, &RAM[physical_address]);
- mem.install_rom(logical_address+0xf00, logical_address+0xfff, 0, 0, &RAM[0xff00]);
- mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
+ mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
+ mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
+ mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
+ //mem.nop_readwrite(logical_address+0x042, logical_address+0x7ff);
+ mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
+ mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
+ }
+ else if (m_system_type == FLEX_DC4_PIAIDE) // 2k ram for piaide on s09 board
+ {
+ //mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
+ //mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
+ //mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
+ //mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
+ mem.install_ram(logical_address+0x000, logical_address+0x7ff, &RAM[0xf000]);
+ mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
+ mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
+ }
+ else // assume DMF3 controller
+ {
+ mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
+ mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
+ mem.install_readwrite_handler(logical_address+0x024, logical_address+0x024, read8_delegate(FUNC(swtpc09_state::dmf3_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_control_reg_w),this));
+ mem.install_readwrite_handler(logical_address+0x025, logical_address+0x025, read8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_w),this));
+ //mem.nop_readwrite(logical_address+0x030, logical_address+0x03f);
+ mem.install_readwrite_handler(logical_address+0x040, logical_address+0x04f, read8_delegate(FUNC(via6522_device::read), via), write8_delegate(FUNC(via6522_device::write), via));
+ //mem.nop_readwrite(logical_address+0x050, logical_address+0x7ff);
+ mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
+ mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
+ }
+ }
+ else if (offset==0x0f) // then we need to leave in top part of ram and dat write
+ {
+ mem.install_ram(logical_address, logical_address+0x0eff, 0, 0, &RAM[physical_address]);
+ mem.install_rom(logical_address+0xf00, logical_address+0xfff, 0, 0, &RAM[0xff00]);
+ mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
}
- else // all the rest is treated as ram, 1MB ram emulated
- {
- mem.install_ram(logical_address, logical_address+0x0fff, &RAM[physical_address]);
- }
+ else // all the rest is treated as ram, 1MB ram emulated
+ {
+ mem.install_ram(logical_address, logical_address+0x0fff, &RAM[physical_address]);
+ }
-// unused code to limit to 256k ram
+// unused code to limit to 256k ram
// else if (!(a12_to_a15 & 0x0c) ) // limit ram to 256k || a12_to_a15 == 0x02
// {
// memory_install_ram(space, logical_address, logical_address+0x0fff, 0, 0, &RAM[physical_address]);
-// }
+// }
//
-// else // all the rest is treated as unallocated
+// else // all the rest is treated as unallocated
// {
// memory_nop_readwrite(space, logical_address, logical_address+0x0fff, 0, 0);
-// }
+// }
}
@@ -720,11 +720,11 @@ READ8_MEMBER( swtpc09_state::m6844_r )
/* a read here clears the DMA end flag */
m_m6844_channel[offset - 0x10].control &= ~0x80;
- if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear
- {
- swtpc09_irq_handler(0x01, CLEAR_LINE);
- m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7
- LOG(("swtpc09_6844_r interrupt cleared \n"));
+ if (m_m6844_interrupt & 0x80) // if interrupt is active, then clear
+ {
+ swtpc09_irq_handler(0x01, CLEAR_LINE);
+ m_m6844_interrupt &= 0x7f; // clear interrupt indication bit 7
+ LOG(("swtpc09_6844_r interrupt cleared \n"));
}
break;
@@ -746,16 +746,16 @@ READ8_MEMBER( swtpc09_state::m6844_r )
/* 0x17-0x1f not used */
default: break;
}
- //LOG(("swtpc09_6844_r %02X %02X\n", offset, result & 0xff));
+ //LOG(("swtpc09_6844_r %02X %02X\n", offset, result & 0xff));
- if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
- {
- return ~result & 0xff;
+ if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
+ {
+ return ~result & 0xff;
+ }
+ else
+ {
+ return result & 0xff;
}
- else
- {
- return result & 0xff;
- }
}
@@ -763,10 +763,10 @@ WRITE8_MEMBER( swtpc09_state::m6844_w )
{
int i;
- if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
- data = ~data & 0xff;
+ if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 controller data bus is inverted to 6844
+ data = ~data & 0xff;
- LOG(("swtpc09_6844_w %02X %02X\n", offset, data));
+ LOG(("swtpc09_6844_w %02X %02X\n", offset, data));
/* switch off the offset we were given */
switch (offset)
{
@@ -849,7 +849,7 @@ WRITE8_MEMBER( swtpc09_state::m6844_w )
/* interrupt control */
case 0x15:
m_m6844_interrupt = (m_m6844_interrupt & 0x80) | (data & 0x7f);
- LOG(("swtpc09_m_m6844_interrupt_w %02X\n", m_m6844_interrupt));
+ LOG(("swtpc09_m_m6844_interrupt_w %02X\n", m_m6844_interrupt));
break;
/* chaining control */
@@ -865,13 +865,13 @@ WRITE8_MEMBER( swtpc09_state::m6844_w )
DRIVER_INIT_MEMBER( swtpc09_state, swtpc09 )
{
- int i;
- m_pia_counter = 0; // init ptm/pia counter to 0
- m_term_data = 0; // terminal keyboard input
- m_fdc_status = 0; // for floppy controller
- m_system_type = FLEX_DMF2;
- m_interrupt = 0;
- m_active_interrupt = FALSE;
+ int i;
+ m_pia_counter = 0; // init ptm/pia counter to 0
+ m_term_data = 0; // terminal keyboard input
+ m_fdc_status = 0; // for floppy controller
+ m_system_type = FLEX_DMF2;
+ m_interrupt = 0;
+ m_active_interrupt = FALSE;
/* reset the 6844 */
for (i = 0; i < 4; i++)
@@ -887,13 +887,13 @@ DRIVER_INIT_MEMBER( swtpc09_state, swtpc09 )
DRIVER_INIT_MEMBER( swtpc09_state, swtpc09i )
{
- int i;
- m_pia_counter = 0; // init ptm/pia counter to 0
- m_term_data = 0; // terminal keyboard input
- m_fdc_status = 0; // for floppy controller
- m_system_type = FLEX_DC4_PIAIDE;
- m_interrupt = 0;
- m_active_interrupt = FALSE;
+ int i;
+ m_pia_counter = 0; // init ptm/pia counter to 0
+ m_term_data = 0; // terminal keyboard input
+ m_fdc_status = 0; // for floppy controller
+ m_system_type = FLEX_DC4_PIAIDE;
+ m_interrupt = 0;
+ m_active_interrupt = FALSE;
/* reset the 6844 */
for (i = 0; i < 4; i++)
@@ -909,13 +909,13 @@ DRIVER_INIT_MEMBER( swtpc09_state, swtpc09i )
DRIVER_INIT_MEMBER( swtpc09_state, swtpc09u )
{
- int i;
- m_pia_counter = 0; //init ptm/pia counter to 0
- m_term_data = 0; //terminal keyboard input
- m_fdc_status = 0; // for floppy controller
- m_system_type = UNIFLEX_DMF2;
- m_interrupt = 0;
- m_active_interrupt = FALSE;
+ int i;
+ m_pia_counter = 0; //init ptm/pia counter to 0
+ m_term_data = 0; //terminal keyboard input
+ m_fdc_status = 0; // for floppy controller
+ m_system_type = UNIFLEX_DMF2;
+ m_interrupt = 0;
+ m_active_interrupt = FALSE;
/* reset the 6844 */
for (i = 0; i < 4; i++)
@@ -931,14 +931,14 @@ DRIVER_INIT_MEMBER( swtpc09_state, swtpc09u )
DRIVER_INIT_MEMBER( swtpc09_state, swtpc09d3 )
{
- int i;
- m_pia_counter = 0; //init ptm/pia counter to 0
- m_term_data = 0; //terminal keyboard input
- m_fdc_status = 0; // for floppy controller
- m_via_ca1_input = 0;
- m_system_type = UNIFLEX_DMF3;
- m_interrupt = 0;
- m_active_interrupt = FALSE;
+ int i;
+ m_pia_counter = 0; //init ptm/pia counter to 0
+ m_term_data = 0; //terminal keyboard input
+ m_fdc_status = 0; // for floppy controller
+ m_via_ca1_input = 0;
+ m_system_type = UNIFLEX_DMF3;
+ m_interrupt = 0;
+ m_active_interrupt = FALSE;
/* reset the 6844 */
diff --git a/src/mess/machine/thomson.c b/src/mess/machine/thomson.c
index 2d0a5923e42..118d8d19f1b 100644
--- a/src/mess/machine/thomson.c
+++ b/src/mess/machine/thomson.c
@@ -4161,14 +4161,14 @@ void thomson_state::mo6_update_cart_bank()
{
if ( bank_is_read_only )
{
- space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
- space.nop_write( 0xb000, 0xefff);
+ space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.nop_write( 0xb000, 0xefff);
}
else
{
space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
}
}
}
@@ -4186,14 +4186,14 @@ void thomson_state::mo6_update_cart_bank()
{
if (m_to8_cart_vpage < 4)
{
- space.install_write_handler( 0xb000, 0xbfff, write8_delegate(FUNC(thomson_state::mo6_vcart_lo_w),this));
- space.install_write_handler( 0xc000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_vcart_hi_w),this));
+ space.install_write_handler( 0xb000, 0xbfff, write8_delegate(FUNC(thomson_state::mo6_vcart_lo_w),this));
+ space.install_write_handler( 0xc000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_vcart_hi_w),this));
}
else
{
- space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
}
}
LOG_BANK(( "mo6_update_cart_bank: update CART bank %i write status to %s\n",
@@ -4210,8 +4210,8 @@ void thomson_state::mo6_update_cart_bank()
{
if ( m_old_cart_bank < 0 || m_old_cart_bank > 3 )
{
- space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
space.nop_write( 0xb000, 0xefff);
}
LOG_BANK(( "mo6_update_cart_bank: CART is external cartridge bank %i (A7CB style)\n", bank ));
@@ -4229,14 +4229,14 @@ void thomson_state::mo6_update_cart_bank()
{
if ( bank_is_read_only )
{
- space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
space.nop_write( 0xb000, 0xefff);
}
else
{
- space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
}
}
LOG_BANK(( "mo6_update_cart_bank: CART is RAM bank %i (MO5 compat.) (%s)\n",
@@ -4247,14 +4247,14 @@ void thomson_state::mo6_update_cart_bank()
{
if ( bank_is_read_only )
{
- space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
space.nop_write( 0xb000, 0xefff);
}
else
{
- space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_readwrite_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_readwrite_bank( 0xc000, 0xefff, MO6_CART_HI );
}
LOG_BANK(( "mo5_update_cart_bank: update CART bank %i write status to %s\n",
m_to8_cart_vpage,
@@ -4281,8 +4281,8 @@ void thomson_state::mo6_update_cart_bank()
{
if ( m_old_cart_bank < 4 || m_old_cart_bank > 7 )
{
- space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
space.install_write_handler( 0xb000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_cartridge_w),this) );
}
LOG_BANK(( "mo6_update_cart_bank: CART is internal ROM bank %i\n", b ));
@@ -4296,10 +4296,10 @@ void thomson_state::mo6_update_cart_bank()
bank = m_thom_cart_bank % m_thom_cart_nb_banks;
if ( bank != m_old_cart_bank )
{
- if ( m_old_cart_bank < 0 || m_old_cart_bank > 3 )
+ if ( m_old_cart_bank < 0 || m_old_cart_bank > 3 )
{
- space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
- space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
+ space.install_read_bank( 0xb000, 0xbfff, MO6_CART_LO );
+ space.install_read_bank( 0xc000, 0xefff, MO6_CART_HI );
space.install_write_handler( 0xb000, 0xefff, write8_delegate(FUNC(thomson_state::mo6_cartridge_w),this) );
space.install_read_handler( 0xbffc, 0xbfff, read8_delegate(FUNC(thomson_state::mo6_cartridge_r),this) );
}
diff --git a/src/mess/machine/ti99/990_hd.h b/src/mess/machine/ti99/990_hd.h
index 5445ea45a99..770c2d428d6 100644
--- a/src/mess/machine/ti99/990_hd.h
+++ b/src/mess/machine/ti99/990_hd.h
@@ -14,7 +14,7 @@ class ti990_hdc_device : public device_t
{
public:
ti990_hdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
template<class _Object> static devcb2_base &static_set_int_callback(device_t &device, _Object object) { return downcast<ti990_hdc_device &>(device).m_interrupt_callback.set_callback(object); }
DECLARE_READ16_MEMBER(read);
@@ -62,7 +62,7 @@ private:
/* disk geometry */
unsigned int cylinders, heads, sectors_per_track, bytes_per_sector;
};
-
+
UINT16 m_w[8];
devcb2_write_line m_interrupt_callback;
diff --git a/src/mess/machine/ti99/grom.c b/src/mess/machine/ti99/grom.c
index e519c02f6e8..6fce88c1fb6 100644
--- a/src/mess/machine/ti99/grom.c
+++ b/src/mess/machine/ti99/grom.c
@@ -94,7 +94,7 @@
*/
ti99_grom_device::ti99_grom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: bus8z_device(mconfig, GROM, "TI-99 GROM device", tag, owner, clock, "ti99_grom", __FILE__),
- m_gromready(*this)
+ m_gromready(*this)
{
}
diff --git a/src/mess/machine/ti99/grom.h b/src/mess/machine/ti99/grom.h
index 38eb39c048a..1599db84dd3 100644
--- a/src/mess/machine/ti99/grom.h
+++ b/src/mess/machine/ti99/grom.h
@@ -40,9 +40,9 @@ class ti99_grom_device : public bus8z_device, ti99grom_config
{
public:
ti99_grom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
template<class _Object> static devcb2_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<ti99_grom_device &>(device).m_gromready.set_callback(object); }
-
+
DECLARE_READ8Z_MEMBER(readz);
DECLARE_WRITE8_MEMBER(write);
diff --git a/src/mess/machine/ti99/gromport.c b/src/mess/machine/ti99/gromport.c
index d8737b56d48..c126ac7bb9f 100644
--- a/src/mess/machine/ti99/gromport.c
+++ b/src/mess/machine/ti99/gromport.c
@@ -1391,15 +1391,15 @@ static GROM_CONFIG(grom7_config)
*/
static MACHINE_CONFIG_FRAGMENT( ti99_cartridge )
MCFG_GROM_ADD( GROM3_TAG, grom3_config )
- MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
+ MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
MCFG_GROM_ADD( GROM4_TAG, grom4_config )
- MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
+ MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
MCFG_GROM_ADD( GROM5_TAG, grom5_config )
- MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
+ MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
MCFG_GROM_ADD( GROM6_TAG, grom6_config )
- MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
+ MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
MCFG_GROM_ADD( GROM7_TAG, grom7_config )
- MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
+ MCFG_GROM_READY_CALLBACK(WRITELINE(ti99_cartridge_device, ready_line))
MACHINE_CONFIG_END
machine_config_constructor ti99_cartridge_device::device_mconfig_additions() const
@@ -2428,7 +2428,7 @@ rpk* rpk_reader::open(emu_options &options, const char *filename, const char *sy
catch (rpk_exception &exp)
{
newrpk->close();
- if (layout_xml != NULL) xml_file_free(layout_xml);
+ if (layout_xml != NULL) xml_file_free(layout_xml);
if (zipfile != NULL) zip_file_close(zipfile);
if (layout_text != NULL) global_free_array(layout_text);
@@ -2436,7 +2436,7 @@ rpk* rpk_reader::open(emu_options &options, const char *filename, const char *sy
throw exp;
}
- if (layout_xml != NULL) xml_file_free(layout_xml);
+ if (layout_xml != NULL) xml_file_free(layout_xml);
if (zipfile != NULL) zip_file_close(zipfile);
if (layout_text != NULL) global_free_array(layout_text);
diff --git a/src/mess/machine/ti99/speech8.h b/src/mess/machine/ti99/speech8.h
index ffcfabb89af..9e57dec76f6 100644
--- a/src/mess/machine/ti99/speech8.h
+++ b/src/mess/machine/ti99/speech8.h
@@ -27,7 +27,7 @@ class ti998_spsyn_device : public bus8z_device
{
public:
ti998_spsyn_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
template<class _Object> static devcb2_base &set_ready_wr_callback(device_t &device, _Object object) { return downcast<ti998_spsyn_device &>(device).m_ready.set_callback(object); }
DECLARE_READ8Z_MEMBER(readz);
diff --git a/src/mess/machine/x68k_kbd.c b/src/mess/machine/x68k_kbd.c
index 8bea0665d7a..6888867c092 100644
--- a/src/mess/machine/x68k_kbd.c
+++ b/src/mess/machine/x68k_kbd.c
@@ -355,9 +355,9 @@ void x68k_state::x68k_keyboard_push_scancode(unsigned char code)
//m_mfp.rsr |= 0x80; // Buffer full
//if(ioport("options")->read() & 0x01)
//{
- // m_current_vector[6] = 0x4c;
- // m_maincpu->set_input_line_and_vector(6,ASSERT_LINE,0x4c);
- // logerror("MFP: Receive buffer full IRQ sent\n");
+ // m_current_vector[6] = 0x4c;
+ // m_maincpu->set_input_line_and_vector(6,ASSERT_LINE,0x4c);
+ // logerror("MFP: Receive buffer full IRQ sent\n");
//}
}
}
diff --git a/src/mess/machine/zx8302.h b/src/mess/machine/zx8302.h
index 9ca86201fa1..4575e52b136 100644
--- a/src/mess/machine/zx8302.h
+++ b/src/mess/machine/zx8302.h
@@ -64,7 +64,7 @@
#define MCFG_ZX8302_OUT_NETOUT_CB(_devcb) \
devcb = &zx8302_device::set_out_netout_callback(*device, DEVCB2_##_devcb);
-
+
#define MCFG_ZX8302_OUT_MDSELCK_CB(_devcb) \
devcb = &zx8302_device::set_out_mdselck_callback(*device, DEVCB2_##_devcb);
@@ -79,7 +79,7 @@
#define MCFG_ZX8302_OUT_RAW1_CB(_devcb) \
devcb = &zx8302_device::set_out_raw1_callback(*device, DEVCB2_##_devcb);
-
+
#define MCFG_ZX8302_IN_RAW1_CB(_devcb) \
devcb = &zx8302_device::set_in_raw1_callback(*device, DEVCB2_##_devcb);
@@ -102,7 +102,7 @@ class zx8302_device : public device_t,
public:
// construction/destruction
zx8302_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
static void set_rtc_clock(device_t &device, int rtc_clock) { downcast<zx8302_device &>(device).m_rtc_clock = rtc_clock; }
template<class _Object> static devcb2_base &set_out_ipl1l_callback(device_t &device, _Object object) { return downcast<zx8302_device &>(device).m_out_ipl1l_cb.set_callback(object); }
template<class _Object> static devcb2_base &set_out_baudx4_callback(device_t &device, _Object object) { return downcast<zx8302_device &>(device).m_out_baudx4_cb.set_callback(object); }
@@ -239,9 +239,9 @@ private:
UINT8 m_status; // status register
// IPC communication state
- int m_comdata_from_ipc; // pending data from IPC->68000
- int m_comdata_to_cpu; // communication data IPC->68000
- int m_comdata_to_ipc; // communication data 68000->IPC
+ int m_comdata_from_ipc; // pending data from IPC->68000
+ int m_comdata_to_cpu; // communication data IPC->68000
+ int m_comdata_to_ipc; // communication data 68000->IPC
int m_comctl; // communication control
int m_ipc_state; // communication state
int m_ipc_busy; // IPC busy