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-rw-r--r--src/mess/drivers/a7800.c12
-rw-r--r--src/mess/drivers/adam.c150
-rw-r--r--src/mess/drivers/alphasma.c16
-rw-r--r--src/mess/drivers/altos5.c10
-rw-r--r--src/mess/drivers/apc.c154
-rw-r--r--src/mess/drivers/apple3.c2
-rw-r--r--src/mess/drivers/bw2.c56
-rw-r--r--src/mess/drivers/ng_aes.c242
-rw-r--r--src/mess/drivers/pc100.c64
-rw-r--r--src/mess/drivers/pc9801.c2
10 files changed, 354 insertions, 354 deletions
diff --git a/src/mess/drivers/a7800.c b/src/mess/drivers/a7800.c
index 47a88b0013e..514d3276e32 100644
--- a/src/mess/drivers/a7800.c
+++ b/src/mess/drivers/a7800.c
@@ -9,14 +9,14 @@
2002/05/13 kubecj added more banks for bankswitching
added PAL machine description
changed clock to be precise
-
- 2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
- color palette with hue shift/start
- based on observation of several
- systems across multiple displays
+
+ 2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
+ color palette with hue shift/start
+ based on observation of several
+ systems across multiple displays
2012/11/09 Robert Tuccitto Fixed 3 degree hue begin point
- miscalculation of color palette
+ miscalculation of color palette
***************************************************************************/
diff --git a/src/mess/drivers/adam.c b/src/mess/drivers/adam.c
index 67d09b499d5..bacab0adc91 100644
--- a/src/mess/drivers/adam.c
+++ b/src/mess/drivers/adam.c
@@ -626,18 +626,18 @@ WRITE8_MEMBER( adam_state::mioc_w )
{
/*
- bit description
+ bit description
- 0 Lower memory option 0
- 1 Lower memory option 1
- 2 Upper memory option 0
- 3 Upper memory option 1
- 4
- 5
- 6
- 7
+ 0 Lower memory option 0
+ 1 Lower memory option 1
+ 2 Upper memory option 0
+ 3 Upper memory option 1
+ 4
+ 5
+ 6
+ 7
- */
+ */
m_mioc = data;
}
@@ -666,18 +666,18 @@ WRITE8_MEMBER( adam_state::adamnet_w )
{
/*
- bit description
+ bit description
- 0 Network reset
- 1 EOS enable
- 2
- 3
- 4
- 5
- 6
- 7
+ 0 Network reset
+ 1 EOS enable
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
- */
+ */
if (BIT(m_an, 0) && !BIT(data, 0))
{
@@ -698,18 +698,18 @@ WRITE8_MEMBER( adam_state::m6801_p1_w )
{
/*
- bit description
+ bit description
- 0 BA8
- 1 BA9
- 2 BA10
- 3 BA11
- 4 BA12
- 5 BA13
- 6 BA14
- 7 BA15
+ 0 BA8
+ 1 BA9
+ 2 BA10
+ 3 BA11
+ 4 BA12
+ 5 BA13
+ 6 BA14
+ 7 BA15
- */
+ */
m_ba = (data << 8) | (m_ba & 0xff);
}
@@ -723,15 +723,15 @@ READ8_MEMBER( adam_state::m6801_p2_r )
{
/*
- bit description
+ bit description
- 0 M6801 mode bit 0
- 1 M6801 mode bit 1
- 2 M6801 mode bit 2
- 3 NET RXD
- 4
+ 0 M6801 mode bit 0
+ 1 M6801 mode bit 1
+ 2 M6801 mode bit 2
+ 3 NET RXD
+ 4
- */
+ */
UINT8 data = M6801_MODE_7;
@@ -750,15 +750,15 @@ WRITE8_MEMBER( adam_state::m6801_p2_w )
{
/*
- bit description
+ bit description
- 0 _DMA
- 1
- 2 _BWR
- 3
- 4 NET TXD
+ 0 _DMA
+ 1
+ 2 _BWR
+ 3
+ 4 NET TXD
- */
+ */
// DMA
m_dma = BIT(data, 0);
@@ -779,18 +779,18 @@ READ8_MEMBER( adam_state::m6801_p3_r )
{
/*
- bit description
+ bit description
- 0 BD0
- 1 BD1
- 2 BD2
- 3 BD3
- 4 BD4
- 5 BD5
- 6 BD6
- 7 BD7
+ 0 BD0
+ 1 BD1
+ 2 BD2
+ 3 BD3
+ 4 BD4
+ 5 BD5
+ 6 BD6
+ 7 BD7
- */
+ */
return m_data_out;
}
@@ -804,18 +804,18 @@ WRITE8_MEMBER( adam_state::m6801_p3_w )
{
/*
- bit description
+ bit description
- 0 BD0
- 1 BD1
- 2 BD2
- 3 BD3
- 4 BD4
- 5 BD5
- 6 BD6
- 7 BD7
+ 0 BD0
+ 1 BD1
+ 2 BD2
+ 3 BD3
+ 4 BD4
+ 5 BD5
+ 6 BD6
+ 7 BD7
- */
+ */
m_data_in = data;
}
@@ -829,18 +829,18 @@ WRITE8_MEMBER( adam_state::m6801_p4_w )
{
/*
- bit description
+ bit description
- 0 BA0
- 1 BA1
- 2 BA2
- 3 BA3
- 4 BA4
- 5 BA5
- 6 BA6
- 7 BA7
+ 0 BA0
+ 1 BA1
+ 2 BA2
+ 3 BA3
+ 4 BA4
+ 5 BA5
+ 6 BA6
+ 7 BA7
- */
+ */
m_ba = (m_ba & 0xff00) | data;
}
@@ -1168,7 +1168,7 @@ static MACHINE_CONFIG_START( adam, adam_state )
MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_LEFT_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot1_intf, adam_slot1_devices, "adamlink", NULL)
MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_CENTER_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot2_intf, adam_slot2_devices, NULL, NULL)
MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_RIGHT_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot3_intf, adam_slot3_devices, "ram", NULL)
-
+
// internal ram
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("64K")
diff --git a/src/mess/drivers/alphasma.c b/src/mess/drivers/alphasma.c
index ce0456aa66e..9f649d96c3c 100644
--- a/src/mess/drivers/alphasma.c
+++ b/src/mess/drivers/alphasma.c
@@ -4,10 +4,10 @@
08/28/2012 Skeleton driver
- TODO:
- - define video HW capabilities
- - "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
- is actually a r/w bank register.
+ TODO:
+ - define video HW capabilities
+ - "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
+ is actually a r/w bank register.
****************************************************************************/
@@ -30,7 +30,7 @@ public:
virtual void machine_start();
virtual void palette_init();
-// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};
@@ -41,8 +41,8 @@ static ADDRESS_MAP_START(alphasmart_mem, AS_PROGRAM, 8, alphasmart_state)
ADDRESS_MAP_END
static ADDRESS_MAP_START(alphasmart_io, AS_IO, 8, alphasmart_state)
-// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
-// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
+// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
+// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
ADDRESS_MAP_END
/* Input ports */
@@ -79,7 +79,7 @@ static MACHINE_CONFIG_START( alphasmart, alphasmart_state )
MCFG_CPU_PROGRAM_MAP(alphasmart_mem)
MCFG_CPU_IO_MAP(alphasmart_io)
MCFG_CPU_CONFIG(alphasmart_hc11_config)
-// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
+// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
MCFG_HD44780_ADD("hd44780", alphasmart_4line_display)
diff --git a/src/mess/drivers/altos5.c b/src/mess/drivers/altos5.c
index f4aa618fe31..dc445117f6d 100644
--- a/src/mess/drivers/altos5.c
+++ b/src/mess/drivers/altos5.c
@@ -1,6 +1,6 @@
/***************************************************************************
- Altos 5-15
+ Altos 5-15
****************************************************************************/
@@ -19,7 +19,7 @@ public:
DECLARE_READ8_MEMBER(altos_2f_r);
DECLARE_WRITE8_MEMBER( kbd_put );
- UINT8 m_term_data;
+ UINT8 m_term_data;
required_device<cpu_device> m_maincpu;
virtual void machine_reset();
};
@@ -48,7 +48,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(altos5_io, AS_IO, 8, altos5_state)
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x2e, 0x2e) AM_DEVWRITE(TERMINAL_TAG, generic_terminal_device, write)
- AM_RANGE(0x2f, 0x2f) AM_READ(altos_2f_r)
+ AM_RANGE(0x2f, 0x2f) AM_READ(altos_2f_r)
ADDRESS_MAP_END
/* Input ports */
@@ -67,9 +67,9 @@ static MACHINE_CONFIG_START( altos5, altos5_state )
MCFG_CPU_ADD("maincpu", Z80, XTAL_16MHz / 4)
MCFG_CPU_PROGRAM_MAP(altos5_mem)
MCFG_CPU_IO_MAP(altos5_io)
-
+
/* video hardware */
- MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
+ MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
MACHINE_CONFIG_END
diff --git a/src/mess/drivers/apc.c b/src/mess/drivers/apc.c
index abe49007c4c..4c808150436 100644
--- a/src/mess/drivers/apc.c
+++ b/src/mess/drivers/apc.c
@@ -1,50 +1,50 @@
/***************************************************************************
- Advanced Personal Computer (c) 1982 NEC
-
- preliminary driver by Angelo Salese
-
- TODO:
- - video emulation
- - Floppy device
- - keyboard
- - Understand interrupt sources
- - NMI seems valid, dumps a x86 stack to vram?
- - Unknown RTC device type;
- - What are exactly APU and MPU devices? They sounds scary ...
- - DMA hook-ups
- - serial ports
- - parallel ports
- - Extract info regarding Hard Disk functionality
- - Various unknown ports
- - What kind of external ROM actually maps at 0xa****?
+ Advanced Personal Computer (c) 1982 NEC
+
+ preliminary driver by Angelo Salese
+
+ TODO:
+ - video emulation
+ - Floppy device
+ - keyboard
+ - Understand interrupt sources
+ - NMI seems valid, dumps a x86 stack to vram?
+ - Unknown RTC device type;
+ - What are exactly APU and MPU devices? They sounds scary ...
+ - DMA hook-ups
+ - serial ports
+ - parallel ports
+ - Extract info regarding Hard Disk functionality
+ - Various unknown ports
+ - What kind of external ROM actually maps at 0xa****?
============================================================================
- front ^
- |
- card
- ----
- 69PFCU 7220 PFCU1R 2764
- 69PTS 7220
- -
- 69PFB2 8086/8087 DFBU2J PFBU2L 2732
- 69SNB RAM
+ front ^
+ |
+ card
+ ----
+ 69PFCU 7220 PFCU1R 2764
+ 69PTS 7220
+ -
+ 69PFB2 8086/8087 DFBU2J PFBU2L 2732
+ 69SNB RAM
----------------------------------------------------------------------------
- i/o memory map (preliminary):
- 0x00 - 0x1f DMA
- 0x20 - 0x23 i8259 master
- 0x28 - 0x2f i8259 slave (even), pit8253 (odd)
- 0x30 - 0x37 serial i8251, even #1 / odd #2
- 0x38 - 0x3f DMA segments
- 0x40 - 0x43 upd7220, even chr / odd bitmap
- 0x48 - 0x4f keyboard
- 0x50 - 0x53 upd765
- 0x58 rtc
- 0x5a - 0x5e APU
- 0x60 MPU (melody)
- 0x61 - 0x67 (Mirror of pit8253?)
- 0x68 - 0x6f parallel port
+ i/o memory map (preliminary):
+ 0x00 - 0x1f DMA
+ 0x20 - 0x23 i8259 master
+ 0x28 - 0x2f i8259 slave (even), pit8253 (odd)
+ 0x30 - 0x37 serial i8251, even #1 / odd #2
+ 0x38 - 0x3f DMA segments
+ 0x40 - 0x43 upd7220, even chr / odd bitmap
+ 0x48 - 0x4f keyboard
+ 0x50 - 0x53 upd765
+ 0x58 rtc
+ 0x5a - 0x5e APU
+ 0x60 MPU (melody)
+ 0x61 - 0x67 (Mirror of pit8253?)
+ 0x68 - 0x6f parallel port
----------------------------------------------------------------------------
0xfe3c2: checks if the floppy has a valid string for booting (either "CP/M-86"
@@ -172,33 +172,33 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
int xi,yi;
int x;
UINT8 char_size;
-// UINT8 interlace_on;
+// UINT8 interlace_on;
-// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
-// return;
+// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
+// return;
-// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
+// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
char_size = 16;
for(x=0;x<pitch;x++)
{
UINT8 tile_data;
-// UINT8 secret,reverse,u_line,v_line;
+// UINT8 secret,reverse,u_line,v_line;
UINT8 color;
UINT8 tile,attr,pen;
UINT32 tile_addr;
-// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
+// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
tile_addr = addr+(x*(1));
tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x007f;
attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff);
-// secret = (attr & 1) ^ 1;
+// secret = (attr & 1) ^ 1;
//blink = attr & 2;
-// reverse = attr & 4;
-// u_line = attr & 8;
-// v_line = attr & 0x10;
+// reverse = attr & 4;
+// u_line = attr & 8;
+// v_line = attr & 0x10;
color = (attr & 0xe0) >> 5;
for(yi=0;yi<lr;yi++)
@@ -207,19 +207,19 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
{
int res_x,res_y;
-// res_x = (x*8+xi) * (state->m_video_ff[WIDTH40_REG]+1);
+// res_x = (x*8+xi) * (state->m_video_ff[WIDTH40_REG]+1);
res_x = (x*8+xi) * (1);
res_y = y*lr+yi;
if(res_x > 640 || res_y > char_size*25) //TODO
continue;
-// tile_data = secret ? 0 : (state->m_char_rom[tile*char_size+interlace_on*0x800+yi]);
+// tile_data = secret ? 0 : (state->m_char_rom[tile*char_size+interlace_on*0x800+yi]);
tile_data = (state->m_char_rom[tile+yi*0x80]);
-// if(reverse) { tile_data^=0xff; }
-// if(u_line && yi == 7) { tile_data = 0xff; }
-// if(v_line) { tile_data|=8; }
+// if(reverse) { tile_data^=0xff; }
+// if(u_line && yi == 7) { tile_data = 0xff; }
+// if(v_line) { tile_data|=8; }
if(cursor_on && cursor_addr == tile_addr)
tile_data^=0xff;
@@ -232,13 +232,13 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
if(pen)
bitmap.pix16(res_y, res_x) = pen;
-// if(state->m_video_ff[WIDTH40_REG])
-// {
-// if(res_x+1 > 640 || res_y > char_size*25) //TODO
-// continue;
+// if(state->m_video_ff[WIDTH40_REG])
+// {
+// if(res_x+1 > 640 || res_y > char_size*25) //TODO
+// continue;
-// bitmap.pix16(res_y, res_x+1) = pen;
-// }
+// bitmap.pix16(res_y, res_x+1) = pen;
+// }
}
}
}
@@ -387,7 +387,7 @@ WRITE8_MEMBER(apc_state::apc_dma_w)
static ADDRESS_MAP_START( apc_map, AS_PROGRAM, 16, apc_state )
AM_RANGE(0x00000, 0x9ffff) AM_RAM
-// AM_RANGE(0xa0000, 0xaffff) space for an external ROM
+// AM_RANGE(0xa0000, 0xaffff) space for an external ROM
AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("ipl", 0)
ADDRESS_MAP_END
@@ -396,18 +396,18 @@ static ADDRESS_MAP_START( apc_io, AS_IO, 16, apc_state )
AM_RANGE(0x00, 0x1f) AM_READWRITE8(apc_dma_r, apc_dma_w,0xff00)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, 0x00ff) // i8259
AM_RANGE(0x28, 0x2f) AM_READWRITE8(apc_port_28_r, apc_port_28_w, 0xffff)
-// 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
+// 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
AM_RANGE(0x38, 0x3f) AM_WRITE8(apc_dma_segments_w,0x00ff)
AM_RANGE(0x40, 0x43) AM_READWRITE8(apc_gdc_r, apc_gdc_w, 0xffff)
// 0x46 UPD7220 reset interrupt
AM_RANGE(0x48, 0x4f) AM_READWRITE8(apc_kbd_r, apc_kbd_w, 0x00ff)
AM_RANGE(0x50, 0x53) AM_DEVICE8("upd765", upd765a_device, map, 0x00ff ) // upd765
-// 0x5a APU data (Arithmetic Processing Unit!)
-// 0x5e APU status/command
+// 0x5a APU data (Arithmetic Processing Unit!)
+// 0x5e APU status/command
AM_RANGE(0x60, 0x67) AM_READWRITE8(apc_port_60_r, apc_port_60_w, 0xffff)
-// 0x60 Melody Processing Unit
-// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
-// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
+// 0x60 Melody Processing Unit
+// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
+// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
ADDRESS_MAP_END
static INPUT_PORTS_START( apc )
@@ -468,15 +468,15 @@ INPUT_PORTS_END
void apc_state::fdc_drq(bool state)
{
-// printf("%02x DRQ\n",state);
-// i8237_dreq0_w(m_dma, state);
+// printf("%02x DRQ\n",state);
+// i8237_dreq0_w(m_dma, state);
m_dmac->dreq1_w(state);
}
void apc_state::fdc_irq(bool state)
{
-// printf("IRQ %d\n",state);
+// printf("IRQ %d\n",state);
pic8259_ir3_w(machine().device("pic8259_slave"), state);
}
@@ -628,7 +628,7 @@ WRITE_LINE_MEMBER(apc_state::apc_dma_hrq_changed)
m_dmac->hack_w(state);
-// printf("%02x HLDA\n",state);
+// printf("%02x HLDA\n",state);
}
WRITE_LINE_MEMBER( apc_state::apc_tc_w )
@@ -655,7 +655,7 @@ WRITE8_MEMBER(apc_state::apc_dma_write_byte)
address_space &program = m_maincpu->space(AS_PROGRAM);
offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
-// printf("%08x %02x\n",addr,data);
+// printf("%08x %02x\n",addr,data);
program.write_byte(addr, data);
}
@@ -673,7 +673,7 @@ WRITE_LINE_MEMBER(apc_state::apc_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma
READ8_MEMBER(apc_state::test_r)
{
-// printf("2dd DACK R\n");
+// printf("2dd DACK R\n");
return m_fdc->dma_r();
}
@@ -767,8 +767,8 @@ ROM_START( apc )
ROM_LOAD16_BYTE( "pfbu2j.bin", 0x00000, 0x001000, CRC(86970df5) SHA1(be59c5dad3bd8afc21e9f2f1404553d4371978be) )
ROM_LOAD16_BYTE( "pfbu2l.bin", 0x00001, 0x001000, CRC(38df2e70) SHA1(a37ccaea00c2b290610d354de08b489fa897ec48) )
-// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
-// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
+// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
+// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
ROM_REGION( 0x2000, "gfx", ROMREGION_ERASE00 )
ROM_LOAD("pfcu1r.bin", 0x000000, 0x002000, CRC(683efa94) SHA1(43157984a1746b2e448f3236f571011af9a3aa73) )
diff --git a/src/mess/drivers/apple3.c b/src/mess/drivers/apple3.c
index 1175bf3fe68..36b75dce5d2 100644
--- a/src/mess/drivers/apple3.c
+++ b/src/mess/drivers/apple3.c
@@ -72,7 +72,7 @@ static MACHINE_CONFIG_START( apple3, apple3_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M6502, 2000000) /* 2 MHz */
MCFG_CPU_PROGRAM_MAP(apple3_map)
-// MCFG_CPU_CONFIG( apple3_m6502_interface )
+// MCFG_CPU_CONFIG( apple3_m6502_interface )
MCFG_CPU_PERIODIC_INT_DRIVER(apple3_state, apple3_interrupt, 192)
MCFG_QUANTUM_TIME(attotime::from_hz(60))
diff --git a/src/mess/drivers/bw2.c b/src/mess/drivers/bw2.c
index 46fe26b2e8c..4c54ec60648 100644
--- a/src/mess/drivers/bw2.c
+++ b/src/mess/drivers/bw2.c
@@ -367,16 +367,16 @@ WRITE8_MEMBER( bw2_state::ppi_pa_w )
{
/*
- PA0 KB0 Keyboard line select 0
- PA1 KB1 Keyboard line select 1
- PA2 KB2 Keyboard line select 2
- PA3 KB3 Keyboard line select 3
- PA4 /DS0 Drive select 0
- PA5 /DS1 Drive select 1
- PA6 Select RS232 connector
- PA7 /STROBE to centronics printer
+ PA0 KB0 Keyboard line select 0
+ PA1 KB1 Keyboard line select 1
+ PA2 KB2 Keyboard line select 2
+ PA3 KB3 Keyboard line select 3
+ PA4 /DS0 Drive select 0
+ PA5 /DS1 Drive select 1
+ PA6 Select RS232 connector
+ PA7 /STROBE to centronics printer
- */
+ */
// keyboard
m_kb = data & 0x0f;
@@ -398,16 +398,16 @@ READ8_MEMBER( bw2_state::ppi_pb_r )
{
/*
- PB0 Keyboard column status of selected line
- PB1 Keyboard column status of selected line
- PB2 Keyboard column status of selected line
- PB3 Keyboard column status of selected line
- PB4 Keyboard column status of selected line
- PB5 Keyboard column status of selected line
- PB6 Keyboard column status of selected line
- PB7 Keyboard column status of selected line
+ PB0 Keyboard column status of selected line
+ PB1 Keyboard column status of selected line
+ PB2 Keyboard column status of selected line
+ PB3 Keyboard column status of selected line
+ PB4 Keyboard column status of selected line
+ PB5 Keyboard column status of selected line
+ PB6 Keyboard column status of selected line
+ PB7 Keyboard column status of selected line
- */
+ */
static const char *const rownames[] = { "Y0", "Y1", "Y2", "Y3", "Y4", "Y5", "Y6", "Y7", "Y8", "Y9" };
@@ -425,12 +425,12 @@ WRITE8_MEMBER( bw2_state::ppi_pc_w )
{
/*
- PC0 Memory bank select
- PC1 Memory bank select
- PC2 Memory bank select
- PC3 Not connected
+ PC0 Memory bank select
+ PC1 Memory bank select
+ PC2 Memory bank select
+ PC3 Not connected
- */
+ */
m_bank = data & 0x07;
}
@@ -439,12 +439,12 @@ READ8_MEMBER( bw2_state::ppi_pc_r )
{
/*
- PC4 BUSY from centronics printer
- PC5 M/FDBK motor feedback
- PC6 RLSD Carrier detect from RS232
- PC7 /PROT Write protected disk
+ PC4 BUSY from centronics printer
+ PC5 M/FDBK motor feedback
+ PC6 RLSD Carrier detect from RS232
+ PC7 /PROT Write protected disk
- */
+ */
UINT8 data = 0;
diff --git a/src/mess/drivers/ng_aes.c b/src/mess/drivers/ng_aes.c
index 0067e200841..989aa9117f9 100644
--- a/src/mess/drivers/ng_aes.c
+++ b/src/mess/drivers/ng_aes.c
@@ -92,22 +92,22 @@ static UINT8* CDEmuReadQChannel(int NeoCDSectorLBA)
if(neocd.cd == NULL) // no cd is there, bail out
return QChannelData;
-// NeoCDSectorLBA
+// NeoCDSectorLBA
switch (CDEmuStatus) {
case reading:
case playing: {
-
+
UINT32 msf;
msf = lba_to_msf_alt(NeoCDSectorLBA+150);
QChannelData[0] = cdrom_get_track(neocd.cd, NeoCDSectorLBA);
-
+
QChannelData[1] = (msf >> 16)&0xff;
QChannelData[2] = (msf >> 8)&0xff;
QChannelData[3] = (msf >> 0)&0xff;
-
+
int elapsedlba;
elapsedlba = NeoCDSectorLBA - neocd.toc->tracks[ cdrom_get_track(neocd.cd, NeoCDSectorLBA) ].physframeofs;
msf = lba_to_msf_alt (elapsedlba);
@@ -115,7 +115,7 @@ static UINT8* CDEmuReadQChannel(int NeoCDSectorLBA)
QChannelData[4] = (msf >> 16)&0xff;
QChannelData[5] = (msf >> 8)&0xff;
QChannelData[6] = (msf >> 0)&0xff;
-
+
if (QChannelData[0]==1)
QChannelData[7] = 0x4;
else
@@ -140,7 +140,7 @@ static UINT8* CDEmuReadTOC(INT32 track)
static unsigned char TOCEntry[4];
- if(neocd.cd == NULL)
+ if(neocd.cd == NULL)
return TOCEntry;
@@ -252,12 +252,12 @@ static void NeoSetTextSlot(INT32 nSlot)
static void MapVectorTable(bool bMapBoardROM)
{
/*
- if (!bMapBoardROM && Neo68KROMActive) {
- SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
- } else {
- SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
- }
- */
+ if (!bMapBoardROM && Neo68KROMActive) {
+ SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
+ } else {
+ SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
+ }
+ */
}
@@ -404,26 +404,26 @@ public:
void ng_aes_state::SekWriteWord(UINT32 a, UINT16 d)
{
-// printf("write word %08x %04x\n", a, d);
+// printf("write word %08x %04x\n", a, d);
curr_space->write_word(a,d);
}
void ng_aes_state::SekWriteByte(UINT32 a, UINT8 d)
{
-// printf("write byte %08x %02x\n", a, d);
+// printf("write byte %08x %02x\n", a, d);
curr_space->write_byte(a,d);
}
UINT32 ng_aes_state::SekReadByte(UINT32 a)
{
-// printf("read byte %08x\n", a);
+// printf("read byte %08x\n", a);
return curr_space->read_byte(a);
}
UINT32 ng_aes_state::SekReadWord(UINT32 a)
{
-// printf("read WORD %08x\n", a);
+// printf("read WORD %08x\n", a);
return curr_space->read_word(a);
}
@@ -947,44 +947,44 @@ void ng_aes_state::NeoCDReadSector()
if ((nff0002 & 0x0500)) {
if (NeoCDAssyStatus == 1 && bNeoCDLoadSector) {
-// if (LC8951RegistersW[10] & 0x80) {
+// if (LC8951RegistersW[10] & 0x80) {
NeoCDSectorLBA++;
NeoCDSectorLBA = CDEmuLoadSector(NeoCDSectorLBA, NeoCDSectorData + 4) -1;
-// }
+// }
if (LC8951RegistersW[10] & 0x80) {
LC8951UpdateHeader();
-
+
LC8951RegistersR[12] = 0x80; // STAT0
LC8951RegistersR[13] = 0; // STAT1
LC8951RegistersR[14] = 0x10; // STAT2
LC8951RegistersR[15] = 0; // STAT3
-
-// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
+
+// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
// CDZ protection hack? (error correction on the CDC should correct this?)
#if 1
if (NeoCDSectorData[4 + 64] == 'g' && !strncmp(NeoCDSectorData + 4, "Copyright by SNK", 16)) {
-// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
-// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
-
+// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
+// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
+
NeoCDSectorData[4 + 64] = 'f';
-
- // LC8951RegistersR[12] = 0x00; // STAT0
+
+ // LC8951RegistersR[12] = 0x00; // STAT0
}
#endif
nIRQAcknowledge &= ~0x20;
NeoCDIRQUpdate(0);
-
+
LC8951RegistersR[1] &= ~0x20;
-// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
+// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
}
}
bNeoCDLoadSector = true;
-// bNeoCDLoadSector = false;
+// bNeoCDLoadSector = false;
}
}
@@ -992,9 +992,9 @@ void ng_aes_state::NeoCDReadSector()
UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
{
-// if ((sekAddress & 0x0FFFFF) < 16)
-// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
-
+// if ((sekAddress & 0x0FFFFF) < 16)
+// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
+
sekAddress ^= 1;
switch (nActiveTransferArea) {
@@ -1012,18 +1012,18 @@ UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
return NeoTextRAM[(sekAddress & 0x3FFFF) >> 1];
break;
}
-
+
return ~0;
}
void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int is_byte_transfer)
{
-// if ((sekAddress & 0x0FFFFF) < 16)
-// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
+// if ((sekAddress & 0x0FFFFF) < 16)
+// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
if (!nTransferWriteEnable) {
-// return;
+// return;
}
int address;
@@ -1033,14 +1033,14 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
switch (nActiveTransferArea) {
case 0: // Sprites
address = (nSpriteTransferBank + (sekAddress & 0x0FFFFF));
-
+
// wtf? is this just due to how we decode the sprite gfx or is something bad happening?
if ((address&3)==0) NeoSpriteRAM[address] = byteValue;
if ((address&3)==1) NeoSpriteRAM[address^3] = byteValue;
if ((address&3)==2) NeoSpriteRAM[address^3] = byteValue;
if ((address&3)==3) NeoSpriteRAM[address] = byteValue;
- // NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
+ // NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
break;
case 1: // ADPCM
YM2610ADPCMAROM[nNeoActiveSlot][nADPCMTransferBank + ((sekAddress & 0x0FFFFF) >> 1)] = byteValue;
@@ -1058,7 +1058,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
break;
case 5: // Text
NeoTextRAM[(sekAddress & 0x3FFFF) >> 1] = byteValue;
-// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
+// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
break;
}
}
@@ -1067,7 +1067,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
{
-// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
switch (sekAddress & 0xFFFF) {
@@ -1077,10 +1077,10 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
// LC8951 registers
case 0x0100:
-// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
return nLC8951Register;
case 0x0102: {
-// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
INT32 reg = LC8951RegistersR[nLC8951Register];
@@ -1101,14 +1101,14 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
// CD mechanism communication
case 0x0160:
- return NeoCDCommsread();
+ return NeoCDCommsread();
case 0x011C: // region
return ~((0x10 | (NeoSystem & 3)) << 8);
}
-// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
return ~0;
}
@@ -1116,20 +1116,20 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
{
-// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
int byteValue = wordValue & 0xff;
switch (sekAddress & 0xFFFE) {
case 0x0002:
-// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
- nff0002 = wordValue;
+// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
+ nff0002 = wordValue;
// LC8951RegistersR[1] |= 0x20;
//if (nff0002 & 0x0500)
- // nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
+ // nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
//else
- // nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
+ // nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
break;
@@ -1182,7 +1182,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x007E:
NeoCDDMAMode = wordValue;
-// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
break;
// upload DMA controller program
@@ -1195,16 +1195,16 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x008A:
case 0x008C:
case 0x008E:
-// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
break;
// LC8951 registers
case 0x0100:
nLC8951Register = byteValue & 0x0F;
-// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
break;
case 0x0102:
-// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
switch (nLC8951Register) {
case 3: // DBCH
LC8951RegistersW[ 3] = byteValue & 0x0F;
@@ -1217,10 +1217,10 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
LC8951RegistersW[ 7] = ~0x00;
LC8951RegistersR[ 1] &= ~0x40;
break;
-// case 10:
-// LC8951RegistersW[nLC8951Register] = byteValue;
-// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
-// break;
+// case 10:
+// LC8951RegistersW[nLC8951Register] = byteValue;
+// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
+// break;
case 11:
LC8951RegistersW[11] = byteValue; // CTRL1
LC8951UpdateHeader();
@@ -1235,43 +1235,43 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break;
case 0x0104:
-// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
nActiveTransferArea = byteValue;
break;
case 0x0120:
-// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
NeoSetSpriteSlot(1);
memset(NeoCDOBJBankUpdate, 0, sizeof(NeoCDOBJBankUpdate));
break;
case 0x0122:
-// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
+// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
break;
case 0x0126:
-// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
curr_space->machine().scheduler().synchronize();
curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
break;
case 0x0128:
-// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
NeoSetTextSlot(1);
break;
case 0x0140:
-// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
video_reset();
break;
case 0x0142:
-// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
break;
case 0x0146:
-// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
curr_space->machine().scheduler().synchronize();
curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
break;
case 0x0148:
-// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
video_reset();
break;
@@ -1284,7 +1284,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break;
case 0x016c:
-// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
+// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
MapVectorTable(!(byteValue == 0xFF));
@@ -1293,7 +1293,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break;
case 0x016e:
-// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
+// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
nTransferWriteEnable = byteValue;
break;
@@ -1301,19 +1301,19 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x0180: {
static UINT8 clara = 0;
if (!byteValue && clara) {
-// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
-// NeoCDCommsReset();
+// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
+// NeoCDCommsReset();
}
- clara = byteValue;
+ clara = byteValue;
break;
}
case 0x0182: {
static UINT8 clara = 0;
if (!byteValue && clara) {
-// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
//ZetReset();
}
- clara = byteValue;
+ clara = byteValue;
break;
}
case 0x01A0:
@@ -1325,10 +1325,10 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
default: {
-// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
+// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
}
}
-
+
}
@@ -1394,12 +1394,12 @@ void ng_aes_state::NeoCDDoDMA()
// Here, only bus access is used to get a rough approximation --
// each read/write takes a single cycle, setup and everything else is ignored.
-// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
+// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
switch (NeoCDDMAMode) {
case 0xCFFD: {
-// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
+// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
// - DMA controller 0x7E -> 0xCFFD (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@@ -1425,7 +1425,7 @@ void ng_aes_state::NeoCDDoDMA()
}
case 0xE2DD: {
-// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
+// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xE2DD (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@@ -1450,7 +1450,7 @@ void ng_aes_state::NeoCDDoDMA()
}
case 0xFC2D: {
-// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
+// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xFC2D (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@@ -1494,7 +1494,7 @@ void ng_aes_state::NeoCDDoDMA()
// - DMA controller program[14] -> 0xFCF5 (PC: 0xC0A1A0)
case 0xFE6D: {
-// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
+// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// - DMA controller 0x7E -> 0xFE6D (PC: 0xC0FD7A)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0FD7C)
@@ -1516,15 +1516,15 @@ void ng_aes_state::NeoCDDoDMA()
if (NeoCDDMAAddress2 == 0x0800) {
// MapVectorTable(false);
-// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
-// extern INT32 bRunPause;
-// bRunPause = 1;
+// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
+// extern INT32 bRunPause;
+// bRunPause = 1;
}
break;
}
case 0xFEF5: {
-// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
+// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xFEF5 (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@@ -1548,7 +1548,7 @@ if (NeoCDDMAAddress2 == 0x0800) {
}
case 0xFFC5: {
-// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
+// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// - DMA controller 0x7E -> 0xFFC5 (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@@ -1592,7 +1592,7 @@ if (NeoCDDMAAddress2 == 0x0800) {
// - DMA controller program[14] -> 0x13FC (PC: 0xC0A1A0)
case 0xFFDD: {
-// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
+// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
// - DMA controller 0x7E -> 0xFFDD (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@@ -1637,14 +1637,14 @@ void ng_aes_state::NeoCDProcessCommand()
case 0:
break;
case 1:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
CDEmuStop();
NeoCDAssyStatus = 0x0E;
bNeoCDLoadSector = false;
break;
case 2:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDCommsStatusFIFO[1] = NeoCDCommsCommandFIFO[3];
switch (NeoCDCommsCommandFIFO[3]) {
@@ -1659,7 +1659,7 @@ void ng_aes_state::NeoCDProcessCommand()
NeoCDCommsStatusFIFO[6] = ChannelData[3] / 10;
NeoCDCommsStatusFIFO[7] = ChannelData[3] % 10;
-
+
NeoCDCommsStatusFIFO[8] = ChannelData[7];
// //bprintf(PRINT_ERROR, _T(" %02i %02i:%02i:%02i %02i:%02i:%02i %02i\n"), ChannelData[0], ChannelData[1], ChannelData[2], ChannelData[3], ChannelData[4], ChannelData[5], ChannelData[6], ChannelData[7]);
@@ -1786,7 +1786,7 @@ void ng_aes_state::NeoCDProcessCommand()
NeoCDSectorLBA -= CD_FRAMES_PREGAP;
CDEmuStartRead();
-// LC8951RegistersR[1] |= 0x20;
+// LC8951RegistersR[1] |= 0x20;
} else {
if (CDEmuGetStatus() == reading) {
@@ -1802,22 +1802,22 @@ void ng_aes_state::NeoCDProcessCommand()
break;
}
case 4:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
CDEmuPause();
break;
case 5:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
-// NeoCDAssyStatus = 9;
-// bNeoCDLoadSector = false;
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// NeoCDAssyStatus = 9;
+// bNeoCDLoadSector = false;
break;
case 6:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 4;
bNeoCDLoadSector = false;
break;
case 7:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 1;
bNeoCDLoadSector = true;
break;
@@ -1830,7 +1830,7 @@ void ng_aes_state::NeoCDProcessCommand()
case 13:
case 14:
case 15:
-// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
+// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 9;
bNeoCDLoadSector = false;
break;
@@ -1853,13 +1853,13 @@ void ng_aes_state::NeoCDCommsControl(UINT8 clock, UINT8 send)
printf("has command %02x\n", NeoCDCommsCommandFIFO[0]);
-// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
+// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
for (INT32 i = 0; i < 9; i++) {
-// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
+// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
sum += NeoCDCommsCommandFIFO[i];
}
sum = ~(sum + 5) & 0x0F;
-// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
+// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
if (sum == NeoCDCommsCommandFIFO[9]) {
printf("request to process command %02x\n", NeoCDCommsCommandFIFO[0]);
@@ -1892,21 +1892,21 @@ void ng_aes_state::NeoCDCommsControl(UINT8 clock, UINT8 send)
// status send complete
-// if (NeoCDCommsStatusFIFO[0] || NeoCDCommsStatusFIFO[1]) {
-// INT32 sum = 0;
+// if (NeoCDCommsStatusFIFO[0] || NeoCDCommsStatusFIFO[1]) {
+// INT32 sum = 0;
//
-// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
-// for (INT32 i = 0; i < 9; i++) {
-// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
-// sum += NeoCDCommsStatusFIFO[i];
-// }
-// sum = ~(sum + 5) & 0x0F;
-// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
-// }
-
-// if (NeoCDAssyStatus == 0xE) {
-// NeoCDAssyStatus = 9;
-// }
+// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
+// for (INT32 i = 0; i < 9; i++) {
+// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
+// sum += NeoCDCommsStatusFIFO[i];
+// }
+// sum = ~(sum + 5) & 0x0F;
+// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
+// }
+
+// if (NeoCDAssyStatus == 0xE) {
+// NeoCDAssyStatus = 9;
+// }
}
}
@@ -1956,7 +1956,7 @@ char* ng_aes_state::LC8915InitTransfer()
}
return NeoCDSectorData + ((LC8951RegistersW[5] << 8) | LC8951RegistersW[4]);
-}
+}
void ng_aes_state::LC8915EndTransfer()
{
@@ -2014,7 +2014,7 @@ READ16_MEMBER(ng_aes_state::neocd_transfer_r)
UINT16 ret = 0x0000;
-
+
if (mem_mask & 0x00ff)
{
ret |= neogeoReadTransfer(0xe00000+ (offset*2)+1, is_byte_transfer) & 0xff;
@@ -2038,7 +2038,7 @@ WRITE16_MEMBER(ng_aes_state::neocd_transfer_w)
{
neogeoWriteTransfer(0xe00000+ (offset*2), data>>8, is_byte_transfer);
}
-
+
if (mem_mask & 0x00ff)
{
neogeoWriteTransfer(0xe00000+ (offset*2)+1, data&0xff, is_byte_transfer);
@@ -2426,10 +2426,10 @@ static ADDRESS_MAP_START( neocd_audio_io_map, AS_IO, 8, ng_aes_state )
AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r)
AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */
-// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
-// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
-// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
-// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
+// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
+// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
+// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
+// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w)
AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */
ADDRESS_MAP_END
diff --git a/src/mess/drivers/pc100.c b/src/mess/drivers/pc100.c
index c4c37e2e2fd..0bfadfa77cf 100644
--- a/src/mess/drivers/pc100.c
+++ b/src/mess/drivers/pc100.c
@@ -2,8 +2,8 @@
NEC PC-100
- preliminary driver by Angelo Salese
- Thanks to Carl for the i8259 tip;
+ preliminary driver by Angelo Salese
+ Thanks to Carl for the i8259 tip;
TODO:
- floppy support (no images available right now);
@@ -20,33 +20,33 @@
F8216: FA cli
F8217: 0A E9 or ch,cl
F8219: 74 15 je 0F8230h
- - Second one is for the vblank irq timing:
- F8238: 8B D3 mov dx,bx
- F823A: 8B D9 mov bx,cx
- F823C: CF iret
- F824D: E4 02 in al,2h
- F824F: 8A E0 mov ah,al
- F8251: B0 EF mov al,0EFh
- F8253: E6 02 out 2h,al
- F8255: BB 00 00 mov bx,0h
- F8258: BA 00 00 mov dx,0h
- F825B: B9 20 4E mov cx,4E20h
- F825E: FB sti
- F825F: E2 FE loop 0F825Fh ;calculates the vblank here
- F8261: FA cli
- F8262: 8A C4 mov al,ah
- F8264: E6 02 out 2h,al
- F8266: 2B D3 sub dx,bx
- F8268: 81 FA 58 1B cmp dx,1B58h
- F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
- F826E: 81 FA 40 1F cmp dx,1F40h
- F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
- F8274: B1 05 mov cl,5h
- F8276: E8 CB 03 call 0F8644h
- F8279: E8 79 FF call 0F81F5h
- F827C: EB FE jmp 0F827Ch
- F827E: B0 FF mov al,0FFh
- fwiw with current timings, we get DX=0x1f09, enough for passing the test;
+ - Second one is for the vblank irq timing:
+ F8238: 8B D3 mov dx,bx
+ F823A: 8B D9 mov bx,cx
+ F823C: CF iret
+ F824D: E4 02 in al,2h
+ F824F: 8A E0 mov ah,al
+ F8251: B0 EF mov al,0EFh
+ F8253: E6 02 out 2h,al
+ F8255: BB 00 00 mov bx,0h
+ F8258: BA 00 00 mov dx,0h
+ F825B: B9 20 4E mov cx,4E20h
+ F825E: FB sti
+ F825F: E2 FE loop 0F825Fh ;calculates the vblank here
+ F8261: FA cli
+ F8262: 8A C4 mov al,ah
+ F8264: E6 02 out 2h,al
+ F8266: 2B D3 sub dx,bx
+ F8268: 81 FA 58 1B cmp dx,1B58h
+ F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
+ F826E: 81 FA 40 1F cmp dx,1F40h
+ F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
+ F8274: B1 05 mov cl,5h
+ F8276: E8 CB 03 call 0F8644h
+ F8279: E8 79 FF call 0F81F5h
+ F827C: EB FE jmp 0F827Ch
+ F827E: B0 FF mov al,0FFh
+ fwiw with current timings, we get DX=0x1f09, enough for passing the test;
****************************************************************************/
@@ -352,9 +352,9 @@ GFXDECODE_END
WRITE8_MEMBER( pc100_state::rtc_porta_w )
{
/*
- ---- -x-- chip select
- ---- --x- read
- ---- ---x write
+ ---- -x-- chip select
+ ---- --x- read
+ ---- ---x write
*/
m_rtc->write_w(data & 1);
diff --git a/src/mess/drivers/pc9801.c b/src/mess/drivers/pc9801.c
index c5862950b46..95b530cee9e 100644
--- a/src/mess/drivers/pc9801.c
+++ b/src/mess/drivers/pc9801.c
@@ -9,7 +9,7 @@
- proper 8251 uart hook-up on keyboard
- boot is too slow right now, might be due of the floppy / HDD devices
- investigate on POR bit
- - Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
+ - Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
TODO (PC-9801RS):
- floppy disk hook-up;