diff options
Diffstat (limited to 'src/lib/netlist/macro')
-rw-r--r-- | src/lib/netlist/macro/nlm_cd4xxx.cpp | 79 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_cd4xxx.h | 3 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_opamp.cpp | 161 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_other.cpp | 5 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.cpp | 61 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.h | 15 |
6 files changed, 282 insertions, 42 deletions
diff --git a/src/lib/netlist/macro/nlm_cd4xxx.cpp b/src/lib/netlist/macro/nlm_cd4xxx.cpp index 95fff085b9e..d169e2790f5 100644 --- a/src/lib/netlist/macro/nlm_cd4xxx.cpp +++ b/src/lib/netlist/macro/nlm_cd4xxx.cpp @@ -6,6 +6,7 @@ #include "devices/nld_system.h" #include "devices/nld_4020.h" #include "devices/nld_4066.h" +#include "devices/nld_4316.h" /* * CD4001BC: Quad 2-Input NOR Buffered B Series Gate @@ -31,14 +32,14 @@ static NETLIST_START(CD4001_DIP) DUMMY_INPUT(VSS) DUMMY_INPUT(VDD) - DIPPINS( /* +--------------+ */ - s1.A, /* A1 |1 ++ 14| VCC */ VSS.I, - s1.B, /* B1 |2 13| A6 */ s4.B, - s1.Q, /* A2 |3 12| Y6 */ s4.A, - s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q, - s2.A, /* A3 |5 10| Y5 */ s3.Q, - s2.B, /* Y3 |6 9| A4 */ s3.B, - VDD.I, /* GND |7 8| Y4 */ s3.A + DIPPINS( /* +--------------+ */ + s1.A, /* A1 |1 ++ 14| VCC */ VSS.I, + s1.B, /* B1 |2 13| A6 */ s4.B, + s1.Q, /* A2 |3 12| Y6 */ s4.A, + s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q, + s2.A, /* A3 |5 10| Y5 */ s3.Q, + s2.B, /* Y3 |6 9| A4 */ s3.B, + VDD.I, /* GND |7 8| Y4 */ s3.A /* +--------------+ */ ) @@ -115,14 +116,14 @@ static NETLIST_START(CD4066_DIP) PARAM(C.BASER, 270.0) PARAM(D.BASER, 270.0) - DIPPINS( /* +--------------+ */ - A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD, - A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL, - B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL, - B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1, - B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2, - C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1, - A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2 + DIPPINS( /* +--------------+ */ + A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD, + A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL, + B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL, + B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1, + B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2, + C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1, + A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2 /* +--------------+ */ ) NETLIST_END() @@ -141,18 +142,47 @@ static NETLIST_START(CD4016_DIP) PARAM(C.BASER, 1000.0) PARAM(D.BASER, 1000.0) - DIPPINS( /* +--------------+ */ - A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD, - A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL, - B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL, - B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1, - B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2, - C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1, - A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2 + DIPPINS( /* +--------------+ */ + A.R.1, /* INOUTA |1 ++ 14| VDD */ A.PS.VDD, + A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL, + B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL, + B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1, + B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2, + C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1, + A.PS.VSS, /* VSS |7 8| INOUTC */ C.R.2 /* +--------------+ */ ) NETLIST_END() +static NETLIST_START(CD4316_DIP) + CD4316_GATE(A) + CD4316_GATE(B) + CD4316_GATE(C) + CD4316_GATE(D) + + NET_C(A.E, B.E, C.E, D.E) + NET_C(A.PS.VDD, B.PS.VDD, C.PS.VDD, D.PS.VDD) + NET_C(A.PS.VSS, B.PS.VSS, C.PS.VSS, D.PS.VSS) + + PARAM(A.BASER, 45.0) + PARAM(B.BASER, 45.0) + PARAM(C.BASER, 45.0) + PARAM(D.BASER, 45.0) + + DIPPINS( /* +--------------+ */ + A.R.2, /* 1Z |1 ++ 16| VCC */ A.PS.VDD, + A.R.1, /* 1Y |2 15| 1S */ A.S, + B.R.1, /* 2Y |3 14| 4S */ D.S, + B.R.2, /* 2Z |4 4316 13| 4Z */ D.R.2, + B.S, /* 2S |5 12| 4Y */ D.R.1, + C.S, /* 3S |6 11| 3Y */ C.R.1, + A.E, /* /E |7 10| 3Z */ C.R.2, + A.PS.VSS, /* GND |8 9| VEE */ VEE + /* +--------------+ */ + ) + +NETLIST_END() + NETLIST_START(CD4XXX_lib) TRUTHTABLE_START(CD4001_NOR, 2, 1, "") @@ -169,5 +199,6 @@ NETLIST_START(CD4XXX_lib) LOCAL_LIB_ENTRY(CD4020_DIP) LOCAL_LIB_ENTRY(CD4016_DIP) LOCAL_LIB_ENTRY(CD4066_DIP) + LOCAL_LIB_ENTRY(CD4316_DIP) NETLIST_END() diff --git a/src/lib/netlist/macro/nlm_cd4xxx.h b/src/lib/netlist/macro/nlm_cd4xxx.h index acc47f45d21..de10ff7a64d 100644 --- a/src/lib/netlist/macro/nlm_cd4xxx.h +++ b/src/lib/netlist/macro/nlm_cd4xxx.h @@ -41,6 +41,9 @@ #define CD4016_DIP(name) \ NET_REGISTER_DEV(CD4016_DIP, name) +#define CD4316_DIP(name) \ + NET_REGISTER_DEV(CD4016_DIP, name) + /* ---------------------------------------------------------------------------- * External declarations * ---------------------------------------------------------------------------*/ diff --git a/src/lib/netlist/macro/nlm_opamp.cpp b/src/lib/netlist/macro/nlm_opamp.cpp index e7571dfd910..08dc5f60b27 100644 --- a/src/lib/netlist/macro/nlm_opamp.cpp +++ b/src/lib/netlist/macro/nlm_opamp.cpp @@ -6,18 +6,18 @@ #include "devices/nld_system.h" /* - * Generic layout with 4 opamps, VCC on pint 4 and GND on pin 11 + * Generic layout with 4 opamps, VCC on pin 4 and GND on pin 11 */ static NETLIST_START(opamp_layout_4_4_11) - DIPPINS( /* +--------------+ */ - A.OUT, /* |1 ++ 14| */ D.OUT, - A.MINUS, /* |2 13| */ D.MINUS, - A.PLUS, /* |3 12| */ D.PLUS, - A.VCC, /* |4 11| */ A.GND, - B.PLUS, /* |5 10| */ C.PLUS, - B.MINUS, /* |6 9| */ C.MINUS, - B.OUT, /* |7 8| */ C.OUT + DIPPINS( /* +--------------+ */ + A.OUT, /* |1 ++ 14| */ D.OUT, + A.MINUS, /* |2 13| */ D.MINUS, + A.PLUS, /* |3 12| */ D.PLUS, + A.VCC, /* |4 11| */ A.GND, + B.PLUS, /* |5 10| */ C.PLUS, + B.MINUS, /* |6 9| */ C.MINUS, + B.OUT, /* |7 8| */ C.OUT /* +--------------+ */ ) NET_C(A.GND, B.GND, C.GND, D.GND) @@ -25,21 +25,100 @@ static NETLIST_START(opamp_layout_4_4_11) NETLIST_END() /* - * Generic layout with 2 opamps, VCC on pint 8 and GND on pin 4 + * Generic layout with 2 opamps, VCC on pin 8 and GND on pin 4 */ static NETLIST_START(opamp_layout_2_8_4) - DIPPINS( /* +--------------+ */ - A.OUT, /* |1 ++ 8| */ A.VCC, - A.MINUS, /* |2 7| */ B.OUT, - A.PLUS, /* |3 6| */ B.MINUS, - A.GND, /* |4 5| */ B.PLUS + DIPPINS( /* +--------------+ */ + A.OUT, /* |1 ++ 8| */ A.VCC, + A.MINUS, /* |2 7| */ B.OUT, + A.PLUS, /* |3 6| */ B.MINUS, + A.GND, /* |4 5| */ B.PLUS /* +--------------+ */ ) NET_C(A.GND, B.GND) NET_C(A.VCC, B.VCC) NETLIST_END() +/* + * Generic layout with 2 opamps, VCC+ on pins 9/13, VCC- on pin 4 and compensation + */ + +static NETLIST_START(opamp_layout_2_13_9_4) + DIPPINS( /* +--------------+ */ + A.MINUS, /* |1 ++ 14| */ A.N2, + A.PLUS, /* |2 13| */ A.VCC, + A.N1, /* |3 12| */ A.OUT, + A.GND, /* |4 11| */ NC, + B.N1, /* |5 10| */ B.OUT, + B.PLUS, /* |6 9| */ B.VCC, + B.MINUS /* |7 8| */ B.N2 + /* +--------------+ */ + ) + NET_C(A.GND, B.GND) +NETLIST_END() + +/* + * Generic layout with 1 opamp, VCC+ on pin 7, VCC- on pin 4 and compensation + */ + +static NETLIST_START(opamp_layout_1_7_4) + DIPPINS( /* +--------------+ */ + OFFSET.N1, /* |1 ++ 8| */ NC, + MINUS, /* |2 7| */ VCC.PLUS, + PLUS, /* |3 6| */ OUT, + VCC.MINUS, /* |4 5| */ OFFSET.N2 + /* +--------------+ */ + ) + NET_C(A.GND, VCC.MINUS) + NET_C(A.VCC, VCC.PLUS) + NET_C(A.MINUS, MINUS) + NET_C(A.PLUS, PLUS) + NET_C(A.OUT, OUT) +NETLIST_END() + +/* + * Generic layout with 1 opamp, VCC+ on pin 8, VCC- on pin 5 and compensation + */ + +static NETLIST_START(opamp_layout_1_8_5) + DIPPINS( /* +--------------+ */ + NC.1, /* |1 10| */ NC.3, + OFFSET.N1, /* |2 9| */ NC.2, + MINUS, /* |3 8| */ VCC.PLUS, + PLUS, /* |4 7| */ OUT, + VCC.MINUS, /* |5 6| */ OFFSET.N2 + /* +--------------+ */ + ) + NET_C(A.GND, VCC.MINUS) + NET_C(A.VCC, VCC.PLUS) + NET_C(A.MINUS, MINUS) + NET_C(A.PLUS, PLUS) + NET_C(A.OUT, OUT) +NETLIST_END() + +/* + * Generic layout with 1 opamp, VCC+ on pin 11, VCC- on pin 6 and compensation + */ + +static NETLIST_START(opamp_layout_1_11_6) + DIPPINS( /* +--------------+ */ + NC.1, /* |1 ++ 14| */ NC.7, + NC.2, /* |2 13| */ NC.6, + OFFSET.N1, /* |3 12| */ NC.5, + MINUS, /* |4 11| */ VCC.PLUS, + PLUS, /* |5 10| */ OUT, + VCC.MINUS, /* |6 9| */ OFFSET.N2, + NC.3, /* |7 8| */ NC.4 + /* +--------------+ */ + ) + NET_C(A.GND, VCC.MINUS) + NET_C(A.VCC, VCC.PLUS) + NET_C(A.MINUS, MINUS) + NET_C(A.PLUS, PLUS) + NET_C(A.OUT, OUT) +NETLIST_END() + static NETLIST_START(MB3614_DIP) OPAMP(A, "MB3614") OPAMP(B, "MB3614") @@ -68,17 +147,67 @@ static NETLIST_START(LM358_DIP) NETLIST_END() +static NETLIST_START(UA741_DIP8) + OPAMP(A, "UA741") + + INCLUDE(opamp_layout_1_7_4) + +NETLIST_END() + +static NETLIST_START(UA741_DIP10) + OPAMP(A, "UA741") + + INCLUDE(opamp_layout_1_8_5) + +NETLIST_END() + +static NETLIST_START(UA741_DIP14) + OPAMP(A, "UA741") + + INCLUDE(opamp_layout_1_11_6) + +NETLIST_END() + +static NETLIST_START(LM747_DIP) + OPAMP(A, "LM747") + OPAMP(B, "LM747") + + INCLUDE(opamp_layout_2_13_9_4) + NET_C(A.VCC, B.VCC) + +NETLIST_END() + +static NETLIST_START(LM747A_DIP) + OPAMP(A, "LM747A") + OPAMP(B, "LM747A") + + INCLUDE(opamp_layout_2_13_9_4) + NET_C(A.VCC, B.VCC) + +NETLIST_END() + NETLIST_START(OPAMP_lib) LOCAL_LIB_ENTRY(opamp_layout_4_4_11) LOCAL_LIB_ENTRY(opamp_layout_2_8_4) + LOCAL_LIB_ENTRY(opamp_layout_2_13_9_4) + LOCAL_LIB_ENTRY(opamp_layout_1_7_4) + LOCAL_LIB_ENTRY(opamp_layout_1_8_5) + LOCAL_LIB_ENTRY(opamp_layout_1_11_6) NET_MODEL("LM324 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.00075)") NET_MODEL("LM358 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.001)") NET_MODEL("MB3614 OPAMP(TYPE=3 VLH=1.4 VLL=0.02 FPF=2 UGF=500k SLEW=0.6M RI=1000k RO=50 DAB=0.0002)") + NET_MODEL("UA741 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=75 DAB=0.0017)") + NET_MODEL("LM747 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=50 DAB=0.0017)") + NET_MODEL("LM747A OPAMP(TYPE=3 VLH=2.0 VLL=2.0 FPF=5 UGF=1000k SLEW=0.7M RI=6000k RO=50 DAB=0.0015)") LOCAL_LIB_ENTRY(MB3614_DIP) LOCAL_LIB_ENTRY(LM324_DIP) LOCAL_LIB_ENTRY(LM358_DIP) - + LOCAL_LIB_ENTRY(UA741_DIP8) + LOCAL_LIB_ENTRY(UA741_DIP10) + LOCAL_LIB_ENTRY(UA741_DIP14) + LOCAL_LIB_ENTRY(LM747_DIP) + LOCAL_LIB_ENTRY(LM747A_DIP) NETLIST_END() diff --git a/src/lib/netlist/macro/nlm_other.cpp b/src/lib/netlist/macro/nlm_other.cpp index 68c0ea57d36..84a3af4dc04 100644 --- a/src/lib/netlist/macro/nlm_other.cpp +++ b/src/lib/netlist/macro/nlm_other.cpp @@ -36,7 +36,7 @@ static NETLIST_START(MC14584B_DIP) s1.A, /* A1 |1 ++ 14| VCC */ VCC.I, s1.Q, /* Y1 |2 13| A6 */ s6.A, s2.A, /* A2 |3 12| Y6 */ s6.Q, - s2.Q, /* Y2 |4 7416 11| A5 */ s5.A, + s2.Q, /* Y2 |4 MC14584B 11| A5 */ s5.A, s3.A, /* A3 |5 10| Y5 */ s5.Q, s3.Q, /* Y3 |6 9| A4 */ s4.A, GND.I, /* GND |7 8| Y4 */ s4.Q @@ -49,7 +49,8 @@ NETLIST_START(otheric_lib) TT_HEAD(" A | Q ") TT_LINE(" 0 | 1 |100") TT_LINE(" 1 | 0 |100") - TT_FAMILY("FAMILY(IVL=2.1 IVH=2.7 OVL=0.05 OVH=4.95 ORL=10.0 ORH=10.0)") + // 2.1V negative going and 2.7V positive going at 5V + TT_FAMILY("FAMILY(FV=0 IVL=0.42 IVH=0.54 OVL=0.05 OVH=0.05 ORL=10.0 ORH=10.0)") TRUTHTABLE_END() LOCAL_LIB_ENTRY(MC14584B_DIP) diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp index 646ae44a86b..2120d88eb3f 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.cpp +++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp @@ -540,6 +540,44 @@ static NETLIST_START(TTL_7486_DIP) ) NETLIST_END() +/* + * DM74260: Dual 5-Input NOR Gates + * _________ + * Y = A+B+C+D+E + * +---+---+---+---+---++---+ + * | A | B | B | B | B || Y | + * +===+===+===+===+===++===+ + * | 0 | 0 | 0 | 0 | 0 || 1 | + * | 0 | 0 | 0 | 0 | 1 || 0 | + * | 0 | 0 | 0 | 1 | 0 || 0 | + * | 0 | 0 | 1 | 0 | 0 || 0 | + * | 0 | 1 | 0 | 0 | 0 || 0 | + * | 1 | 0 | 0 | 0 | 0 || 0 | + * +---+---+---+---+---++---+ + * + * Naming conventions follow Texas Instruments datasheet + * + */ + +static NETLIST_START(TTL_74260_DIP) + TTL_74260_GATE(s1) + TTL_74260_GATE(s2) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + + DIPPINS( /* +--------------+ */ + s1.C, /* C1 |1 ++ 14| VCC */ VCC.I, + s1.D, /* D1 |2 13| B1 */ s1.B, + s1.E, /* E1 |3 12| A1 */ s1.A, + s2.E, /* E2 |4 74260 11| D2 */ s2.D, + s1.Q, /* Y1 |5 10| C2 */ s2.C, + s2.Q, /* Y2 |6 9| B2 */ s2.B, + GND.I, /* GND |7 8| A2 */ s2.A + /* +--------------+ */ + ) +NETLIST_END() + NETLIST_START(TTL74XX_lib) TRUTHTABLE_START(TTL_7400_GATE, 2, 1, "") @@ -788,6 +826,28 @@ NETLIST_START(TTL74XX_lib) TT_FAMILY("74XX") TRUTHTABLE_END() + TRUTHTABLE_START(TTL_74260_GATE, 5, 1, "") + TT_HEAD("A,B,C,D,E|Q ") + TT_LINE("0,0,0,0,0|1|10") + TT_LINE("X,X,X,X,1|0|12") + TT_LINE("X,X,X,1,X|0|12") + TT_LINE("X,X,1,X,X|0|12") + TT_LINE("X,1,X,X,X|0|12") + TT_LINE("1,X,X,X,X|0|12") + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(TTL_74260_NOR, 5, 1, "A,B,C,D,E") + TT_HEAD("A,B,C,D,E|Q ") + TT_LINE("0,0,0,0,0|1|10") + TT_LINE("X,X,X,X,1|0|12") + TT_LINE("X,X,X,1,X|0|12") + TT_LINE("X,X,1,X,X|0|12") + TT_LINE("X,1,X,X,X|0|12") + TT_LINE("1,X,X,X,X|0|12") + TT_FAMILY("74XX") + TRUTHTABLE_END() + LOCAL_LIB_ENTRY(TTL_7400_DIP) LOCAL_LIB_ENTRY(TTL_7402_DIP) LOCAL_LIB_ENTRY(TTL_7404_DIP) @@ -802,4 +862,5 @@ NETLIST_START(TTL74XX_lib) LOCAL_LIB_ENTRY(TTL_7432_DIP) LOCAL_LIB_ENTRY(TTL_7437_DIP) LOCAL_LIB_ENTRY(TTL_7486_DIP) + LOCAL_LIB_ENTRY(TTL_74260_DIP) NETLIST_END() diff --git a/src/lib/netlist/macro/nlm_ttl74xx.h b/src/lib/netlist/macro/nlm_ttl74xx.h index 54b9dfa6e44..44b3db63bd3 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.h +++ b/src/lib/netlist/macro/nlm_ttl74xx.h @@ -185,6 +185,21 @@ #define TTL_7486_DIP(name) \ NET_REGISTER_DEV(TTL_7486_DIP, name) + +#define TTL_74260_GATE(name) \ + NET_REGISTER_DEV(TTL_74260_GATE, name) + +#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \ + NET_REGISTER_DEV(TTL_74260_NOR, name) \ + NET_CONNECT(name, A, cA) \ + NET_CONNECT(name, B, cB) \ + NET_CONNECT(name, C, cC) \ + NET_CONNECT(name, D, cD) \ + NET_CONNECT(name, E, cE) + +#define TTL_74260_DIP(name) \ + NET_REGISTER_DEV(TTL_74260_DIP, name) + /* ---------------------------------------------------------------------------- * External declarations * ---------------------------------------------------------------------------*/ |