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-rw-r--r--src/lib/netlist/macro/modules/nlmod_icl8038_dip.cpp62
-rw-r--r--src/lib/netlist/macro/modules/nlmod_ne556_dip.cpp25
-rw-r--r--src/lib/netlist/macro/modules/nlmod_rtest.cpp13
-rw-r--r--src/lib/netlist/macro/nlm_base.h31
-rw-r--r--src/lib/netlist/macro/nlm_base_lib.cpp (renamed from src/lib/netlist/macro/nlm_base.cpp)99
-rw-r--r--src/lib/netlist/macro/nlm_cd4xxx.cpp202
-rw-r--r--src/lib/netlist/macro/nlm_cd4xxx.h58
-rw-r--r--src/lib/netlist/macro/nlm_cd4xxx_lib.cpp978
-rw-r--r--src/lib/netlist/macro/nlm_opamp.cpp374
-rw-r--r--src/lib/netlist/macro/nlm_opamp.h41
-rw-r--r--src/lib/netlist/macro/nlm_opamp_lib.cpp685
-rw-r--r--src/lib/netlist/macro/nlm_other.cpp55
-rw-r--r--src/lib/netlist/macro/nlm_other.h32
-rw-r--r--src/lib/netlist/macro/nlm_otheric_lib.cpp209
-rw-r--r--src/lib/netlist/macro/nlm_roms_lib.cpp453
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx.cpp1394
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx.h313
-rw-r--r--src/lib/netlist/macro/nlm_ttl74xx_lib.cpp3653
18 files changed, 6152 insertions, 2525 deletions
diff --git a/src/lib/netlist/macro/modules/nlmod_icl8038_dip.cpp b/src/lib/netlist/macro/modules/nlmod_icl8038_dip.cpp
new file mode 100644
index 00000000000..dac830bcb88
--- /dev/null
+++ b/src/lib/netlist/macro/modules/nlmod_icl8038_dip.cpp
@@ -0,0 +1,62 @@
+// license:BSD-3-Clause
+// copyright-holders:Ryan Holtz
+
+#include "devices/net_lib.h"
+
+//
+// ICL8038 is broadly similar to a 566 VCO, and can be simulated partially as such.
+//
+
+NETLIST_START(ICL8038_DIP)
+{
+ VCVS(VI, 1)
+ CCCS(CI1, -1)
+ CCCS(CI2, 2)
+ SYS_COMPD(COMP)
+ SYS_DSW2(SW)
+ VCVS(VO, 1)
+ RES(R_SHUNT, RES_R(50))
+
+ PARAM(VO.RO, 50)
+ PARAM(COMP.MODEL, "FAMILY(TYPE=CUSTOM IVL=0.16 IVH=0.4 OVL=0.01 OVH=0.01 ORL=50 ORH=50)")
+ PARAM(SW.GOFF, 0) // This has to be zero to block current sources
+
+ NET_C(VI.OP, CI1.IN, CI2.IN)
+ NET_C(CI1.OP, VO.IP)
+ NET_C(COMP.Q, SW.I)
+ NET_C(CI2.OP, SW.2)
+ NET_C(COMP.VCC, R_SHUNT.1)
+ NET_C(SW.1, R_SHUNT.2)
+ NET_C(SW.3, VO.IP)
+ NET_C(VO.OP, COMP.IN)
+
+ // Avoid singular Matrix due to G=0 switch
+ RES(RX1, 1e10)
+ RES(RX2, 1e10)
+ NET_C(RX1.1, SW.1)
+ NET_C(RX2.1, SW.3)
+
+ NET_C(COMP.GND, RX1.2, RX2.2)
+
+ RES(R1, 5000)
+ RES(R2, 5000)
+ RES(R3, 5000)
+
+ // Square output wave
+ VCVS(V_SQR, 1)
+ NET_C(COMP.Q, V_SQR.IP)
+
+ NET_C(COMP.GND, SW.GND, VI.ON, VI.IN, CI1.ON, CI2.ON, VO.IN, VO.ON, R2.2, V_SQR.IN, V_SQR.ON)
+ NET_C(COMP.VCC, SW.VCC, R1.2)
+ NET_C(COMP.IP, R1.1, R2.1, R3.1)
+ NET_C(COMP.Q, R3.2)
+
+ ALIAS(11, VI.ON) // GND
+ ALIAS(9, V_SQR.OP) // Square out
+ ALIAS(3, VO.OP) // Triangle out
+ ALIAS(8, VI.IP) // VC
+ ALIAS(4, CI1.IP) // R1
+ ALIAS(5, CI2.IP) // R2
+ ALIAS(10, VO.IP) // C1
+ ALIAS(6, COMP.VCC) // V+
+}
diff --git a/src/lib/netlist/macro/modules/nlmod_ne556_dip.cpp b/src/lib/netlist/macro/modules/nlmod_ne556_dip.cpp
new file mode 100644
index 00000000000..fa6924cda92
--- /dev/null
+++ b/src/lib/netlist/macro/modules/nlmod_ne556_dip.cpp
@@ -0,0 +1,25 @@
+// license:BSD-3-Clause
+// copyright-holders:Ryan Holtz
+//
+
+#include "devices/net_lib.h"
+
+NETLIST_START(NE556_DIP)
+{
+ NE555(A)
+ NE555(B)
+
+ NET_C(A.GND, B.GND)
+ NET_C(A.VCC, B.VCC)
+
+ DIPPINS( /* +--------------+ */
+ A.DISCH, /* 1DISCH |1 ++ 14| VCC */ A.VCC,
+ A.THRESH, /* 1THRES |2 13| 2DISCH */ B.DISCH,
+ A.CONT, /* 1CONT |3 12| 2THRES */ B.THRESH,
+ A.RESET, /* 1RESET |4 NE556 11| 2CONT */ B.CONT,
+ A.OUT, /* 1OUT |5 10| 2RESET */ B.RESET,
+ A.TRIG, /* 1TRIG |6 9| 2OUT */ B.OUT,
+ A.GND, /* GND |7 8| 2TRIG */ B.TRIG
+ /* +--------------+ */
+ )
+}
diff --git a/src/lib/netlist/macro/modules/nlmod_rtest.cpp b/src/lib/netlist/macro/modules/nlmod_rtest.cpp
new file mode 100644
index 00000000000..39c8cd5e63e
--- /dev/null
+++ b/src/lib/netlist/macro/modules/nlmod_rtest.cpp
@@ -0,0 +1,13 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+#include "devices/net_lib.h"
+
+NETLIST_START(RTEST)
+{
+
+ RES(R1, RES_K(10))
+ ALIAS(1, R1.1)
+ ALIAS(2, R1.2)
+
+}
diff --git a/src/lib/netlist/macro/nlm_base.h b/src/lib/netlist/macro/nlm_base.h
deleted file mode 100644
index 6a88ad5a1be..00000000000
--- a/src/lib/netlist/macro/nlm_base.h
+++ /dev/null
@@ -1,31 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#ifndef NLM_BASE_H_
-#define NLM_BASE_H_
-
-/*
- * Provide base environment for netlist
- *
- */
-
-#ifndef __PLIB_PREPROCESSOR__
-
-#include "netlist/nl_setup.h"
-
-/* ----------------------------------------------------------------------------
- * Netlist Macros
- * ---------------------------------------------------------------------------*/
-
-/* ----------------------------------------------------------------------------
- * DIP only macros
- * ---------------------------------------------------------------------------*/
-
-/* ----------------------------------------------------------------------------
- * External declarations
- * ---------------------------------------------------------------------------*/
-
-NETLIST_EXTERNAL(base)
-
-#endif
-
-#endif
diff --git a/src/lib/netlist/macro/nlm_base.cpp b/src/lib/netlist/macro/nlm_base_lib.cpp
index 3a8e2b5eb0d..276e9335422 100644
--- a/src/lib/netlist/macro/nlm_base.cpp
+++ b/src/lib/netlist/macro/nlm_base_lib.cpp
@@ -1,21 +1,27 @@
-// license:GPL-2.0+
+// license:CC0-1.0
// copyright-holders:Couriersud
-#include "netlist/nl_setup.h"
-#include "netlist/devices/net_lib.h"
-#include "nlm_base.h"
+
+// Specific technical terms
+// spell-checker: words Iave, Vishay, Zdiodes, Icrating, Vceo
+
+#include "devices/net_lib.h"
/* ----------------------------------------------------------------------------
* Diode Models
* ---------------------------------------------------------------------------*/
static NETLIST_START(diode_models)
- NET_MODEL("D _(IS=1e-15 N=1)")
+{
+ NET_MODEL("D _(IS=1e-15 N=1 NBV=3 IBV=0.001 BV=1E9)")
NET_MODEL("1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
// FIXME: 1N916 currently only a copy of 1N914!
NET_MODEL("1N916 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
NET_MODEL("1N4001 D(Is=14.11n N=1.984 Rs=33.89m Ikf=94.81 Xti=3 Eg=1.11 Cjo=25.89p M=.44 Vj=.3245 Fc=.5 Bv=75 Ibv=10u Tt=5.7u Iave=1 Vpk=50 mfg=GI type=silicon)")
+ NET_MODEL("1N4002 D(IS=65.4p RS=42.2m BV=100 IBV=5.00u CJO=14.8p M=0.333 N=1.36 TT=2.88u)")
NET_MODEL("1N4148 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)")
+ NET_MODEL("1N4154 D(Is=0.1n Rs=4 N=1.67 Cjo=2p M=.333 tt=3n Iave=150m Vpk=35 Bv=60 Ibv=0.1p mfg=Vishay type=silicon)")
+ NET_MODEL("1N4454 D(Is=168.1e-21 Rs=.1 N=1 Cjo=2p M=.333 tt=5.771n Iave=400m Vpk=35 Bv=75 Ibv=100u mfg=OnSemi type=silicon)")
NET_MODEL("1S1588 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75)")
NET_MODEL("1N34A D( Bv=75 Cjo=0.5e-12 Eg=0.67 Ibv=18e-3 Is=2e-7 Rs=7 N=1.3 Vj=0.1 M=0.27 type=germanium)")
@@ -25,26 +31,37 @@ static NETLIST_START(diode_models)
NET_MODEL("LedBlue D(IS=93.2p RS=42M N=7.47 BV=5 IBV=10U CJO=2.97P VJ=.75 M=.333 TT=4.32U Iave=40m Vpk=5 type=LED)")
NET_MODEL("LedWhite D(Is=0.27n Rs=5.65 N=6.79 Cjo=42p Iave=30m Vpk=5 type=LED)")
-NETLIST_END()
+ // Zdiodes ...
+
+ // not really found anywhere, just took the 5239 and changed the
+ // breakdown voltage to 5.1 according to the datasheet
+ NET_MODEL("1N5231 D(BV=5.1 IBV=0.020 NBV=1)")
+ NET_MODEL("1N5236B D(BV=7.5 IS=27.5p RS=33.8 N=1.10 CJO=58.2p VJ=0.750 M=0.330 TT=50.1n)")
+ NET_MODEL("1N5240 D(BV=10 IS=14.4p RS=32.0 N=1.10 CJO=24.1p VJ=0.750 M=0.330 TT=50.1n)")
+ NET_MODEL("1N5240B D(BV=10 IS=14.4p RS=32.0 N=1.10 CJO=24.1p VJ=0.750 M=0.330 TT=50.1n)")
+
+}
/* ----------------------------------------------------------------------------
* Mosfet Models
* ---------------------------------------------------------------------------*/
static NETLIST_START(mosfet_models)
+{
//NET_MODEL("NMOS _(VTO=0.0 N=1.0 IS=1E-14 KP=2E-5 UO=600 PHI=0.6 LD=0.0 L=1.0 TOX=1E-7 W=1.0 NSUB=0.0 GAMMA=0.0 RD=0.0 RS=0.0 LAMBDA=0.0)")
//NET_MODEL("PMOS _(VTO=0.0 N=1.0 IS=1E-14 KP=2E-5 UO=600 PHI=0.6 LD=0.0 L=1.0 TOX=1E-7 W=1.0 NSUB=0.0 GAMMA=0.0 RD=0.0 RS=0.0 LAMBDA=0.0)")
// NMOS_DEFAULT and PMOS_DEFAULT are created in nl_setup.cpp
NET_MODEL("NMOS NMOS_DEFAULT(VTO=0.0 N=1.0 IS=1E-14 KP=0.0 UO=600 PHI=0.0 LD=0.0 L=100e-6 TOX=1E-7 W=100e-6 NSUB=0.0 GAMMA=0.0 RD=0.0 RS=0.0 LAMBDA=0.0 CGSO=0 CGDO=0 CGBO=0)")
NET_MODEL("PMOS PMOS_DEFAULT(VTO=0.0 N=1.0 IS=1E-14 KP=0.0 UO=600 PHI=0.0 LD=0.0 L=100e-6 TOX=1E-7 W=100e-6 NSUB=0.0 GAMMA=0.0 RD=0.0 RS=0.0 LAMBDA=0.0 CGSO=0 CGDO=0 CGBO=0)")
-NETLIST_END()
+}
/* ----------------------------------------------------------------------------
* BJT Models
* ---------------------------------------------------------------------------*/
static NETLIST_START(bjt_models)
+{
NET_MODEL("NPN _(IS=1e-15 BF=100 NF=1 BR=1 NR=1 CJE=0 CJC=0)")
NET_MODEL("PNP _(IS=1e-15 BF=100 NF=1 BR=1 NR=1 CJE=0 CJC=0)")
@@ -56,10 +73,26 @@ static NETLIST_START(bjt_models)
NET_MODEL("2N3645 PNP(IS=650.6E-18 ISE=54.81E-15 ISC=0 XTI=3 BF=231.7 BR=3.563 IKF=1.079 IKR=0 XTB=1.5 VAF=115.7 VAR=35 VJE=0.65 VJC=0.65 RE=0.15 RC=0.715 RB=10 CJE=19.82E-12 CJC=14.76E-12 XCJC=0.75 FC=0.5 NF=1 NR=1 NE=1.829 NC=2 MJE=0.3357 MJC=0.5383 TF=603.7E-12 TR=111.3E-9 ITF=0.65 VTF=5 XTF=1.7 EG=1.11 KF=0 AF=1 VCEO=60 ICRATING=500m MFG=NSC)")
// 3644 = 3645 Difference between 3644 and 3645 is voltage rating. 3644: VCBO=45, 3645: VCBO=60
NET_MODEL("2N3644 PNP(IS=650.6E-18 ISE=54.81E-15 ISC=0 XTI=3 BF=231.7 BR=3.563 IKF=1.079 IKR=0 XTB=1.5 VAF=115.7 VAR=35 VJE=0.65 VJC=0.65 RE=0.15 RC=0.715 RB=10 CJE=19.82E-12 CJC=14.76E-12 XCJC=0.75 FC=0.5 NF=1 NR=1 NE=1.829 NC=2 MJE=0.3357 MJC=0.5383 TF=603.7E-12 TR=111.3E-9 ITF=0.65 VTF=5 XTF=1.7 EG=1.11 KF=0 AF=1 VCEO=60 ICRATING=500m MFG=NSC)")
+ NET_MODEL("2N3702 PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=133.8 Ne=1.832 Ise=97.16f Ikf=1.081 Xtb=1.5 Br=3.73 Nc=2 Isc=0 Ikr=0 Rc=.715 Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 Tr=114.1n Tf=761.3p Itf=.65 Vtf=5 Xtf=1.7 Rb=10 mfg=National)")
+ NET_MODEL("2N3704 NPN(IS=26.03f VAF=90.7 Bf=736.1K IKF=.1983 XTB=1.5 BR=1.024 CJC=11.01p CJE=24.07p RB=10 RC=.5 RE=.5 TR=233.8n TF=1.03n ITF=0 VTF=0 XTF=0 mfg=Motorola)")
+ // SPICE model parameters taken from Fairchild Semiconductor datasheet
+ NET_MODEL("2N3904 NPN(IS=1E-14 VAF=100 Bf=300 IKF=0.4 XTB=1.5 BR=4 CJC=4E-12 CJE=8E-12 RB=20 RC=0.1 RE=0.1 TR=250E-9 TF=350E-12 ITF=1 VTF=2 XTF=3 Vceo=40 Icrating=200m mfg=Philips)")
+ // SPICE model parameters taken from Fairchild Semiconductor datasheet
+ NET_MODEL("2N3906 PNP(Is=1.41f Xti=3 Eg=1.11 Vaf=18.7 Bf=180.7 Ne=1.5 Ise=0 Ikf=80m Xtb=1.5 Br=4.977 Nc=2 Isc=0 Ikr=0 Rc=2.5 Cjc=9.728p Mjc=.5776 Vjc=.75 Fc=.5 Cje=8.063p Mje=.3677 Vje=.75 Tr=33.42n Tf=179.3p Itf=.4 Vtf=4 Xtf=6 Rb=10)")
// 2N5190 = BC817-25
NET_MODEL("2N5190 NPN(IS=9.198E-14 NF=1.003 ISE=4.468E-16 NE=1.65 BF=338.8 IKF=0.4913 VAF=107.9 NR=1.002 ISC=5.109E-15 NC=1.071 BR=29.48 IKR=0.193 VAR=25 RB=1 IRB=1000 RBM=1 RE=0.2126 RC=0.143 XTB=0 EG=1.11 XTI=3 CJE=3.825E-11 VJE=0.7004 MJE=0.364 TF=5.229E-10 XTF=219.7 VTF=3.502 ITF=7.257 PTF=0 CJC=1.27E-11 VJC=0.4431 MJC=0.3983 XCJC=0.4555 TR=7E-11 CJS=0 VJS=0.75 MJS=0.333 FC=0.905 Vceo=45 Icrating=500m mfg=Philips)")
NET_MODEL("2N4401 NPN(IS=26.03f XTI=3 EG=1.11 VAF=90.7 BF=4.292K NE=1.244 ISE=26.03f IKF=0.2061 XTB=1.5 BR=1.01 NC=2 ISC=0 IKR=0 RC=0.5 CJC=11.01p MJC=0.3763 VJC=0.75 FC=0.5 CJE=24.07p MJE=0.3641 VJE=0.75 TR=233.7n TF=466.5p ITF=0 VTF=0 XTF=0 RB=10 VCEO=40)")
+ NET_MODEL("2N4403 PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=216.2 Ne=1.829 Ise=58.72f Ikf=1.079 Xtb=1.5 Br=3.578 Nc=2 Isc=0 Ikr=0 Rc=.715 Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 Tr=111.6n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)")
+ NET_MODEL("2N4124 NPN(IS=6.734f XTI=3 EG=1.11 VAF=74.03 BF=495 NE=1.28 ISE=6.734f IKF=69.35m XTB=1.5 BR=0.7214 NC=2 ISC=0 IKR=0 RC=1 CJC=3.638p MJC=0.3085 VJC=0.75 FC=0.5 CJE=4.493p MJE=0.2593 VJE=0.75 TR=238.3n TF=301.3p ITF=.4 VTF=4 XTF=2 RB=10 VCEO=25)")
+ NET_MODEL("2N4126 PNP(IS=1.41f XTI=3 EG=1.11 VAF=18.7 BF=203.7 NE=1.5 ISE=0 IKF=80m XTB=1.5 BR=4.924 NC=2 ISC=0 IKR=0 RC=2.5 CJC=9.728p MJC=0.5776 VJC=0.75 FC=0.5 CJE=8.063p MJE=0.3677 VJE=0.75 TR=33.23n TF=179.3p ITF=.4 VTF=4 XTF=6 RB=10 VCEO=25)")
+ // SPICE model parameters taken from http://ltwiki.org/files/LTspiceIV/Vendor%20List/Fairchild/2N/index.html
+ NET_MODEL("2N5210 NPN(Is=5.911f Xti=3 Eg=1.11 Vaf=62.37 Bf=809.9 Ne=1.358 Ise=5.911f Ikf=14.26m Xtb=1.5 Br=1.287 Nc=2 Isc=0 Ikr=0 Rc=1.61 Cjc=4.017p Mjc=.3174 Vjc=.75 Fc=.5 Cje=4.973p Mje=.4146 Vje=.75 Tr=4.68n Tf=820.9p Itf=.35 Vtf=4 Xtf=7 Rb=10)")
+ // SPICE model parameters taken from https://www.onsemi.com/support/design-resources/models?rpn=2N6107
+ NET_MODEL("2N6107 PNP(IS=7.62308e-14 BF=6692.56 NF=0.85 VAF=10 IKF=0.032192 ISE=2.07832e-13 NE=2.41828 BR=15.6629 NR=1.5 VAR=1.44572 IKR=0.32192 ISC=4.75e-16 NC=3.9375 RB=7.19824 IRB=0.1 RBM=0.1 RE=0.0001 RC=0.355458 XTB=0.1 XTI=2.97595 EG=1.206 CJE=1.84157e-10 VJE=0.99 MJE=0.347177 TF=6.63757e-09 XTF=1.50003 VTF=1.0001 ITF=1 CJC=1.06717e-10 VJC=0.942679 MJC=0.245405 XCJC=0.8 FC=0.533334 CJS=0 VJS=0.75 MJS=0.5 TR=1.32755e-07 PTF=0 KF=0 AF=1)")
+ // SPICE model parameters taken from https://www.onsemi.com/support/design-resources/models?rpn=2N6292
+ NET_MODEL("2N6292 NPN(IS=9.3092e-13 BF=2021.8 NF=0.85 VAF=63.2399 IKF=1 ISE=1.92869e-13 NE=1.97024 BR=40.0703 NR=1.5 VAR=0.89955 IKR=10 ISC=4.92338e-16 NC=3.9992 RB=6.98677 IRB=0.1 RBM=0.1 RE=0.0001 RC=0.326141 XTB=0.1 XTI=2.86739 EG=1.206 CJE=1.84157e-10 VJE=0.99 MJE=0.347174 TF=6.73756e-09 XTF=1.49917 VTF=0.997395 ITF=0.998426 CJC=1.06717e-10 VJC=0.942694 MJC=0.245406 XCJC=0.8 FC=0.533405 CJS=0 VJS=0.75 MJS=0.5 TR=6.0671e-08 PTF=0 KF=0 AF=1)")
+
NET_MODEL("2SC945 NPN(IS=3.577E-14 BF=2.382E+02 NF=1.01 VAF=1.206E+02 IKF=3.332E-01 ISE=3.038E-16 NE=1.205 BR=1.289E+01 NR=1.015 VAR=1.533E+01 IKR=2.037E-01 ISC=3.972E-14 NC=1.115 RB=3.680E+01 IRB=1.004E-04 RBM=1 RE=8.338E-01 RC=1.557E+00 CJE=1.877E-11 VJE=7.211E-01 MJE=3.486E-01 TF=4.149E-10 XTF=1.000E+02 VTF=9.956 ITF=5.118E-01 PTF=0 CJC=6.876p VJC=3.645E-01 MJC=3.074E-01 TR=5.145E-08 XTB=1.5 EG=1.11 XTI=3 FC=0.5 Vceo=50 Icrating=100m MFG=NEC)")
NET_MODEL("BC237B NPN(IS=1.8E-14 ISE=5.0E-14 ISC=1.72E-13 XTI=3 BF=400 BR=35.5 IKF=0.14 IKR=0.03 XTB=1.5 VAF=80 VAR=12.5 VJE=0.58 VJC=0.54 RE=0.6 RC=0.25 RB=0.56 CJE=13E-12 CJC=4E-12 XCJC=0.75 FC=0.5 NF=0.9955 NR=1.005 NE=1.46 NC=1.27 MJE=0.33 MJC=0.33 TF=0.64E-9 TR=50.72E-9 EG=1.11 KF=0 AF=1 VCEO=45 ICRATING=100M MFG=ZETEX)")
@@ -68,30 +101,39 @@ static NETLIST_START(bjt_models)
NET_MODEL("BC817-25 NPN(IS=9.198E-14 NF=1.003 ISE=4.468E-16 NE=1.65 BF=338.8 IKF=0.4913 VAF=107.9 NR=1.002 ISC=5.109E-15 NC=1.071 BR=29.48 IKR=0.193 VAR=25 RB=1 IRB=1000 RBM=1 RE=0.2126 RC=0.143 XTB=0 EG=1.11 XTI=3 CJE=3.825E-11 VJE=0.7004 MJE=0.364 TF=5.229E-10 XTF=219.7 VTF=3.502 ITF=7.257 PTF=0 CJC=1.27E-11 VJC=0.4431 MJC=0.3983 XCJC=0.4555 TR=7E-11 CJS=0 VJS=0.75 MJS=0.333 FC=0.905 Vceo=45 Icrating=500m mfg=Philips)")
NET_MODEL("9013 NPN(IS=3.40675E-14 BF=166 VAF=67 IKF=1.164 ISE=12.37e-15 NE=2 BR=15.17 VAR=40.84 IKR=0.261352 ISC=1.905E-15 NC=1.066 RB=63.2 IRB=5.62E-6 RBM=22.1 RE=0.02 RC=0.7426 CJE=3.53E-11 VJE=0.808 MJE=0.372 CJC=1.74E-11 VJC=0.614 MJC=0.388 XCJC=0.349 XTB=1.4025 EG=1.0999 XTI=3 VC=0.5 VCEO=20)")
-NETLIST_END()
+}
/* ----------------------------------------------------------------------------
* Family models
* ---------------------------------------------------------------------------*/
static NETLIST_START(family_models)
- NET_MODEL("FAMILY _(TYPE=CUSTOM FV=5 IVL=0.16 IVH=0.4 OVL=0.1 OVH=1.0 ORL=1.0 ORH=130.0)")
+{
+
+ // FAMILIES always need a type. UNKNOWN below will break
+ NET_MODEL("FAMILY _(TYPE=UNKNOWN IVL=0.16 IVH=0.4 OVL=0.1 OVH=1.0 ORL=1.0 ORH=130.0)")
NET_MODEL("OPAMP _()")
NET_MODEL("SCHMITT_TRIGGER _()")
- NET_MODEL("74XXOC FAMILY(FV=5 IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.05 ORL=10.0 ORH=1.0e8)")
- NET_MODEL("74XX FAMILY(TYPE=TTL)")
- NET_MODEL("CD4XXX FAMILY(TYPE=CD4XXX)")
-NETLIST_END()
+ NET_MODEL("74XX FAMILY(TYPE=TTL IVL=0.16 IVH=0.4 OVL=0.1 OVH=1.0 ORL=1.0 ORH=130)")
+
+ // CMOS
+ // low input 1.5 , high input trigger 3.5 at 5V supply
+ // output offsets, low for CMOS, thus 0.05
+ // output currents: see https://www.classe.cornell.edu/~ib38/teaching/p360/lectures/wk09/l26/EE2301Exp3F10.pdf
+ // typical CMOS may sink 0.4mA while output stays <= 0.4V
+ NET_MODEL("CD4XXX FAMILY(TYPE=CMOS IVL=0.3 IVH=0.7 OVL=0.05 OVH=0.05 ORL=500 ORH=500)")
+
+ NET_MODEL("74XXOC FAMILY(TYPE=TTL IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.05 ORL=10.0 ORH=1.0e8)")
+}
/* ----------------------------------------------------------------------------
* Always included
* ---------------------------------------------------------------------------*/
-NETLIST_START(base)
- TTL_INPUT(ttlhigh, 1)
- TTL_INPUT(ttllow, 0)
- NET_REGISTER_DEV(GND, GND)
+NETLIST_START(base_lib)
+{
+ NET_REGISTER_DEV(GNDA, GND)
NET_REGISTER_DEV(PARAMETER, NETLIST)
LOCAL_SOURCE(diode_models)
@@ -99,19 +141,26 @@ NETLIST_START(base)
LOCAL_SOURCE(mosfet_models)
LOCAL_SOURCE(family_models)
- LOCAL_SOURCE(TTL74XX_lib)
- LOCAL_SOURCE(CD4XXX_lib)
- LOCAL_SOURCE(OPAMP_lib)
- LOCAL_SOURCE(otheric_lib)
+ EXTERNAL_SOURCE(ttl74xx_lib)
+ EXTERNAL_SOURCE(cd4xxx_lib)
+ EXTERNAL_SOURCE(opamp_lib)
+ EXTERNAL_SOURCE(otheric_lib)
+ EXTERNAL_SOURCE(roms_lib)
+
+ EXTERNAL_SOURCE(modules_lib)
INCLUDE(diode_models)
INCLUDE(bjt_models)
INCLUDE(mosfet_models)
INCLUDE(family_models)
- INCLUDE(TTL74XX_lib)
- INCLUDE(CD4XXX_lib)
- INCLUDE(OPAMP_lib)
+
+ INCLUDE(ttl74xx_lib)
+ INCLUDE(cd4xxx_lib)
+ INCLUDE(opamp_lib)
INCLUDE(otheric_lib)
+ INCLUDE(roms_lib)
+
+ INCLUDE(modules_lib)
-NETLIST_END()
+}
diff --git a/src/lib/netlist/macro/nlm_cd4xxx.cpp b/src/lib/netlist/macro/nlm_cd4xxx.cpp
deleted file mode 100644
index 8844b3f8154..00000000000
--- a/src/lib/netlist/macro/nlm_cd4xxx.cpp
+++ /dev/null
@@ -1,202 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#include "nlm_cd4xxx.h"
-
-#include "netlist/devices/nld_4020.h"
-#include "netlist/devices/nld_4066.h"
-#include "netlist/devices/nld_4316.h"
-#include "netlist/devices/nld_system.h"
-
-/*
- * CD4001BC: Quad 2-Input NOR Buffered B Series Gate
- *
- * +--------------+
- * A1 |1 ++ 14| VCC
- * B1 |2 13| A6
- * A2 |3 12| Y6
- * Y2 |4 4001 11| A5
- * A3 |5 10| Y5
- * Y3 |6 9| A4
- * GND |7 8| Y4
- * +--------------+
- *
- */
-
-static NETLIST_START(CD4001_DIP)
- CD4001_NOR(s1)
- CD4001_NOR(s2)
- CD4001_NOR(s3)
- CD4001_NOR(s4)
-
- NET_C(s1.VCC, s2.VCC, s3.VCC, s4.VCC)
- NET_C(s1.VDD, s2.VDD, s3.VDD, s4.VDD)
- DIPPINS( /* +--------------+ */
- s1.A, /* A1 |1 ++ 14| VCC */ s1.VCC,
- s1.B, /* B1 |2 13| A6 */ s4.B,
- s1.Q, /* A2 |3 12| Y6 */ s4.A,
- s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q,
- s2.A, /* A3 |5 10| Y5 */ s3.Q,
- s2.B, /* Y3 |6 9| A4 */ s3.B,
- s1.VDD, /* GND |7 8| Y4 */ s3.A
- /* +--------------+ */
- )
-
-NETLIST_END()
-
-/* CD4020: 14-Stage Ripple Carry Binary Counters
- *
- * +--------------+
- * Q12 |1 ++ 16| VDD
- * Q13 |2 15| Q11
- * Q14 |3 14| Q10
- * Q6 |4 4020 13| Q8
- * Q5 |5 12| Q9
- * Q7 |6 11| RESET
- * Q4 |7 10| IP (Input pulses)
- * VSS |8 9| Q1
- * +--------------+
- *
- * Naming conventions follow Texas Instruments datasheet
- *
- * FIXME: Timing depends on VDD-VSS
- * This needs a cmos d-a/a-d proxy implementation.
- */
-
-static NETLIST_START(CD4020_DIP)
-
- CD4020(s1)
- DIPPINS( /* +--------------+ */
- s1.Q12, /* Q12 |1 ++ 16| VDD */ s1.VDD,
- s1.Q13, /* Q13 |2 15| Q11 */ s1.Q11,
- s1.Q14, /* Q14 |3 14| Q10 */ s1.Q10,
- s1.Q6, /* Q6 |4 4020 13| Q8 */ s1.Q8,
- s1.Q5, /* Q5 |5 12| Q9 */ s1.Q9,
- s1.Q7, /* Q7 |6 11| RESET */ s1.RESET,
- s1.Q4, /* Q4 |7 10| IP */ s1.IP,
- s1.VSS, /* VSS |8 9| Q1 */ s1.Q1
- /* +--------------+ */
- )
- /*
- * IP = (Input pulses)
- */
-
-NETLIST_END()
-
-/* CD4066: Quad Bilateral Switch
- *
- * +--------------+
- * INOUTA |1 ++ 14| VDD
- * OUTINA |2 13| CONTROLA
- * OUTINB |3 12| CONTROLD
- * INOUTB |4 4066 11| INOUTD
- * CONTROLB |5 10| OUTIND
- * CONTROLC |6 9| OUTINC
- * VSS |7 8| INOUTC
- * +--------------+
- *
- * FIXME: These devices are slow (~125 ns). THis is currently not reflected
- *
- * Naming conventions follow National semiconductor datasheet
- *
- */
-
-static NETLIST_START(CD4066_DIP)
- CD4066_GATE(A)
- CD4066_GATE(B)
- CD4066_GATE(C)
- CD4066_GATE(D)
-
- NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
- NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
-
- PARAM(A.BASER, 270.0)
- PARAM(B.BASER, 270.0)
- PARAM(C.BASER, 270.0)
- PARAM(D.BASER, 270.0)
-
- DIPPINS( /* +--------------+ */
- A.R.1, /* INOUTA |1 ++ 14| VDD */ A.VDD,
- A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
- B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
- B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1,
- B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
- C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
- A.VSS, /* VSS |7 8| INOUTC */ C.R.2
- /* +--------------+ */
- )
-NETLIST_END()
-
-static NETLIST_START(CD4016_DIP)
- CD4066_GATE(A)
- CD4066_GATE(B)
- CD4066_GATE(C)
- CD4066_GATE(D)
-
- NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
- NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
-
- PARAM(A.BASER, 1000.0)
- PARAM(B.BASER, 1000.0)
- PARAM(C.BASER, 1000.0)
- PARAM(D.BASER, 1000.0)
-
- DIPPINS( /* +--------------+ */
- A.R.1, /* INOUTA |1 ++ 14| VDD */ A.VDD,
- A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
- B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
- B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1,
- B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
- C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
- A.VSS, /* VSS |7 8| INOUTC */ C.R.2
- /* +--------------+ */
- )
-NETLIST_END()
-
-static NETLIST_START(CD4316_DIP)
- CD4316_GATE(A)
- CD4316_GATE(B)
- CD4316_GATE(C)
- CD4316_GATE(D)
-
- NET_C(A.E, B.E, C.E, D.E)
- NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
- NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
-
- PARAM(A.BASER, 45.0)
- PARAM(B.BASER, 45.0)
- PARAM(C.BASER, 45.0)
- PARAM(D.BASER, 45.0)
-
- DIPPINS( /* +--------------+ */
- A.R.2, /* 1Z |1 ++ 16| VCC */ A.VDD,
- A.R.1, /* 1Y |2 15| 1S */ A.S,
- B.R.1, /* 2Y |3 14| 4S */ D.S,
- B.R.2, /* 2Z |4 4316 13| 4Z */ D.R.2,
- B.S, /* 2S |5 12| 4Y */ D.R.1,
- C.S, /* 3S |6 11| 3Y */ C.R.1,
- A.E, /* /E |7 10| 3Z */ C.R.2,
- A.VSS, /* GND |8 9| VEE */ VEE
- /* +--------------+ */
- )
-
-NETLIST_END()
-
-NETLIST_START(CD4XXX_lib)
-
- TRUTHTABLE_START(CD4001_NOR, 2, 1, "")
- TT_HEAD("A , B | Q ")
- TT_LINE("0,0|1|85")
- TT_LINE("X,1|0|120")
- TT_LINE("1,X|0|120")
- TT_FAMILY("CD4XXX")
- TRUTHTABLE_END()
-
- LOCAL_LIB_ENTRY(CD4001_DIP)
-
- /* DIP ONLY */
- LOCAL_LIB_ENTRY(CD4020_DIP)
- LOCAL_LIB_ENTRY(CD4016_DIP)
- LOCAL_LIB_ENTRY(CD4066_DIP)
- LOCAL_LIB_ENTRY(CD4316_DIP)
-
-NETLIST_END()
diff --git a/src/lib/netlist/macro/nlm_cd4xxx.h b/src/lib/netlist/macro/nlm_cd4xxx.h
deleted file mode 100644
index d4d9c97fdc2..00000000000
--- a/src/lib/netlist/macro/nlm_cd4xxx.h
+++ /dev/null
@@ -1,58 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#ifndef NLD_CD4XXX_H_
-#define NLD_CD4XXX_H_
-
-#include "netlist/nl_setup.h"
-
-/*
- * Devices:
- *
- * CD4001_NOR : single gate
- * CD4001_DIP : dip package
- * CD4020_DIP : dip package (device model in core)
- * CD4016_DIP : dip package (device model in core)
- * CD4066_DIP : dip package (device model in core)
- *
- */
-
-#ifndef __PLIB_PREPROCESSOR__
-
-/* ----------------------------------------------------------------------------
- * Netlist Macros
- * ---------------------------------------------------------------------------*/
-
-#ifndef NL_AUTO_DEVICES
-
-#define CD4001_NOR(name) \
- NET_REGISTER_DEV(CD4001_NOR, name)
-
-#define CD4001_DIP(name) \
- NET_REGISTER_DEV(CD4001_DIP, name)
-
-/* ----------------------------------------------------------------------------
- * DIP only macros
- * ---------------------------------------------------------------------------*/
-
-#define CD4020_DIP(name) \
- NET_REGISTER_DEV(CD4020_DIP, name)
-
-#define CD4066_DIP(name) \
- NET_REGISTER_DEV(CD4066_DIP, name)
-
-#define CD4016_DIP(name) \
- NET_REGISTER_DEV(CD4016_DIP, name)
-
-#define CD4316_DIP(name) \
- NET_REGISTER_DEV(CD4016_DIP, name)
-
-#endif
-/* ----------------------------------------------------------------------------
- * External declarations
- * ---------------------------------------------------------------------------*/
-
-NETLIST_EXTERNAL(CD4XXX_lib)
-
-#endif
-
-#endif
diff --git a/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp b/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp
new file mode 100644
index 00000000000..0a0f75c8732
--- /dev/null
+++ b/src/lib/netlist/macro/nlm_cd4xxx_lib.cpp
@@ -0,0 +1,978 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+#include "devices/net_lib.h"
+
+//- Identifier: CD4001_DIP
+//- Title: CD4001BM/CD4001BC Quad 2-Input NOR Buffered B Series Gate
+//- Pinalias: A1,B1,Y1,Y2,A2,B2,VSS,A3,B3,Y3,Y4,A4,B4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/108518_DS.pdf
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 1 |
+//- | X | 1 || 0 |
+//- | 1 | X || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(CD4001_DIP)
+{
+ CD4001_GATE(A)
+ CD4001_GATE(B)
+ CD4001_GATE(C)
+ CD4001_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ DIPPINS(
+ /*# +--------------+ */
+ A.A, /*# A1 |1 ++ 14| VDD */ A.VDD, //
+ A.B, /*# B1 |2 13| B4 */ D.B, //
+ A.Q, /*# Y1 |3 12| A4 */ D.A, //
+ B.Q, /*# Y2 |4 4001 11| Y4 */ D.Q, //
+ B.A, /*# A2 |5 10| Y3 */ C.Q, //
+ B.B, /*# B2 |6 9| B3 */ C.B, //
+ A.VSS, /*# VSS |7 8| A3 */ C.A //
+ /*# +--------------+ */
+ )
+}
+
+//- Identifier: CD4006_DIP
+//- Title: CD4006BM/CD4006BC 18-Stage Static Shift Register
+//- Pinalias: D1,NC,CLOCK,D2,D3,D4,VSS,D4P4,D4P5,D3P4,D2P4,D2P5,D1P4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005942.PDF
+//-
+static NETLIST_START(CD4006_DIP)
+{
+ CD4006(A)
+ NC_PIN(NC)
+
+ DIPPINS( /* +--------------+ */
+ A.D1, /* D1 |1 ++ 14| VDD */ A.VDD,
+ NC.I, /* NC |2 13| D1+4 */ A.D1P4,
+ A.CLOCK, /* CLOCK |3 12| D2+5 */ A.D2P5,
+ A.D2, /* D2 |4 4006 11| D2+4 */ A.D2P4,
+ A.D3, /* D3 |5 10| D3+4 */ A.D3P4,
+ A.D4, /* D4 |6 9| D4+5 */ A.D4P5,
+ A.VSS, /* VSS |7 8| D4+4 */ A.D4P4
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4011_DIP
+//- Title: CD4011BM/CD4011BC Quad 2-Input NAND Buffered B Series Gate
+//- Pinalias: A1,B1,Y1,Y2,A2,B2,VSS,A3,B3,Y3,Y4,A4,B4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/108518_DS.pdf
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | X | 0 || 1 |
+//- | 0 | X || 1 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(CD4011_DIP)
+{
+ CD4011_GATE(A)
+ CD4011_GATE(B)
+ CD4011_GATE(C)
+ CD4011_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A |1 ++ 14| VDD */ A.VDD,
+ A.B, /* B |2 13| H */ D.B,
+ A.Q, /* J |3 12| G */ D.A,
+ B.Q, /* K |4 4011 11| M */ D.Q,
+ B.A, /* C |5 10| L */ C.Q,
+ B.B, /* D |6 9| F */ C.B,
+ A.VSS, /* VSS |7 8| E */ C.A
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4013_DIP
+//- Title: CD4013BM/CD4013BC Dual D Flip-Flop
+//- Pinalias: Q1,QQ1,CLOCK1,RESET1,DATA1,SET1,VSS,SET2,DATA2,RESET2,CLOCK2,QQ2,Q2,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/150/108670_DS.pdf
+//-
+//- +-----+---+---+---++---+----+
+//- | CLK | D | R | S || Q | QQ |
+//- +=====+===+===+===++===+====+
+//- | 0-1 | 0 | 0 | 0 || 0 | 1 |
+//- | 0-1 | 1 | 0 | 0 || 1 | 0 |
+//- | 1-0 | X | 0 | 0 || Q | QQ |
+//- | X | X | 1 | 0 || 0 | 1 |
+//- | X | X | 0 | 1 || 1 | 0 |
+//- | X | X | 1 | 1 || 1 | 1 |
+//- +-----+---+---+---++---+----+
+//-
+static NETLIST_START(CD4013_DIP)
+{
+ CD4013(A)
+ CD4013(B)
+
+ NET_C(A.VDD, B.VDD)
+ NET_C(A.VSS, B.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.Q, /* Q1 |1 ++ 14| VDD */ A.VDD,
+ A.QQ, /* Q1Q |2 13| Q2 */ B.Q,
+ A.CLOCK, /* CLOCK1 |3 12| Q2Q */ B.QQ,
+ A.RESET, /* RESET1 |4 4013 11| CLOCK2 */ B.CLOCK,
+ A.DATA, /* DATA1 |5 10| RESET2 */ B.RESET,
+ A.SET, /* SET1 |6 9| DATA2 */ B.DATA,
+ A.VSS, /* VSS |7 8| SET2 */ B.SET
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4016_DIP
+//- Title: CD4016BM/CD4016BC Quad Bilateral Switch
+//- Pinalias: INOUTA,OUTINA,OUTINB,INOUTB,CONTROLB,CONTROLC,VSS,INOUTC,OUTINC,OUTIND,INOUTD,CONTROLD,CONTROLA,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/185/108711_DS.pdf
+//-
+static NETLIST_START(CD4016_DIP)
+{
+ CD4066_GATE(A)
+ CD4066_GATE(B)
+ CD4066_GATE(C)
+ CD4066_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ PARAM(A.BASER, 1000.0)
+ PARAM(B.BASER, 1000.0)
+ PARAM(C.BASER, 1000.0)
+ PARAM(D.BASER, 1000.0)
+
+ DIPPINS( /* +--------------+ */
+ A.R.1, /* INOUTA |1 ++ 14| VDD */ A.VDD,
+ A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
+ B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
+ B.R.2, /* INOUTB |4 4016 11| INOUTD */ D.R.1,
+ B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
+ C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
+ A.VSS, /* VSS |7 8| INOUTC */ C.R.2
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4017_DIP
+//- Title: CD4017BM/CD4017BC Decade Counter/Divider with 10 Decoded Outputs
+//- Pinalias: Q5,Q1,Q0,Q2,Q6,Q7,Q3,VSS,Q8,Q4,Q9,CARRY_OUT,CLOCK_ENABLE,CLOCK,RESET,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/108736_DS.pdf
+//-
+static NETLIST_START(CD4017_DIP)
+{
+ CD4017(A)
+
+ DIPPINS( /* +--------------+ */
+ A.Q5, /* Q5 |1 ++ 16| VDD */ A.VDD,
+ A.Q1, /* Q1 |2 15| RESET */ A.RESET,
+ A.Q0, /* Q0 |3 14| CLOCK */ A.CLK,
+ A.Q2, /* Q2 |4 4017 13| CLOCK ENABLE */ A.CLKEN,
+ A.Q6, /* Q6 |5 12| CARRY OUT */ A.CO,
+ A.Q7, /* Q7 |6 11| Q9 */ A.Q9,
+ A.Q3, /* Q3 |7 10| Q4 */ A.Q4,
+ A.VSS, /* VSS |8 9| Q8 */ A.Q8
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4020_DIP
+//- Title: CD4020BC 14-Stage Ripple Carry Binary Counters
+//- Pinalias: Q12,Q13,Q14,Q6,Q5,Q7,Q4,VSS,Q1,PHI1,RESET,Q9,Q8,Q10,Q11,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/90/109006_DS.pdf
+//-
+static NETLIST_START(CD4020_DIP)
+{
+ CD4020(A)
+
+ DIPPINS( /* +--------------+ */
+ A.Q12, /* Q12 |1 ++ 16| VDD */ A.VDD,
+ A.Q13, /* Q13 |2 15| Q11 */ A.Q11,
+ A.Q14, /* Q14 |3 14| Q10 */ A.Q10,
+ A.Q6, /* Q6 |4 4020 13| Q8 */ A.Q8,
+ A.Q5, /* Q5 |5 12| Q9 */ A.Q9,
+ A.Q7, /* Q7 |6 11| RESET */ A.RESET,
+ A.Q4, /* Q4 |7 10| PHI1 */ A.IP,
+ A.VSS, /* VSS |8 9| Q1 */ A.Q1
+ /* +--------------+ */)
+}
+
+//- Identifier: CD4022_DIP
+//- Title: CD4022BM/CD4022BC Divide-by-8 Counter/Divider with 8 Decoded Outputs
+//- Pinalias: Q1,Q0,Q2,Q5,Q6,NC,Q3,VSS,NC,Q7,Q4,CARRY_OUT,CLOCK_ENABLE,CLOCK,RESET,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/108736_DS.pdf
+//-
+static NETLIST_START(CD4022_DIP)
+{
+ CD4022(A)
+ NC_PIN(NC)
+
+ DIPPINS( /* +--------------+ */
+ A.Q1, /* Q1 |1 ++ 16| VDD */ A.VDD,
+ A.Q0, /* Q0 |2 15| RESET */ A.RESET,
+ A.Q2, /* Q2 |3 14| CLOCK */ A.CLK,
+ A.Q5, /* Q5 |4 4022 13| CLOCK ENABLE */ A.CLKEN,
+ A.Q6, /* Q6 |5 12| CARRY OUT */ A.CO,
+ NC.I, /* NC |6 11| Q4 */ A.Q4,
+ A.Q3, /* Q3 |7 10| Q7 */ A.Q7,
+ A.VSS, /* VSS |8 9| NC */ NC.I
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4024_DIP
+//- Title: CD4024BM/CD4024BC 7-Stage Ripple Carry Binary Counter
+//- Pinalias: IP,RESET,Q7,Q6,Q5,Q4,VSS,NC,Q3,NC,Q2,Q1,NC,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/120/108894_DS.pdf
+//-
+static NETLIST_START(CD4024_DIP)
+{
+ CD4024(A)
+ NC_PIN(NC)
+
+ DIPPINS( /* +--------------+ */
+ A.IP, /* IP |1 ++ 14| VDD */ A.VDD,
+ A.RESET, /* RESET |2 13| NC */ NC.I,
+ A.Q7, /* Q7 |3 12| Q1 */ A.Q1,
+ A.Q6, /* Q6 |4 4024 11| Q2 */ A.Q2,
+ A.Q5, /* Q5 |5 10| NC */ NC.I,
+ A.Q4, /* Q4 |6 9| Q3 */ A.Q3,
+ A.VSS, /* VSS |7 8| NC */ NC.I
+ /* +--------------+ */)
+}
+
+//- Identifier: CD4029_DIP
+//- Title: CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter
+//- Pinalias: PE,Q4,J4,J1,CI,Q1,CO,VSS,BD,UD,Q2,J2,J3,Q3,CLK,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/108968_DS.pdf
+//- See nld_4029.cpp for tables explaining the counting order for all states
+//-
+//- Counter Sequences:
+//-
+//- B/D high (Binary), U/D high (Up)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || A |
+//- | A || 1 | 0 | 1 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 | 1 || C |
+//- | C || 1 | 1 | 0 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 | 1 || E |
+//- | E || 1 | 1 | 1 | 0 | 1 || F |
+//- | F || 1 | 1 | 1 | 1 |0|CI|| 0 |
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- B/D high (Binary), U/D low (Down)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | F || 1 | 1 | 1 | 1 | 1 || E |
+//- | E || 1 | 1 | 1 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 | 1 || C |
+//- | C || 1 | 1 | 0 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 | 1 || A |
+//- | A || 1 | 0 | 1 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 0 |
+//- | 0 || 0 | 0 | 0 | 0 |0|CI|| F |
+//- | F || 1 | 1 | 1 | 1 | 1 || E |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- B/D low (Decimal), U/D high (Up)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 |0|CI|| 0 |
+//- | A || 1 | 0 | 1 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 |0|CI|| 6 |
+//- | C || 1 | 1 | 0 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 |0|CI|| 4 |
+//- | E || 1 | 1 | 1 | 0 | 1 || F |
+//- | F || 1 | 1 | 1 | 1 |0|CI|| 2 |
+//- | 0 || 0 | 0 | 0 | 0 | 1 || 1 |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- B/D low (Decimal), U/D low (Down)
+//- +-------++----+----+----+----+----++-------+
+//- | COUNT || Q4 | Q3 | Q2 | Q1 | CO || NEXT |
+//- +=======++====+====+====+====+====++=======+
+//- | F || 1 | 1 | 1 | 1 | 1 || E |
+//- | E || 1 | 1 | 1 | 0 | 1 || D |
+//- | D || 1 | 1 | 0 | 1 | 1 || C |
+//- | C || 1 | 1 | 0 | 0 | 1 || B |
+//- | B || 1 | 0 | 1 | 1 | 1 || A |
+//- | A || 1 | 0 | 1 | 0 | 1 || 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+//- | 8 || 1 | 0 | 0 | 0 | 1 || 7 |
+//- | 7 || 0 | 1 | 1 | 1 | 1 || 6 |
+//- | 6 || 0 | 1 | 1 | 0 | 1 || 5 |
+//- | 5 || 0 | 1 | 0 | 1 | 1 || 4 |
+//- | 4 || 0 | 1 | 0 | 0 | 1 || 3 |
+//- | 3 || 0 | 0 | 1 | 1 | 1 || 2 |
+//- | 2 || 0 | 0 | 1 | 0 | 1 || 1 |
+//- | 1 || 0 | 0 | 0 | 1 | 1 || 0 |
+//- | 0 || 0 | 0 | 0 | 0 |0|CI|| 9 |
+//- | 9 || 1 | 0 | 0 | 1 | 1 || 8 |
+//- +-------++----+----+----+----+----++-------+
+//-
+//- Note that in all cases where Carry-out is generating a non-1 signal (0 | Carry-in),
+//- this signal is asynchronous, so if carry-in changes the carry-out value will
+//- change immediately.
+//-
+//- Preset/Carry in function table
+//- +-----+-----+-----++----+----+----+----+
+//- | PE | CLK | CI || Q1 | Q2 | Q3 | Q4 |
+//- +=====+=====+=====++====+====+====+====+
+//- | 1 | X | X || J1 | J2 | J3 | J4 |
+//- | 0 | X | 1 || Q1 | Q2 | Q3 | Q4 |
+//- | 0 | ./` | 0 || COUNT |
+//- +-----+-----+-----++----+----+----+----+
+//-
+static NETLIST_START(CD4029_DIP)
+{
+ CD4029(A)
+
+ DIPPINS( /* +--------------+ */
+ A.PE, /* PE |1 ++ 16| VDD */ A.VDD,
+ A.Q4, /* Q4 |2 15| CLK */ A.CLK,
+ A.J4, /* J4 |3 14| Q3 */ A.Q3,
+ A.J1, /* J1 |4 4029 13| J3 */ A.J3,
+ A.CI, /* CI |5 12| J2 */ A.J2,
+ A.Q1, /* Q1 |6 11| Q2 */ A.Q2,
+ A.CO, /* CO |7 10| U/D */ A.UD,
+ A.VSS, /* VSS |8 9| B/D */ A.BD
+ /* +--------------+ */)
+}
+
+//- Identifier: CD4030_DIP
+//- Title: CD4030M/CD4030C Quad EXCLUSIVE-OR Gate
+//- Pinalias: A1,B1,Y1,Y2,A2,B2,VSS,A3,B3,Y3,Y4,A4,B4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- https://www.uni-kl.de/elektronik-lager/418055
+//-
+static NETLIST_START(CD4030_DIP)
+{
+ CD4030_GATE(A)
+ CD4030_GATE(B)
+ CD4030_GATE(C)
+ CD4030_GATE(D)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
+ A.B, /* B1 |2 13| B4 */ D.B,
+ A.Q, /* Y1 |3 12| A4 */ D.A,
+ B.Q, /* Y2 |4 4030 11| Y4 */ D.Q,
+ B.A, /* A2 |5 10| Y3 */ C.Q,
+ B.B, /* B2 |6 9| B3 */ C.B,
+ A.VSS, /* VSS |7 8| A3 */ C.A
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4042_DIP
+//- Title: CD4042BM/CD4042BC Quad Clocked D Latch
+//- Pinalias: Q4,Q1,QQ1,D1,CLK,POL,D2,VSS,QQ2,Q2,Q3,QQ3,D3,D4,QQ4,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is partially implemented.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005966.PDF
+//-
+//- +-----+-----+----++----+-----+
+//- | POL | CLK | Dx || Qx | QQx |
+//- +=====+=====+====++====+=====+
+//- | 0 | 0 | X || Qx | /Qx |
+//- | 0 | 1 | D || D | /D |
+//- | 1 | 1 | X || Qx | /Qx |
+//- | 1 | 0 | D || D | /D |
+//- +-----+-----+----++----+-----+
+//- Note that since this is a level triggered transparent latch,
+//- as long as POL ^ CLK == true, the latch is transparent, and
+//- if D changes Q and QQ(/Q) will instantly change.
+//-
+static NETLIST_START(CD4042_DIP)
+{
+ CD4042(A)
+
+ DIPPINS( /* +--------------+ */
+ A.Q4, /* Q4 |1 ++ 16| VDD */ A.VDD,
+ A.Q1, /* Q1 |2 15| Q4Q */ A.Q4Q,
+ A.Q1Q, /* Q1Q |3 14| D4 */ A.D4,
+ A.D1, /* D1 |4 4042 13| D3 */ A.D3,
+ A.CLK, /* CLK |5 12| Q3Q */ A.Q3Q,
+ A.POL, /* POL |6 11| Q3 */ A.Q3,
+ A.D2, /* D2 |7 10| Q2 */ A.Q2,
+ A.VSS, /* VSS |8 9| Q2Q */ A.Q2Q
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4049_DIP
+//- Title: CD4049UBM/CD4049UBC Hex Inverting Buffer
+//- Pinalias: VDD,G,A,H,B,I,C,VSS,D,J,E,K,NC,F,L,NC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/134/109125_DS.pdf
+//-
+static NETLIST_START(CD4049_DIP)
+{
+ CD4049_GATE(A)
+ CD4049_GATE(B)
+ CD4049_GATE(C)
+ CD4049_GATE(D)
+ CD4049_GATE(E)
+ CD4049_GATE(F)
+ NC_PIN(NC)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
+
+ //DIPPINS( /* +--------------+ */
+ // A.VDD, /* VCC |1 ++ 16| NC */ NC.I,
+ // A.G, /*G=/A |2 15| L=/F*/ F.L,
+ // A.A, /* A |3 14| F */ F.F,
+ // B.H, /*H=/B |4 13| NC */ NC.I,
+ // B.B, /* B |5 4049 12| K=/E*/ E.K,
+ // C.I, /*I=/C |6 11| E */ E.E,
+ // C.C, /* C |7 10| J=/D*/ D.J,
+ // A.VSS, /* VSS |8 9| D */ D.D
+ // /* +--------------+ */
+ //)
+ DIPPINS( /* +--------------+ */
+ A.VDD, /* VCC |1 ++ 16| NC */ NC.I,
+ A.Q, /*G=/A |2 15| L=/F*/ F.Q,
+ A.A, /* A |3 14| F */ F.A,
+ B.Q, /*H=/B |4 13| NC */ NC.I,
+ B.A, /* B |5 4049 12| K=/E*/ E.Q,
+ C.Q, /*I=/C |6 11| E */ E.A,
+ C.A, /* C |7 10| J=/D*/ D.Q,
+ A.VSS, /* VSS |8 9| D */ D.A
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4053_DIP
+//- Title: CD4053BM/CD4053BC Triple 2-Channel AnalogMultiplexer/Demultiplexer
+//- Pinalias: INOUTBY,INOUTBX,INOUTCY,OUTINC,INOUTCX,INH,VEE,VSS,C,B,A,INOUTAX,INOUTAY,OUTINA,OUTINB,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005662.PDF
+//-
+static NETLIST_START(CD4053_DIP)
+{
+ CD4053_GATE(A)
+ CD4053_GATE(B)
+ CD4053_GATE(C)
+
+ NET_C(A.VEE, B.VEE, C.VEE)
+ NET_C(A.VDD, B.VDD, C.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS)
+ NET_C(A.INH, B.INH, C.INH)
+
+ PARAM(A.BASER, 270.0)
+ PARAM(B.BASER, 270.0)
+ PARAM(C.BASER, 270.0)
+
+ DIPPINS( /* +--------------+ */
+ B.Y, /* INOUTBY |1 ++ 16| VDD */ A.VDD,
+ B.X, /* INOUTBX |2 15| OUTINB */ B.XY,
+ C.Y, /* INOUTCY |3 14| OUTINA */ A.XY,
+ C.XY, /* OUTINC |4 4053 13| INOUTAY */ A.Y,
+ C.X, /* INOUTCX |5 12| INOUTAX */ A.X,
+ A.INH, /* INH |6 11| A */ A.S,
+ A.VEE, /* VEE |7 10| B */ B.S,
+ A.VSS, /* VSS |8 9| C */ C.S
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4066_DIP
+//- Title: CD4066BM/CD4066BC Quad Bilateral Switch
+//- Pinalias: INOUTA,OUTINA,OUTINB,INOUTB,CONTROLB,CONTROLC,VSS,INOUTC,OUTINC,OUTIND,INOUTD,CONTROLD,CONTROLA,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS005665.PDF
+//-
+static NETLIST_START(CD4066_DIP)
+{
+ CD4066_GATE(A)
+ CD4066_GATE(B)
+ CD4066_GATE(C)
+ CD4066_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ PARAM(A.BASER, 270.0)
+ PARAM(B.BASER, 270.0)
+ PARAM(C.BASER, 270.0)
+ PARAM(D.BASER, 270.0)
+
+ DIPPINS( /* +--------------+ */
+ A.R.1, /* INOUTA |1 ++ 14| VDD */ A.VDD,
+ A.R.2, /* OUTINA |2 13| CONTROLA */ A.CTL,
+ B.R.1, /* OUTINB |3 12| CONTROLD */ D.CTL,
+ B.R.2, /* INOUTB |4 4066 11| INOUTD */ D.R.1,
+ B.CTL, /* CONTROLB |5 10| OUTIND */ D.R.2,
+ C.CTL, /* CONTROLC |6 9| OUTINC */ C.R.1,
+ A.VSS, /* VSS |7 8| INOUTC */ C.R.2
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4069_DIP
+//- Title: CD4069UBM/CD4069UBC Inverter Circuits
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,VSS,Y4,A4,Y5,A5,Y6,A6,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
+//-
+static NETLIST_START(CD4069_DIP)
+{
+ CD4069_GATE(A)
+ CD4069_GATE(B)
+ CD4069_GATE(C)
+ CD4069_GATE(D)
+ CD4069_GATE(E)
+ CD4069_GATE(F)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
+ A.Q, /* Y1 |2 13| A6 */ F.A,
+ B.A, /* A2 |3 12| Y6 */ F.Q,
+ B.Q, /* Y2 |4 4069 11| A5 */ E.A,
+ C.A, /* A3 |5 10| Y5 */ E.Q,
+ C.Q, /* Y3 |6 9| A4 */ D.A,
+ A.VSS, /* VSS |7 8| Y4 */ D.Q
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4070_DIP
+//- Title: CD4070BM/CD4070BC Quad 2-Input EXCLUSIVE-OR Gate
+//- Pinalias: A,B,J,K,C,D,VSS,E,F,L,M,G,H,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/150/206783_DS.pdf
+//-
+static NETLIST_START(CD4070_DIP)
+{
+ CD4070_GATE(A)
+ CD4070_GATE(B)
+ CD4070_GATE(C)
+ CD4070_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A |1 ++ 14| VDD */ A.VDD,
+ A.B, /* B |2 13| H */ D.B,
+ A.Q, /* J |3 12| G */ D.A,
+ B.Q, /* K |4 4070 11| M */ D.Q,
+ B.A, /* C |5 10| L */ C.Q,
+ B.B, /* D |6 9| F */ C.B,
+ A.VSS, /* VSS |7 8| E */ C.A
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4071_DIP
+//- Title: CD4071BC Quad 2-Input OR Buffered B Series Gate
+//- Pinalias: A,B,J,K,C,D,VSS,E,F,L,M,G,H,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/185/109289_DS.pdf
+//-
+static NETLIST_START(CD4071_DIP)
+{
+ CD4071_GATE(A)
+ CD4071_GATE(B)
+ CD4071_GATE(C)
+ CD4071_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A |1 ++ 14| VDD */ A.VDD,
+ A.B, /* B |2 13| H */ D.B,
+ A.Q, /* J |3 12| G */ D.A,
+ B.Q, /* K |4 4071 11| M */ D.Q,
+ B.A, /* C |5 10| L */ C.Q,
+ B.B, /* D |6 9| F */ C.B,
+ A.VSS, /* VSS |7 8| E */ C.A
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4076_DIP
+//- Title: CD4076BM/CD4076BC TRI-STATE(R) Quad D Flip-Flop
+//- Pinalias: OD1,OD2,OA,OB,OC,OD,CLK,VSS,ID1,ID2,ID,IC,IB,IA,CLR,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- Voltage-dependent timing is not implemented.
+//- FunctionTable:
+//- http://www.bitsavers.org/components/national/_dataBooks/1981_Natonal_CMOS_Databook.pdf 5-186 (pdf page 567)
+//-
+//- Function table for ID1/2 pins
+//- +-----+-----+-----+----+-----++-----+
+//- | ID1 | ID2 | CLR | Ix | CLK || iOx |
+//- +=====+=====+=====+====+=====++=====+
+//- | X | X | 0 | X | 0 || iOx |
+//- | X | X | 0 | X | 1 || iOx |
+//- | 1 | X | 0 | X | 0>1 || iOx |
+//- | X | 1 | 0 | X | 0>1 || iOx |
+//- | 0 | 0 | 0 | 0 | 0>1 || 0 |
+//- | 0 | 0 | 0 | 1 | 0>1 || 1 |
+//- | X | X | 1 | X | X || 0 |
+//- +-----+-----+-----+----+-----++-----+
+//- Note: iOX is an internal signal, the output of each D-latch
+//-
+//- Function table for OD1/2 pins vs output of the internal D-latches
+//- +-----+-----+-----++-----+
+//- | OD1 | OD2 | iOx || Ox |
+//- +=====+=====+=====++=====+
+//- | 1 | X | X || Z |
+//- | X | 1 | X || Z |
+//- | 0 | 0 | 0 || 0 |
+//- | 0 | 0 | 1 || 1 |
+//- +-----+-----+-----++-----+
+//-
+static NETLIST_START(CD4076_DIP)
+{
+ CD4076(A)
+
+ DIPPINS( /* +--------------+ */
+ A.OD1, /* OD1 |1 ++ 16| VDD */ A.VDD,
+ A.OD2, /* OD2 |2 15| CLR */ A.CLR,
+ A.OA, /* OA |3 14| IA */ A.IA,
+ A.OB, /* OB |4 4076 13| IB */ A.IB,
+ A.OC, /* OC |5 12| IC */ A.IC,
+ A.OD, /* OD |6 11| ID */ A.ID,
+ A.CLK, /* CLK |7 10| ID2 */ A.ID2,
+ A.VSS, /* VSS |8 9| ID1 */ A.ID1
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4081_DIP
+//- Title: CD4081BC Quad 2-Input AND Buffered B Series Gate
+//- Pinalias: A,B,J,K,C,D,VSS,E,F,L,M,G,H,VDD
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/185/109289_DS.pdf
+//-
+static NETLIST_START(CD4081_DIP)
+{
+ CD4081_GATE(A)
+ CD4081_GATE(B)
+ CD4081_GATE(C)
+ CD4081_GATE(D)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.A, /* A |1 ++ 14| VDD */ A.VDD,
+ A.B, /* B |2 13| H */ D.B,
+ A.Q, /* J |3 12| G */ D.A,
+ B.Q, /* K |4 4081 11| M */ D.Q,
+ B.A, /* C |5 10| L */ C.Q,
+ B.B, /* D |6 9| F */ C.B,
+ A.VSS, /* VSS |7 8| E */ C.A
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4316_DIP
+//- Title: 74HC/HCT4316 Quad bilateral switches
+//- Pinalias: 1Z,1Y,2Y,2Z,2S,3S,EQ,GND,VEE,3Z,3Y,4Y,4Z,4S,1S,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Philips datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/philips/74HCT4316.pdf
+//-
+static NETLIST_START(CD4316_DIP)
+{
+ CD4316_GATE(A)
+ CD4316_GATE(B)
+ CD4316_GATE(C)
+ CD4316_GATE(D)
+
+ NET_C(A.E, B.E, C.E, D.E)
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
+
+ PARAM(A.BASER, 45.0)
+ PARAM(B.BASER, 45.0)
+ PARAM(C.BASER, 45.0)
+ PARAM(D.BASER, 45.0)
+
+ DIPPINS( /* +--------------+ */
+ A.R.2, /* 1Z |1 ++ 16| VCC */ A.VDD,
+ A.R.1, /* 1Y |2 15| 1S */ A.S,
+ B.R.1, /* 2Y |3 14| 4S */ D.S,
+ B.R.2, /* 2Z |4 4316 13| 4Z */ D.R.2,
+ B.S, /* 2S |5 12| 4Y */ D.R.1,
+ C.S, /* 3S |6 11| 3Y */ C.R.1,
+ A.E, /* EQ |7 10| 3Z */ C.R.2,
+ A.VSS, /* GND |8 9| VEE */ VEE
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: CD4538_DIP
+//- Title: CD4538BC Dual Precision Monostable
+//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50871/FAIRCHILD/CD4538.html
+//-
+static NETLIST_START(CD4538_DIP)
+{
+ CD4538(A)
+ CD4538(B)
+
+ NET_C(A.VDD, B.VDD)
+ NET_C(A.VSS, B.VSS)
+
+ DIPPINS( /* +--------------+ */
+ A.C, /* 1Z |1 ++ 16| VCC */ A.VDD,
+ A.RC, /* 1Y |2 15| 1S */ B.C,
+ A.CLRQ, /* 2Y |3 14| 4S */ B.RC,
+ A.A, /* 2Z |4 4316 13| 4Z */ B.CLRQ,
+ A.B, /* 2S |5 12| 4Y */ B.A,
+ A.Q, /* 3S |6 11| 3Y */ B.B,
+ A.QQ, /* EQ |7 10| 3Z */ B.Q,
+ A.VSS, /* GND |8 9| VEE */ B.QQ
+ /* +--------------+ */
+ )
+}
+
+//FIXME: Documentation
+static NETLIST_START(MM5837_DIP)
+{
+ MM5837(A)
+ NC_PIN(NC)
+
+ // Create a parameter freq for the dip model
+ // The default will be A's FREQ parameter.
+ DEFPARAM(FREQ, "$(@.A.FREQ")
+ PARAM(A.FREQ, "$(@.FREQ)")
+
+ DIPPINS( /* +--------+ */
+ A.VDD, /* VDD |1 ++ 8| NC */ NC.I,
+ A.VGG, /* VGG |2 7| NC */ NC.I,
+ A.OUT, /* OUT |3 6| NC */ NC.I,
+ A.VSS, /* VSS |4 5| NC */ NC.I
+ /* +--------+ */
+ )
+}
+
+static TRUTH_TABLE(CD4001_GATE, 2, 1, "")
+{
+ TT_HEAD("A , B | Q ")
+ TT_LINE("0,0|1|110")
+ TT_LINE("X,1|0|120")
+ TT_LINE("1,X|0|120")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4011_GATE, 2, 1, "")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,X|1|100")
+ TT_LINE("X,0|1|100")
+ TT_LINE("1,1|0|100")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4030_GATE, 2, 1, "")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,0|0|100")
+ TT_LINE("0,1|1|100")
+ TT_LINE("1,0|1|100")
+ TT_LINE("1,1|0|100")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4049_GATE, 1, 1, "")
+{
+ TT_HEAD("A|Q ")
+ TT_LINE("0|1|45")
+ TT_LINE("1|0|45")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4069_GATE, 1, 1, "")
+{
+ TT_HEAD("A|Q ")
+ TT_LINE("0|1|55")
+ TT_LINE("1|0|55")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4070_GATE, 2, 1, "")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,0|0|15")
+ TT_LINE("0,1|1|22")
+ TT_LINE("1,0|1|22")
+ TT_LINE("1,1|0|15")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4071_GATE, 2, 1, "")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,0|0|200")
+ TT_LINE("0,1|1|200")
+ TT_LINE("1,0|1|200")
+ TT_LINE("1,1|1|200")
+ TT_FAMILY("CD4XXX")
+}
+
+static TRUTH_TABLE(CD4081_GATE, 2, 1, "")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,0|0|200")
+ TT_LINE("0,1|0|200")
+ TT_LINE("1,0|0|200")
+ TT_LINE("1,1|1|200")
+ TT_FAMILY("CD4XXX")
+}
+
+NETLIST_START(cd4xxx_lib)
+{
+
+ TRUTHTABLE_ENTRY(CD4001_GATE)
+ TRUTHTABLE_ENTRY(CD4011_GATE)
+ TRUTHTABLE_ENTRY(CD4030_GATE)
+ TRUTHTABLE_ENTRY(CD4049_GATE)
+ TRUTHTABLE_ENTRY(CD4069_GATE)
+ TRUTHTABLE_ENTRY(CD4070_GATE)
+ TRUTHTABLE_ENTRY(CD4071_GATE)
+ TRUTHTABLE_ENTRY(CD4081_GATE)
+
+ LOCAL_LIB_ENTRY(CD4001_DIP)
+ LOCAL_LIB_ENTRY(CD4011_DIP)
+ LOCAL_LIB_ENTRY(CD4030_DIP)
+ LOCAL_LIB_ENTRY(CD4049_DIP)
+ LOCAL_LIB_ENTRY(CD4069_DIP)
+ LOCAL_LIB_ENTRY(CD4070_DIP)
+ LOCAL_LIB_ENTRY(CD4071_DIP)
+ LOCAL_LIB_ENTRY(CD4081_DIP)
+
+ /* DIP ONLY */
+ LOCAL_LIB_ENTRY(CD4006_DIP)
+ LOCAL_LIB_ENTRY(CD4013_DIP)
+ LOCAL_LIB_ENTRY(CD4017_DIP)
+ LOCAL_LIB_ENTRY(CD4022_DIP)
+ LOCAL_LIB_ENTRY(CD4020_DIP)
+ LOCAL_LIB_ENTRY(CD4024_DIP)
+ LOCAL_LIB_ENTRY(CD4029_DIP)
+ LOCAL_LIB_ENTRY(CD4042_DIP)
+ LOCAL_LIB_ENTRY(CD4053_DIP)
+ LOCAL_LIB_ENTRY(CD4066_DIP)
+ LOCAL_LIB_ENTRY(CD4016_DIP)
+ LOCAL_LIB_ENTRY(CD4076_DIP)
+ LOCAL_LIB_ENTRY(CD4316_DIP)
+ LOCAL_LIB_ENTRY(CD4538_DIP)
+
+ LOCAL_LIB_ENTRY(MM5837_DIP)
+
+}
diff --git a/src/lib/netlist/macro/nlm_opamp.cpp b/src/lib/netlist/macro/nlm_opamp.cpp
deleted file mode 100644
index 34c0791e312..00000000000
--- a/src/lib/netlist/macro/nlm_opamp.cpp
+++ /dev/null
@@ -1,374 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#include "nlm_opamp.h"
-#include "netlist/devices/net_lib.h"
-
-/*
- * 0 = Basic hack (Norton with just amplification, no voltage cutting)
- * 1 = Model from LTSPICE mailing list - slow!
- * 2 = Simplified model using diode inputs and netlist TYPE=3
- * 3 = Model according to datasheet
- *
- * For Money Money 1 and 3 delivery comparable results.
- * 3 is simpler (less BJTs) and converges a lot faster.
- */
-#define USE_LM3900_MODEL (3)
-
-/*
- * Generic layout with 4 opamps, VCC on pin 4 and GND on pin 11
- */
-
-static NETLIST_START(opamp_layout_4_4_11)
- DIPPINS( /* +--------------+ */
- A.OUT, /* |1 ++ 14| */ D.OUT,
- A.MINUS, /* |2 13| */ D.MINUS,
- A.PLUS, /* |3 12| */ D.PLUS,
- A.VCC, /* |4 11| */ A.GND,
- B.PLUS, /* |5 10| */ C.PLUS,
- B.MINUS, /* |6 9| */ C.MINUS,
- B.OUT, /* |7 8| */ C.OUT
- /* +--------------+ */
- )
- NET_C(A.GND, B.GND, C.GND, D.GND)
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
-NETLIST_END()
-
-/*
- * Generic layout with 2 opamps, VCC on pin 8 and GND on pin 4
- */
-
-static NETLIST_START(opamp_layout_2_8_4)
- DIPPINS( /* +--------------+ */
- A.OUT, /* |1 ++ 8| */ A.VCC,
- A.MINUS, /* |2 7| */ B.OUT,
- A.PLUS, /* |3 6| */ B.MINUS,
- A.GND, /* |4 5| */ B.PLUS
- /* +--------------+ */
- )
- NET_C(A.GND, B.GND)
- NET_C(A.VCC, B.VCC)
-NETLIST_END()
-
-/*
- * Generic layout with 2 opamps, VCC+ on pins 9/13, VCC- on pin 4 and compensation
- */
-
-static NETLIST_START(opamp_layout_2_13_9_4)
- DIPPINS( /* +--------------+ */
- A.MINUS, /* |1 ++ 14| */ A.N2,
- A.PLUS, /* |2 13| */ A.VCC,
- A.N1, /* |3 12| */ A.OUT,
- A.GND, /* |4 11| */ NC,
- B.N1, /* |5 10| */ B.OUT,
- B.PLUS, /* |6 9| */ B.VCC,
- B.MINUS, /* |7 8| */ B.N2
- /* +--------------+ */
- )
- NET_C(A.GND, B.GND)
-NETLIST_END()
-
-/*
- * Generic layout with 1 opamp, VCC+ on pin 7, VCC- on pin 4 and compensation
- */
-
-static NETLIST_START(opamp_layout_1_7_4)
- DIPPINS( /* +--------------+ */
- OFFSET.N1, /* |1 ++ 8| */ NC,
- MINUS, /* |2 7| */ VCC.PLUS,
- PLUS, /* |3 6| */ OUT,
- VCC.MINUS, /* |4 5| */ OFFSET.N2
- /* +--------------+ */
- )
- NET_C(A.GND, VCC.MINUS)
- NET_C(A.VCC, VCC.PLUS)
- NET_C(A.MINUS, MINUS)
- NET_C(A.PLUS, PLUS)
- NET_C(A.OUT, OUT)
-NETLIST_END()
-
-/*
- * Generic layout with 1 opamp, VCC+ on pin 8, VCC- on pin 5 and compensation
- */
-
-static NETLIST_START(opamp_layout_1_8_5)
- DIPPINS( /* +--------------+ */
- NC.1, /* |1 10| */ NC.3,
- OFFSET.N1, /* |2 9| */ NC.2,
- MINUS, /* |3 8| */ VCC.PLUS,
- PLUS, /* |4 7| */ OUT,
- VCC.MINUS, /* |5 6| */ OFFSET.N2
- /* +--------------+ */
- )
- NET_C(A.GND, VCC.MINUS)
- NET_C(A.VCC, VCC.PLUS)
- NET_C(A.MINUS, MINUS)
- NET_C(A.PLUS, PLUS)
- NET_C(A.OUT, OUT)
-NETLIST_END()
-
-/*
- * Generic layout with 1 opamp, VCC+ on pin 11, VCC- on pin 6 and compensation
- */
-
-static NETLIST_START(opamp_layout_1_11_6)
- DIPPINS( /* +--------------+ */
- NC.1, /* |1 ++ 14| */ NC.7,
- NC.2, /* |2 13| */ NC.6,
- OFFSET.N1, /* |3 12| */ NC.5,
- MINUS, /* |4 11| */ VCC.PLUS,
- PLUS, /* |5 10| */ OUT,
- VCC.MINUS, /* |6 9| */ OFFSET.N2,
- NC.3, /* |7 8| */ NC.4
- /* +--------------+ */
- )
- NET_C(A.GND, VCC.MINUS)
- NET_C(A.VCC, VCC.PLUS)
- NET_C(A.MINUS, MINUS)
- NET_C(A.PLUS, PLUS)
- NET_C(A.OUT, OUT)
-NETLIST_END()
-
-static NETLIST_START(MB3614_DIP)
- OPAMP(A, "MB3614")
- OPAMP(B, "MB3614")
- OPAMP(C, "MB3614")
- OPAMP(D, "MB3614")
-
- INCLUDE(opamp_layout_4_4_11)
-
-NETLIST_END()
-
-static NETLIST_START(LM324_DIP)
- OPAMP(A, "LM324")
- OPAMP(B, "LM324")
- OPAMP(C, "LM324")
- OPAMP(D, "LM324")
-
- INCLUDE(opamp_layout_4_4_11)
-
-NETLIST_END()
-
-static NETLIST_START(LM2902_DIP)
- // Same datasheet and mostly same characteristics as LM324
- OPAMP(A, "LM324")
- OPAMP(B, "LM324")
- OPAMP(C, "LM324")
- OPAMP(D, "LM324")
-
- INCLUDE(opamp_layout_4_4_11)
-
-NETLIST_END()
-
-static NETLIST_START(LM358_DIP)
- OPAMP(A, "LM358")
- OPAMP(B, "LM358")
-
- INCLUDE(opamp_layout_2_8_4)
-
-NETLIST_END()
-
-static NETLIST_START(UA741_DIP8)
- OPAMP(A, "UA741")
-
- INCLUDE(opamp_layout_1_7_4)
-
-NETLIST_END()
-
-static NETLIST_START(UA741_DIP10)
- OPAMP(A, "UA741")
-
- INCLUDE(opamp_layout_1_8_5)
-
-NETLIST_END()
-
-static NETLIST_START(UA741_DIP14)
- OPAMP(A, "UA741")
-
- INCLUDE(opamp_layout_1_11_6)
-
-NETLIST_END()
-
-static NETLIST_START(LM747_DIP)
- OPAMP(A, "LM747")
- OPAMP(B, "LM747")
-
- INCLUDE(opamp_layout_2_13_9_4)
- NET_C(A.VCC, B.VCC)
-
-NETLIST_END()
-
-static NETLIST_START(LM747A_DIP)
- OPAMP(A, "LM747A")
- OPAMP(B, "LM747A")
-
- INCLUDE(opamp_layout_2_13_9_4)
- NET_C(A.VCC, B.VCC)
-
-NETLIST_END()
-
-#if USE_LM3900_MODEL == 0
-static NETLIST_START(LM3900)
-
- /*
- * Fast norton opamp model without bandwidth
- */
-
- /* Terminal definitions for calling netlists */
-
- ALIAS(PLUS, R1.1) // Positive input
- ALIAS(MINUS, R2.1) // Negative input
- ALIAS(OUT, G1.OP) // Opamp output ...
- ALIAS(GND, G1.ON) // V- terminal
- ALIAS(VCC, DUMMY.I) // V+ terminal
-
- DUMMY_INPUT(DUMMY)
-
- /* The opamp model */
-
- RES(R1, 1)
- RES(R2, 1)
- NET_C(R1.1, G1.IP)
- NET_C(R2.1, G1.IN)
- NET_C(R1.2, R2.2, G1.ON)
- VCVS(G1)
- PARAM(G1.G, 10000000)
- //PARAM(G1.RI, 1)
- PARAM(G1.RO, RES_K(8))
-
-NETLIST_END()
-#endif
-
-#if USE_LM3900_MODEL == 1
-// LTSPICE MODEL OF LM3900 FROM NATIONAL SEMICONDUCTOR
-// MADE BY HELMUT SENNEWALD, 8/6/2004
-// THE LM3900 IS A SO CALLED NORTON AMPLIFIER.
-//
-// PIN ORDER: IN+ IN- VCC VSS OUT
-static NETLIST_START(LM3900)
- PARAM(E1.G, 0.5)
- //ALIAS(IN+, Q2.B)
- //ALIAS(IN-, Q2.C)
- //ALIAS(VCC, Q10.C)
- //ALIAS(VSS, Q2.E)
-
- ALIAS(PLUS, Q2.B)
- ALIAS(MINUS, Q2.C)
- ALIAS(VCC, Q10.C)
- ALIAS(GND, Q2.E)
- ALIAS(OUT, Q6.C)
-
- //CS(B1/*I=LIMIT(0, V(VCC,VSS)/10K, 0.2m)*/)
- CS(B1, 2e-4)
- CAP(C1, CAP_P(6.000000))
- VCVS(E1)
- QBJT_EB(Q1, "LM3900_NPN1")
- QBJT_EB(Q10, "LM3900_NPN1")
- QBJT_EB(Q11, "LM3900_NPN1")
- QBJT_EB(Q12, "LM3900_NPN1")
- QBJT_EB(Q2, "LM3900_NPN1")
- QBJT_EB(Q3, "LM3900_NPN1")
- QBJT_EB(Q4, "LM3900_PNP1")
- QBJT_EB(Q5, "LM3900_PNP1")
- QBJT_EB(Q6, "LM3900_PNP1")
- QBJT_EB(Q7, "LM3900_PNP1")
- QBJT_EB(Q8, "LM3900_NPN1")
- QBJT_EB(Q9, "LM3900_NPN1")
- RES(R1, RES_K(2.000000))
- RES(R6, RES_K(1.600000))
- NET_C(Q11.B, Q12.B, R6.2)
- NET_C(Q5.C, Q5.B, B1.P, Q4.B)
- NET_C(Q8.C, Q8.B, B1.N, R1.1, E1.IP)
- NET_C(Q9.B, R1.2)
- NET_C(R6.1, E1.OP)
- NET_C(Q10.C, Q5.E, Q4.E, Q11.C, Q12.C)
- NET_C(Q2.C, Q3.B, Q12.E)
- NET_C(Q2.E, Q3.E, Q9.E, C1.2, Q1.E, Q8.E, E1.ON, E1.IN, Q7.C)
- NET_C(Q3.C, Q6.B, C1.1, Q7.B)
- NET_C(Q6.E, Q10.B, Q4.C)
- NET_C(Q6.C, Q10.E, Q9.C, Q7.E)
- NET_C(Q2.B, Q1.C, Q1.B, Q11.E)
-NETLIST_END()
-#endif
-
-#if USE_LM3900_MODEL == 2
-static NETLIST_START(LM3900)
- OPAMP(A, "LM3900")
-
- DIODE(D1, "D(IS=1e-15 N=1)")
- CCCS(CS1) // Current Mirror
-
- ALIAS(VCC, A.VCC)
- ALIAS(GND, A.GND)
- ALIAS(PLUS, A.PLUS)
- ALIAS(MINUS, A.MINUS)
- ALIAS(OUT, A.OUT)
-
- NET_C(A.PLUS, CS1.IP)
- NET_C(D1.A, CS1.IN)
- NET_C(CS1.OP, A.MINUS)
- NET_C(CS1.ON, A.GND, D1.K)
-
-NETLIST_END()
-#endif
-
-#if USE_LM3900_MODEL == 3
-static NETLIST_START(LM3900)
-
- ALIAS(VCC, Q5.C)
- ALIAS(GND, Q1.E)
- ALIAS(PLUS, Q1.B)
- ALIAS(MINUS, Q1.C)
- ALIAS(OUT, Q5.E)
-
- CAP(C1, CAP_P(6.000000))
- CS(I1, 1.300000e-3)
- CS(I2, 200e-6)
- QBJT_EB(Q1, "NPN")
- QBJT_EB(Q2, "NPN")
- QBJT_EB(Q3, "PNP")
- QBJT_EB(Q4, "PNP")
- QBJT_EB(Q5, "NPN")
- QBJT_EB(Q6, "NPN")
- NET_C(Q3.E, Q5.B, I2.2)
- NET_C(Q3.C, Q4.E, Q5.E, I1.1)
- NET_C(Q5.C, I2.1)
- NET_C(Q1.B, Q6.C, Q6.B)
- NET_C(Q1.E, Q2.E, Q4.C, C1.2, I1.2, Q6.E)
- NET_C(Q1.C, Q2.B)
- NET_C(Q2.C, Q3.B, Q4.B, C1.1)
-NETLIST_END()
-#endif
-
-NETLIST_START(OPAMP_lib)
- LOCAL_LIB_ENTRY(opamp_layout_4_4_11)
- LOCAL_LIB_ENTRY(opamp_layout_2_8_4)
- LOCAL_LIB_ENTRY(opamp_layout_2_13_9_4)
- LOCAL_LIB_ENTRY(opamp_layout_1_7_4)
- LOCAL_LIB_ENTRY(opamp_layout_1_8_5)
- LOCAL_LIB_ENTRY(opamp_layout_1_11_6)
-
- NET_MODEL("LM324 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.00075)")
- NET_MODEL("LM358 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.001)")
- NET_MODEL("MB3614 OPAMP(TYPE=3 VLH=1.4 VLL=0.02 FPF=10 UGF=1000k SLEW=0.6M RI=1000k RO=50 DAB=0.002)")
- NET_MODEL("UA741 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=75 DAB=0.0017)")
- NET_MODEL("LM747 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=50 DAB=0.0017)")
- NET_MODEL("LM747A OPAMP(TYPE=3 VLH=2.0 VLL=2.0 FPF=5 UGF=1000k SLEW=0.7M RI=6000k RO=50 DAB=0.0015)")
- // TI and Motorola Datasheets differ - below are Motorola values values SLEW is average of LH and HL
- NET_MODEL("LM3900 OPAMP(TYPE=3 VLH=1.0 VLL=0.03 FPF=2k UGF=4M SLEW=10M RI=10M RO=2k DAB=0.0015)")
-
-#if USE_LM3900_MODEL == 1
- NET_MODEL("LM3900_NPN1 NPN(IS=1E-14 BF=150 TF=1E-9 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5 IKF=0.002)")
- NET_MODEL("LM3900_PNP1 PNP(IS=1E-14 BF=40 TF=1E-7 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5)")
-#endif
- LOCAL_LIB_ENTRY(MB3614_DIP)
- LOCAL_LIB_ENTRY(LM324_DIP)
- LOCAL_LIB_ENTRY(LM358_DIP)
- LOCAL_LIB_ENTRY(LM2902_DIP)
- LOCAL_LIB_ENTRY(UA741_DIP8)
- LOCAL_LIB_ENTRY(UA741_DIP10)
- LOCAL_LIB_ENTRY(UA741_DIP14)
- LOCAL_LIB_ENTRY(LM747_DIP)
- LOCAL_LIB_ENTRY(LM747A_DIP)
- LOCAL_LIB_ENTRY(LM3900)
-
-NETLIST_END()
diff --git a/src/lib/netlist/macro/nlm_opamp.h b/src/lib/netlist/macro/nlm_opamp.h
deleted file mode 100644
index 13d2254d952..00000000000
--- a/src/lib/netlist/macro/nlm_opamp.h
+++ /dev/null
@@ -1,41 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#ifndef NLM_OPAMP_H_
-#define NLM_OPAMP_H_
-
-#include "netlist/nl_setup.h"
-
-#ifndef __PLIB_PREPROCESSOR__
-
-/* ----------------------------------------------------------------------------
- * Netlist Macros
- * ---------------------------------------------------------------------------*/
-
-#ifndef NL_AUTO_DEVICES
-
-#define MB3614_DIP(name) \
- NET_REGISTER_DEV(MB3614_DIP, name)
-
-#define LM324_DIP(name) \
- NET_REGISTER_DEV(LM324_DIP, name)
-
-#define LM2902_DIP(name) \
- NET_REGISTER_DEV(LM2902_DIP, name)
-
-#define LM358_DIP(name) \
- NET_REGISTER_DEV(LM358_DIP, name)
-
-#define LM3900(name) \
- NET_REGISTER_DEV(LM3900, name)
-
-#endif
-
-/* ----------------------------------------------------------------------------
- * External declarations
- * ---------------------------------------------------------------------------*/
-
-NETLIST_EXTERNAL(OPAMP_lib)
-
-#endif
-
-#endif
diff --git a/src/lib/netlist/macro/nlm_opamp_lib.cpp b/src/lib/netlist/macro/nlm_opamp_lib.cpp
new file mode 100644
index 00000000000..26e9adba7c8
--- /dev/null
+++ b/src/lib/netlist/macro/nlm_opamp_lib.cpp
@@ -0,0 +1,685 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+#include "devices/net_lib.h"
+
+/*
+ * 0 = Basic hack (Norton with just amplification, no voltage cutting)
+ * 1 = Model from LTSPICE mailing list - slow!
+ * 2 = Simplified model using diode inputs and netlist
+ * 3 = Model according to datasheet
+ * 4 = Faster model by Colin Howell
+ *
+ * For Money Money 1 and 3 delivery comparable results.
+ * 3 is simpler (less BJTs) and converges a lot faster.
+ *
+ * Model 4 uses a lot less resources and pn-junctions. The preferred new normal.
+ */
+#define USE_LM3900_MODEL (4)
+
+/*
+ * Generic layout with 4 opamps, VCC on pin 4 and GND on pin 11
+ */
+
+static NETLIST_START(opamp_layout_4_4_11)
+{
+ DIPPINS( /* +--------------+ */
+ A.OUT, /* |1 ++ 14| */ D.OUT,
+ A.MINUS, /* |2 13| */ D.MINUS,
+ A.PLUS, /* |3 12| */ D.PLUS,
+ A.VCC, /* |4 11| */ A.GND,
+ B.PLUS, /* |5 10| */ C.PLUS,
+ B.MINUS, /* |6 9| */ C.MINUS,
+ B.OUT, /* |7 8| */ C.OUT
+ /* +--------------+ */
+ )
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+}
+
+/*
+ * Generic layout with 2 opamps, VCC on pin 8 and GND on pin 4
+ */
+
+static NETLIST_START(opamp_layout_2_8_4)
+{
+ DIPPINS( /* +--------------+ */
+ A.OUT, /* |1 ++ 8| */ A.VCC,
+ A.MINUS, /* |2 7| */ B.OUT,
+ A.PLUS, /* |3 6| */ B.MINUS,
+ A.GND, /* |4 5| */ B.PLUS
+ /* +--------------+ */
+ )
+ NET_C(A.GND, B.GND)
+ NET_C(A.VCC, B.VCC)
+}
+
+/*
+ * Generic layout with 2 opamps, VCC+ on pins 9/13, VCC- on pin 4 and compensation
+ */
+
+static NETLIST_START(opamp_layout_2_13_9_4)
+{
+ DIPPINS( /* +--------------+ */
+ A.MINUS, /* |1 ++ 14| */ A.N2,
+ A.PLUS, /* |2 13| */ A.VCC,
+ A.N1, /* |3 12| */ A.OUT,
+ A.GND, /* |4 11| */ NC,
+ B.N1, /* |5 10| */ B.OUT,
+ B.PLUS, /* |6 9| */ B.VCC,
+ B.MINUS, /* |7 8| */ B.N2
+ /* +--------------+ */
+ )
+ NET_C(A.GND, B.GND)
+}
+
+/*
+ * Generic layout with 1 opamp, VCC+ on pin 7, VCC- on pin 4 and compensation
+ * // FIXME: Offset inputs are not supported!
+ */
+
+static NETLIST_START(opamp_layout_1_7_4)
+{
+ DIPPINS( /* +--------------+ */
+ NC /* OFFSET */, /* |1 ++ 8| */ NC,
+ A.MINUS, /* |2 7| */ A.VCC,
+ A.PLUS, /* |3 6| */ A.OUT,
+ A.GND, /* |4 5| */ NC /* OFFSET */
+ /* +--------------+ */
+ )
+}
+
+/*
+ * Generic layout with 1 opamp, VCC+ on pin 8, VCC- on pin 5 and compensation
+ */
+
+static NETLIST_START(opamp_layout_1_8_5)
+{
+ DIPPINS( /* +--------------+ */
+ NC.1, /* |1 10| */ NC.3,
+ OFFSET.N1, /* |2 9| */ NC.2,
+ MINUS, /* |3 8| */ VCC.PLUS,
+ PLUS, /* |4 7| */ OUT,
+ VCC.MINUS, /* |5 6| */ OFFSET.N2
+ /* +--------------+ */
+ )
+ NET_C(A.GND, VCC.MINUS)
+ NET_C(A.VCC, VCC.PLUS)
+ NET_C(A.MINUS, MINUS)
+ NET_C(A.PLUS, PLUS)
+ NET_C(A.OUT, OUT)
+}
+
+/*
+ * Generic layout with 1 opamp, VCC+ on pin 11, VCC- on pin 6 and compensation
+ */
+
+static NETLIST_START(opamp_layout_1_11_6)
+{
+ DIPPINS( /* +--------------+ */
+ NC.1, /* |1 ++ 14| */ NC.7,
+ NC.2, /* |2 13| */ NC.6,
+ OFFSET.N1, /* |3 12| */ NC.5,
+ MINUS, /* |4 11| */ VCC.PLUS,
+ PLUS, /* |5 10| */ OUT,
+ VCC.MINUS, /* |6 9| */ OFFSET.N2,
+ NC.3, /* |7 8| */ NC.4
+ /* +--------------+ */
+ )
+ NET_C(A.GND, VCC.MINUS)
+ NET_C(A.VCC, VCC.PLUS)
+ NET_C(A.MINUS, MINUS)
+ NET_C(A.PLUS, PLUS)
+ NET_C(A.OUT, OUT)
+}
+
+static NETLIST_START(MB3614_DIP)
+{
+ OPAMP(A, "MB3614")
+ OPAMP(B, "MB3614")
+ OPAMP(C, "MB3614")
+ OPAMP(D, "MB3614")
+
+ INCLUDE(opamp_layout_4_4_11)
+
+}
+
+static NETLIST_START(MC3340_DIP)
+{
+ // A netlist description of the Motorola MC3340 Electronic Attenuator
+ // IC, a voltage-controlled amplifier/attenuator. It amplifies or
+ // attenuates an input signal according to the voltage of a second,
+ // control signal, with a maximum gain of about 12-13 dB (about a
+ // factor of 4 in voltage), and higher control voltages giving greater
+ // attenuation, which scales logarithmically.
+
+ // The netlist here is based on the circuit schematic given in
+ // Motorola's own data books, especially the most recent ones
+ // published in the 1990s (e.g. _Motorola Analog/Interface ICs Device
+ // Data, Vol. II_ (1996), p. 9-67), which are the only schematics that
+ // include resistor values. However, the 1990s schematics are missing
+ // one crossover connection which is present in older schematics
+ // published in the 1970s (e.g. _Motorola Linear Integrated Circuits_
+ // (1979), p. 5-130). This missing connection is clearly an error
+ // which has been fixed in this netlist; without it, the circuit won't
+ // amplify properly, generating only a very weak output signal.
+
+ // The 1990s schematics also omit a couple of diodes which are present
+ // in the 1970s schematics. Both of these diodes have been included
+ // here. One raises the minimum control voltage at which signal
+ // attenuation starts, so it makes the netlist's profile of
+ // attenuation vs. control voltage better match Motorola's charts for
+ // the device. The other affects the level of the input "midpoint",
+ // and including it makes the engine sound closer to that on real
+ // 280-ZZZAP machines.
+
+ // The Motorola schematics do not label components, so I've created my
+ // own labeling scheme based on numbering components on the schematics
+ // from top to bottom, left to right, with resistors also getting
+ // their value (expressed European-style to avoid decimal points) as
+ // part of the name. The netlist is also listed following the
+ // schematics in roughly top-to-bottom, left-to-right order.
+
+ // A very simple model is used for the transistors here, based on the
+ // generic NPN default but with a larger scale current. Again, this
+ // was chosen to better match the netlist's attenuation vs. control
+ // voltage profile to that given in Motorola's charts for the device.
+
+ // The MC3340 has the same circuit internally as an older Motorola
+ // device, the MFC6040, which was replaced by the MC3340 in the
+ // mid-1970s. The two chips differ only in packaging. Older arcade
+ // games which use the MFC6040 may also benefit from this netlist
+ // implementation.
+
+ RES(R1_5K1, RES_K(5.1))
+
+ DIODE(D1, "D(IS=1e-15 N=1)")
+
+ RES(R2_4K7, RES_K(4.7))
+
+ QBJT_EB(Q1, "NPN(IS=1E-13 BF=100)")
+
+ RES(R3_750, RES_R(750))
+ RES(R4_10K, RES_K(10))
+
+ QBJT_EB(Q2, "NPN(IS=1E-13 BF=100)")
+
+ RES(R5_750, RES_R(750))
+ RES(R6_3K9, RES_K(3.9))
+
+ RES(R7_5K1, RES_K(5.1))
+ RES(R8_20K, RES_K(20))
+
+ DIODE(D2, "D(IS=1e-15 N=1)")
+
+ RES(R9_510, RES_R(510))
+
+ QBJT_EB(Q3, "NPN(IS=1E-13 BF=100)")
+
+ QBJT_EB(Q4, "NPN(IS=1E-13 BF=100)")
+
+ QBJT_EB(Q5, "NPN(IS=1E-13 BF=100)")
+
+ RES(R10_1K3, RES_K(1.3))
+
+ QBJT_EB(Q6, "NPN(IS=1E-13 BF=100)")
+
+ RES(R11_5K1, RES_K(5.1))
+
+ QBJT_EB(Q7, "NPN(IS=1E-13 BF=100)")
+
+ QBJT_EB(Q8, "NPN(IS=1E-13 BF=100)")
+
+ RES(R12_1K5, RES_K(1.5))
+
+ RES(R13_6K2, RES_K(6.2))
+
+ QBJT_EB(Q9, "NPN(IS=1E-13 BF=100)")
+
+ RES(R14_5K1, RES_K(5.1))
+
+ QBJT_EB(Q10, "NPN(IS=1E-13 BF=100)")
+
+ RES(R15_5K1, RES_K(5.1))
+
+ RES(R16_200, RES_R(200))
+
+ RES(R17_5K1, RES_K(5.1))
+
+ DIODE(D3, "D(IS=1e-15 N=1)")
+
+ RES(R18_510, RES_R(510))
+
+ ALIAS(VCC, R1_5K1.1)
+ NET_C(R1_5K1.1, Q1.C, Q2.C, R7_5K1.1, Q3.C, Q4.C, Q7.C,
+ R13_6K2.1, Q10.C, R17_5K1.1)
+ // Location of first diode present on 1970s schematics but omitted on
+ // 1990s ones. Including it raises the control voltage threshold for
+ // attenuation significantly.
+ NET_C(R1_5K1.2, D1.A, Q1.B)
+ NET_C(D1.K, R2_4K7.1)
+ NET_C(R2_4K7.2, GND)
+
+ NET_C(Q1.E, R3_750.1, R5_750.1)
+ NET_C(R3_750.2, R4_10K.1, Q2.B)
+ NET_C(R4_10K.2, GND)
+
+ NET_C(R5_750.2, R6_3K9.1, Q3.B)
+ ALIAS(CONTROL, R6_3K9.2)
+
+ ALIAS(INPUT, Q5.B)
+
+ NET_C(INPUT, R8_20K.1)
+ // Location of second diode present on 1970s schematics but omitted on
+ // 1990s ones. Including it is critical to making the tone of the
+ // output engine sound match that of real 280-ZZZAP machines.
+ NET_C(R7_5K1.2, R8_20K.2, D2.A)
+ NET_C(D2.K, R9_510.1)
+ NET_C(R9_510.2, GND)
+
+ NET_C(Q4.E, Q6.E, Q5.C)
+ NET_C(Q5.E, R10_1K3.1)
+ NET_C(R10_1K3.2, GND)
+
+ NET_C(Q6.B, Q7.B, Q2.E, R11_5K1.1)
+ NET_C(R11_5K1.2, GND)
+
+ NET_C(Q7.E, Q9.E, Q8.C)
+ NET_C(Q8.E, R12_1K5.1)
+ NET_C(R12_1K5.2, GND)
+
+ NET_C(Q4.B, Q9.B, Q3.E, R14_5K1.1)
+ NET_C(R14_5K1.2, GND)
+
+ // This is where the cross-connection is erroneously omitted from
+ // 1990s schematics.
+ NET_C(Q6.C, R13_6K2.2, Q9.C, Q10.B)
+
+ // Connection for external frequency compensation capacitor; unused
+ // here.
+ ALIAS(ROLLOFF, Q10.B)
+
+ NET_C(Q10.E, R16_200.1, R15_5K1.1)
+ NET_C(R15_5K1.2, GND)
+ ALIAS(OUTPUT, R16_200.2)
+
+ NET_C(R17_5K1.2, D3.A, Q8.B)
+ NET_C(D3.K, R18_510.1)
+ ALIAS(GND, R18_510.2)
+
+ ALIAS(1, INPUT)
+ ALIAS(2, CONTROL)
+ ALIAS(3, GND)
+ ALIAS(6, ROLLOFF)
+ ALIAS(7, OUTPUT)
+ ALIAS(8, VCC)
+}
+
+static NETLIST_START(TL081_DIP)
+{
+ OPAMP(A, "TL084")
+
+ INCLUDE(opamp_layout_1_7_4)
+
+}
+
+static NETLIST_START(TL082_DIP)
+{
+ OPAMP(A, "TL084")
+ OPAMP(B, "TL084")
+
+ INCLUDE(opamp_layout_2_8_4)
+
+}
+
+static NETLIST_START(TL084_DIP)
+{
+ OPAMP(A, "TL084")
+ OPAMP(B, "TL084")
+ OPAMP(C, "TL084")
+ OPAMP(D, "TL084")
+
+ INCLUDE(opamp_layout_4_4_11)
+
+}
+
+static NETLIST_START(LM324_DIP)
+{
+ OPAMP(A, "LM324")
+ OPAMP(B, "LM324")
+ OPAMP(C, "LM324")
+ OPAMP(D, "LM324")
+
+ INCLUDE(opamp_layout_4_4_11)
+
+}
+
+static NETLIST_START(LM2902_DIP)
+{
+ // Same datasheet and mostly same characteristics as LM324
+ OPAMP(A, "LM324")
+ OPAMP(B, "LM324")
+ OPAMP(C, "LM324")
+ OPAMP(D, "LM324")
+
+ INCLUDE(opamp_layout_4_4_11)
+
+}
+
+static NETLIST_START(LM348_DIP)
+{
+ OPAMP(A, "UA741")
+ OPAMP(B, "UA741")
+ OPAMP(C, "UA741")
+ OPAMP(D, "UA741")
+
+ INCLUDE(opamp_layout_4_4_11)
+
+}
+
+static NETLIST_START(LM358_DIP)
+{
+ OPAMP(A, "LM358")
+ OPAMP(B, "LM358")
+
+ INCLUDE(opamp_layout_2_8_4)
+
+}
+
+static NETLIST_START(UA741_DIP8)
+{
+ OPAMP(A, "UA741")
+
+ INCLUDE(opamp_layout_1_7_4)
+
+}
+
+static NETLIST_START(UA741_DIP10)
+{
+ OPAMP(A, "UA741")
+
+ INCLUDE(opamp_layout_1_8_5)
+
+}
+
+static NETLIST_START(UA741_DIP14)
+{
+ OPAMP(A, "UA741")
+
+ INCLUDE(opamp_layout_1_11_6)
+
+}
+
+static NETLIST_START(MC1558_DIP)
+{
+ OPAMP(A, "UA741")
+ OPAMP(B, "UA741")
+
+ INCLUDE(opamp_layout_2_8_4)
+
+}
+
+static NETLIST_START(LM747_DIP)
+{
+ OPAMP(A, "LM747")
+ OPAMP(B, "LM747")
+
+ INCLUDE(opamp_layout_2_13_9_4)
+ NET_C(A.VCC, B.VCC)
+
+}
+
+static NETLIST_START(LM747A_DIP)
+{
+ OPAMP(A, "LM747A")
+ OPAMP(B, "LM747A")
+
+ INCLUDE(opamp_layout_2_13_9_4)
+ NET_C(A.VCC, B.VCC)
+
+}
+
+//- Identifier: AN6551_SIL
+//- Title: AN6551 Dual Operational Amplifier
+//- Pinalias: VCC,A.OUT,A-,A+,GND,B+,B-,B.OUT,VCC
+//- Package: SIL
+//- NamingConvention: Naming conventions follow Panasonic datasheet
+//- FunctionTable:
+//- https://datasheetspdf.com/pdf-file/182163/PanasonicSemiconductor/AN6551/1
+//-
+static NETLIST_START(AN6551_SIL)
+{
+ OPAMP(A, "AN6551")
+ OPAMP(B, "AN6551")
+
+ NET_C(A.GND, B.GND)
+
+ ALIAS(1, A.VCC)
+ ALIAS(2, A.OUT)
+ ALIAS(3, A.MINUS)
+ ALIAS(4, A.PLUS)
+ ALIAS(5, A.GND)
+ ALIAS(6, B.PLUS)
+ ALIAS(7, B.MINUS)
+ ALIAS(8, B.OUT)
+ ALIAS(9, B.VCC)
+}
+
+#if USE_LM3900_MODEL == 0
+static NETLIST_START(LM3900)
+{
+
+ /*
+ * Fast norton opamp model without bandwidth
+ */
+
+ /* Terminal definitions for calling netlists */
+
+ ALIAS(PLUS, R1.1) // Positive input
+ ALIAS(MINUS, R2.1) // Negative input
+ ALIAS(OUT, G1.OP) // Opamp output ...
+ ALIAS(GND, G1.ON) // V- terminal
+ ALIAS(VCC, DUMMY.1) // V+ terminal
+
+ RES(DUMMY, RES_K(1))
+ NET_C(DUMMY.2, GND)
+
+ /* The opamp model */
+
+ RES(R1, 1)
+ RES(R2, 1)
+ NET_C(R1.1, G1.IP)
+ NET_C(R2.1, G1.IN)
+ NET_C(R1.2, R2.2, G1.ON)
+ VCVS(G1, 10000000)
+ //PARAM(G1.RI, 1)
+ PARAM(G1.RO, RES_K(8))
+
+}
+#endif
+
+#if USE_LM3900_MODEL == 1
+// LTSPICE MODEL OF LM3900 FROM NATIONAL SEMICONDUCTOR
+// MADE BY HELMUT SENNEWALD, 8/6/2004
+// THE LM3900 IS A SO CALLED NORTON AMPLIFIER.
+//
+// PIN ORDER: IN+ IN- VCC VSS OUT
+static NETLIST_START(LM3900)
+{
+ PARAM(E1.G, 0.5)
+ //ALIAS(IN+, Q2.B)
+ //ALIAS(IN-, Q2.C)
+ //ALIAS(VCC, Q10.C)
+ //ALIAS(VSS, Q2.E)
+
+ ALIAS(PLUS, Q2.B)
+ ALIAS(MINUS, Q2.C)
+ ALIAS(VCC, Q10.C)
+ ALIAS(GND, Q2.E)
+ ALIAS(OUT, Q6.C)
+
+ //CS(B1/*I=LIMIT(0, V(VCC,VSS)/10K, 0.2m)*/)
+ CS(B1, 2e-4)
+ CAP(C1, CAP_P(6.000000))
+ VCVS(E1, 1)
+ QBJT_EB(Q1, "LM3900_NPN1")
+ QBJT_EB(Q10, "LM3900_NPN1")
+ QBJT_EB(Q11, "LM3900_NPN1")
+ QBJT_EB(Q12, "LM3900_NPN1")
+ QBJT_EB(Q2, "LM3900_NPN1")
+ QBJT_EB(Q3, "LM3900_NPN1")
+ QBJT_EB(Q4, "LM3900_PNP1")
+ QBJT_EB(Q5, "LM3900_PNP1")
+ QBJT_EB(Q6, "LM3900_PNP1")
+ QBJT_EB(Q7, "LM3900_PNP1")
+ QBJT_EB(Q8, "LM3900_NPN1")
+ QBJT_EB(Q9, "LM3900_NPN1")
+ RES(R1, RES_K(2.000000))
+ RES(R6, RES_K(1.600000))
+ NET_C(Q11.B, Q12.B, R6.2)
+ NET_C(Q5.C, Q5.B, B1.P, Q4.B)
+ NET_C(Q8.C, Q8.B, B1.N, R1.1, E1.IP)
+ NET_C(Q9.B, R1.2)
+ NET_C(R6.1, E1.OP)
+ NET_C(Q10.C, Q5.E, Q4.E, Q11.C, Q12.C)
+ NET_C(Q2.C, Q3.B, Q12.E)
+ NET_C(Q2.E, Q3.E, Q9.E, C1.2, Q1.E, Q8.E, E1.ON, E1.IN, Q7.C)
+ NET_C(Q3.C, Q6.B, C1.1, Q7.B)
+ NET_C(Q6.E, Q10.B, Q4.C)
+ NET_C(Q6.C, Q10.E, Q9.C, Q7.E)
+ NET_C(Q2.B, Q1.C, Q1.B, Q11.E)
+}
+#endif
+
+#if USE_LM3900_MODEL == 2
+static NETLIST_START(LM3900)
+{
+ OPAMP(A, "LM3900")
+
+ DIODE(D1, "D(IS=1e-15 N=1)")
+ CCCS(CS1, 1) // Current Mirror
+
+ ALIAS(VCC, A.VCC)
+ ALIAS(GND, A.GND)
+ ALIAS(PLUS, A.PLUS)
+ ALIAS(MINUS, A.MINUS)
+ ALIAS(OUT, A.OUT)
+
+ NET_C(A.PLUS, CS1.IP)
+ NET_C(D1.A, CS1.IN)
+ NET_C(CS1.ON, A.MINUS)
+ NET_C(CS1.OP, A.GND, D1.K)
+
+}
+#endif
+
+#if USE_LM3900_MODEL == 3
+static NETLIST_START(LM3900)
+{
+
+ ALIAS(VCC, Q5.C)
+ ALIAS(GND, Q1.E)
+ ALIAS(PLUS, Q1.B)
+ ALIAS(MINUS, Q1.C)
+ ALIAS(OUT, Q5.E)
+
+ CAP(C1, CAP_P(6.000000))
+ CS(I1, 1.300000e-3)
+ CS(I2, 200e-6)
+ QBJT_EB(Q1, "NPN")
+ QBJT_EB(Q2, "NPN")
+ QBJT_EB(Q3, "PNP")
+ QBJT_EB(Q4, "PNP")
+ QBJT_EB(Q5, "NPN")
+ QBJT_EB(Q6, "NPN")
+ NET_C(Q3.E, Q5.B, I2.2)
+ NET_C(Q3.C, Q4.E, Q5.E, I1.1)
+ NET_C(Q5.C, I2.1)
+ NET_C(Q1.B, Q6.C, Q6.B)
+ NET_C(Q1.E, Q2.E, Q4.C, C1.2, I1.2, Q6.E)
+ NET_C(Q1.C, Q2.B)
+ NET_C(Q2.C, Q3.B, Q4.B, C1.1)
+}
+#endif
+
+#if USE_LM3900_MODEL == 4
+static NETLIST_START(LM3900)
+{
+ OPAMP(A, "OPAMP(TYPE=3 VLH=0.5 VLL=0.03 FPF=2k UGF=2.5M SLEW=1M RI=10M RO=100 DAB=0.0015)")
+
+ DIODE(D1, "D(IS=6e-15 N=1)")
+ DIODE(D2, "D(IS=6e-15 N=1)")
+ CCCS(CS1, 1) // Current Mirror
+
+ ALIAS(VCC, A.VCC)
+ ALIAS(GND, A.GND)
+ ALIAS(OUT, A.OUT)
+
+ ALIAS(PLUS, CS1.IP)
+ NET_C(D1.A, CS1.IN)
+ NET_C(A.GND, D1.K)
+
+ CS(CS_BIAS, 10e-6)
+ NET_C(A.VCC, CS_BIAS.P)
+
+ ALIAS(MINUS, CS1.OP)
+ NET_C(CS1.ON, A.GND)
+
+ CCVS(VS1, 200000) // current-to-voltage gain
+ NET_C(CS1.OP, VS1.IP)
+ NET_C(VS1.IN, CS_BIAS.N, D2.A)
+ NET_C(D2.K, A.GND)
+ NET_C(VS1.OP, A.MINUS)
+ NET_C(VS1.ON, A.PLUS, A.GND)
+}
+#endif
+
+NETLIST_START(opamp_lib)
+{
+ LOCAL_LIB_ENTRY(opamp_layout_4_4_11)
+ LOCAL_LIB_ENTRY(opamp_layout_2_8_4)
+ LOCAL_LIB_ENTRY(opamp_layout_2_13_9_4)
+ LOCAL_LIB_ENTRY(opamp_layout_1_7_4)
+ LOCAL_LIB_ENTRY(opamp_layout_1_8_5)
+ LOCAL_LIB_ENTRY(opamp_layout_1_11_6)
+
+ // FIXME: JFET Opamp may need better model
+ // VLL and VHH for +-6V RI=10^12 (for numerical stability 10^9 is used below
+ // RO from data sheet
+ NET_MODEL("TL084 OPAMP(TYPE=3 VLH=0.75 VLL=0.75 FPF=10 UGF=3000k SLEW=13M RI=1000M RO=192 DAB=0.0014)")
+
+ NET_MODEL("LM324 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.00075)")
+ NET_MODEL("LM358 OPAMP(TYPE=3 VLH=2.0 VLL=0.2 FPF=5 UGF=500k SLEW=0.3M RI=1000k RO=50 DAB=0.001)")
+ NET_MODEL("MB3614 OPAMP(TYPE=3 VLH=1.4 VLL=0.02 FPF=3 UGF=1000k SLEW=0.6M RI=1000k RO=100 DAB=0.002)")
+ NET_MODEL("UA741 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=75 DAB=0.0017)")
+ NET_MODEL("LM747 OPAMP(TYPE=3 VLH=1.0 VLL=1.0 FPF=5 UGF=1000k SLEW=0.5M RI=2000k RO=50 DAB=0.0017)")
+ NET_MODEL("LM747A OPAMP(TYPE=3 VLH=2.0 VLL=2.0 FPF=5 UGF=1000k SLEW=0.7M RI=6000k RO=50 DAB=0.0015)")
+ NET_MODEL("LM748 OPAMP(TYPE=3 VLH=2.0 VLL=2.0 FPF=5 UGF=800k SLEW=0.7M RI=800k RO=60 DAB=0.001)")
+ // TI and Motorola datasheets differ - below are Motorola values, SLEW is average of LH and HL
+ NET_MODEL("LM3900 OPAMP(TYPE=3 VLH=1.0 VLL=0.03 FPF=2k UGF=4M SLEW=10M RI=10M RO=2k DAB=0.0015)")
+
+ NET_MODEL("AN6551 OPAMP(TYPE=3 VLH=1.0 VLL=0.03 FPF=20 UGF=2M SLEW=1M RI=10M RO=200 DAB=0.0015)")
+
+ #if USE_LM3900_MODEL == 1
+ NET_MODEL("LM3900_NPN1 NPN(IS=1E-14 BF=150 TF=1E-9 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5 IKF=0.002)")
+ NET_MODEL("LM3900_PNP1 PNP(IS=1E-14 BF=40 TF=1E-7 CJC=1E-12 CJE=1E-12 VAF=150 RB=100 RE=5)")
+#endif
+ LOCAL_LIB_ENTRY(MB3614_DIP)
+ LOCAL_LIB_ENTRY(MC3340_DIP)
+ LOCAL_LIB_ENTRY(TL081_DIP)
+ LOCAL_LIB_ENTRY(TL082_DIP)
+ LOCAL_LIB_ENTRY(TL084_DIP)
+ LOCAL_LIB_ENTRY(LM324_DIP)
+ LOCAL_LIB_ENTRY(LM348_DIP)
+ LOCAL_LIB_ENTRY(LM358_DIP)
+ LOCAL_LIB_ENTRY(LM2902_DIP)
+ LOCAL_LIB_ENTRY(UA741_DIP8)
+ LOCAL_LIB_ENTRY(UA741_DIP10)
+ LOCAL_LIB_ENTRY(UA741_DIP14)
+ LOCAL_LIB_ENTRY(MC1558_DIP)
+ LOCAL_LIB_ENTRY(LM747_DIP)
+ LOCAL_LIB_ENTRY(LM747A_DIP)
+ LOCAL_LIB_ENTRY(LM3900)
+ LOCAL_LIB_ENTRY(AN6551_SIL)
+
+}
diff --git a/src/lib/netlist/macro/nlm_other.cpp b/src/lib/netlist/macro/nlm_other.cpp
deleted file mode 100644
index befbc99a364..00000000000
--- a/src/lib/netlist/macro/nlm_other.cpp
+++ /dev/null
@@ -1,55 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#include "nlm_other.h"
-
-#include "netlist/devices/nld_system.h"
-
-/*
- * MC14584B: Hex Schmitt Trigger
- * ON Semiconductor
- *
- * +--------------+
- * A1 |1 ++ 14| VCC
- * Y1 |2 13| A6
- * A2 |3 12| Y6
- * Y2 |4 MC14584B 11| A5
- * A3 |5 10| Y5
- * Y3 |6 9| A4
- * GND |7 8| Y4
- * +--------------+
- *
- */
-
-static NETLIST_START(MC14584B_DIP)
- MC14584B_GATE(A)
- MC14584B_GATE(B)
- MC14584B_GATE(C)
- MC14584B_GATE(D)
- MC14584B_GATE(E)
- MC14584B_GATE(F)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.Q, /* Y1 |2 13| A6 */ F.A,
- B.A, /* A2 |3 12| Y6 */ F.Q,
- B.Q, /* Y2 |4 MC14584B 11| A5 */ E.A,
- C.A, /* A3 |5 10| Y5 */ E.Q,
- C.Q, /* Y3 |6 9| A4 */ D.A,
- A.GND,/* GND |7 8| Y4 */ D.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-NETLIST_START(otheric_lib)
- TRUTHTABLE_START(MC14584B_GATE, 1, 1, "")
- TT_HEAD(" A | Q ")
- TT_LINE(" 0 | 1 |100")
- TT_LINE(" 1 | 0 |100")
- // 2.1V negative going and 2.7V positive going at 5V
- TT_FAMILY("FAMILY(FV=0 IVL=0.42 IVH=0.54 OVL=0.05 OVH=0.05 ORL=10.0 ORH=10.0)")
- TRUTHTABLE_END()
-
- LOCAL_LIB_ENTRY(MC14584B_DIP)
-NETLIST_END()
diff --git a/src/lib/netlist/macro/nlm_other.h b/src/lib/netlist/macro/nlm_other.h
deleted file mode 100644
index ee231fbd6db..00000000000
--- a/src/lib/netlist/macro/nlm_other.h
+++ /dev/null
@@ -1,32 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#ifndef NLM_OTHER_H_
-#define NLM_OTHER_H_
-
-#include "netlist/nl_setup.h"
-
-#ifndef __PLIB_PREPROCESSOR__
-
-/* ----------------------------------------------------------------------------
- * Netlist Macros
- * ---------------------------------------------------------------------------*/
-
-#ifndef NL_AUTO_DEVICES
-
-#define MC14584B_GATE(name) \
- NET_REGISTER_DEV(MC14584B_GATE, name)
-
-#define MC14584B_DIP(name) \
- NET_REGISTER_DEV(MC14584B_DIP, name)
-
-#endif
-
-/* ----------------------------------------------------------------------------
- * External declarations
- * ---------------------------------------------------------------------------*/
-
-NETLIST_EXTERNAL(otheric_lib)
-
-#endif
-
-#endif
diff --git a/src/lib/netlist/macro/nlm_otheric_lib.cpp b/src/lib/netlist/macro/nlm_otheric_lib.cpp
new file mode 100644
index 00000000000..086801b0f3a
--- /dev/null
+++ b/src/lib/netlist/macro/nlm_otheric_lib.cpp
@@ -0,0 +1,209 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+#include "devices/net_lib.h"
+
+/*
+ * MC14584B: Hex Schmitt Trigger
+ * ON Semiconductor
+ *
+ * +--------------+
+ * A1 |1 ++ 14| VCC
+ * Y1 |2 13| A6
+ * A2 |3 12| Y6
+ * Y2 |4 MC14584B 11| A5
+ * A3 |5 10| Y5
+ * Y3 |6 9| A4
+ * GND |7 8| Y4
+ * +--------------+
+ *
+ */
+
+static NETLIST_START(MC14584B_DIP)
+{
+ MC14584B_GATE(A)
+ MC14584B_GATE(B)
+ MC14584B_GATE(C)
+ MC14584B_GATE(D)
+ MC14584B_GATE(E)
+ MC14584B_GATE(F)
+
+ NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, F.VDD)
+ NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
+ DIPPINS( /* +--------------+ */
+ A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
+ A.Q, /* Y1 |2 13| A6 */ F.A,
+ B.A, /* A2 |3 12| Y6 */ F.Q,
+ B.Q, /* Y2 |4 MC14584B 11| A5 */ E.A,
+ C.A, /* A3 |5 10| Y5 */ E.Q,
+ C.Q, /* Y3 |6 9| A4 */ D.A,
+ A.VSS,/* VSS |7 8| Y4 */ D.Q
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: NE566_DIP
+//- Title: NE566 Voltage Controlled Oscillator
+//- Pinalias: GND,NC,SQUARE,TRIANGLE,MODULATION,R1,C1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- This implementation is focused on performance. There may be edge cases
+//- which lead to issues and ringing.
+//.
+//- Example: ne566.cpp,ne566_example
+//- FunctionTable:
+//- https://www.egr.msu.edu/eceshop/Parts_Inventory/datasheets/lm566.pdf
+//-
+//.
+
+static NETLIST_START(NE566_DIP)
+{
+
+ VCVS(VI, 1)
+ CCCS(CI1, -1)
+ CCCS(CI2, 1)
+ SYS_COMPD(COMP)
+ SYS_DSW2(SW)
+ VCVS(VO, 1)
+ DIODE(DC, "D")
+ DIODE(DM, "D")
+ RES(ROD, 5200)
+ RES(ROU, 200)
+
+ PARAM(VO.RO, 50)
+ PARAM(COMP.MODEL, "FAMILY(TYPE=CUSTOM IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.1 ORL=50 ORH=50)")
+ PARAM(SW.GOFF, 0) // This has to be zero to block current sources
+
+ NET_C(CI2.IN, VI.OP)
+ NET_C(CI2.IP, CI1.IN)
+ NET_C(COMP.Q, SW.I)
+ NET_C(SW.1, CI1.OP)
+ NET_C(SW.3, CI2.OP)
+ NET_C(SW.2, VO.IP)
+ NET_C(VO.OP, COMP.IN)
+
+ // Avoid singular Matrix due to G=0 switch
+ RES(RX1, 1e10)
+ RES(RX2, 1e10)
+ NET_C(RX1.1, SW.1)
+ NET_C(RX2.1, SW.3)
+
+ NET_C(COMP.GND, RX1.2, RX2.2)
+
+ // Block if VC < V+ - ~4
+ VS(VM, 3)
+ PARAM(VM.RI, 10)
+ NET_C(VM.1, COMP.VCC)
+ NET_C(VM.2, DM.A)
+ NET_C(DM.K, VI.OP)
+
+ // Block if VC > V+
+ NET_C(COMP.GND, DC.A)
+ NET_C(SW.2, DC.K)
+
+ RES(R1, 5000)
+ RES(R2, 1800)
+ RES(R3, 6000)
+
+ // Square output wave
+ AFUNC(FO, 2, "min(A1-1,A0 + 5)")
+ NET_C(COMP.QQ, FO.A0)
+ NET_C(FO.Q, ROU.1)
+ NET_C(ROU.2, ROD.1)
+
+ NET_C(COMP.GND, SW.GND, VI.ON, VI.IN, CI1.ON, CI2.ON, VO.IN, VO.ON, R2.2, ROD.2)
+ NET_C(COMP.VCC, SW.VCC, R1.2)
+ NET_C(COMP.IP, R1.1, R2.1, R3.1)
+ NET_C(COMP.Q, R3.2)
+
+ ALIAS(1, VI.ON) // GND
+ ALIAS(3, ROD.1) // Square out
+ ALIAS(4, VO.OP) // Diag out
+ ALIAS(5, VI.IP) // VC
+ ALIAS(6, CI1.IP) // R1
+ ALIAS(7, SW.2) // C1
+ ALIAS(8, COMP.VCC) // V+
+
+ NET_C(COMP.VCC, FO.A1)
+
+
+}
+
+//- Identifier: NE555_DIP
+//- Title: NE555 PRECISION TIMERS
+//- Pinalias: GND,TRIG,OUT,RESET,CONT,THRES,DISCH,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas instrument datasheet
+//- Limitations: Internal resistor network currently fixed to 5k
+//- If TRIG and TRESH are connected overshoot compensation will be enabled.
+//- The approach is raw but delivers results (at 5 to 10 steps per discharge/charge)
+//- within a couple of percent. Please take into account that any datasheet
+//- formulas are idealistic. Neither capacitor, resistor, internal resistor
+//- tolerances are taken into account. Nor are ambient temperature and chip
+//- temperature. Thus the result is considered acceptable.
+//- The datasheet states a maximum discharge of 200mA, this is not modelled
+//- Instead an impedance of 1 Ohm is used.
+//-
+//- Example: ne555_astable.c,ne555_example
+//- FunctionTable:
+//-
+//- |RESET|TRIGGER VOLTAGE|THRESHOLD VOLTAGE|OUTPUT|DISCHARGE SWITCH|
+//- |:---:|:-------------:|:---------------:|:----:|:--------------:|
+//- |Low | Irrelevant | Irrelevant | Low | On |
+//- |High | <1/3 VDD | Irrelevant | High | Off |
+//- |High | >1/3 VDD | >2/3 VDD | Low | On |
+//- |High | >1/3 VDD | <2/3 VDD | As previously established||
+//-
+static NETLIST_START(NE555_DIP)
+{
+
+ NE555(A)
+
+ ALIAS(1, A.GND) // Pin 1
+ ALIAS(2, A.TRIG) // Pin 2
+ ALIAS(3, A.OUT) // Pin 3
+ ALIAS(4, A.RESET) // Pin 4
+ ALIAS(5, A.CONT) // Pin 5
+ ALIAS(6, A.THRESH) // Pin 6
+ ALIAS(7, A.DISCH) // Pin 7
+ ALIAS(8, A.VCC) // Pin 8
+
+}
+
+static NETLIST_START(MC1455P_DIP)
+{
+
+ MC1455P(A)
+
+ ALIAS(1, A.GND) // Pin 1
+ ALIAS(2, A.TRIG) // Pin 2
+ ALIAS(3, A.OUT) // Pin 3
+ ALIAS(4, A.RESET) // Pin 4
+ ALIAS(5, A.CONT) // Pin 5
+ ALIAS(6, A.THRESH) // Pin 6
+ ALIAS(7, A.DISCH) // Pin 7
+ ALIAS(8, A.VCC) // Pin 8
+
+}
+
+static TRUTH_TABLE(MC14584B_GATE, 1, 1, "")
+{
+ TT_HEAD(" A | Q ")
+ TT_LINE(" 0 | 1 |100")
+ TT_LINE(" 1 | 0 |100")
+ // 2.1V negative going and 2.7V positive going at 5V
+ TT_FAMILY("FAMILY(TYPE=CMOS IVL=0.42 IVH=0.54 OVL=0.05 OVH=0.05 ORL=10.0 ORH=10.0)")
+}
+
+NETLIST_START(otheric_lib)
+{
+
+ TRUTHTABLE_ENTRY(MC14584B_GATE)
+
+ LOCAL_LIB_ENTRY(MC14584B_DIP)
+ LOCAL_LIB_ENTRY(NE566_DIP)
+ LOCAL_LIB_ENTRY(NE555_DIP)
+ LOCAL_LIB_ENTRY(MC1455P_DIP)
+}
+
diff --git a/src/lib/netlist/macro/nlm_roms_lib.cpp b/src/lib/netlist/macro/nlm_roms_lib.cpp
new file mode 100644
index 00000000000..ede3feae85d
--- /dev/null
+++ b/src/lib/netlist/macro/nlm_roms_lib.cpp
@@ -0,0 +1,453 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+#include "devices/net_lib.h"
+
+
+//- Identifier: PROM_82S126_DIP
+//- Title: 82S126 1K-bit TTL bipolar PROM
+//- Pinalias: A6,A5,A4,A3,A0,A1,A2,GND,O4,O3,O2,O1,CE1Q,CE2Q,A7,VCC
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- Param: FORCE_TRISTATE_LOGIC
+//- Set this parameter to 1 force tristate outputs into logic mode.
+//- This should be done only if the device enable inputs are connected
+//- in a way which always enables the device.
+//- Param: MODEL
+//- Overwrite the default model of the device. Use with care.
+//- NamingConvention: Naming conventions follow Philips Components-Signetics datasheet
+//- Limitations:
+//- Currently OC is not supported.
+//-
+//- Example: 82S126.cpp,82S126_example
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/philips/82S129.pdf
+//-
+
+static NETLIST_START(PROM_82S126_DIP)
+{
+
+ PROM_82S126(A)
+
+ DEFPARAM(ROM, "unknown")
+ DEFPARAM(FORCE_TRISTATE_LOGIC, 0)
+ DEFPARAM(MODEL, "$(@.A.MODEL)")
+ PARAM(A.ROM, "$(@.ROM)")
+ PARAM(A.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(A.MODEL, "$(@.MODEL)")
+ ALIAS(1, A.A6)
+ ALIAS(2, A.A5)
+ ALIAS(3, A.A4)
+ ALIAS(4, A.A3)
+ ALIAS(5, A.A0)
+ ALIAS(6, A.A1)
+ ALIAS(7, A.A2)
+ ALIAS(8, A.GND)
+ ALIAS(9, A.O4)
+ ALIAS(10, A.O3)
+ ALIAS(11, A.O2)
+ ALIAS(12, A.O1)
+ ALIAS(13, A.CE1Q)
+ ALIAS(14, A.CE2Q)
+ ALIAS(15, A.A7)
+ ALIAS(16, A.VCC)
+}
+
+//- Identifier: PROM_74S287_DIP
+//- Title: 74S287 (256 x 4) 1024-Bit TTL PROM
+//- Pinalias: A6,A5,A4,A3,A0,A1,A2,GND,O3,O2,O1,O0,CE1Q,CE2Q,A7,VCC
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- Param: FORCE_TRISTATE_LOGIC
+//- Set this parameter to 1 force tristate outputs into logic mode.
+//- This should be done only if the device enable inputs are connected
+//- in a way which always enables the device.
+//- Param: MODEL
+//- Overwrite the default model of the device. Use with care.
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations:
+//- None.
+//-
+//- Example: 74S287.cpp,74S287_example
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet_pdf/national-semiconductor/DM54S287AJ_to_DM74S287V.pdf
+//-
+
+static NETLIST_START(PROM_74S287_DIP)
+{
+
+ PROM_74S287(A)
+
+ DEFPARAM(ROM, "unknown")
+ DEFPARAM(FORCE_TRISTATE_LOGIC, 0)
+ DEFPARAM(MODEL, "$(@.A.MODEL)")
+ PARAM(A.ROM, "$(@.ROM)")
+ PARAM(A.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(A.MODEL, "$(@.MODEL)")
+ ALIAS(1, A.A6)
+ ALIAS(2, A.A5)
+ ALIAS(3, A.A4)
+ ALIAS(4, A.A3)
+ ALIAS(5, A.A0)
+ ALIAS(6, A.A1)
+ ALIAS(7, A.A2)
+ ALIAS(8, A.GND)
+ ALIAS(9, A.O3)
+ ALIAS(10, A.O2)
+ ALIAS(11, A.O1)
+ ALIAS(12, A.O0)
+ ALIAS(13, A.CE1Q)
+ ALIAS(14, A.CE2Q)
+ ALIAS(15, A.A7)
+ ALIAS(16, A.VCC)
+}
+
+//- Identifier: PROM_82S123_DIP
+//- Title: 82S123 256 bit TTL bipolar PROM
+//- Pinalias: O1,O2,O3,O4,O5,O6,O7,GND,O8,A0,A1,A2,A3,A4,CEQ,VCC
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- Param: FORCE_TRISTATE_LOGIC
+//- Set this parameter to 1 force tristate outputs into logic mode.
+//- This should be done only if the device enable inputs are connected
+//- in a way which always enables the device.
+//- Param: MODEL
+//- Overwrite the default model of the device. Use with care.
+//- NamingConvention: Naming conventions follow Philips Components-Signetics datasheet
+//- Limitations:
+//- Currently OC is not supported.
+//-
+//- Example: 82S123.cpp,82S123_example
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/philips/82S123.pdf
+//-
+
+static NETLIST_START(PROM_82S123_DIP)
+{
+
+ PROM_82S123(A)
+
+ DEFPARAM(ROM, "unknown")
+ DEFPARAM(FORCE_TRISTATE_LOGIC, 0)
+ DEFPARAM(MODEL, "$(@.A.MODEL)")
+ PARAM(A.ROM, "$(@.ROM)")
+ PARAM(A.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(A.MODEL, "$(@.MODEL)")
+ ALIAS(1, A.O0)
+ ALIAS(2, A.O1)
+ ALIAS(3, A.O2)
+ ALIAS(4, A.O3)
+ ALIAS(5, A.O4)
+ ALIAS(6, A.O5)
+ ALIAS(7, A.O6)
+ ALIAS(8, A.GND)
+
+ ALIAS(9, A.O7)
+ ALIAS(10, A.A0)
+ ALIAS(11, A.A1)
+ ALIAS(12, A.A2)
+ ALIAS(13, A.A3)
+ ALIAS(14, A.A4)
+ ALIAS(15, A.CEQ)
+ ALIAS(16, A.VCC)
+}
+
+/*
+ * nld_82S16.h
+ *
+ * DM82S16: 256 Bit bipolar ram
+ *
+ * +--------------+
+ * A1 |1 ++ 16| VCC
+ * A0 |2 15| A2
+ * CE1Q |3 14| A3
+ * CE2Q |4 82S16 13| DIN
+ * CE3Q |5 12| WEQ
+ * DOUTQ |6 11| A7
+ * A4 |7 10| A6
+ * GND |8 9| A5
+ * +--------------+
+ *
+ *
+ * Naming conventions follow Signetics datasheet
+ */
+
+
+//- Identifier: EPROM_2716_DIP
+//- Title: 2716 16K (2K x 8) UV ERASABLE PROM
+//- Pinalias: A7,A6,A6,A4,A4,A2,A1,A0,O0,O1,O2,GND,O3,O4,O5,O6,O7,CE1Q/CE,A10,CE2Q/OE,VPP,A9,A8,VCC
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- Param: FORCE_TRISTATE_LOGIC
+//- Set this parameter to 1 force tristate outputs into logic mode.
+//- This should be done only if the device enable inputs are connected
+//- in a way which always enables the device.
+//- Param: MODEL
+//- Overwrite the default model of the device. Use with care.
+//- NamingConvention: Naming conventions follow Intel datasheet
+//- Limitations:
+//- Currently OC is not supported.
+//-
+//- Example: 2716.cpp,2716_example
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/400/500340_DS.pdf
+//-
+static NETLIST_START(EPROM_2716_DIP)
+{
+
+ EPROM_2716(A)
+
+ DEFPARAM(ROM, "unknown")
+ DEFPARAM(FORCE_TRISTATE_LOGIC, 0)
+ DEFPARAM(MODEL, "$(@.A.MODEL)")
+ PARAM(A.ROM, "$(@.ROM)")
+ PARAM(A.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(A.MODEL, "$(@.MODEL)")
+ ALIAS(1, A.A7)
+ ALIAS(2, A.A6)
+ ALIAS(3, A.A5)
+ ALIAS(4, A.A4)
+ ALIAS(5, A.A3)
+ ALIAS(6, A.A2)
+ ALIAS(7, A.A1)
+ ALIAS(8, A.A0)
+ ALIAS(9, A.O0)
+ ALIAS(10, A.O1)
+ ALIAS(11, A.O2)
+ ALIAS(12, A.GND)
+
+ ALIAS(13, A.O3)
+ ALIAS(14, A.O4)
+ ALIAS(15, A.O5)
+ ALIAS(16, A.O6)
+ ALIAS(17, A.O7)
+ ALIAS(18, A.CE1Q) // CEQ
+ ALIAS(19, A.A10)
+ ALIAS(20, A.CE2Q) // OEQ
+ ALIAS(22, A.A9)
+ ALIAS(23, A.A8)
+ ALIAS(24, A.VCC)
+}
+
+/* DM82S16: 256 Bit bipolar ram
+ *
+ * +--------------+
+ * A1 |1 ++ 16| VCC
+ * A0 |2 15| A2
+ * CE1Q |3 14| A3
+ * CE2Q |4 82S16 13| DIN
+ * CE3Q |5 12| WEQ
+ * DOUTQ |6 11| A7
+ * A4 |7 10| A6
+ * GND |8 9| A5
+ * +--------------+
+ *
+ * Naming conventions follow Signetics datasheet
+ */
+
+static NETLIST_START(TTL_82S16_DIP)
+{
+ TTL_82S16(A)
+
+ DIPPINS( /* +--------------+ */
+ A.A1, /* A1 |1 ++ 16| VCC */ A.VCC,
+ A.A0, /* A0 |2 15| A2 */ A.A2,
+ A.CE1Q, /* CE1Q |3 14| A3 */ A.A3,
+ A.CE2Q, /* CE2Q |4 82S16 13| DIN */ A.DIN,
+ A.CE3Q, /* CE3Q |5 12| WEQ */ A.WEQ,
+ A.DOUTQ, /* DOUTQ |6 11| A7 */ A.A7,
+ A.A4, /* A4 |7 10| A6 */ A.A6,
+ A.GND, /* GND |8 9| A5 */ A.A5
+ /* +--------------+ */
+ )
+}
+
+/* 82S115: 4K-bit TTL bipolar PROM (512 x 8)
+ *
+ * +--------------+
+ * A3 |1 ++ 24| VCC
+ * A4 |2 23| A2
+ * A5 |3 22| A1
+ * A6 |4 82S115 21| A0
+ * A7 |5 20| CE1Q
+ * A8 |6 19| CE2
+ * O1 |7 18| STROBE
+ * O2 |8 17| O8
+ * O3 |9 16| O7
+ * O4 |10 15| O6
+ * FE2 |11 14| O5
+ * GND |12 13| FE1
+ * +--------------+
+ */
+
+static NETLIST_START(PROM_82S115_DIP)
+{
+ PROM_82S115(A)
+ NC_PIN(NC)
+
+ DIPPINS( /* +--------------+ */
+ A.A3, /* A3 |1 ++ 24| VCC */ A.VCC,
+ A.A4, /* A4 |2 23| A2 */ A.A2,
+ A.A5, /* A5 |3 22| A1 */ A.A1,
+ A.A6, /* A6 |4 82S115 21| A0 */ A.A0,
+ A.A7, /* A7 |5 20| CE1Q */ A.CE1Q,
+ A.A8, /* A8 |6 19| CE2 */ A.CE2,
+ A.O1, /* O1 |7 18| STROBE */ A.STROBE,
+ A.O2, /* O2 |8 17| O8 */ A.O8,
+ A.O3, /* O3 |9 16| O7 */ A.O7,
+ A.O4, /* O4 |10 15| O6 */ A.O6,
+ NC.I, /* FE2 |11 14| O5 */ A.O5,
+ A.GND, /* GND |12 13| FE1 */ NC.I
+ /* +--------------+ */
+ )
+}
+
+//- Identifier: PROM_MK28000_DIP
+//- Title: MK28000 (2048 x 8 or 4096 x 4) 16384-Bit TTL PROM
+//- Pinalias: VCC,A1,A2,A3,A4,A5,A6,A10,GND,A9,A8,A7,ARQ,OE2,A11,O8,O7,O6,O5,O4,O3,O2,O1,OE1
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- NamingConvention: Naming conventions follow Mostek datasheet
+//- Limitations:
+//- None.
+
+static NETLIST_START(PROM_MK28000_DIP)
+{
+
+ PROM_MK28000(A)
+
+ DEFPARAM(ROM, "unknown")
+ PARAM(A.ROM, "$(@.ROM)")
+ ALIAS(1, A.VCC)
+ ALIAS(2, A.A1)
+ ALIAS(3, A.A2)
+ ALIAS(4, A.A3)
+ ALIAS(5, A.A4)
+ ALIAS(6, A.A5)
+ ALIAS(7, A.A6)
+ ALIAS(8, A.A10)
+ ALIAS(9, A.GND)
+ ALIAS(10, A.A9)
+ ALIAS(11, A.A8)
+ ALIAS(12, A.A7)
+ ALIAS(13, A.ARQ)
+ ALIAS(14, A.OE2)
+ ALIAS(15, A.A11)
+ ALIAS(16, A.O8)
+ ALIAS(17, A.O7)
+ ALIAS(18, A.O6)
+ ALIAS(19, A.O5)
+ ALIAS(20, A.O4)
+ ALIAS(21, A.O3)
+ ALIAS(22, A.O2)
+ ALIAS(23, A.O1)
+ ALIAS(24, A.OE1)
+}
+
+//- Identifier: ROM_MCM14524_DIP
+//- Title: MCM14524 1024-BIT READ ONLY MEMORY
+//- Pinalias: CLK,EN,B0,B1,B2,B3,A2,GND,A3,A4,A5,A6,A7,A1,A0,VCC
+//- Package: DIP
+//- Param: ROM
+//- The name of the source to load the rom content from
+//- NamingConvention: Naming conventions follow Motorola datasheet
+//- Limitations:
+//- Voltage-dependent timing is partially implemented.
+//- FunctionTable:
+//- http://www.bitsavers.org/components/motorola/_dataBooks/1978_Motorola_CMOS_Data_Book.pdf 7-439 (pdf page 488)
+
+static NETLIST_START(ROM_MCM14524_DIP)
+{
+
+ ROM_MCM14524(A)
+
+ DEFPARAM(ROM, "unknown")
+ PARAM(A.ROM, "$(@.ROM)")
+
+ /* Motorola MCM14524: */
+ DIPPINS( /* +-----..-----+ */
+ A.CLK, /* /CLK |1 16| VDD */ A.VCC,
+ A.EN, /* CE |2 15| A0 */ A.A0,
+ A.B0, /* B0 |3 MCM 14| A1 */ A.A1,
+ A.B1, /* B1 |4 14524 13| A7 */ A.A7,
+ A.B2, /* B2 |5 12| A6 */ A.A6,
+ A.B3, /* B3 |6 11| A5 */ A.A5,
+ A.A2, /* A2 |7 10| A4 */ A.A4,
+ A.GND, /* VSS |8 9| A3 */ A.A3
+ /* +------------+ */
+ )
+}
+
+/* 2102: 1024 x 1-bit Static RAM
+ *
+ * +--------------+
+ * A6 |1 ++ 16| A7
+ * A5 |2 15| A8
+ * RWQ |3 14| A9
+ * A1 |4 82S16 13| CEQ
+ * A2 |5 12| DO
+ * A3 |6 11| DI
+ * A4 |7 10| VCC
+ * A0 |8 9| GND
+ * +--------------+
+ */
+static NETLIST_START(RAM_2102A_DIP)
+{
+ RAM_2102A(A)
+
+ DIPPINS( /* +--------------+ */
+ A.A6, /* A6 |1 ++ 16| A7 */ A.A7,
+ A.A5, /* A5 |2 15| A8 */ A.A8,
+ A.RWQ, /* RWQ |3 14| A9 */ A.A9,
+ A.A1, /* A1 |4 82S16 13| CEQ */ A.CEQ,
+ A.A2, /* A2 |5 12| DO */ A.DO,
+ A.A3, /* A3 |6 11| DI */ A.DI,
+ A.A4, /* A4 |7 10| VCC */ A.VCC,
+ A.A0, /* A0 |8 9| GND */ A.GND
+ /* +--------------+ */
+ )
+}
+
+//FIXME: Documentation
+static NETLIST_START(ROM_TMS4800_DIP)
+{
+ ROM_TMS4800(A)
+
+ DIPPINS( /* +----------------+ */
+ A.VSS, /* VSS |1 ++ 24| OE1 */ A.OE1,
+ A.A1, /* A1 |2 23| O1 */ A.O1,
+ A.A2, /* A2 |3 22| O2 */ A.O2,
+ A.A3, /* A3 |4 TMS-4800 21| O3 */ A.O3,
+ A.A4, /* A4 |5 20| O4 */ A.O4,
+ A.A5, /* A5 |6 19| O5 */ A.O5,
+ A.A6, /* A6 |7 18| O6 */ A.O6,
+ A.A10, /* A10 |8 17| O7 */ A.O7,
+ A.VGG, /* VGG |9 16| O8 */ A.O8,
+ A.A9, /* A9 |10 15| A11 */ A.A11,
+ A.A8, /* A8 |11 14| OE2 */ A.OE2,
+ A.A7, /* A7 |12 13| AR */ A.AR
+ /* +----------------+ */
+ )
+}
+
+
+NETLIST_START(roms_lib)
+{
+
+ LOCAL_LIB_ENTRY(PROM_82S123_DIP)
+ LOCAL_LIB_ENTRY(PROM_82S126_DIP)
+ LOCAL_LIB_ENTRY(PROM_74S287_DIP)
+ LOCAL_LIB_ENTRY(EPROM_2716_DIP)
+ LOCAL_LIB_ENTRY(TTL_82S16_DIP)
+ LOCAL_LIB_ENTRY(PROM_82S115_DIP)
+ LOCAL_LIB_ENTRY(PROM_MK28000_DIP)
+ LOCAL_LIB_ENTRY(ROM_MCM14524_DIP)
+ LOCAL_LIB_ENTRY(RAM_2102A_DIP)
+ LOCAL_LIB_ENTRY(ROM_TMS4800_DIP)
+ }
+
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp
deleted file mode 100644
index fb175ae0c18..00000000000
--- a/src/lib/netlist/macro/nlm_ttl74xx.cpp
+++ /dev/null
@@ -1,1394 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#include "nlm_ttl74xx.h"
-
-#include "netlist/devices/nld_schmitt.h"
-#include "netlist/devices/nld_system.h"
-
-
-/*
- * DM7400: Quad 2-Input NAND Gates
- *
- * _
- * Y = AB
- * +---+---++---+
- * | A | B || Y |
- * +===+===++===+
- * | 0 | 0 || 1 |
- * | 0 | 1 || 1 |
- * | 1 | 0 || 1 |
- * | 1 | 1 || 0 |
- * +---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7400_DIP)
- TTL_7400_GATE(A)
- TTL_7400_GATE(B)
- TTL_7400_GATE(C)
- TTL_7400_GATE(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| B4 */ D.B,
- A.Q, /* Y1 |3 12| A4 */ D.A,
- B.A, /* A2 |4 7400 11| Y4 */ D.Q,
- B.B, /* B2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7402: Quad 2-Input NOR Gates
- *
- * Y = A+B
- * +---+---++---+
- * | A | B || Y |
- * +===+===++===+
- * | 0 | 0 || 1 |
- * | 0 | 1 || 0 |
- * | 1 | 0 || 0 |
- * | 1 | 1 || 0 |
- * +---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7402_DIP)
- TTL_7402_GATE(A)
- TTL_7402_GATE(B)
- TTL_7402_GATE(C)
- TTL_7402_GATE(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.Q, /* Y1 |1 ++ 14| VCC */ A.VCC,
- A.A, /* A1 |2 13| Y4 */ D.Q,
- A.B, /* B1 |3 12| B4 */ D.B,
- B.Q, /* Y2 |4 7402 11| A4 */ D.A,
- B.A, /* A2 |5 10| Y3 */ C.Q,
- B.B, /* B2 |6 9| B3 */ C.B,
- A.GND,/* GND |7 8| A3 */ C.A
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7404: Hex Inverting Gates
- *
- * Y = A
- * +---++---+
- * | A || Y |
- * +===++===+
- * | 0 || 1 |
- * | 1 || 0 |
- * +---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7404_DIP)
- TTL_7404_GATE(A)
- TTL_7404_GATE(B)
- TTL_7404_GATE(C)
- TTL_7404_GATE(D)
- TTL_7404_GATE(E)
- TTL_7404_GATE(F)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.Q, /* Y1 |2 13| A6 */ F.A,
- B.A, /* A2 |3 12| Y6 */ F.Q,
- B.Q, /* Y2 |4 7404 11| A5 */ E.A,
- C.A, /* A3 |5 10| Y5 */ E.Q,
- C.Q, /* Y3 |6 9| A4 */ D.A,
- A.GND,/* GND |7 8| Y4 */ D.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7408: Quad 2-Input AND Gates
- *
- *
- * Y = AB
- * +---+---++---+
- * | A | B || Y |
- * +===+===++===+
- * | 0 | 0 || 0 |
- * | 0 | 1 || 0 |
- * | 1 | 0 || 0 |
- * | 1 | 1 || 1 |
- * +---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7408_DIP)
- TTL_7408_GATE(A)
- TTL_7408_GATE(B)
- TTL_7408_GATE(C)
- TTL_7408_GATE(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| B4 */ D.B,
- A.Q, /* Y1 |3 12| A4 */ D.A,
- B.A, /* A2 |4 7400 11| Y4 */ D.Q,
- B.B, /* B2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7410: Triple 3-Input NAND Gates
- * __
- * Y = ABC
- * +---+---+---++---+
- * | A | B | C || Y |
- * +===+===+===++===+
- * | X | X | 0 || 1 |
- * | X | 0 | X || 1 |
- * | 0 | X | X || 1 |
- * | 1 | 1 | 1 || 0 |
- * +---+---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7410_DIP)
- TTL_7410_GATE(A)
- TTL_7410_GATE(B)
- TTL_7410_GATE(C)
-
- NET_C(A.VCC, B.VCC, C.VCC)
- NET_C(A.GND, B.GND, C.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| C1 */ A.C,
- B.A, /* A2 |3 12| Y1 */ A.Q,
- B.B, /* B2 |4 7410 11| C3 */ C.C,
- B.C, /* C2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7411: Triple 3-Input AND Gates
- *
- * Y = ABC
- * +---+---+---++---+
- * | A | B | C || Y |
- * +===+===+===++===+
- * | X | X | 0 || 0 |
- * | X | 0 | X || 0 |
- * | 0 | X | X || 0 |
- * | 1 | 1 | 1 || 1 |
- * +---+---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7411_DIP)
- TTL_7411_GATE(A)
- TTL_7411_GATE(B)
- TTL_7411_GATE(C)
-
- NET_C(A.VCC, B.VCC, C.VCC)
- NET_C(A.GND, B.GND, C.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| C1 */ A.C,
- B.A, /* A2 |3 12| Y1 */ A.Q,
- B.B, /* B2 |4 7411 11| C3 */ C.C,
- B.C, /* C2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7414/DM74LS14: Hex Inverter with
- * Schmitt Trigger Inputs
- *
- */
-
-static NETLIST_START(TTL_7414_GATE)
- SCHMITT_TRIGGER(X, "DM7414")
- ALIAS(A, X.A)
- ALIAS(Q, X.Q)
- ALIAS(GND, X.GND)
-NETLIST_END()
-
-static NETLIST_START(TTL_74LS14_GATE)
- SCHMITT_TRIGGER(X, "DM74LS14")
- ALIAS(A, X.A)
- ALIAS(Q, X.Q)
- ALIAS(GND, X.GND)
-NETLIST_END()
-
-static NETLIST_START(TTL_7414_DIP)
- SCHMITT_TRIGGER(A, "DM7414")
- SCHMITT_TRIGGER(B, "DM7414")
- SCHMITT_TRIGGER(C, "DM7414")
- SCHMITT_TRIGGER(D, "DM7414")
- SCHMITT_TRIGGER(E, "DM7414")
- SCHMITT_TRIGGER(F, "DM7414")
-
- NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
- DUMMY_INPUT(VCC)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ VCC.I,
- A.Q, /* Y1 |2 13| A6 */ F.A,
- B.A, /* A2 |3 12| Y6 */ F.Q,
- B.Q, /* Y2 |4 7414 11| A5 */ E.A,
- C.A, /* A3 |5 10| Y5 */ E.Q,
- C.Q, /* Y3 |6 9| A4 */ D.A,
- A.GND, /* GND |7 8| Y4 */ D.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-static NETLIST_START(TTL_74LS14_DIP)
- SCHMITT_TRIGGER(A, "DM74LS14")
- SCHMITT_TRIGGER(B, "DM74LS14")
- SCHMITT_TRIGGER(C, "DM74LS14")
- SCHMITT_TRIGGER(D, "DM74LS14")
- SCHMITT_TRIGGER(E, "DM74LS14")
- SCHMITT_TRIGGER(F, "DM74LS14")
-
- NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
- DUMMY_INPUT(VCC)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ VCC.I,
- A.Q, /* Y1 |2 13| A6 */ F.A,
- B.A, /* A2 |3 12| Y6 */ F.Q,
- B.Q, /* Y2 |4 74LS14 11| A5 */ E.A,
- C.A, /* A3 |5 10| Y5 */ E.Q,
- C.Q, /* Y3 |6 9| A4 */ D.A,
- A.GND, /* GND |7 8| Y4 */ D.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7416: Hex Inverting Buffers with
- * High Voltage Open-Collector Outputs
- *
- */
-
-static NETLIST_START(TTL_7416_DIP)
- TTL_7416_GATE(A)
- TTL_7416_GATE(B)
- TTL_7416_GATE(C)
- TTL_7416_GATE(D)
- TTL_7416_GATE(E)
- TTL_7416_GATE(F)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.Q, /* Y1 |2 13| A6 */ F.A,
- B.A, /* A2 |3 12| Y6 */ F.Q,
- B.Q, /* Y2 |4 7416 11| A5 */ E.A,
- C.A, /* A3 |5 10| Y5 */ E.Q,
- C.Q, /* Y3 |6 9| A4 */ D.A,
- A.GND,/* GND |7 8| Y4 */ D.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7420: Dual 4-Input NAND Gates
- *
- * ___
- * Y = ABCD
- * +---+---+---+---++---+
- * | A | B | C | D || Y |
- * +===+===+===+===++===+
- * | X | X | X | 0 || 1 |
- * | X | X | 0 | X || 1 |
- * | X | 0 | X | X || 1 |
- * | 0 | X | X | X || 1 |
- * | 1 | 1 | 1 | 1 || 0 |
- * +---+---+---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet *
- */
-
-static NETLIST_START(TTL_7420_DIP)
- TTL_7420_GATE(A)
- TTL_7420_GATE(B)
-
- NET_C(A.VCC, B.VCC)
- NET_C(A.GND, B.GND)
- DUMMY_INPUT(NC)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| D2 */ B.D,
- NC.I, /* NC |3 12| C2 */ B.C,
- A.C, /* C1 |4 7420 11| NC */ NC.I,
- A.D, /* D1 |5 10| B2 */ B.B,
- A.Q, /* Y1 |6 9| A2 */ B.A,
- A.GND,/* GND |7 8| Y2 */ B.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7425: Dual 4-Input NOR Gates
- *
- * ______
- * Y = A+B+C+D
- * +---+---+---+---+---++---+
- * | A | B | C | D | X || Y |
- * +===+===+===+===+===++===+
- * | X | X | X | X | 0 || Z |
- * | 0 | 0 | 0 | 0 | 1 || 1 |
- * | X | X | X | 1 | 1 || 0 |
- * | X | X | 1 | X | 1 || 0 |
- * | X | 1 | X | X | 1 || 0 |
- * | 1 | X | X | X | 1 || 0 |
- * +---+---+---+---+---++---+
- *
- * FIXME: The "X" input and high impedance output are currently not simulated.
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7425_DIP)
- TTL_7425_GATE(A)
- TTL_7425_GATE(B)
-
- NET_C(A.VCC, B.VCC)
- NET_C(A.GND, B.GND)
- DUMMY_INPUT(X)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| D2 */ B.D,
- X.I, /* X1 |3 12| C2 */ B.C,
- A.C, /* C1 |4 7425 11| X2 */ X.I,
- A.D, /* D1 |5 10| B2 */ B.B,
- A.Q, /* Y1 |6 9| A2 */ B.A,
- A.GND,/* GND |7 8| Y2 */ B.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7427: Triple 3-Input NOR Gates
- *
- * ____
- * Y = A+B+C
- * +---+---+---++---+
- * | A | B | C || Y |
- * +===+===+===++===+
- * | X | X | 1 || 0 |
- * | X | 1 | X || 0 |
- * | 1 | X | X || 0 |
- * | 0 | 0 | 0 || 1 |
- * +---+---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7427_DIP)
- TTL_7427_GATE(A)
- TTL_7427_GATE(B)
- TTL_7427_GATE(C)
-
- NET_C(A.VCC, B.VCC, C.VCC)
- NET_C(A.GND, B.GND, C.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| C1 */ A.C,
- B.A, /* A2 |3 12| Y1 */ A.Q,
- B.B, /* B2 |4 7427 11| C3 */ C.C,
- B.C, /* C2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7430: 8-Input NAND Gate
- *
- * _______
- * Y = ABCDEFGH
- * +---+---+---+---+---+---+---+---++---+
- * | A | B | C | D | E | F | G | H || Y |
- * +===+===+===+===+===+===+===+===++===+
- * | X | X | X | X | X | X | X | 0 || 1 |
- * | X | X | X | X | X | X | 0 | X || 1 |
- * | X | X | X | X | X | 0 | X | X || 1 |
- * | X | X | X | X | 0 | X | X | X || 1 |
- * | X | X | X | 0 | X | X | X | X || 1 |
- * | X | X | 0 | X | X | X | X | X || 1 |
- * | X | 0 | X | X | X | X | X | X || 1 |
- * | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || 0 |
- * +---+---+---+---+---+---+---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- */
-
-static NETLIST_START(TTL_7430_DIP)
- TTL_7430_GATE(A)
-
- DUMMY_INPUT(NC)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A |1 ++ 14| VCC */ A.VCC,
- A.B, /* B |2 13| NC */ NC.I,
- A.C, /* C |3 12| H */ A.H,
- A.D, /* D |4 7430 11| G */ A.G,
- A.E, /* E |5 10| NC */ NC.I,
- A.F, /* F |6 9| NC */ NC.I,
- A.GND,/* GND |7 8| Y */ A.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7432: Quad 2-Input OR Gates
- *
- * __
- * Y = A+B
- * +---+---++---+
- * | A | B || Y |
- * +===+===++===+
- * | 0 | 0 || 0 |
- * | 0 | 1 || 1 |
- * | 1 | 0 || 1 |
- * | 1 | 1 || 1 |
- * +---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7432_DIP)
- TTL_7432_GATE(A)
- TTL_7432_GATE(B)
- TTL_7432_GATE(C)
- TTL_7432_GATE(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| B4 */ D.B,
- A.Q, /* Y1 |3 12| A4 */ D.A,
- B.A, /* A2 |4 7400 11| Y4 */ D.Q,
- B.B, /* B2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-
-/*
- * DM7437: Quad 2-Input NAND Gates
- *
- * _
- * Y = AB
- * +---+---++---+
- * | A | B || Y |
- * +===+===++===+
- * | 0 | 0 || 1 |
- * | 0 | 1 || 1 |
- * | 1 | 0 || 1 |
- * | 1 | 1 || 0 |
- * +---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- * NOTE: Same as 7400, but drains higher output currents.
- * Netlist currently does not model over currents (should it ever?)
- */
-
-static NETLIST_START(TTL_7437_DIP)
- TTL_7437_GATE(A)
- TTL_7437_GATE(B)
- TTL_7437_GATE(C)
- TTL_7437_GATE(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| B4 */ D.B,
- A.Q, /* Y1 |3 12| A4 */ D.A,
- B.A, /* A2 |4 7400 11| Y4 */ D.Q,
- B.B, /* B2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM7486: Quad 2-Input Exclusive-OR Gates
- *
- * Y = A+B
- * +---+---++---+
- * | A | B || Y |
- * +===+===++===+
- * | 0 | 0 || 0 |
- * | 0 | 1 || 1 |
- * | 1 | 0 || 1 |
- * | 1 | 1 || 0 |
- * +---+---++---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_7486_DIP)
- TTL_7486_GATE(A)
- TTL_7486_GATE(B)
- TTL_7486_GATE(C)
- TTL_7486_GATE(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
- A.B, /* B1 |2 13| B4 */ D.B,
- A.Q, /* Y1 |3 12| A4 */ D.A,
- B.A, /* A2 |4 7486 11| Y4 */ D.Q,
- B.B, /* B2 |5 10| B3 */ C.B,
- B.Q, /* Y2 |6 9| A3 */ C.A,
- A.GND,/* GND |7 8| Y3 */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-#if (USE_TRUTHTABLE_74107)
-#ifndef __PLIB_PREPROCESSOR__
-#define TTL_74107_TT(name) \
- NET_REGISTER_DEV(TTL_74107, name)
-#endif
-
-static NETLIST_START(TTL_74107_DIP)
- TTL_74107_TT(A)
- TTL_74107_TT(B)
-
- NET_C(A.VCC, B.VCC)
- NET_C(A.GND, B.GND)
-
- DIPPINS( /* +--------------+ */
- A.J, /* 1J |1 ++ 14| VCC */ A.VCC,
- A.QQ, /* 1QQ |2 13| 1CLRQ */ A.CLRQ,
- A.Q, /* 1Q |3 12| 1CLK */ A.CLK,
- A.K, /* 1K |4 74107 11| 2K */ B.K,
- B.Q, /* 2Q |5 10| 2CLRQ */ B.CLRQ,
- B.QQ, /* 2QQ |6 9| 2CLK */ B.CLK,
- B.GND, /* GND |7 8| 2J */ B.J
- /* +--------------+ */
- )
-
-NETLIST_END()
-#endif
-
-
-/*
- * DM74155/DM74156: Dual 2-Line to 4-Line Decoders/Demultiplexers
- *
- * +-----+-------++-----------------+
- * | B A | G1 C1 || 1Y0 1Y1 1Y2 1Y3 |
- * +=====+=======++=================+
- * | X X | 1 X || 1 1 1 1 |
- * | 0 0 | 0 1 || 0 1 1 1 |
- * | 0 1 | 0 1 || 1 0 1 1 |
- * | 1 0 | 0 1 || 1 1 0 1 |
- * | 1 1 | 0 1 || 1 1 1 0 |
- * | X X | X 0 || 1 1 1 1 |
- * +-----+-------++-----------------+
- *
- * +-----+-------++-----------------+
- * | B A | G2 C2 || 2Y0 2Y1 2Y2 2Y3 |
- * +=====+=======++=================+
- * | X X | 1 X || 1 1 1 1 |
- * | 0 0 | 0 0 || 0 1 1 1 |
- * | 0 1 | 0 0 || 1 0 1 1 |
- * | 1 0 | 0 0 || 1 1 0 1 |
- * | 1 1 | 0 0 || 1 1 1 0 |
- * | X X | X 1 || 1 1 1 1 |
- * +-----+-------++-----------------+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-static NETLIST_START(TTL_74155_DIP)
- NET_REGISTER_DEV(TTL_74155A_GATE, A)
- NET_REGISTER_DEV(TTL_74155B_GATE, B)
-
- NET_C(A.A, B.A)
- NET_C(A.B, B.B)
-
- NET_C(A.VCC, B.VCC)
- NET_C(A.GND, B.GND)
-
- DIPPINS( /* +--------------+ */
- A.C, /* C1 |1 ++ 16| VCC */ A.VCC,
- A.G, /* G1 |2 15| B4 */ B.C,
- A.B, /* B |3 14| B4 */ B.G,
- A.3, /* 1Y3 |4 74155 13| A4 */ B.A,
- B.2, /* 1Y2 |5 12| Y4 */ B.3,
- B.1, /* 1Y1 |6 11| B3 */ B.2,
- B.0, /* 1Y0 |7 10| A3 */ B.1,
- A.GND,/* GND |8 9| Y3 */ B.0
- /* +--------------+ */
- )
-NETLIST_END()
-
-static NETLIST_START(TTL_74156_DIP)
- NET_REGISTER_DEV(TTL_74156A_GATE, A)
- NET_REGISTER_DEV(TTL_74156B_GATE, B)
-
- NET_C(A.A, B.A)
- NET_C(A.B, B.B)
-
- NET_C(A.VCC, B.VCC)
- NET_C(A.GND, B.GND)
-
- DIPPINS( /* +--------------+ */
- A.C, /* C1 |1 ++ 16| VCC */ A.VCC,
- A.G, /* G1 |2 15| B4 */ B.C,
- A.B, /* B |3 14| B4 */ B.G,
- A.3, /* 1Y3 |4 74156 13| A4 */ B.A,
- B.2, /* 1Y2 |5 12| Y4 */ B.3,
- B.1, /* 1Y1 |6 11| B3 */ B.2,
- B.0, /* 1Y0 |7 10| A3 */ B.1,
- A.GND,/* GND |8 9| Y3 */ B.0
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM74260: Dual 5-Input NOR Gates
- * _________
- * Y = A+B+C+D+E
- * +---+---+---+---+---++---+
- * | A | B | B | B | B || Y |
- * +===+===+===+===+===++===+
- * | 0 | 0 | 0 | 0 | 0 || 1 |
- * | 0 | 0 | 0 | 0 | 1 || 0 |
- * | 0 | 0 | 0 | 1 | 0 || 0 |
- * | 0 | 0 | 1 | 0 | 0 || 0 |
- * | 0 | 1 | 0 | 0 | 0 || 0 |
- * | 1 | 0 | 0 | 0 | 0 || 0 |
- * +---+---+---+---+---++---+
- *
- * Naming conventions follow Texas Instruments datasheet
- *
- */
-
-static NETLIST_START(TTL_74260_DIP)
- TTL_74260_GATE(A)
- TTL_74260_GATE(B)
-
- NET_C(A.VCC, B.VCC)
- NET_C(A.GND, B.GND)
-
- DIPPINS( /* +--------------+ */
- A.C, /* C1 |1 ++ 14| VCC */ A.VCC,
- A.D, /* D1 |2 13| B1 */ A.B,
- A.E, /* E1 |3 12| A1 */ A.A,
- B.E, /* E2 |4 74260 11| D2 */ B.D,
- A.Q, /* Y1 |5 10| C2 */ B.C,
- B.Q, /* Y2 |6 9| B2 */ B.B,
- A.GND,/* GND |7 8| A2 */ B.A
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM74279: Quad S-R Latch
- *
- * +---+---+---++---+
- * |S1 |S2 | R || Q |
- * +===+===+===++===+
- * | 0 | 0 | 0 || 1 |
- * | 0 | 1 | 1 || 1 |
- * | 1 | 0 | 1 || 1 |
- * | 1 | 1 | 0 || 0 |
- * | 1 | 1 | 1 ||QP |
- * +---+---+---++---+
- *
- * QP: Previous Q
- *
- * Naming conventions follow Fairchild Semiconductor datasheet
- *
- */
-
-#ifndef __PLIB_PREPROCESSOR__
-#define TTL_74279A(name) \
- NET_REGISTER_DEV(TTL_74279A, name)
-#define TTL_74279B(name) \
- NET_REGISTER_DEV(TTL_74279B, name)
-#endif
-
-static NETLIST_START(TTL_74279_DIP)
- TTL_74279B(A)
- TTL_74279A(B)
- TTL_74279B(C)
- TTL_74279A(D)
-
- NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
- NET_C(A.GND, B.GND, C.GND, D.GND)
-
- DIPPINS( /* +--------------+ */
- A.R, /* 1R |1 ++ 16| VCC */ A.VCC,
- A.S1, /* 1S1 |2 15| 4S */ D.S,
- A.S2, /* 1S2 |3 14| 4R */ D.R,
- A.Q, /* 1Q |4 74279 13| 4Q */ D.Q,
- B.R, /* 2R |5 12| 3S2 */ C.S2,
- B.S, /* 2S |6 11| 3S1 */ C.S1,
- B.Q, /* 2Q |7 10| 3R */ C.R,
- A.GND, /* GND |8 9| 3Q */ C.Q
- /* +--------------+ */
- )
-NETLIST_END()
-
-/*
- * DM9312: One of Eight Line Data Selectors/Multiplexers
- *
- * +--------------+
- * D0 |1 ++ 16| VCC
- * D1 |2 15| Y
- * D2 |3 14| YQ
- * D3 |4 9312 13| C
- * D4 |5 12| B
- * D5 |6 11| A
- * D6 |7 10| G Strobe
- * GND |8 9| D7
- * +--------------+
- * __
- * +---+---+---+---++---+---+
- * | C | B | A | G || Y | YQ|
- * +===+===+===+===++===+===+
- * | X | X | X | 1 || 0| 1 |
- * | 0 | 0 | 0 | 0 || D0|D0Q|
- * | 0 | 0 | 1 | 0 || D1|D1Q|
- * | 0 | 1 | 0 | 0 || D2|D2Q|
- * | 0 | 1 | 1 | 0 || D3|D3Q|
- * | 1 | 0 | 0 | 0 || D4|D4Q|
- * | 1 | 0 | 1 | 0 || D5|D5Q|
- * | 1 | 1 | 0 | 0 || D6|D6Q|
- * | 1 | 1 | 1 | 0 || D7|D7Q|
- * +---+---+---+---++---+---+
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-
-#ifndef __PLIB_PREPROCESSOR__
-#define DM9312_TT(name) \
- NET_REGISTER_DEV(DM9312_TT, name)
-#endif
-
-static NETLIST_START(DM9312_DIP)
- DM9312_TT(s)
-
- DIPPINS( /* +--------------+ */
- s.D0, /* D0 |1 ++ 16| VCC */ s.VCC,
- s.D1, /* D1 |2 15| Y */ s.Y,
- s.D2, /* D2 |3 14| YQ */ s.YQ,
- s.D3, /* D3 |4 9312 13| C */ s.C,
- s.D4, /* D4 |5 12| B */ s.B,
- s.D5, /* D5 |6 11| A */ s.A,
- s.D6, /* D6 |7 10| G */ s.G, //Strobe
- s.GND, /* GND |8 9| D7 */ s.D7
- /* +--------------+ */
- )
-NETLIST_END()
-
-#if (USE_TRUTHTABLE_7448)
-
-/*
- * DM7448: BCD to 7-Segment decoders/drivers
- *
- * +--------------+
- * B |1 ++ 16| VCC
- * C |2 15| f
- * LAMP TEST |3 14| g
- * BI/RBQ |4 7448 13| a
- * RBI |5 12| b
- * D |6 11| c
- * A |7 10| d
- * GND |8 9| e
- * +--------------+
- *
- *
- * Naming conventions follow National Semiconductor datasheet
- *
- */
-#ifndef __PLIB_PREPROCESSOR__
-#define TTL_7448_TT(name) \
- NET_REGISTER_DEV(TTL_7448_TT, name)
-#endif
-
-static NETLIST_START(TTL_7448_DIP)
- TTL_7448_TT(s)
-
- DIPPINS( /* +--------------+ */
- s.B, /* B |1 ++ 16| VCC */ s.VCC,
- s.C, /* C |2 15| f */ s.f,
- s.LTQ, /* LTQ |3 14| g */ s.g,
- s.BIQ, /* BIQ |4 7448 13| a */ s.a,
- s.RBIQ, /* RBIQ |5 12| b */ s.b,
- s.D, /* D |6 11| c */ s.c,
- s.A, /* A |7 10| d */ s.d,
- s.GND, /* GND |8 9| e */ s.e
- /* +--------------+ */
- )
-NETLIST_END()
-#endif
-
-NETLIST_START(TTL74XX_lib)
- NET_MODEL("DM7414 SCHMITT_TRIGGER(VTP=1.7 VTM=0.9 VI=4.35 RI=6.15k VOH=3.5 ROH=120 VOL=0.1 ROL=37.5 TPLH=15 TPHL=15)")
- NET_MODEL("TTL_7414_GATE SCHMITT_TRIGGER(VTP=1.7 VTM=0.9 VI=4.35 RI=6.15k VOH=3.5 ROH=120 VOL=0.1 ROL=37.5 TPLH=15 TPHL=15)")
- NET_MODEL("DM74LS14 SCHMITT_TRIGGER(VTP=1.6 VTM=0.8 VI=4.4 RI=19.3k VOH=3.45 ROH=130 VOL=0.1 ROL=31.2 TPLH=15 TPHL=15)")
- //NET_MODEL("DM7414 FAMILY(FV=5 IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.05 ORL=10.0 ORH=1.0e8)")
-
-
- TRUTHTABLE_START(TTL_7400_GATE, 2, 1, "")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,X|1|22")
- TT_LINE("X,0|1|22")
- TT_LINE("1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7400_NAND, 2, 1, "+A,+B,@VCC,@GND")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,X|1|22")
- TT_LINE("X,0|1|22")
- TT_LINE("1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7402_GATE, 2, 1, "")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,0|1|22")
- TT_LINE("X,1|0|15")
- TT_LINE("1,X|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7402_NOR, 2, 1, "+A,+B,@VCC,@GND")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,0|1|22")
- TT_LINE("X,1|0|15")
- TT_LINE("1,X|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7404_GATE, 1, 1, "")
- TT_HEAD(" A | Q ")
- TT_LINE(" 0 | 1 |22")
- TT_LINE(" 1 | 0 |15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7404_INVERT, 1, 1, "+A,@VCC,@GND")
- TT_HEAD(" A | Q ")
- TT_LINE(" 0 | 1 |22")
- TT_LINE(" 1 | 0 |15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7408_GATE, 2, 1, "")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,X|0|15")
- TT_LINE("X,0|0|15")
- TT_LINE("1,1|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7408_AND, 2, 1, "+A,+B,@VCC,@GND")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,X|0|15")
- TT_LINE("X,0|0|15")
- TT_LINE("1,1|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7410_NAND, 3, 1, "+A,+B,+C,@VCC,@GND")
- TT_HEAD("A,B,C|Q ")
- TT_LINE("0,X,X|1|22")
- TT_LINE("X,0,X|1|22")
- TT_LINE("X,X,0|1|22")
- TT_LINE("1,1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7410_GATE, 3, 1, "")
- TT_HEAD("A,B,C|Q ")
- TT_LINE("0,X,X|1|22")
- TT_LINE("X,0,X|1|22")
- TT_LINE("X,X,0|1|22")
- TT_LINE("1,1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7411_AND, 3, 1, "+A,+B,+C,@VCC,@GND")
- TT_HEAD("A,B,C|Q ")
- TT_LINE("0,X,X|0|15")
- TT_LINE("X,0,X|0|15")
- TT_LINE("X,X,0|0|15")
- TT_LINE("1,1,1|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7411_GATE, 3, 1, "")
- TT_HEAD("A,B,C|Q ")
- TT_LINE("0,X,X|0|15")
- TT_LINE("X,0,X|0|15")
- TT_LINE("X,X,0|0|15")
- TT_LINE("1,1,1|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7416_GATE, 1, 1, "")
- TT_HEAD(" A | Q ")
- TT_LINE(" 0 | 1 |15")
- TT_LINE(" 1 | 0 |23")
- /* Open Collector */
- TT_FAMILY("74XXOC")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7420_GATE, 4, 1, "")
- TT_HEAD("A,B,C,D|Q ")
- TT_LINE("0,X,X,X|1|22")
- TT_LINE("X,0,X,X|1|22")
- TT_LINE("X,X,0,X|1|22")
- TT_LINE("X,X,X,0|1|22")
- TT_LINE("1,1,1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7420_NAND, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
- TT_HEAD("A,B,C,D|Q ")
- TT_LINE("0,X,X,X|1|22")
- TT_LINE("X,0,X,X|1|22")
- TT_LINE("X,X,0,X|1|22")
- TT_LINE("X,X,X,0|1|22")
- TT_LINE("1,1,1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7425_GATE, 4, 1, "")
- TT_HEAD("A,B,C,D|Q ")
- TT_LINE("1,X,X,X|0|15")
- TT_LINE("X,1,X,X|0|15")
- TT_LINE("X,X,1,X|0|15")
- TT_LINE("X,X,X,1|0|15")
- TT_LINE("0,0,0,0|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7425_NOR, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
- TT_HEAD("A,B,C,D|Q ")
- TT_LINE("1,X,X,X|0|15")
- TT_LINE("X,1,X,X|0|15")
- TT_LINE("X,X,1,X|0|15")
- TT_LINE("X,X,X,1|0|15")
- TT_LINE("0,0,0,0|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7427_GATE, 3, 1, "")
- TT_HEAD("A,B,C|Q ")
- TT_LINE("1,X,X|0|15")
- TT_LINE("X,1,X|0|15")
- TT_LINE("X,X,1|0|15")
- TT_LINE("0,0,0|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7427_NOR, 3, 1, "+A,+B,+C,@VCC,@GND")
- TT_HEAD("A,B,C|Q ")
- TT_LINE("1,X,X|0|15")
- TT_LINE("X,1,X|0|15")
- TT_LINE("X,X,1|0|15")
- TT_LINE("0,0,0|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7430_GATE, 8, 1, "")
- TT_HEAD("A,B,C,D,E,F,G,H|Q ")
- TT_LINE("0,X,X,X,X,X,X,X|1|22")
- TT_LINE("X,0,X,X,X,X,X,X|1|22")
- TT_LINE("X,X,0,X,X,X,X,X|1|22")
- TT_LINE("X,X,X,0,X,X,X,X|1|22")
- TT_LINE("X,X,X,X,0,X,X,X|1|22")
- TT_LINE("X,X,X,X,X,0,X,X|1|22")
- TT_LINE("X,X,X,X,X,X,0,X|1|22")
- TT_LINE("X,X,X,X,X,X,X,0|1|22")
- TT_LINE("1,1,1,1,1,1,1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7430_NAND, 8, 1, "+A,+B,+C,+D,+E,+F,+G,+H,@VCC,@GND")
- TT_HEAD("A,B,C,D,E,F,G,H|Q ")
- TT_LINE("0,X,X,X,X,X,X,X|1|22")
- TT_LINE("X,0,X,X,X,X,X,X|1|22")
- TT_LINE("X,X,0,X,X,X,X,X|1|22")
- TT_LINE("X,X,X,0,X,X,X,X|1|22")
- TT_LINE("X,X,X,X,0,X,X,X|1|22")
- TT_LINE("X,X,X,X,X,0,X,X|1|22")
- TT_LINE("X,X,X,X,X,X,0,X|1|22")
- TT_LINE("X,X,X,X,X,X,X,0|1|22")
- TT_LINE("1,1,1,1,1,1,1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7432_GATE, 2, 1, "")
- TT_HEAD("A,B|Q ")
- TT_LINE("1,X|1|22")
- TT_LINE("X,1|1|22")
- TT_LINE("0,0|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7432_OR, 2, 1, "+A,+B,@VCC,@GND")
- TT_HEAD("A,B|Q ")
- TT_LINE("1,X|1|22")
- TT_LINE("X,1|1|22")
- TT_LINE("0,0|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- /* FIXME: Same as 7400, but drains higher output currents.
- * Netlist currently does not model over currents (should it ever?)
- */
-
- TRUTHTABLE_START(TTL_7437_GATE, 2, 1, "")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,X|1|22")
- TT_LINE("X,0|1|22")
- TT_LINE("1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
-#if (USE_TRUTHTABLE_7448)
- TRUTHTABLE_START(TTL_7448, 7, 7, "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
- TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
-
- TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
-
- // BI/RBO is input output. In the next case it is used as an input will go low.
- TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
-
- TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
-
- // This condition has precedence
- TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
- TT_FAMILY("74XX")
-
- TRUTHTABLE_END()
-
- // FIXME: We need a more elegant solution than defining twice
- TRUTHTABLE_START(TTL_7448_TT, 7, 7, "")
- TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
-
- TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
- TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
-
- // BI/RBO is input output. In the next case it is used as an input will go low.
- TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
-
- TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
-
- // This condition has precedence
- TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
- TT_FAMILY("74XX")
-
- TRUTHTABLE_END()
-
-#endif
-
- TRUTHTABLE_START(TTL_7437_NAND, 2, 1, "+A,+B")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,X|1|22")
- TT_LINE("X,0|1|22")
- TT_LINE("1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7486_GATE, 2, 1, "")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,0|0|15")
- TT_LINE("0,1|1|22")
- TT_LINE("1,0|1|22")
- TT_LINE("1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_7486_XOR, 2, 1, "+A,+B,@VCC,@GND")
- TT_HEAD("A,B|Q ")
- TT_LINE("0,0|0|15")
- TT_LINE("0,1|1|22")
- TT_LINE("1,0|1|22")
- TT_LINE("1,1|0|15")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
-#if (USE_TRUTHTABLE_74107)
- /*
- * +-----+-----+-----+---++---+-----+
- * | CLRQ| CLK | J | K || Q | QQ |
- * +=====+=====+=====+===++===+=====+
- * | 0 | X | X | X || 0 | 1 |
- * | 1 | * | 0 | 0 || Q0| Q0Q |
- * | 1 | * | 1 | 0 || 1 | 0 |
- * | 1 | * | 0 | 1 || 0 | 1 |
- * | 1 | * | 1 | 1 || TOGGLE |
- * +-----+-----+-----+---++---+-----+
- */
- TRUTHTABLE_START(TTL_74107, 6, 4, "+CLK,+J,+K,+CLRQ,@VCC,@GND")
- TT_HEAD("CLRQ, CLK, _CO, J, K,_QX | Q, QQ, CO, QX")
- TT_LINE(" 0, 0, X, X, X, X | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 0, 1, X, X, X, X | 0, 1, 1, 0 | 16, 25, 1, 1")
-
- TT_LINE(" 1, 0, X, 0, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 1, X, 0, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 0, X, 0, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
- TT_LINE(" 1, 1, X, 0, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
-
- TT_LINE(" 1, 0, 1, 1, 0, X | 1, 0, 0, 1 | 25, 16, 1, 1")
- TT_LINE(" 1, 0, 0, 1, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 0, 0, 1, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
- TT_LINE(" 1, 1, X, 1, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 1, X, 1, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
-
- TT_LINE(" 1, 0, 1, 0, 1, X | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 0, 0, 0, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 0, 0, 0, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
- TT_LINE(" 1, 1, X, 0, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 1, X, 0, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
-
- // Toggle
- TT_LINE(" 1, 0, 0, 1, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 0, 0, 1, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
- TT_LINE(" 1, 1, 0, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 1, 0, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
- TT_LINE(" 1, 1, 1, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 1, 1, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
-
- TT_LINE(" 1, 0, 1, 1, 1, 1 | 0, 1, 0, 0 | 16, 25, 1, 1")
- TT_LINE(" 1, 0, 1, 1, 1, 0 | 1, 0, 0, 1 | 25, 16, 1, 1")
- TRUTHTABLE_END()
-#endif
-
- TRUTHTABLE_START(TTL_74155A_GATE, 4, 4, "")
- TT_HEAD("B,A,G,C|0,1,2,3")
- TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
- TT_LINE("X,X,0,0|1,1,1,1|13,13,13,13")
- TT_LINE("0,0,0,1|0,1,1,1|13,13,13,13")
- TT_LINE("0,1,0,1|1,0,1,1|13,13,13,13")
- TT_LINE("1,0,0,1|1,1,0,1|13,13,13,13")
- TT_LINE("1,1,0,1|1,1,1,0|13,13,13,13")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_74155B_GATE, 4, 4, "")
- TT_HEAD("B,A,G,C|0,1,2,3")
- TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
- TT_LINE("X,X,0,1|1,1,1,1|13,13,13,13")
- TT_LINE("0,0,0,0|0,1,1,1|13,13,13,13")
- TT_LINE("0,1,0,0|1,0,1,1|13,13,13,13")
- TT_LINE("1,0,0,0|1,1,0,1|13,13,13,13")
- TT_LINE("1,1,0,0|1,1,1,0|13,13,13,13")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_74156A_GATE, 4, 4, "")
- TT_HEAD("B,A,G,C|0,1,2,3")
- TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
- TT_LINE("X,X,0,0|1,1,1,1|13,13,13,13")
- TT_LINE("0,0,0,1|0,1,1,1|13,13,13,13")
- TT_LINE("0,1,0,1|1,0,1,1|13,13,13,13")
- TT_LINE("1,0,0,1|1,1,0,1|13,13,13,13")
- TT_LINE("1,1,0,1|1,1,1,0|13,13,13,13")
- TT_FAMILY("74XXOC")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_74156B_GATE, 4, 4, "")
- TT_HEAD("B,A,G,C|0,1,2,3")
- TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
- TT_LINE("X,X,0,1|1,1,1,1|13,13,13,13")
- TT_LINE("0,0,0,0|0,1,1,1|13,13,13,13")
- TT_LINE("0,1,0,0|1,0,1,1|13,13,13,13")
- TT_LINE("1,0,0,0|1,1,0,1|13,13,13,13")
- TT_LINE("1,1,0,0|1,1,1,0|13,13,13,13")
- TT_FAMILY("74XXOC")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_74260_GATE, 5, 1, "")
- TT_HEAD("A,B,C,D,E|Q ")
- TT_LINE("0,0,0,0,0|1|10")
- TT_LINE("X,X,X,X,1|0|12")
- TT_LINE("X,X,X,1,X|0|12")
- TT_LINE("X,X,1,X,X|0|12")
- TT_LINE("X,1,X,X,X|0|12")
- TT_LINE("1,X,X,X,X|0|12")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_74260_NOR, 5, 1, "+A,+B,+C,+D,+E,@VCC,@GND")
- TT_HEAD("A,B,C,D,E|Q")
- TT_LINE("0,0,0,0,0|1|10")
- TT_LINE("X,X,X,X,1|0|12")
- TT_LINE("X,X,X,1,X|0|12")
- TT_LINE("X,X,1,X,X|0|12")
- TT_LINE("X,1,X,X,X|0|12")
- TT_LINE("1,X,X,X,X|0|12")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- // FIXME: We need "private" devices
- TRUTHTABLE_START(TTL_74279A, 3, 1, "")
- TT_HEAD("S,R,_Q|Q")
- TT_LINE("0,X,X|1|22")
- TT_LINE("1,0,X|0|27")
- TT_LINE("1,1,0|0|27")
- TT_LINE("1,1,1|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(TTL_74279B, 4, 1, "")
- TT_HEAD("S1,S2,R,_Q|Q")
- TT_LINE("0,X,X,X|1|22")
- TT_LINE("X,0,X,X|1|22")
- TT_LINE("1,1,0,X|0|27")
- TT_LINE("1,1,1,0|0|27")
- TT_LINE("1,1,1,1|1|22")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- TRUTHTABLE_START(DM9312_TT, 12, 2, "+A,+B,+C,+G,+D0,+D1,+D2,+D3,+D4,+D5,+D6,+D7,@VCC,@GND")
- TT_HEAD(" C, B, A, G,D0,D1,D2,D3,D4,D5,D6,D7| Y,YQ")
- TT_LINE(" X, X, X, 1, X, X, X, X, X, X, X, X| 0, 1|33,19")
- TT_LINE(" 0, 0, 0, 0, 0, X, X, X, X, X, X, X| 0, 1|33,28")
- TT_LINE(" 0, 0, 0, 0, 1, X, X, X, X, X, X, X| 1, 0|33,28")
- TT_LINE(" 0, 0, 1, 0, X, 0, X, X, X, X, X, X| 0, 1|33,28")
- TT_LINE(" 0, 0, 1, 0, X, 1, X, X, X, X, X, X| 1, 0|33,28")
- TT_LINE(" 0, 1, 0, 0, X, X, 0, X, X, X, X, X| 0, 1|33,28")
- TT_LINE(" 0, 1, 0, 0, X, X, 1, X, X, X, X, X| 1, 0|33,28")
- TT_LINE(" 0, 1, 1, 0, X, X, X, 0, X, X, X, X| 0, 1|33,28")
- TT_LINE(" 0, 1, 1, 0, X, X, X, 1, X, X, X, X| 1, 0|33,28")
- TT_LINE(" 1, 0, 0, 0, X, X, X, X, 0, X, X, X| 0, 1|33,28")
- TT_LINE(" 1, 0, 0, 0, X, X, X, X, 1, X, X, X| 1, 0|33,28")
- TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 0, X, X| 0, 1|33,28")
- TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 1, X, X| 1, 0|33,28")
- TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 0, X| 0, 1|33,28")
- TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 1, X| 1, 0|33,28")
- TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 0| 0, 1|33,28")
- TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 1| 1, 0|33,28")
- TT_FAMILY("74XX")
- TRUTHTABLE_END()
-
- LOCAL_LIB_ENTRY(TTL_7400_DIP)
- LOCAL_LIB_ENTRY(TTL_7402_DIP)
- LOCAL_LIB_ENTRY(TTL_7404_DIP)
- LOCAL_LIB_ENTRY(TTL_7408_DIP)
- LOCAL_LIB_ENTRY(TTL_7410_DIP)
- LOCAL_LIB_ENTRY(TTL_7411_DIP)
- LOCAL_LIB_ENTRY(TTL_7414_GATE)
- LOCAL_LIB_ENTRY(TTL_74LS14_GATE)
- LOCAL_LIB_ENTRY(TTL_7414_DIP)
- LOCAL_LIB_ENTRY(TTL_74LS14_DIP)
- LOCAL_LIB_ENTRY(TTL_7416_DIP)
- LOCAL_LIB_ENTRY(TTL_7420_DIP)
- LOCAL_LIB_ENTRY(TTL_7425_DIP)
- LOCAL_LIB_ENTRY(TTL_7427_DIP)
- LOCAL_LIB_ENTRY(TTL_7430_DIP)
- LOCAL_LIB_ENTRY(TTL_7432_DIP)
- LOCAL_LIB_ENTRY(TTL_7437_DIP)
-#if (USE_TRUTHTABLE_7448)
- LOCAL_LIB_ENTRY(TTL_7448_DIP)
-#endif
- LOCAL_LIB_ENTRY(TTL_7486_DIP)
-#if (USE_TRUTHTABLE_74107)
- LOCAL_LIB_ENTRY(TTL_74107_DIP)
-#endif
- LOCAL_LIB_ENTRY(TTL_74155_DIP)
- LOCAL_LIB_ENTRY(TTL_74156_DIP)
- LOCAL_LIB_ENTRY(TTL_74260_DIP)
- LOCAL_LIB_ENTRY(TTL_74279_DIP)
- LOCAL_LIB_ENTRY(DM9312_DIP)
-NETLIST_END()
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.h b/src/lib/netlist/macro/nlm_ttl74xx.h
deleted file mode 100644
index 8afc465490d..00000000000
--- a/src/lib/netlist/macro/nlm_ttl74xx.h
+++ /dev/null
@@ -1,313 +0,0 @@
-// license:GPL-2.0+
-// copyright-holders:Couriersud
-#ifndef NLD_TTL74XX_H_
-#define NLD_TTL74XX_H_
-
-#include "netlist/nl_setup.h"
-
-#ifndef __PLIB_PREPROCESSOR__
-
-/* ----------------------------------------------------------------------------
- * Netlist Macros
- * ---------------------------------------------------------------------------*/
-
-#ifndef NL_AUTO_DEVICES
-
-#define TTL_7400_GATE(name) \
- NET_REGISTER_DEV(TTL_7400_GATE, name)
-
-#define TTL_7400_NAND(name, cA, cB) \
- NET_REGISTER_DEV(TTL_7400_NAND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA) \
- NET_CONNECT(name, B, cB)
-
-#define TTL_7400_DIP(name) \
- NET_REGISTER_DEV(TTL_7400_DIP, name)
-
-
-#define TTL_7402_GATE(name) \
- NET_REGISTER_DEV(TTL_7402_GATE, name)
-
-#define TTL_7402_NOR(name, cI1, cI2) \
- NET_REGISTER_DEV(TTL_7402_NOR, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2)
-
-#define TTL_7402_DIP(name) \
- NET_REGISTER_DEV(TTL_7402_DIP, name)
-
-#define TTL_7404_GATE(name) \
- NET_REGISTER_DEV(TTL_7404_GATE, name)
-
-#define TTL_7404_INVERT(name, cA) \
- NET_REGISTER_DEV(TTL_7404_INVERT, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA)
-
-#define TTL_7404_DIP(name) \
- NET_REGISTER_DEV(TTL_7404_DIP, name)
-
-#define TTL_7408_GATE(name) \
- NET_REGISTER_DEV(TTL_7408_GATE, name)
-
-#define TTL_7408_AND(name, cA, cB) \
- NET_REGISTER_DEV(TTL_7408_AND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA) \
- NET_CONNECT(name, B, cB)
-
-#define TTL_7408_DIP(name) \
- NET_REGISTER_DEV(TTL_7408_DIP, name)
-
-#define TTL_7410_GATE(name) \
- NET_REGISTER_DEV(TTL_7410_GATE, name)
-
-#define TTL_7410_NAND(name, cI1, cI2, cI3) \
- NET_REGISTER_DEV(TTL_7410_NAND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2) \
- NET_CONNECT(name, C, cI3)
-
-#define TTL_7410_DIP(name) \
- NET_REGISTER_DEV(TTL_7410_DIP, name)
-
-
-#define TTL_7411_GATE(name) \
- NET_REGISTER_DEV(TTL_7411_GATE, name)
-
-#define TTL_7411_AND(name, cI1, cI2, cI3) \
- NET_REGISTER_DEV(TTL_7411_AND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2) \
- NET_CONNECT(name, C, cI3)
-
-#define TTL_7411_DIP(name) \
- NET_REGISTER_DEV(TTL_7411_DIP, name)
-
-#define TTL_7414_GATE(name) \
- NET_REGISTER_DEV(TTL_7414_GATE, name)
-
-#define TTL_7414_DIP(name) \
- NET_REGISTER_DEV(TTL_7414_DIP, name)
-
-
-#define TTL_74LS14_GATE(name) \
- NET_REGISTER_DEV(TTL_74LS14_GATE, name)
-
-#define TTL_74LS14_DIP(name) \
- NET_REGISTER_DEV(TTL_74LS14_DIP, name)
-
-
-#define TTL_7416_GATE(name) \
- NET_REGISTER_DEV(TTL_7416_GATE, name)
-
-#define TTL_7416_DIP(name) \
- NET_REGISTER_DEV(TTL_7416_DIP, name)
-
-
-#define TTL_7420_GATE(name) \
- NET_REGISTER_DEV(TTL_7420_GATE, name)
-
-#define TTL_7420_NAND(name, cI1, cI2, cI3, cI4) \
- NET_REGISTER_DEV(TTL_7420_NAND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2) \
- NET_CONNECT(name, C, cI3) \
- NET_CONNECT(name, D, cI4)
-
-#define TTL_7420_DIP(name) \
- NET_REGISTER_DEV(TTL_7420_DIP, name)
-
-
-#define TTL_7425_GATE(name) \
- NET_REGISTER_DEV(TTL_7425_GATE, name)
-
-#define TTL_7425_NOR(name, cI1, cI2, cI3, cI4) \
- NET_REGISTER_DEV(TTL_7425_NOR, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2) \
- NET_CONNECT(name, C, cI3) \
- NET_CONNECT(name, D, cI4)
-
-#define TTL_7425_DIP(name) \
- NET_REGISTER_DEV(TTL_7425_DIP, name)
-
-
-#define TTL_7427_GATE(name) \
- NET_REGISTER_DEV(TTL_7427_GATE, name)
-
-#define TTL_7427_NOR(name, cI1, cI2, cI3) \
- NET_REGISTER_DEV(TTL_7427_NOR, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2) \
- NET_CONNECT(name, C, cI3)
-
-#define TTL_7427_DIP(name) \
- NET_REGISTER_DEV(TTL_7427_DIP, name)
-
-
-#define TTL_7430_GATE(name) \
- NET_REGISTER_DEV(TTL_7430_GATE, name)
-
-#define TTL_7430_NAND(name, cI1, cI2, cI3, cI4, cI5, cI6, cI7, cI8)\
- NET_REGISTER_DEV(TTL_7430_NAND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2) \
- NET_CONNECT(name, C, cI3) \
- NET_CONNECT(name, D, cI4) \
- NET_CONNECT(name, E, cI5) \
- NET_CONNECT(name, F, cI6) \
- NET_CONNECT(name, G, cI7) \
- NET_CONNECT(name, H, cI8)
-
-#define TTL_7430_DIP(name) \
- NET_REGISTER_DEV(TTL_7430_DIP, name)
-
-
-#define TTL_7432_GATE(name) \
- NET_REGISTER_DEV(TTL_7432_OR, name)
-
-#define TTL_7432_OR(name, cI1, cI2) \
- NET_REGISTER_DEV(TTL_7432_OR, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cI1) \
- NET_CONNECT(name, B, cI2)
-
-#define TTL_7432_DIP(name) \
- NET_REGISTER_DEV(TTL_7432_DIP, name)
-
-#define TTL_7437_GATE(name) \
- NET_REGISTER_DEV(TTL_7437_GATE, name)
-
-#define TTL_7437_NAND(name, cA, cB) \
- NET_REGISTER_DEV(TTL_7437_NAND, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA) \
- NET_CONNECT(name, B, cB)
-
-#define TTL_7437_DIP(name) \
- NET_REGISTER_DEV(TTL_7437_DIP, name)
-
-
-#if (USE_TRUTHTABLE_7448)
-#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
- NET_REGISTER_DEV(TTL_7448, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA0) \
- NET_CONNECT(name, B, cA1) \
- NET_CONNECT(name, C, cA2) \
- NET_CONNECT(name, D, cA3) \
- NET_CONNECT(name, LTQ, cLTQ) \
- NET_CONNECT(name, BIQ, cBIQ) \
- NET_CONNECT(name, RBIQ, cRBIQ)
-
-#define TTL_7448_DIP(name) \
- NET_REGISTER_DEV(TTL_7448_DIP, name)
-
-#endif
-
-#define TTL_7486_GATE(name) \
- NET_REGISTER_DEV(TTL_7486_GATE, name)
-
-#define TTL_7486_XOR(name, cA, cB) \
- NET_REGISTER_DEV(TTL_7486_XOR, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA) \
- NET_CONNECT(name, B, cB)
-
-#define TTL_7486_DIP(name) \
- NET_REGISTER_DEV(TTL_7486_DIP, name)
-
-#if (USE_TRUTHTABLE_74107)
-#define TTL_74107(name, cCLK, cJ, cK, cCLRQ) \
- NET_REGISTER_DEV(TTL_74107, name) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, CLK, cCLK) \
- NET_CONNECT(name, J, cJ) \
- NET_CONNECT(name, K, cK) \
- NET_CONNECT(name, CLRQ, cCLRQ)
-
-#define TTL_74107_DIP(name) \
- NET_REGISTER_DEV(TTL_74107_DIP, name)
-
-#endif
-
-#define TTL_74155_DIP(name) \
- NET_REGISTER_DEV(TTL_74155_DIP, name)
-
-#define TTL_74156_DIP(name) \
- NET_REGISTER_DEV(TTL_74156_DIP, name)
-
-#define TTL_74260_GATE(name) \
- NET_REGISTER_DEV(TTL_74260_GATE, name)
-
-#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
- NET_REGISTER_DEV(TTL_74260_NOR, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA) \
- NET_CONNECT(name, B, cB) \
- NET_CONNECT(name, C, cC) \
- NET_CONNECT(name, D, cD) \
- NET_CONNECT(name, E, cE)
-
-#define TTL_74260_DIP(name) \
- NET_REGISTER_DEV(TTL_74260_DIP, name)
-
-#define TTL_74279_DIP(name) \
- NET_REGISTER_DEV(TTL_74279_DIP, name)
-
-#define DM9312(name, cA, cB, cC, cSTROBE, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7) \
- NET_REGISTER_DEV(DM9312_TT, name) \
- NET_CONNECT(name, VCC, VCC) \
- NET_CONNECT(name, GND, GND) \
- NET_CONNECT(name, A, cA) \
- NET_CONNECT(name, B, cB) \
- NET_CONNECT(name, C, cC) \
- NET_CONNECT(name, G, cSTROBE) \
- NET_CONNECT(name, D0, cD0) \
- NET_CONNECT(name, D1, cD1) \
- NET_CONNECT(name, D2, cD2) \
- NET_CONNECT(name, D3, cD3) \
- NET_CONNECT(name, D4, cD4) \
- NET_CONNECT(name, D5, cD5) \
- NET_CONNECT(name, D6, cD6) \
- NET_CONNECT(name, D7, cD7)
-
-#define DM9312_DIP(name) \
- NET_REGISTER_DEV(DM9312_DIP, name)
-
-#endif
-
-/* ----------------------------------------------------------------------------
- * External declarations
- * ---------------------------------------------------------------------------*/
-
-NETLIST_EXTERNAL(TTL74XX_lib)
-
-#endif
-
-#endif
diff --git a/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp b/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
new file mode 100644
index 00000000000..2a1d844d512
--- /dev/null
+++ b/src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
@@ -0,0 +1,3653 @@
+// license:CC0-1.0
+// copyright-holders:Couriersud
+
+//#rewritten with sed -e "s_^\(.*\)/\*\(.*\)\*/\(.*\)\$_\1\3 // \2_g" ../macro/nlm_ttl74xx_lib.cpp
+
+#include "devices/net_lib.h"
+
+//- Identifier: TTL_7400_DIP
+//- Title: 5400/DM5400/DM7400 Quad 2-Input NAND Gates
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006613.PDF
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 1 |
+//- | 0 | 1 || 1 |
+//- | 1 | 0 || 1 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7400_DIP)
+{
+ TTL_7400_NAND(A)
+ TTL_7400_NAND(B)
+ TTL_7400_NAND(C)
+ TTL_7400_NAND(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, D.B, // B1 |2 13| B4
+ A.Q, D.A, // Y1 |3 12| A4
+ B.A, D.Q, // A2 |4 7400 11| Y4
+ B.B, C.B, // B2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q) // GND |7 8| Y3
+ // +--------------+
+}
+
+//- Identifier: TTL_7402_DIP
+//- Title: 5402/DM5402/DM7402 Quad 2-Input NOR Gates
+//- Pinalias: Y1,A1,B1,Y2,A2,B2,GND,A3,B3,Y3,A4,B4,Y4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006492.PDF
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 1 |
+//- | 0 | 1 || 0 |
+//- | 1 | 0 || 0 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7402_DIP)
+{
+ TTL_7402_NOR(A)
+ TTL_7402_NOR(B)
+ TTL_7402_NOR(C)
+ TTL_7402_NOR(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.Q, A.VCC, // Y1 |1 ++ 14| VCC
+ A.A, D.Q, // A1 |2 13| Y4
+ A.B, D.B, // B1 |3 12| B4
+ B.Q, D.A, // Y2 |4 7402 11| A4
+ B.A, C.Q, // A2 |5 10| Y3
+ B.B, C.B, // B2 |6 9| B3
+ A.GND, C.A // GND |7 8| A3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7404_DIP
+//- Title: 5404/DM5404/DM7404 Hex Inverting Gates
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006494.PDF
+//-
+//- +---++---+
+//- | A || Y |
+//- +===++===+
+//- | 0 || 1 |
+//- | 1 || 0 |
+//- +---++---+
+//-
+static NETLIST_START(TTL_7404_DIP)
+{
+ TTL_7404_INVERT(A)
+ TTL_7404_INVERT(B)
+ TTL_7404_INVERT(C)
+ TTL_7404_INVERT(D)
+ TTL_7404_INVERT(E)
+ TTL_7404_INVERT(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Q, F.A, // Y1 |2 13| A6
+ B.A, F.Q, // A2 |3 12| Y6
+ B.Q, E.A, // Y2 |4 7404 11| A5
+ C.A, E.Q, // A3 |5 10| Y5
+ C.Q, D.A, // Y3 |6 9| A4
+ A.GND, D.Q // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7406_DIP
+//- Title: DM5406/DM7406 Hex Inverting Buffers with High Voltage Open-Collector Outputs
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations: Open collector behavior currently not simulated.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006496.PDF
+//-
+//- +---++---+
+//- | A || Y |
+//- +===++===+
+//- | 0 || 1 |
+//- | 1 || 0 |
+//- +---++---+
+//-
+static NETLIST_START(TTL_7406_DIP)
+{
+ TTL_7406_GATE(A)
+ TTL_7406_GATE(B)
+ TTL_7406_GATE(C)
+ TTL_7406_GATE(D)
+ TTL_7406_GATE(E)
+ TTL_7406_GATE(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Y, F.A, // Y1 |2 13| A6
+ B.A, F.Y, // A2 |3 12| Y6
+ B.Y, E.A, // Y2 |4 7406 11| A5
+ C.A, E.Y, // A3 |5 10| Y5
+ C.Y, D.A, // Y3 |6 9| A4
+ A.GND, D.Y // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7407_DIP
+//- Title: DM5407/DM7407 Hex Buffers with High Voltage Open-Collector Outputs
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations: Open collector behavior currently not simulated.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006497.PDF
+//-
+//- +---++---+
+//- | A || Y |
+//- +===++===+
+//- | 0 || 0 |
+//- | 1 || 1 |
+//- +---++---+
+//-
+static NETLIST_START(TTL_7407_DIP)
+{
+ TTL_7407_GATE(A)
+ TTL_7407_GATE(B)
+ TTL_7407_GATE(C)
+ TTL_7407_GATE(D)
+ TTL_7407_GATE(E)
+ TTL_7407_GATE(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Y, F.A, // Y1 |2 13| A6
+ B.A, F.Y, // A2 |3 12| Y6
+ B.Y, E.A, // Y2 |4 7407 11| A5
+ C.A, E.Y, // A3 |5 10| Y5
+ C.Y, D.A, // Y3 |6 9| A4
+ A.GND, D.Y // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7408_DIP
+//- Title: 5408/DM5408/DM7408 Quad 2-Input AND Gates
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006498.PDF
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 0 |
+//- | 0 | 1 || 0 |
+//- | 1 | 0 || 0 |
+//- | 1 | 1 || 1 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7408_DIP)
+{
+ TTL_7408_AND(A)
+ TTL_7408_AND(B)
+ TTL_7408_AND(C)
+ TTL_7408_AND(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, D.B, // B1 |2 13| B4
+ A.Q, D.A, // Y1 |3 12| A4
+ B.A, D.Q, // A2 |4 7408 11| Y4
+ B.B, C.B, // B2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7410_DIP
+//- Title: 5410/DM5410/DM7410 Triple 3-Input NAND Gates
+//- Pinalias: A1,B1,A2,B2,C2,Y2,GND,Y3,A3,B3,C3,Y1,C1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006500.PDF
+//-
+//- +---+---+---++---+
+//- | A | B | C || Y |
+//- +===+===+===++===+
+//- | X | X | 0 || 1 |
+//- | X | 0 | X || 1 |
+//- | 0 | X | X || 1 |
+//- | 1 | 1 | 1 || 0 |
+//- +---+---+---++---+
+//-
+static NETLIST_START(TTL_7410_DIP)
+{
+ TTL_7410_NAND(A)
+ TTL_7410_NAND(B)
+ TTL_7410_NAND(C)
+
+ NET_C(A.VCC, B.VCC, C.VCC)
+ NET_C(A.GND, B.GND, C.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, A.C, // B1 |2 13| C1
+ B.A, A.Q, // A2 |3 12| Y1
+ B.B, C.C, // B2 |4 7410 11| C3
+ B.C, C.B, // C2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7411_DIP
+//- Title: DM7411 Triple 3-Input AND Gate
+//- Pinalias: A1,B1,A2,B2,C2,Y2,GND,Y3,A3,B3,C3,Y1,C1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009774.PDF
+//-
+//- +---+---+---++---+
+//- | A | B | C || Y |
+//- +===+===+===++===+
+//- | X | X | 0 || 0 |
+//- | X | 0 | X || 0 |
+//- | 0 | X | X || 0 |
+//- | 1 | 1 | 1 || 1 |
+//- +---+---+---++---+
+//-
+static NETLIST_START(TTL_7411_DIP)
+{
+ TTL_7411_AND(A)
+ TTL_7411_AND(B)
+ TTL_7411_AND(C)
+
+ NET_C(A.VCC, B.VCC, C.VCC)
+ NET_C(A.GND, B.GND, C.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, A.C, // B1 |2 13| C1
+ B.A, A.Q, // A2 |3 12| Y1
+ B.B, C.C, // B2 |4 7411 11| C3
+ B.C, C.B, // C2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7414_DIP
+//- Title: DM5414/DM7414 Hex Inverter withSchmitt Trigger Inputs
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006503.PDF
+//-
+//- +---++---+
+//- | A || Y |
+//- +===++===+
+//- | 0 || 1 |
+//- | 1 || 0 |
+//- +---++---+
+//-
+static NETLIST_START(TTL_7414_GATE)
+{
+ SCHMITT_TRIGGER(X, "DM7414")
+ ALIAS(A, X.A)
+ ALIAS(Q, X.Q)
+ ALIAS(GND, X.GND)
+ ALIAS(VCC, X.VCC)
+}
+
+static NETLIST_START(TTL_74LS14_GATE)
+{
+ SCHMITT_TRIGGER(X, "DM74LS14")
+ ALIAS(A, X.A)
+ ALIAS(Q, X.Q)
+ ALIAS(GND, X.GND)
+ ALIAS(VCC, X.VCC)
+}
+
+static NETLIST_START(TTL_7414_DIP)
+{
+ SCHMITT_TRIGGER(A, "DM7414")
+ SCHMITT_TRIGGER(B, "DM7414")
+ SCHMITT_TRIGGER(C, "DM7414")
+ SCHMITT_TRIGGER(D, "DM7414")
+ SCHMITT_TRIGGER(E, "DM7414")
+ SCHMITT_TRIGGER(F, "DM7414")
+
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Q, F.A, // Y1 |2 13| A6
+ B.A, F.Q, // A2 |3 12| Y6
+ B.Q, E.A, // Y2 |4 7414 11| A5
+ C.A, E.Q, // A3 |5 10| Y5
+ C.Q, D.A, // Y3 |6 9| A4
+ A.GND, D.Q // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+static NETLIST_START(TTL_74LS14_DIP)
+{
+ SCHMITT_TRIGGER(A, "DM74LS14")
+ SCHMITT_TRIGGER(B, "DM74LS14")
+ SCHMITT_TRIGGER(C, "DM74LS14")
+ SCHMITT_TRIGGER(D, "DM74LS14")
+ SCHMITT_TRIGGER(E, "DM74LS14")
+ SCHMITT_TRIGGER(F, "DM74LS14")
+
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Q, F.A, // Y1 |2 13| A6
+ B.A, F.Q, // A2 |3 12| Y6
+ B.Q, E.A, // Y2 |4 74LS14 11| A5
+ C.A, E.Q, // A3 |5 10| Y5
+ C.Q, D.A, // Y3 |6 9| A4
+ A.GND, D.Q // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7416_DIP
+//- Title: DM5416/DM7416 Hex Inverting Buffers with High Voltage Open-Collector Outputs
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006504.PDF
+//-
+//- +---++---+
+//- | A || Y |
+//- +===++===+
+//- | 0 || 1 |
+//- | 1 || 0 |
+//- +---++---+
+//-
+static NETLIST_START(TTL_7416_DIP)
+{
+ TTL_7416_GATE(A)
+ TTL_7416_GATE(B)
+ TTL_7416_GATE(C)
+ TTL_7416_GATE(D)
+ TTL_7416_GATE(E)
+ TTL_7416_GATE(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Q, F.A, // Y1 |2 13| A6
+ B.A, F.Q, // A2 |3 12| Y6
+ B.Q, E.A, // Y2 |4 7416 11| A5
+ C.A, E.Q, // A3 |5 10| Y5
+ C.Q, D.A, // Y3 |6 9| A4
+ A.GND, D.Q // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7417_DIP
+//- Title: DM5417/DM7417 Hex Buffers withHigh Voltage Open-Collector Output
+//- Pinalias: A1,Y1,A2,Y2,A3,Y3,GND,Y4,A4,Y5,A5,Y6,A6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006505.PDF
+//-
+//- +---++---+
+//- | A || Y |
+//- +===++===+
+//- | 0 || 0 |
+//- | 1 || 1 |
+//- +---++---+
+//-
+static NETLIST_START(TTL_7417_DIP)
+{
+ TTL_7417_GATE(A)
+ TTL_7417_GATE(B)
+ TTL_7417_GATE(C)
+ TTL_7417_GATE(D)
+ TTL_7417_GATE(E)
+ TTL_7417_GATE(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.Q, F.A, // Y1 |2 13| A6
+ B.A, F.Q, // A2 |3 12| Y6
+ B.Q, E.A, // Y2 |4 7417 11| A5
+ C.A, E.Q, // A3 |5 10| Y5
+ C.Q, D.A, // Y3 |6 9| A4
+ A.GND, D.Q // GND |7 8| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7420_DIP
+//- Title: 5420/DM5420/DM7420 Dual 4-Input NAND Gates
+//- Pinalias: A1,B1,NC,C1,D1,Y1,GND,Y2,A2,B2,NC,C2,D2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006506.PDF
+//-
+//- +---+---+---+---++---+
+//- | A | B | C | D || Y |
+//- +===+===+===+===++===+
+//- | X | X | X | 0 || 1 |
+//- | X | X | 0 | X || 1 |
+//- | X | 0 | X | X || 1 |
+//- | 0 | X | X | X || 1 |
+//- | 1 | 1 | 1 | 1 || 0 |
+//- +---+---+---+---++---+
+//-
+static NETLIST_START(TTL_7420_DIP)
+{
+ TTL_7420_NAND(A)
+ TTL_7420_NAND(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, B.D, // B1 |2 13| D2
+ NC.I, B.C, // NC |3 12| C2
+ A.C, NC.I, // C1 |4 7420 11| NC
+ A.D, B.B, // D1 |5 10| B2
+ A.Q, B.A, // Y1 |6 9| A2
+ A.GND, B.Q // GND |7 8| Y2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7421_DIP
+//- Title: 54LS21/DM54LS21/DM74LS21 Dual 4-Input AND Gates
+//- Pinalias: A1,B1,NC,C1,D1,Y1,GND,Y2,A2,B2,NC,C2,D2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006356.PDF
+//-
+//- +---+---+---+---++---+
+//- | A | B | C | D || Y |
+//- +===+===+===+===++===+
+//- | X | X | X | 0 || 1 |
+//- | X | X | 0 | X || 1 |
+//- | X | 0 | X | X || 1 |
+//- | 0 | X | X | X || 1 |
+//- | 1 | 1 | 1 | 1 || 0 |
+//- +---+---+---+---++---+
+//-
+static NETLIST_START(TTL_7421_DIP)
+{
+ TTL_7421_AND(A)
+ TTL_7421_AND(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, B.D, // B1 |2 13| D2
+ NC.I, B.C, // NC |3 12| C2
+ A.C, NC.I, // C1 |4 7421 11| NC
+ A.D, B.B, // D1 |5 10| B2
+ A.Q, B.A, // Y1 |6 9| A2
+ A.GND, B.Q // GND |7 8| Y2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7425_DIP
+//- Title: 5425/DM7425 Dual 4-Input NOR Gate (with Strobe)
+//- Pinalias: A1,B1,X1,C1,D1,Y1,GND,Y2,A2,B2,X2,C2,D2
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations: The "X" input and high impedance output are currently not simulated.
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet_pdf/national-semiconductor/5425DMQB_to_DM7425N.pdf
+//-
+//- +---+---+---+---+---++---+
+//- | A | B | C | D | X || Y |
+//- +===+===+===+===+===++===+
+//- | X | X | X | X | 0 || Z |
+//- | 0 | 0 | 0 | 0 | 1 || 1 |
+//- | X | X | X | 1 | 1 || 0 |
+//- | X | X | 1 | X | 1 || 0 |
+//- | X | 1 | X | X | 1 || 0 |
+//- | 1 | X | X | X | 1 || 0 |
+//- +---+---+---+---+---++---+
+//-
+static NETLIST_START(TTL_7425_DIP)
+{
+ TTL_7425_NOR(A)
+ TTL_7425_NOR(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+ NC_PIN(XA) // FIXME: Functionality needs to be implemented
+ NC_PIN(XB) // FIXME: Functionality needs to be implemented
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, B.D, // B1 |2 13| D2
+ XA.I, B.C, // X1 |3 12| C2
+ A.C, XB.I, // C1 |4 7425 11| X2
+ A.D, B.B, // D1 |5 10| B2
+ A.Q, B.A, // Y1 |6 9| A2
+ A.GND, B.Q // GND |7 8| Y2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7427_DIP
+//- Title: DM7427 Triple 3-Input NOR Gates
+//- Pinalias: A1,B1,A2,B2,C2,Y2,GND,Y3,A3,B3,C3,Y1,C1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006509.PDF
+//-
+//- +---+---+---++---+
+//- | A | B | C || Y |
+//- +===+===+===++===+
+//- | X | X | 1 || 0 |
+//- | X | 1 | X || 0 |
+//- | 1 | X | X || 0 |
+//- | 0 | 0 | 0 || 1 |
+//- +---+---+---++---+
+//-
+static NETLIST_START(TTL_7427_DIP)
+{
+ TTL_7427_NOR(A)
+ TTL_7427_NOR(B)
+ TTL_7427_NOR(C)
+
+ NET_C(A.VCC, B.VCC, C.VCC)
+ NET_C(A.GND, B.GND, C.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, A.C, // B1 |2 13| C1
+ B.A, A.Q, // A2 |3 12| Y1
+ B.B, C.C, // B2 |4 7427 11| C3
+ B.C, C.B, // C2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7430_DIP
+//- Title: 5430/DM5430/DM7430 8-Input NAND Gate
+//- Pinalias: A,B,C,D,E,F,GND,Y,NC,NC,G,H,NC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006510.PDF
+//-
+//- +---+---+---+---+---+---+---+---++---+
+//- | A | B | C | D | E | F | G | H || Y |
+//- +===+===+===+===+===+===+===+===++===+
+//- | X | X | X | X | X | X | X | 0 || 1 |
+//- | X | X | X | X | X | X | 0 | X || 1 |
+//- | X | X | X | X | X | 0 | X | X || 1 |
+//- | X | X | X | X | 0 | X | X | X || 1 |
+//- | X | X | X | 0 | X | X | X | X || 1 |
+//- | X | X | 0 | X | X | X | X | X || 1 |
+//- | X | 0 | X | X | X | X | X | X || 1 |
+//- | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || 0 |
+//- +---+---+---+---+---+---+---+---++---+
+//-
+static NETLIST_START(TTL_7430_DIP)
+{
+ TTL_7430_NAND(A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A |1 ++ 14| VCC
+ A.B, NC.I, // B |2 13| NC
+ A.C, A.H, // C |3 12| H
+ A.D, A.G, // D |4 7430 11| G
+ A.E, NC.I, // E |5 10| NC
+ A.F, NC.I, // F |6 9| NC
+ A.GND, A.Q // GND |7 8| Y
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7432_DIP
+//- Title: 5432/DM5432/DM7432 Quad 2-Input OR Gates
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006511.PDF
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 0 |
+//- | 0 | 1 || 1 |
+//- | 1 | 0 || 1 |
+//- | 1 | 1 || 1 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7432_DIP)
+{
+ TTL_7432_OR(A)
+ TTL_7432_OR(B)
+ TTL_7432_OR(C)
+ TTL_7432_OR(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, D.B, // B1 |2 13| B4
+ A.Q, D.A, // Y1 |3 12| A4
+ B.A, D.Q, // A2 |4 7432 11| Y4
+ B.B, C.B, // B2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7437_DIP
+//- Title: 5437/DM5437/DM7437 Quad 2-Input NAND Buffers
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations: Same as 7400, but drains higher output currents. Netlist currently does not model over currents (should it ever?)
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/105/236976_DS.pdf
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 1 |
+//- | 0 | 1 || 1 |
+//- | 1 | 0 || 1 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7437_DIP)
+{
+ TTL_7437_NAND(A)
+ TTL_7437_NAND(B)
+ TTL_7437_NAND(C)
+ TTL_7437_NAND(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, D.B, // B1 |2 13| B4
+ A.Q, D.A, // Y1 |3 12| A4
+ B.A, D.Q, // A2 |4 7437 11| Y4
+ B.B, C.B, // B2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7438_DIP
+//- Title: DM74LS38 Quad 2-Input NAND Buffer with Open-Collector Outputs
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/70/375632_DS.pdf
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 1 |
+//- | 0 | 1 || 1 |
+//- | 1 | 0 || 1 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7438_DIP)
+{
+ TTL_7438_NAND(A)
+ TTL_7438_NAND(B)
+ TTL_7438_NAND(C)
+ TTL_7438_NAND(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, D.B, // B1 |2 13| B4
+ A.Q, D.A, // Y1 |3 12| A4
+ B.A, D.Q, // A2 |4 7438 11| Y4
+ B.B, C.B, // B2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7442_DIP
+//- Title: 5442A/DM5442A/DM7442A BCD to Decimal Decoders
+//- Pinalias: 0,1,2,3,4,5,6,GND,7,8,9,D,C,B,A,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006516.PDF
+//-
+//- +---+---+---+---++---+---+---+---+---+---+---+---+---+---+
+//- | D | C | B | A || 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
+//- +===+===+===+===++===+===+===+===+===+===+===+===+===+===+
+//- | 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 0 | 1 || 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 1 | 0 || 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 1 | 1 || 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
+//- | 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
+//- | 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+//- | 1 | 0 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
+//- | 1 | 0 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | 0 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | 1 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- +---+---+---+---++---+---+---+---+---+---+---+---+---+---+
+//-
+static NETLIST_START(TTL_7442_DIP)
+{
+ NET_REGISTER_DEV(TTL_7442, A)
+
+ DIPPINS( // +--------------+
+ A.Q0, A.VCC, // 0 |1 ++ 16| VCC
+ A.Q1, A.A, // 1 |2 15| A
+ A.Q2, A.B, // 2 |3 14| B
+ A.Q3, A.C, // 3 |4 13| C
+ A.Q4, A.D, // 4 |5 7442 12| D
+ A.Q5, A.Q9, // 5 |6 11| 9
+ A.Q6, A.Q8, // 6 |7 10| 8
+ A.GND, A.Q7 // GND |8 9| 7
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7448_DIP
+//- Title: DM5448/DM48LS48/DM7448/DM74LS48 BCD to 7-Segment Decoder
+//- Pinalias: A1,A2,LTQ,BIQ,RBIQ,A3,A0,GND,e,d,c,b,a,g,f,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS010172.PDF
+//-
+//- +-----+------+----+----+----+----++-----+---+---+---+---+---+---+---+
+//- | LTQ | RBIQ | A3 | A2 | A1 | A0 || BIQ | a | b | c | d | e | f | g |
+//- +=====+======+====+====+====+====++=====+===+===+===+===+===+===+===+
+//- | 1 | 1 | 0 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
+//- | 1 | X | 0 | 0 | 0 | 1 || 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
+//- | 1 | X | 0 | 0 | 1 | 0 || 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
+//- | 1 | X | 0 | 0 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
+//- | 1 | X | 0 | 1 | 0 | 0 || 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
+//- | 1 | X | 0 | 1 | 0 | 1 || 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
+//- | 1 | X | 0 | 1 | 1 | 0 || 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | X | 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
+//- | 1 | X | 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 1 | X | 1 | 0 | 0 | 1 || 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
+//- | 1 | X | 1 | 0 | 1 | 0 || 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
+//- | 1 | X | 1 | 0 | 1 | 1 || 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
+//- | 1 | X | 1 | 1 | 0 | 0 || 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
+//- | 1 | X | 1 | 1 | 0 | 1 || 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 |
+//- | 1 | X | 1 | 1 | 1 | 0 || 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
+//- | 1 | X | 1 | 1 | 1 | 1 || 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+//- | X | X | X | X | X | X || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+//- | 1 | 0 | 0 | 0 | 0 | 0 || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
+//- | 0 | X | X | X | X | X || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- +-----+------+----+----+----+----++-----+---+---+---+---+---+---+---+
+//-
+static NETLIST_START(TTL_7448_DIP)
+{
+
+ TTL_7448(A)
+
+ DIPPINS( // +--------------+
+ A.B, A.VCC, // B |1 ++ 16| VCC
+ A.C, A.f, // C |2 15| f
+ A.LTQ, A.g, // LTQ |3 14| g
+ A.BIQ, A.a, // BIQ |4 7448 13| a
+ A.RBIQ, A.b, // RBIQ |5 12| b
+ A.D, A.c, // D |6 11| c
+ A.A, A.d, // A |7 10| d
+ A.GND, A.e // GND |8 9| e
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7450_DIP
+//- Title: DM7450 Expandable Dual 2-Wide 2-Input AND-OR-INVERT Gate
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations: Expander signal is not implemented
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/105/236976_DS.pdf
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 1 |
+//- | 0 | 1 || 1 |
+//- | 1 | 0 || 1 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7450_DIP)
+{
+ TTL_7450_ANDORINVERT(A)
+ TTL_7450_ANDORINVERT(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // 1A |1 ++ 14| VCC
+ B.A, A.B, // 2A |2 13| 1B
+ B.B, NC.I, // 2B |3 12| 1XQ
+ B.C, NC.I, // 2C |4 7450 11| 1X
+ B.D, A.D, // 2D |5 10| 1D
+ B.Q, A.C, // 2Y |6 9| 1C
+ A.GND, A.Q // GND |7 8| 1Y
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7473_DIP
+//- Title: 5473/DM5473/DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
+//- Pinalias: CLK1,CLR1,K1,VCC,CLK2,CLR2,J2,QQ2,Q2,K2,GND,Q1,QQ1,J1
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet_pdf/national-semiconductor/5473DMQB_to_DM7473N.pdf
+//-
+//- +-----+-------+---+---++---+----+
+//- | CLR | CLK | J | K || Q | QQ |
+//- +=====+=======+===+===++===+====+
+//- | 0 | X | X | X || 0 | 1 |
+//- | 1 | 0-1-0 | 0 | 0 || Q | QQ |
+//- | 1 | 0-1-0 | 1 | 0 || 1 | 0 |
+//- | 1 | 0-1-0 | 0 | 1 || 0 | 1 |
+//- | 1 | 0-1-0 | 1 | 1 || Toggle |
+//- +-----+-------+---+---++---+----+
+//-
+static NETLIST_START(TTL_7473_DIP)
+{
+ TTL_7473(A)
+ TTL_7473(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.CLK, A.J, // CLK1 |1 ++ 14| J1
+ A.CLRQ, A.QQ, // CLR1 |2 13| QQ1
+ A.K, A.Q, // K1 |3 12| Q1
+ A.VCC, A.GND, // VCC |4 7473 11| GND
+ B.CLK, B.K, // CLK2 |5 10| K2
+ B.CLRQ, B.Q, // CLR2 |6 9| Q2
+ B.J, B.QQ // J2 |7 8| QQ2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7473A_DIP
+//- Title: DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
+//- Pinalias: CLK1,CLR1,K1,VCC,CLK2,CLR2,J2,QQ2,Q2,K2,GND,Q1,QQ1,J1
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006372.PDF
+//-
+//- +-----+-----+---+---++---+----+
+//- | CLR | CLK | J | K || Q | QQ |
+//- +=====+=====+===+===++===+====+
+//- | 0 | X | X | X || 0 | 1 |
+//- | 1 | 1-0 | 0 | 0 || Q | QQ |
+//- | 1 | 1-0 | 1 | 0 || 1 | 0 |
+//- | 1 | 1-0 | 0 | 1 || 0 | 1 |
+//- | 1 | 1-0 | 1 | 1 || Toggle |
+//- | 1 | 1 | X | X || Q | QQ |
+//- +-----+-----+---+---++---+----+
+//-
+static NETLIST_START(TTL_7473A_DIP)
+{
+ TTL_7473A(A)
+ TTL_7473A(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.CLK, A.J, // CLK1 |1 ++ 14| J1
+ A.CLRQ, A.QQ, // CLR1 |2 13| QQ1
+ A.K, A.Q, // K1 |3 12| Q1
+ A.VCC, A.GND, // VCC |4 7473A 11| GND
+ B.CLK, B.K, // CLK2 |5 10| K2
+ B.CLRQ, B.Q, // CLR2 |6 9| Q2
+ B.J, B.QQ // J2 |7 8| QQ2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7474_DIP
+//- Title: 5474/DM5474/DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
+//- Pinalias: CLR1,D1,CLK1,PR1,Q1,QQ1,GND,QQ2,Q2,PR2,CLK2,D2,CLR2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006526.PDF
+//-
+//- +----+-----+-----+---++---+----+
+//- | PR | CLR | CLK | D || Q | QQ |
+//- +====+=====+=====+===++===+====+
+//- | 0 | 1 | X | X || 1 | 0 |
+//- | 1 | 0 | X | X || 0 | 1 |
+//- | 0 | 0 | X | X || 1 | 1 | (unstable)
+//- | 1 | 1 | 0-1 | 1 || 1 | 0 |
+//- | 1 | 1 | 0-1 | 0 || 0 | 1 |
+//- | 1 | 1 | 0 | X || Q | QQ |
+//- +----+-----+-----+---++---+----+
+//-
+static NETLIST_START(TTL_7474_DIP)
+{
+ TTL_7474(A)
+ TTL_7474(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // CLR1 |1 ++ 14| VCC
+ A.D, B.CLRQ, // D1 |2 13| CLR2
+ A.CLK, B.D, // CLK1 |3 12| D2
+ A.PREQ, B.CLK, // PR1 |4 7474 11| CLK2
+ A.Q, B.PREQ, // Q1 |5 10| PR2
+ A.QQ, B.Q, // QQ1 |6 9| Q2
+ A.GND, B.QQ // GND |7 8| QQ2
+ // +-------------+
+ )
+}
+
+//- Identifier: TTL_7475_DIP
+//- Title: DM5475/DM7475/DM7475A/DM74LS75 4-bit D Latch
+//- Pinalias: QQ1,D1,D2,E34,VCC,D3,D4,QQ4,Q4,Q3,QQ3,GND,E12,QQ2,Q2,Q1
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- https://archive.org/download/bitsavers_nationaldaTTLDatabook_40452765/1976_National_TTL_Databook.pdf
+//-
+//- +---+---++---+----+
+//- | D | G || Q | QQ |
+//- +===+===++===+====+
+//- | 0 | 1 || 0 | 1 |
+//- | 1 | 1 || 1 | 0 |
+//- | X | 0 || Q | QQ |
+//- +---+---++---+----+
+//-
+static NETLIST_START(TTL_7475_DIP)
+{
+ TTL_7475_GATE(A)
+ TTL_7475_GATE(B)
+ TTL_7475_GATE(C)
+ TTL_7475_GATE(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ NET_C(A.CLK, B.CLK)
+ NET_C(C.CLK, D.CLK)
+
+ DIPPINS( // +--------------+
+ A.QQ, A.Q, // QQ1 |1 ++ 16| Q1
+ A.D, B.Q, // D1 |2 15| Q2
+ B.D, B.QQ, // D2 |3 14| QQ2
+ C.CLK, A.CLK, // E34 |4 7475 13| E12
+ A.VCC, A.GND, // VCC |5 12| GND
+ C.D, C.QQ, // D3 |6 11| QQ3
+ D.D, C.Q, // D4 |7 10| Q3
+ D.QQ, D.Q // QQ4 |8 9| Q4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7477_DIP
+//- Title: DM74LS77 4-bit D Latch
+//- Pinalias: D1,D2,E34,VCC,D3,D4,NC,Q4,Q3,NC,GND,E12,Q2,Q1
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- https://archive.org/download/bitsavers_nationaldaTTLDatabook_40452765/1976_National_TTL_Databook.pdf
+//-
+//- +---+---++---+----+
+//- | D | G || Q | QQ |
+//- +===+===++===+====+
+//- | 0 | 1 || 0 | 1 |
+//- | 1 | 1 || 1 | 0 |
+//- | X | 0 || Q | QQ |
+//- +---+---++---+----+
+//-
+static NETLIST_START(TTL_7477_DIP)
+{
+ TTL_7477_GATE(A)
+ TTL_7477_GATE(B)
+ TTL_7477_GATE(C)
+ TTL_7477_GATE(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ NET_C(A.CLK, B.CLK)
+ NET_C(C.CLK, D.CLK)
+
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.D, A.Q, // D1 |1 ++ 14| Q1
+ B.D, B.Q, // D2 |2 13| Q2
+ C.CLK, A.CLK, // E34 |3 12| E12
+ A.VCC, A.GND, // VCC |4 7477 11| GND
+ C.D, NC.I, // D3 |5 10| NC
+ D.D, C.Q, // D4 |6 9| Q3
+ NC.I, D.Q // NC |7 8| Q4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7483_DIP
+//- Title: DM5483/DM7483/DM74LS83A 4-bit Binary Adders With Fast Carry
+//- Pinalias: A4,S3,A3,B3,VCC,S2,B2,A2,S1,A1,B1,GND,C0,C4,S4,B4
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006378.PDF
+//-
+static NETLIST_START(TTL_7483_DIP)
+{
+ TTL_7483(A)
+
+ DIPPINS( // +--------------+
+ A.A4, A.B4, // A4 |1 ++ 16| B4
+ A.S3, A.S4, // S3 |2 15| S4
+ A.A3, A.C4, // A3 |3 14| C4
+ A.B3, A.C0, // B3 |4 7483 13| C0
+ A.VCC, A.GND, // VCC |5 12| GND
+ A.S2, A.B1, // S2 |6 11| B1
+ A.B2, A.A1, // B2 |7 10| A1
+ A.A2, A.S1 // A2 |8 9| S1
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7485_DIP
+//- Title: DM5485/DM7485/DM74L85/DM74LS85 4-Bit Magnitude Comparators
+//- Pinalias: B3,LTIN,EQIN,GTIN,GTOUT,EQOUT,LTOUT,GND,B0,A0,B1,A1,A2,B2,A3,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006379.PDF
+//-
+static NETLIST_START(TTL_7485_DIP)
+{
+ TTL_7485(A)
+
+ DIPPINS( // +--------------+
+ A.B3, A.VCC, // B3 |1 ++ 16| VCC
+ A.LTIN, A.A3, // LTIN |2 15| A3
+ A.EQIN, A.B2, // EQIN |3 14| B2
+ A.GTIN, A.A2, // GTIN |4 7485 13| A2
+ A.GTOUT, A.A1, // GTOUT |5 12| A1
+ A.EQOUT, A.B1, // EQOUT |6 11| B1
+ A.LTOUT, A.A0, // LTOUT |7 10| A0
+ A.GND, A.B0 // GND |8 9| B0
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7486_DIP
+//- Title: 5486/DM5486/DM7486 Quad 2-Input Exclusive-OR Gates
+//- Pinalias: A1,B1,Y1,A2,B2,Y2,GND,Y3,A3,B3,Y4,A4,B4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006531.PDF
+//-
+//- +---+---++---+
+//- | A | B || Y |
+//- +===+===++===+
+//- | 0 | 0 || 0 |
+//- | 0 | 1 || 1 |
+//- | 1 | 0 || 1 |
+//- | 1 | 1 || 0 |
+//- +---+---++---+
+//-
+static NETLIST_START(TTL_7486_DIP)
+{
+ TTL_7486_XOR(A)
+ TTL_7486_XOR(B)
+ TTL_7486_XOR(C)
+ TTL_7486_XOR(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 14| VCC
+ A.B, D.B, // B1 |2 13| B4
+ A.Q, D.A, // Y1 |3 12| A4
+ B.A, D.Q, // A2 |4 7486 11| Y4
+ B.B, C.B, // B2 |5 10| B3
+ B.Q, C.A, // Y2 |6 9| A3
+ A.GND, C.Q // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7490_DIP
+//- Title: DM5490/DM7490A Decade Counter
+//- Pinalias: B,R01,R02,NC,VCC,R91,R92,QC,QB,GND,QD,QA,NC,A
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006533.PDF
+//-
+//- BCD Count Sequence BCD Bi-Quinary
+//- +-------++----+----+----+----+ +-------++----+----+----+----+
+//- | Count || QD | QC | QB | QA | | Count || QD | QC | QB | QA |
+//- +=======++====+====+====+====+ +=======++====+====+====+====+
+//- | 0 || 0 | 0 | 0 | 0 | | 0 || 0 | 0 | 0 | 0 |
+//- | 1 || 0 | 0 | 0 | 1 | | 1 || 0 | 0 | 0 | 1 |
+//- | 2 || 0 | 0 | 1 | 0 | | 2 || 0 | 0 | 1 | 0 |
+//- | 3 || 0 | 0 | 1 | 1 | | 3 || 0 | 0 | 1 | 1 |
+//- | 4 || 0 | 1 | 0 | 0 | | 4 || 0 | 1 | 0 | 0 |
+//- | 5 || 0 | 1 | 0 | 1 | | 5 || 1 | 0 | 0 | 0 |
+//- | 6 || 0 | 1 | 1 | 0 | | 6 || 1 | 0 | 0 | 1 |
+//- | 7 || 0 | 1 | 1 | 1 | | 7 || 1 | 0 | 1 | 0 |
+//- | 8 || 1 | 0 | 0 | 0 | | 8 || 1 | 0 | 1 | 1 |
+//- | 9 || 1 | 0 | 0 | 1 | | 9 || 1 | 1 | 0 | 0 |
+//- +-------++----+----+----+----+ +-------++----+----+----+----+
+//-
+//- Reset/Count Function Table
+//- +-----+-----+-----+-----++----+----+----+----+
+//- | R01 | R02 | R91 | R92 || QD | QC | QB | QA |
+//- +=====+=====+=====+=====++====+====+====+====+
+//- | 1 | 1 | 0 | X || 0 | 0 | 0 | 0 |
+//- | 1 | 1 | X | 0 || 0 | 0 | 0 | 0 |
+//- | X | X | 1 | 1 || 1 | 0 | 0 | 1 |
+//- | X | 0 | X | 0 || COUNT |
+//- | 0 | X | 0 | X || COUNT |
+//- | 0 | X | X | 0 || COUNT |
+//- | X | 0 | 0 | X || COUNT |
+//- +-----+-----+-----+-----++----+----+----+----+
+//-
+static NETLIST_START(TTL_7490_DIP)
+{
+ TTL_7490(A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.B, A.A, // B |1 ++ 14| A
+ A.R1, NC.I, // R01 |2 13| NC
+ A.R2, A.QA, // R02 |3 12| QA
+ NC.I, A.QD, // NC |4 7490 11| QD
+ A.VCC, A.GND, // VCC |5 10| GND
+ A.R91, A.QB, // R91 |6 9| QB
+ A.R92, A.QC // R92 |7 8| QC
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7492_DIP
+//- Title: SN5492A, SN54LS92, SN7492A, SN74LS92 Divide-By-Twelve Counter
+//- Pinalias: CKB,NC,NC,NC,VCC,R01,R02,QD,QC,GND,QB,QA,NC,CLKA
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/27430/TI/SN7492A.html
+//-
+//- Count Sequence
+//- +-------++----+----+----+----+
+//- | Count || QD | QC | QB | QA |
+//- +=======++====+====+====+====+
+//- | 0 || 0 | 0 | 0 | 0 |
+//- | 1 || 0 | 0 | 0 | 1 |
+//- | 2 || 0 | 0 | 1 | 0 |
+//- | 3 || 0 | 0 | 1 | 1 |
+//- | 4 || 0 | 1 | 0 | 0 |
+//- | 5 || 0 | 1 | 0 | 1 |
+//- | 6 || 1 | 0 | 0 | 0 |
+//- | 7 || 1 | 0 | 0 | 1 |
+//- | 8 || 1 | 0 | 1 | 0 |
+//- | 9 || 1 | 0 | 1 | 1 |
+//- | 10 || 1 | 1 | 0 | 0 |
+//- | 11 || 1 | 1 | 0 | 1 |
+//- +-------++----+----+----+----+
+//-
+//- Reset/Count Function Table
+//- +-----+-----++----+----+----+----+
+//- | R01 | R02 || QD | QC | QB | QA |
+//- +=====+=====++====+====+====+====+
+//- | 1 | 1 || 0 | 0 | 0 | 0 |
+//- | 0 | X || COUNT |
+//- | X | 0 || COUNT |
+//- +-----+-----++----+----+----+----+
+//-
+static NETLIST_START(TTL_7492_DIP)
+{
+ TTL_7492(A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.B, A.A, // CLKB |1 ++ 14| CLKA
+ NC.I, NC.I, // NC |2 13| NC
+ NC.I, A.QA, // NC |3 12| QA
+ NC.I, A.QD, // NC |4 7492 11| QD
+ A.VCC, A.GND, // VCC |5 10| GND
+ A.R1, A.QB, // R01 |6 9| QB
+ A.R2, A.QC // R02 |7 8| QC
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7493_DIP
+//- Title: 7493 Binary Counters
+//- Pinalias: B,R01,R02,NC,VCC,NC,NC,QC,QB,GND,QD,QA,NC,A
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- Limitations: Internal resistor network currently fixed to 5k
+//- more limitations
+//- Example: ne555_astable.c,ne555_example
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006533.PDF
+//-
+//- Counter Sequence
+//-
+//- | COUNT || QD | QC | QB | QA |
+//- |------:||:--:|:--:|:--:|:--:|
+//- | 0 || 0 | 0 | 0 | 0 |
+//- | 1 || 0 | 0 | 0 | 1 |
+//- | 2 || 0 | 0 | 1 | 0 |
+//- | 3 || 0 | 0 | 1 | 1 |
+//- | 4 || 0 | 1 | 0 | 0 |
+//- | 5 || 0 | 1 | 0 | 1 |
+//- | 6 || 0 | 1 | 1 | 0 |
+//- | 7 || 0 | 1 | 1 | 1 |
+//- | 8 || 1 | 0 | 0 | 0 |
+//- | 9 || 1 | 0 | 0 | 1 |
+//- | 10 || 1 | 0 | 1 | 0 |
+//- | 11 || 1 | 0 | 1 | 1 |
+//- | 12 || 1 | 1 | 0 | 0 |
+//- | 13 || 1 | 1 | 0 | 1 |
+//- | 14 || 1 | 1 | 1 | 0 |
+//- | 15 || 1 | 1 | 1 | 1 |
+//-
+//- Note C Output QA is connected to input B
+//-
+//- Reset Count Function table
+//-
+//- | R01 | R02 | QD | QC | QB | QA |
+//- |:---:|:---:|:--:|:--:|:--:|:--:|
+//- | 1 | 1 | 0 | 0 | 0 | 0 |
+//- | 0 | X | COUNT ||||
+//- | X | 0 | COUNT ||||
+//-
+//-
+
+static NETLIST_START(TTL_7493_DIP)
+{
+ TTL_7493(A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.CLKB, A.CLKA, // CLKB |1 ++ 14| CLKA
+ A.R1, NC.I, // R01 |2 13| NC
+ A.R2, A.QA, // R02 |3 12| QA
+ NC.I, A.QD, // NC |4 7493 11| QD
+ A.VCC, A.GND, // VCC |5 10| GND
+ NC.I, A.QB, // NC |6 9| QB
+ NC.I, A.QC // NC |7 8| QC
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_7497_DIP
+//- Title: 5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier
+//- Pinalias: S1,S4,S5,S0,ZQ,Y,TCQ,GND,CP,EZQ,CEQ,EY,MR,S2,S3,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009780.PDF
+//-
+static NETLIST_START(TTL_7497_DIP)
+{
+ TTL_7497(A)
+
+ DIPPINS( // +--------------+
+ A.B1, A.VCC, // S1 |1 ++ 16| VCC
+ A.B4, A.B3, // S4 |2 15| S3
+ A.B5, A.B2, // S5 |3 14| S2
+ A.B0, A.CLR, // S0 |4 7497 13| MR
+ A.ZQ, A.UNITYQ, // ZQ |5 12| EY
+ A.Y, A.ENQ, // Y |6 11| CEQ
+ A.ENOUTQ, A.STRBQ, // TCQ |7 10| EZQ
+ A.GND, A.CLK // GND |8 9| CP
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74107_DIP
+//- Title: SN54107, SN74107 Dual J-K Flip-Flops With Clear
+//- Pinalias: 1J,1QQ,1Q,1K,2Q,2QQ,GND,2J,2CLK,2CLRQ,2K,1CLK,1CLRQ,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/840452/TI1/SN74107.html
+//-
+//- +------+-------+---+---++---+----+
+//- | CLRQ | CLK | J | K || Q | QQ |
+//- +======+=======+===+===++===+====+
+//- | 0 | X | X | X || 0 | 1 |
+//- | 1 | 0-1-0 | 0 | 0 || Q | QQ |
+//- | 1 | 0-1-0 | 1 | 0 || 1 | 0 |
+//- | 1 | 0-1-0 | 0 | 1 || 0 | 1 |
+//- | 1 | 0-1-0 | 1 | 1 || TOGGLE |
+//- +------+-------+---+---++---+----+
+//-
+static NETLIST_START(TTL_74107_DIP)
+{
+ TTL_74107(A)
+ TTL_74107(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.J, A.VCC, // 1J |1 ++ 14| VCC
+ A.QQ, A.CLRQ, // 1QQ |2 13| 1CLRQ
+ A.Q, A.CLK, // 1Q |3 12| 1CLK
+ A.K, B.K, // 1K |4 74107 11| 2K
+ B.Q, B.CLRQ, // 2Q |5 10| 2CLRQ
+ B.QQ, B.CLK, // 2QQ |6 9| 2CLK
+ B.GND, B.J // GND |7 8| 2J
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74107A_DIP
+//- Title: DM54LS107A/DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops withClear and Complementary Outputs
+//- Pinalias: J1,QQ1,Q1,K1,Q2,QQ2,GND,J2,CLK2,CLRQ2,K2,CLK1,CLRQ1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006367.PDF
+//-
+//- +------+-----+---+---++---+----+
+//- | CLRQ | CLK | J | K || Q | QQ |
+//- +======+=====+===+===++===+====+
+//- | 0 | X | X | X || 0 | 1 |
+//- | 1 | 1-0 | 0 | 0 || Q | QQ |
+//- | 1 | 1-0 | 1 | 0 || 1 | 0 |
+//- | 1 | 1-0 | 0 | 1 || 0 | 1 |
+//- | 1 | 1-0 | 1 | 1 || TOGGLE |
+//- | 1 | 1 | X | X || Q | QQ |
+//- +------+-----+---+---++---+----+
+//-
+static NETLIST_START(TTL_74107A_DIP)
+{
+ TTL_74107A(A)
+ TTL_74107A(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.J, A.VCC, // J1 |1 ++ 14| VCC
+ A.QQ, A.CLRQ, // QQ1 |2 13| CLRQ1
+ A.Q, A.CLK, // Q1 |3 12| CLK1
+ A.K, B.K, // K1 |4 74107A 11| K2
+ B.Q, B.CLRQ, // Q2 |5 10| CLRQ2
+ B.QQ, B.CLK, // QQ2 |6 9| CLK2
+ B.GND, B.J // GND |7 8| J2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74113_DIP
+//- Title: DM54S113/DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs
+//- Pinalias: CLK1,K1,J1,PRQ1,Q1,QQ1,GND,QQ2,Q2,PRQ2,J2,K2,CLK2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006460.PDF
+//-
+//- +-----+-----+---+---++---+----+
+//- | PRQ | CLK | J | K || Q | QQ |
+//- +=====+=====+===+===++===+====+
+//- | 0 | X | X | X || 1 | 0 |
+//- | 1 | 1-0 | 0 | 0 || Q | QQ |
+//- | 1 | 1-0 | 1 | 0 || 1 | 0 |
+//- | 1 | 1-0 | 0 | 1 || 0 | 1 |
+//- | 1 | 1-0 | 1 | 1 || TOGGLE |
+//- | 1 | 1 | X | X || Q | QQ |
+//- +-----+-----+---+---++---+----+
+//-
+static NETLIST_START(TTL_74113_DIP)
+{
+ TTL_74113(A)
+ TTL_74113(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.CLK, A.VCC, // CLK1 |1 ++ 14| VCC
+ A.K, B.CLK, // K1 |2 13| CLK2
+ A.J, B.K, // J1 |3 12| K2
+ A.SETQ, B.J, // PRQ1 |4 74113 11| J2
+ A.Q, B.SETQ, // Q1 |5 10| PRQ2
+ A.QQ, B.Q, // QQ1 |6 9| Q2
+ A.GND, B.QQ // GND |7 8| QQ2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74113A_DIP
+//- Title: DM54S113/DM74S113 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs
+//- Pinalias: CLK1,K1,J1,PRQ1,Q1,QQ1,GND,QQ2,Q2,PRQ2,J2,K2,CLK2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/131122/TI/SN74LS113A.html
+//-
+//- +------+-----+---+---++---+----+
+//- | PREQ | CLK | J | K || Q | QQ |
+//- +======+=====+===+===++===+====+
+//- | 0 | X | X | X || 1 | 0 |
+//- | 1 | 1-0 | 0 | 0 || Q | QQ |
+//- | 1 | 1-0 | 1 | 0 || 1 | 0 |
+//- | 1 | 1-0 | 0 | 1 || 0 | 1 |
+//- | 1 | 1-0 | 1 | 1 || TOGGLE |
+//- | 1 | 1 | X | X || Q | QQ |
+//- +------+-----+---+---++---+----+
+//-
+static NETLIST_START(TTL_74113A_DIP)
+{
+ TTL_74113A(A)
+ TTL_74113A(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.CLK, A.VCC, // CLK1 |1 ++ 14| VCC
+ A.K, B.CLK, // K1 |2 13| CLK2
+ A.J, B.K, // J1 |3 12| K2
+ A.SETQ, B.J, // PRQ1 |4 74113A 11| J2
+ A.Q, B.SETQ, // Q1 |5 10| PRQ2
+ A.QQ, B.Q, // QQ1 |6 9| Q2
+ A.GND, B.QQ // GND |7 8| QQ2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74121_DIP
+//- Title: DM74121 One-Shot with Clear and Complementary Outputs
+//- Pinalias: QQ,NC,A1,A2,B,Q,GND,NC,RINT,C,RC,NC,NC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50894/FAIRCHILD/74121.html
+//-
+static NETLIST_START(TTL_74121_DIP)
+{
+ TTL_74121(A)
+ NC_PIN(NC)
+ RES(RINT, RES_K(2))
+ RES(RD, RES_M(1000))
+
+ NET_C(RINT.2, A.RC)
+ // Avoid error messages if RINT is not used.
+ NET_C(RINT.1, RD.2)
+ NET_C(RD.1, A.GND)
+
+ DIPPINS( // +--------------+
+ A.QQ, A.VCC, // QQ |1 ++ 14| VCC
+ NC.I, NC.I, // NC |2 13| NC
+ A.A1, NC.I, // A1 |3 12| NC
+ A.A2, A.RC, // A2 |4 74121 11| REXT/CEXT
+ A.B, A.C, // B |5 10| CEXT
+ A.Q, RINT.1, // Q |6 9| RINT
+ A.GND, NC.I // GND |7 8| NC
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74123_DIP
+//- Title: DM74123 Dual Retriggerable One-Shot with Clear and Complementary Outputs
+//- Pinalias: A1,B1,CLRQ1,QQ1,Q2,C2,RC2,GND,A2,B2,CLRQ2,QQ2,Q1,C1,RC1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/50893/FAIRCHILD/DM74123.html
+//-
+static NETLIST_START(TTL_74123_DIP)
+{
+ TTL_74123(A)
+ TTL_74123(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A1 |1 ++ 16| VCC
+ A.B, A.RC, // B1 |2 15| RC1
+ A.CLRQ, A.C, // CLRQ1 |3 14| C1
+ A.QQ, A.Q, // QQ1 |4 74123 13| Q1
+ B.Q, B.QQ, // Q2 |5 12| QQ2
+ B.C, B.CLRQ, // C2 |6 11| CLRQ
+ B.RC, B.B, // RC2 |7 10| B2
+ A.GND, B.A // GND |8 9| A2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74125_DIP
+//- Title: SN74125 QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
+//- Pinalias: 1GQ,1A,1Y,2GQ,2A,2Y,GND,3Y,3A,3GQ,4Y,4A,4GQ,VCC
+//- Package: DIP
+//- Param: FORCE_TRISTATE_LOGIC
+//- Set this parameter to 1 force tristate outputs into logic mode.
+//- This should be done only if the device enable inputs are connected
+//- in a way which always enables the device.
+//- NamingConvention: Naming conventions follow Texas instruments datasheet
+//- Limitations:
+//- No limitations
+//-
+//- Example: 74125.cpp,74125_example
+//-
+//- FunctionTable:
+//-
+//- | GQ | A | Y |
+//- |:---:|:--:|:--:|
+//- | L | L | L |
+//- | L | H | H |
+//- | H | X | Z |
+//-
+static NETLIST_START(TTL_74125_DIP)
+{
+ TTL_74125_GATE(A)
+ TTL_74125_GATE(B)
+ TTL_74125_GATE(C)
+ TTL_74125_GATE(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DEFPARAM(FORCE_TRISTATE_LOGIC, "$(@.A.FORCE_TRISTATE_LOGIC")
+ PARAM(A.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(B.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(C.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(D.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+
+ DIPPINS( // +--------------+
+ A.GQ, A.VCC, // 1GQ |1 ++ 14| VCC
+ A.A, D.GQ, // 1A |2 13| 4GQ
+ A.Y, D.A, // 1Y |3 12| 4A
+ B.GQ, D.Y, // 2GQ |4 74125 11| 4Y
+ B.A, C.GQ, // 2A |5 10| 3GQ
+ B.Y, C.A, // 2Y |6 9| 3A
+ A.GND, C.Y // GND |7 8| 3Y
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74126_DIP
+//- Title: DM74LS126A Quad 3-STATE Buffer
+//- Pinalias: C1,A1,Y1,C2,A2,Y2,GND,Y3,A3,C3,Y4,A4,C4,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/50/232293_DS.pdf
+//-
+//- +---+---++------+
+//- | A | C || Y |
+//- +===+===++======+
+//- | 0 | 1 || 0 |
+//- | 1 | 1 || 1 |
+//- | X | 0 || Hi-Z |
+//- +---+---++------+
+//-
+static NETLIST_START(TTL_74126_DIP)
+{
+ TTL_74126_GATE(A)
+ TTL_74126_GATE(B)
+ TTL_74126_GATE(C)
+ TTL_74126_GATE(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DEFPARAM(FORCE_TRISTATE_LOGIC, 0)
+ PARAM(A.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(B.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(C.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+ PARAM(D.FORCE_TRISTATE_LOGIC, "$(@.FORCE_TRISTATE_LOGIC)")
+
+ DIPPINS( // +--------------+
+ A.G, A.VCC, // C1 |1 ++ 14| VCC
+ A.A, D.G, // A1 |2 13| C4
+ A.Y, D.A, // Y1 |3 12| A4
+ B.G, D.Y, // C2 |4 74126 11| Y4
+ B.A, C.G, // A2 |5 10| C3
+ B.Y, C.A, // Y2 |6 9| A3
+ A.GND, C.Y // GND |7 8| Y3
+ // +--------------+
+ )
+}
+
+// FIXME: Pinalias completely wrong.
+
+//- Identifier: TTL_74139_DIP
+//- Title: 54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers
+//- Pinalias: G1,A1,B1,1Y0,1Y1,1Y2,1Y3,GND,2Y3,2Y2,2Y1,2Y0,B2,A2,G2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/166/375388_DS.pdf
+//-
+//- +---+-------+-------------+
+//- | E | A0 A1 | O0 O1 O2 O3 |
+//- +===+=======+=============+
+//- | 1 | X X | 1 1 1 1 |
+//- | 0 | 0 0 | 0 1 1 1 |
+//- | 0 | 1 0 | 1 0 1 1 |
+//- | 0 | 0 1 | 1 1 0 1 |
+//- | 0 | 1 1 | 1 1 1 0 |
+//- +---+-------+-------------+
+//-
+static NETLIST_START(TTL_74139_DIP)
+{
+ NET_REGISTER_DEV(TTL_74139_GATE, A)
+ NET_REGISTER_DEV(TTL_74139_GATE, B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.E, A.VCC, // /Ea |1 ++ 16| VCC
+ A.A, B.E, // A0a |2 15| /Eb
+ A.B, B.A, // A1a |3 14| A0b
+ A.O0, B.B, // /O0a |4 74139 13| A1b
+ A.O1, B.O0, // /O1a |5 12| /O0b
+ A.O2, B.O1, // /O2a |6 11| /O1b
+ A.O3, B.O2, // /O3a |7 10| /O2b
+ A.GND, B.O3 // GND |8 9| /O3b
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74147_DIP
+//- Title: SN74147 10-Line to 4-Line priority encoder
+//- Pinalias: 4,5,6,7,8,C,B,GND,A,9,1,2,3,D,NC,Vcc
+//- Package: DIP-16
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://www.ti.com/lit/ds/symlink/sn74ls148.pdf
+//-
+//- 10-line to 4 line encoder
+//- +-----+-----+-----+-----+-----+-----+-----+-----+-----+---+---+---+---+
+//- | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | D | C | B | A |
+//- +=====+=====+=====+=====+=====+=====+=====+=====+=====+===+===+===+===+
+//- | H | H | H | H | H | H | H | H | H | H | H | H | H |
+//- | X | X | X | X | X | X | X | X | L | L | H | H | L |
+//- | X | X | X | X | X | X | X | L | H | L | H | H | H |
+//- | X | X | X | X | X | X | L | H | H | H | L | L | L |
+//- | X | X | X | X | X | L | H | H | H | H | L | L | H |
+//- | X | X | X | X | L | H | H | H | H | H | L | H | L |
+//- | X | X | X | L | H | H | H | H | H | H | L | H | H |
+//- | X | X | L | H | H | H | H | H | H | H | H | L | L |
+//- | X | L | H | H | H | H | H | H | H | H | H | L | H |
+//- | L | H | H | H | H | H | H | H | H | H | H | H | L |
+//- +-----+-----+-----+-----+-----+-----+-----+-----+-----+---+---+---+---+
+static NETLIST_START(TTL_74147_DIP)
+{
+ NET_REGISTER_DEV(TTL_74147_GATE, A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.I4, A.VCC, // 4 |1 ++ 16| VCC
+ A.I5, NC.I, // 5 |2 15| NC
+ A.I6, A.D, // 6 |3 14| D
+ A.I7, A.I3, // 7 |4 74147 13| 3
+ A.I8, A.I2, // 8 |5 12| 2
+ A.C, A.I1, // C |6 11| 1
+ A.B, A.I9, // B |7 10| 9
+ A.GND, A.A // GND |8 9| A
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74148_DIP
+//- Title: SN74148 8-line to 3-line priority encoders
+//- Pinalias: 4,5,6,7,EI,A2,A1,GND,A0,0,1,2,3,GS,E0,Vcc
+//- Package: DIP-16
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://www.ti.com/lit/ds/symlink/sn74ls148.pdf
+//-
+//- 10-line to 4 line encoder
+//- +-----+-----+-----+-----+-----+-----+-----+-----+-----+----+----+----+----+----+
+//- | EI | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | A2 | A1 | A0 | GS | E0 |
+//- +=====+=====+=====+=====+=====+=====+=====+=====+=====+====+====+====+====+====+
+//- | H | X | X | X | X | X | X | X | X | H | H | H | H | H |
+//- | L | H | X | H | H | H | H | H | H | H | H | H | H | L |
+//- | L | X | X | X | X | X | X | X | L | L | L | L | L | H |
+//- | L | X | X | X | X | X | X | L | H | L | L | H | L | H |
+//- | L | X | X | X | X | X | L | H | H | L | H | L | L | H |
+//- | L | X | X | X | X | L | H | H | H | L | H | H | L | H |
+//- | L | X | X | X | L | H | H | H | H | H | L | L | L | H |
+//- | L | X | X | L | H | H | H | H | H | H | L | H | L | H |
+//- | L | X | L | H | H | H | H | H | H | H | H | L | L | H |
+//- | L | L | H | H | H | H | H | H | H | H | H | H | L | H |
+//- +-----+-----+-----+-----+-----+-----+-----+-----+-----+----+----+----+----+----+
+static NETLIST_START(TTL_74148_DIP)
+{
+ NET_REGISTER_DEV(TTL_74148_GATE, A)
+
+ DIPPINS( // +--------------+
+ A.I4, A.VCC, // 4 |1 ++ 16| VCC
+ A.I5, A.E0, // 5 |2 15| E0
+ A.I6, A.GS, // 6 |3 14| GS
+ A.I7, A.I3, // 7 |4 74148 13| 3
+ A.EI, A.I2, // EI |5 12| 2
+ A.A2, A.I1, // A2 |6 11| 1
+ A.A1, A.I0, // A1 |7 10| 0
+ A.GND, A.A0 // GND |8 9| A0
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74151_DIP
+//- Title: SN74151 Data selector/multiplexer
+//- Pinalias: D3,D2,D1,D0,Y,W,G,Gnd,C,B,A,D7,D6,D5,D4,Vcc
+//- Package: DIP-16
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://www.ti.com/lit/ds/symlink/sn74ls151.pdf
+//-
+//- +---+---+----+--++----+-----+
+//- | C | B | A | G || Y | W |
+//- +===+===+===+===++====+=====+
+//- | X | X | X | H || L | H |
+//- | L | L | L | L || D0 | ~D0 |
+//- | L | L | H | L || D1 | ~D1 |
+//- | L | H | L | L || D2 | ~D2 |
+//- | L | H | H | L || D3 | ~D3 |
+//- | H | L | L | L || D4 | ~D4 |
+//- | H | L | H | L || D5 | ~D5 |
+//- | H | H | L | L || D6 | ~D6 |
+//- | H | H | H | L || D7 | ~D7 |
+//- +---+---+---+---++----+-----+
+//-
+static NETLIST_START(TTL_74151_DIP)
+{
+ NET_REGISTER_DEV(TTL_74151_GATE, A)
+
+ DIPPINS( // +--------------+
+ A.D3, A.VCC, // D3 |1 ++ 16| VCC
+ A.D2, A.D4, // D2 |2 15| D4
+ A.D1, A.D5, // D1 |3 14| D5
+ A.D0, A.D6, // D0 |4 74151 13| D6
+ A.Y, A.D7, // Y |5 12| D7
+ A.W, A.A, // W |6 11| A
+ A.G, A.B, // G |7 10| B
+ A.GND, A.C // GND |8 9| C
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74153_DIP
+//- Title: 54153/DM54153/DM74153 Dual 4-Line to 1-LineData Selectors/Multiplexers
+//- Pinalias: G1,B,1C3,1C2,1C1,1C0,Y1,GND,Y2,2C0,2C1,2C2,2C3,A,G2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006547.PDF
+//-
+//- +---+---+----+----+----+----+---++---+
+//- | B | A | C0 | C1 | C2 | C3 | G || Y |
+//- +===+===+====+====+====+====+===++===+
+//- | X | X | X | X | X | X | 1 || 0 |
+//- | 0 | 0 | 0 | X | X | X | 0 || 0 |
+//- | 0 | 0 | 1 | X | X | X | 0 || 1 |
+//- | 0 | 1 | X | 0 | X | X | 0 || 0 |
+//- | 0 | 1 | X | 1 | X | X | 0 || 1 |
+//- | 1 | 0 | X | X | 0 | X | 0 || 0 |
+//- | 1 | 0 | X | X | 1 | X | 0 || 1 |
+//- | 1 | 1 | X | X | X | 0 | 0 || 0 |
+//- | 1 | 1 | X | X | X | 1 | 0 || 1 |
+//- +---+---+----+----+----+----+---++---+
+//-
+static NETLIST_START(TTL_74153_DIP)
+{
+ NET_REGISTER_DEV(TTL_74153, A)
+ NET_REGISTER_DEV(TTL_74153, B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ NET_C(A.A, B.A)
+ NET_C(A.B, B.B)
+
+ DIPPINS( // +--------------+
+ A.G, A.VCC, // G1 |1 ++ 16| VCC
+ A.B, B.G, // B |2 15| G2
+ A.C3, A.A, // 1C3 |3 14| A
+ A.C2, B.C3, // 1C2 |4 74153 13| 2C3
+ A.C1, B.C2, // 1C1 |5 12| 2C2
+ A.C0, B.C1, // 1C0 |6 11| 2C1
+ A.AY, B.C0, // Y1 |7 10| 2C0
+ A.GND, B.AY // GND |8 9| Y2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74155_DIP
+//- Title: 54LS155/DM54LS155/DM74LS155 Dual 2-Line to 4-Line Decoders/Demultiplexers
+//- Pinalias: C1,G1,B,1Y3,1Y2,1Y1,1Y0,GND,2Y0,2Y1,2Y2,2Y3,A,G2,C2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006395.PDF
+//-
+//- 2-line-to-4-line decoder 2-line-to-4-line decoder
+//- +---+---+----+----++-----+-----+-----+-----+ +---+---+----+----++-----+-----+-----+-----+
+//- | B | A | G1 | C1 || 1Y0 | 1Y1 | 1Y2 | 1Y3 | | B | A | G2 | C2 || 2Y0 | 2Y1 | 2Y2 | 2Y3 |
+//- +===+===+====+====++=====+=====+=====+=====+ +===+===+====+====++=====+=====+=====+=====+
+//- | X | X | 1 | X || 1 | 1 | 1 | 1 | | X | X | 1 | X || 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 0 | 1 || 0 | 1 | 1 | 1 | | 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 |
+//- | 0 | 1 | 0 | 1 || 1 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 || 1 | 0 | 1 | 1 |
+//- | 1 | 0 | 0 | 1 || 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 || 1 | 1 | 0 | 1 |
+//- | 1 | 1 | 0 | 1 || 1 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 || 1 | 1 | 1 | 0 |
+//- | X | X | X | 0 || 1 | 1 | 1 | 1 | | X | X | X | 1 || 1 | 1 | 1 | 1 |
+//- +---+---+----+----++-----+-----+-----+-----+ +---+---+----+----++-----+-----+-----+-----+
+//-
+//- 3-line-to-8-line decoder
+//- +---+---+---+---++-----+-----+-----+-----+-----+-----+-----+-----+
+//- | C | B | A | G || 2Y0 | 2Y1 | 2Y2 | 2Y3 | 1Y0 | 1Y1 | 1Y2 | 1Y3 |
+//- +===+===+===+===++=====+=====+=====+=====+=====+=====+=====+=====+
+//- | X | X | X | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 1 | 0 || 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 0 | 0 || 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 1 | 0 || 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
+//- | 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
+//- | 1 | 0 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
+//- | 1 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+//- | 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
+//- +---+---+---+---++-----+-----+-----+-----+-----+-----+-----+-----+
+//-
+static NETLIST_START(TTL_74155_DIP)
+{
+ NET_REGISTER_DEV(TTL_74155A_GATE, A)
+ NET_REGISTER_DEV(TTL_74155B_GATE, B)
+
+ NET_C(A.A, B.A)
+ NET_C(A.B, B.B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.C, A.VCC, // C1 |1 ++ 16| VCC
+ A.G, B.C, // G1 |2 15| C2
+ A.B, B.G, // B |3 14| G2
+ A.Y3, B.A, // 1Y3 |4 74155 13| A
+ B.Y2, B.Y3, // 1Y2 |5 12| 2Y3
+ B.Y1, B.Y2, // 1Y1 |6 11| 2Y2
+ B.Y0, B.Y1, // 1Y0 |7 10| 2Y1
+ A.GND, B.Y0 // GND |8 9| 2Y0
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74156_DIP
+//- Title: 54LS156/DM54LS156/DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers with Open-Collector Outputs
+//- Pinalias: C1,G1,B,1Y3,1Y2,1Y1,1Y0,GND,2Y0,2Y1,2Y2,2Y3,A,G2,C2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006395.PDF
+//-
+//- 2-line-to-4-line decoder 2-line-to-4-line decoder
+//- +---+---+----+----++-----+-----+-----+-----+ +---+---+----+----++-----+-----+-----+-----+
+//- | B | A | G1 | C1 || 1Y0 | 1Y1 | 1Y2 | 1Y3 | | B | A | G2 | C2 || 2Y0 | 2Y1 | 2Y2 | 2Y3 |
+//- +===+===+====+====++=====+=====+=====+=====+ +===+===+====+====++=====+=====+=====+=====+
+//- | X | X | 1 | X || 1 | 1 | 1 | 1 | | X | X | 1 | X || 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 0 | 1 || 0 | 1 | 1 | 1 | | 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 |
+//- | 0 | 1 | 0 | 1 || 1 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 || 1 | 0 | 1 | 1 |
+//- | 1 | 0 | 0 | 1 || 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 || 1 | 1 | 0 | 1 |
+//- | 1 | 1 | 0 | 1 || 1 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 || 1 | 1 | 1 | 0 |
+//- | X | X | X | 0 || 1 | 1 | 1 | 1 | | X | X | X | 1 || 1 | 1 | 1 | 1 |
+//- +---+---+----+----++-----+-----+-----+-----+ +---+---+----+----++-----+-----+-----+-----+
+//-
+//- 3-line-to-8-line decoder
+//- +---+---+---+---++-----+-----+-----+-----+-----+-----+-----+-----+
+//- | C | B | A | G || 2Y0 | 2Y1 | 2Y2 | 2Y3 | 1Y0 | 1Y1 | 1Y2 | 1Y3 |
+//- +===+===+===+===++=====+=====+=====+=====+=====+=====+=====+=====+
+//- | X | X | X | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 0 | 1 | 0 || 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 0 | 0 || 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
+//- | 0 | 1 | 1 | 0 || 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
+//- | 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
+//- | 1 | 0 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
+//- | 1 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
+//- | 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
+//- +---+---+---+---++-----+-----+-----+-----+-----+-----+-----+-----+
+//-
+static NETLIST_START(TTL_74156_DIP)
+{
+ NET_REGISTER_DEV(TTL_74156A_GATE, A)
+ NET_REGISTER_DEV(TTL_74156B_GATE, B)
+
+ NET_C(A.A, B.A)
+ NET_C(A.B, B.B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.C, A.VCC, // C1 |1 ++ 16| VCC
+ A.G, B.C, // G1 |2 15| C2
+ A.B, B.G, // B |3 14| G2
+ A.Y3, B.A, // 1Y3 |4 74156 13| A
+ B.Y2, B.Y3, // 1Y2 |5 12| 2Y3
+ B.Y1, B.Y2, // 1Y1 |6 11| 2Y2
+ B.Y0, B.Y1, // 1Y0 |7 10| 2Y1
+ A.GND, B.Y0 // GND |8 9| 2Y0
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74157_DIP
+//- Title: 54157/DM54157/DM74157 Quad 2-Line to 1-Line Data Selectors/Multiplexers
+//- Pinalias: S,A1,B1,Y1,A2,B2,Y2,GND,Y3,B3,A3,Y4,B4,A4,G,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/120/236599_DS.pdf
+//-
+//- +---+---+---+---++---+
+//- | G | S | A | B || Y |
+//- +===+===+===+===++===+
+//- | 1 | X | X | X || 0 |
+//- | 0 | 0 | 0 | X || 0 |
+//- | 0 | 0 | 1 | X || 1 |
+//- | 0 | 1 | X | 0 || 0 |
+//- | 0 | 1 | X | 1 || 1 |
+//- +---+---+---+---++---+
+//-
+static NETLIST_START(TTL_74157_DIP)
+{
+ NET_REGISTER_DEV(TTL_74157_GATE, A)
+ NET_REGISTER_DEV(TTL_74157_GATE, B)
+ NET_REGISTER_DEV(TTL_74157_GATE, C)
+ NET_REGISTER_DEV(TTL_74157_GATE, D)
+
+ NET_C(A.E, B.E, C.E, D.E)
+ NET_C(A.S, B.S, C.S, D.S)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.S, A.VCC, // S |1 ++ 16| VCC
+ A.I, A.E, // A1 |2 15| G
+ A.J, D.I, // B1 |3 14| A4
+ A.O, D.J, // Y1 |4 74157 13| B4
+ B.I, D.O, // A2 |5 12| Y4
+ B.J, C.I, // B2 |6 11| A3
+ B.O, C.J, // Y2 |7 10| B3
+ A.GND, C.O // GND |8 9| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74161_DIP
+//- Title: DM54161/DM74161 Synchronous 4-Bit Counter
+//- Pinalias: CLRQ,CLK,A,B,C,D,ENP,GND,LOADQ,ENT,QD,QC,QB,QA,RC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006551.PDF
+//-
+static NETLIST_START(TTL_74161_DIP)
+{
+ TTL_74161(A)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // /CLEAR |1 ++ 16| VCC
+ A.CLK, A.RC, // CLOCK |2 15| RC
+ A.A, A.QA, // A |3 14| QA
+ A.B, A.QB, // B |4 74161 13| QB
+ A.C, A.QC, // C |5 12| QC
+ A.D, A.QD, // D |6 11| QD
+ A.ENP, A.ENT, // Enable P |7 10| Enable T
+ A.GND, A.LOADQ // GND |8 9| /LOAD
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74163_DIP
+//- Title: DM74163 Synchronous 4-Bit Counter
+//- Pinalias: CLRQ,CLK,A,B,C,D,ENP,GND,LOADQ,ENT,QD,QC,QB,QA,RC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006551.PDF
+//-
+static NETLIST_START(TTL_74163_DIP)
+{
+ TTL_74163(A)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // /CLEAR |1 ++ 16| VCC
+ A.CLK, A.RC, // CLOCK |2 15| RC
+ A.A, A.QA, // A |3 14| QA
+ A.B, A.QB, // B |4 74163 13| QB
+ A.C, A.QC, // C |5 12| QC
+ A.D, A.QD, // D |6 11| QD
+ A.ENP, A.ENT, // Enable P |7 10| Enable T
+ A.GND, A.LOADQ // GND |8 9| /LOAD
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74164_DIP
+//- Title: DM74164 8-Bit Serial In/Parallel Out Shift Registers
+//- Pinalias: A,B,QA,QB,QC,QD,GND,CLOCK,CLEAR,QE,QF,QG,QH,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/fairchild/DM74164.pdf
+//-
+//- +-------+-------+---+---++----+----+-----+----+
+//- | CLEAR | CLOCK | A | B || QA | QB | ... | QH |
+//- +=======+=======+===+===++====+====+=====+====+
+//- | 0 | X | X | X || 0 | 0 | ... | 0 |
+//- | 1 | 0 | X | X || QA | QB | ... | QH |
+//- | 1 | 0-1 | 1 | 1 || 1 | QA | ... | QG |
+//- | 1 | 0-1 | 0 | X || 0 | QA | ... | QG |
+//- | 1 | 0-1 | X | 0 || 0 | QA | ... | QG |
+//- +-------+-------+---+---++----+----+-----+----+
+//-
+static NETLIST_START(TTL_74164_DIP)
+{
+ TTL_74164(A)
+
+ DIPPINS( // +--------------+
+ A.A, A.VCC, // A |1 ++ 14| VCC
+ A.B, A.QH, // B |2 13| QH
+ A.QA, A.QG, // QA |3 12| QG
+ A.QB, A.QF, // QB |4 74164 11| QF
+ A.QC, A.QE, // QC |5 10| QE
+ A.QD, A.CLRQ, // QD |6 9| CLRQ
+ A.GND, A.CLK // GND |7 8| CLK
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74165_DIP
+//- Title: 54165/DM74165 8-Bit Parallel-to-Serial Converter
+//- Pinalias: PLQ,CP1,P4,P5,P6,P7,QQ7,GND,Q7,DS,P0,P1,P2,P3,CP2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009782.PDF
+//-
+//- +-----+-----+-----++----+----+----+----+----+----+----+----+
+//- | PLQ | CP1 | CP2 || Q0 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 | Q7 |
+//- +=====+=====+=====++====+====+====+====+====+====+====+====+
+//- | 0 | X | X || P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 |
+//- | 1 | 0 | 0-1 || DS | Q0 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 |
+//- | 1 | 1 | 0-1 || Q0 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 | Q7 |
+//- | 1 | 0-1 | 0 || DS | Q0 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 |
+//- | 1 | 0-1 | 1 || Q0 | Q1 | Q2 | Q3 | Q4 | Q5 | Q6 | Q7 |
+//- +-----+-----+-----++----+----+----+----+----+----+----+----+
+//-
+static NETLIST_START(TTL_74165_DIP)
+{
+ TTL_74165(A)
+
+ DIPPINS( // +--------------+
+ A.SH_LDQ, A.VCC, // PLQ |1 ++ 16| VCC
+ A.CLK, A.CLKINH, // CP1 |2 15| CP2
+ A.E, A.D, // P4 |3 14| P3
+ A.F, A.C, // P5 |4 74165 13| P2
+ A.G, A.B, // P6 |5 12| P1
+ A.H, A.A, // P7 |6 11| P0
+ A.QHQ, A.SER, // QQ7 |7 10| DS
+ A.GND, A.QH // GND |8 9| Q7
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74166_DIP
+//- Title: DM74LS166 8-Bit Parallel-In/Serial-Out Shift Registers
+//- Pinalias: SER,A,B,C,D,CLKINH,CLK,GND,CLRQ,E,F,G,QH,H,SH/LDQ,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006400.PDF
+//-
+//- +------+--------+--------+-----+-----+------++----+----+-----+----+
+//- | CLRQ | SH/LDQ | CLKINH | CLK | SER | A..H || QA | QB | ... | QH |
+//- +======+========+========+=====+=====+======++====+====+=====+====+
+//- | 0 | X | X | X | X | X || 0 | 0 | ... | 0 |
+//- | 1 | X | 0 | 0 | X | X || QA | QB | ... | QH |
+//- | 1 | 0 | 0 | 0-1 | X | a..h || a | b | ... | h |
+//- | 1 | 1 | 0 | 0-1 | 1 | X || 1 | QA | ... | QG |
+//- | 1 | 1 | 0 | 0-1 | 0 | X || 0 | QA | ... | QG |
+//- | 1 | X | 1 | 0-1 | X | X || QA | QB | ... | QH |
+//- +------+--------+--------+-----+-----+------++----+----+-----+----+
+//-
+static NETLIST_START(TTL_74166_DIP)
+{
+ TTL_74166(A)
+
+ DIPPINS( // +--------------+
+ A.SER, A.VCC, // SER |1 ++ 16| VCC
+ A.A, A.SH_LDQ, // A |2 15| SH/LDQ
+ A.B, A.H, // B |3 14| H
+ A.C, A.QH, // C |4 74166 13| QH
+ A.D, A.G, // D |5 12| G
+ A.CLKINH, A.F, // CLKINH |6 11| F
+ A.CLK, A.E, // CLK |7 10| E
+ A.GND, A.CLRQ // GND |8 9| CLRQ
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74174_DIP
+//- Title: DM74174 Hex/Quad D-Type Flip-Flop with Clear
+//- Pinalias: CLRQ,Q1,D1,D2,Q2,D3,Q3,GND,CLK,Q4,D4,Q5,D5,Q6,D6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/fairchild/DM74174.pdf
+//-
+//- +------+-----+---++---+
+//- | CLRQ | CLK | D || Q |
+//- +======+=====+===++===+
+//- | 0 | X | X || 0 |
+//- | 1 | 0-1 | 1 || 1 |
+//- | 1 | 0-1 | 0 || 0 |
+//- | 1 | 0 | X || Q |
+//- +------+-----+---++---+
+//-
+static NETLIST_START(TTL_74174_DIP)
+{
+ TTL_74174(A)
+
+ DIPPINS( // +------------+
+ A.CLRQ, A.VCC, // CLRQ |1 ++ 16| VCC
+ A.Q1, A.Q6, // Q1 |2 15| Q6
+ A.D1, A.D6, // D1 |3 14| D6
+ A.D2, A.D5, // D2 |4 74174 13| D5
+ A.Q2, A.Q5, // Q2 |5 12| Q5
+ A.D3, A.D4, // D3 |6 11| D4
+ A.Q3, A.Q4, // Q3 |7 10| Q4
+ A.GND, A.CLK // GND |8 9| CLK
+ // +------------+
+ )
+}
+
+// FIXME: add documentation
+static NETLIST_START(TTL_74175_DIP)
+{
+ TTL_74175(A)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // CLRQ |1 ++ 16| VCC
+ A.Q1, A.Q4, // Q1 |2 15| Q4
+ A.Q1Q, A.Q4Q, // Q1Q |3 14| Q4Q
+ A.D1, A.D4, // D1 |4 74175 13| D4
+ A.D2, A.D3, // D2 |5 12| D3
+ A.Q2Q, A.Q3Q, // Q2Q |6 11| Q3Q
+ A.Q2, A.Q3, // Q2 |7 10| Q3
+ A.GND, A.CLK // GND |8 9| CLK
+ // +--------------+
+ )
+}
+
+// FIXME: add documentation
+static NETLIST_START(TTL_74192_DIP)
+{
+ TTL_74192(A)
+
+ DIPPINS( // +--------------+
+ A.B, A.VCC, // B |1 ++ 16| VCC
+ A.QB, A.A, // QB |2 15| A
+ A.QA, A.CLEAR, // QA |3 14| CLEAR
+ A.CD, A.BORROWQ, // CD |4 74192 13| BORROWQ
+ A.CU, A.CARRYQ, // CU |5 12| CARRYQ
+ A.QC, A.LOADQ, // QC |6 11| LOADQ
+ A.QD, A.C, // QD |7 10| C
+ A.GND, A.D // GND |8 9| D
+ // +--------------+
+ )
+}
+
+// FIXME: add documentation
+static NETLIST_START(TTL_74193_DIP)
+{
+ TTL_74193(A)
+
+ DIPPINS( // +--------------+
+ A.B, A.VCC, // B |1 ++ 16| VCC
+ A.QB, A.A, // QB |2 15| A
+ A.QA, A.CLEAR, // QA |3 14| CLEAR
+ A.CD, A.BORROWQ, // CD |4 74192 13| BORROWQ
+ A.CU, A.CARRYQ, // CU |5 12| CARRYQ
+ A.QC, A.LOADQ, // QC |6 11| LOADQ
+ A.QD, A.C, // QD |7 10| C
+ A.GND, A.D // GND |8 9| D
+ // +--------------+
+ )
+}
+
+// FIXME: add documentation
+static NETLIST_START(TTL_74194_DIP)
+{
+ TTL_74194(A)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // CLRQ |1 ++ 16| VCC
+ A.SRIN, A.QA, // SRIN |2 15| QA
+ A.A, A.QB, // A |3 14| QB
+ A.B, A.QC, // B |4 74194 13| QC
+ A.C, A.QD, // C |5 12| QD
+ A.D, A.CLK, // D |6 11| CLK
+ A.SLIN, A.S1, // SLIN |7 10| S1
+ A.GND, A.S0 // GND |8 9| S0
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74260_DIP
+//- Title: DM54LS260/DM74LS260 Dual 5-Input NOR Gate
+//- Pinalias: A1,B1,C1,A2,Q1,Q2,GND,B2,C2,D2,E2,D1,E1,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009824.PDF
+//-
+//- +---+---+---+---+---++---+
+//- | A | B | C | D | E || Y |
+//- +===+===+===+===+===++===+
+//- | 0 | 0 | 0 | 0 | 0 || 1 |
+//- | X | X | X | X | 1 || 0 |
+//- | X | X | X | 1 | X || 0 |
+//- | X | X | 1 | X | X || 0 |
+//- | X | 1 | X | X | X || 0 |
+//- | 1 | X | X | X | X || 0 |
+//- +---+---+---+---+---++---+
+//-
+static NETLIST_START(TTL_74260_DIP)
+{
+ TTL_74260_NOR(A)
+ TTL_74260_NOR(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.C, A.VCC, // C1 |1 ++ 14| VCC
+ A.D, A.B, // D1 |2 13| B1
+ A.E, A.A, // E1 |3 12| A1
+ B.E, B.D, // E2 |4 74260 11| D2
+ A.Q, B.C, // Y1 |5 10| C2
+ B.Q, B.B, // Y2 |6 9| B2
+ A.GND, B.A // GND |7 8| A2
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74279_DIP
+//- Title: 54279/DM74279 Quad Set-Reset Latch
+//- Pinalias: 1RQ,1S1Q,1S2Q,1Q,2RQ,2SQ,2Q,GND,3Q,3RQ,3S1Q,3S2Q,4Q,4RQ,4SQ,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009785.PDF
+//-
+//- +-----+-----+----++---+
+//- | S1Q | S2Q | RQ || Q |
+//- +=====+=====+====++===+
+//- | 0 | 0 | 0 || 1 | (as long as SQ1 or SQ2 are low)
+//- | 0 | X | 1 || 1 |
+//- | X | 0 | 1 || 1 |
+//- | 1 | 1 | 0 || 0 |
+//- | 1 | 1 | 1 || Q |
+//- +-----+-----+----++---+
+//-
+#ifndef __PLIB_PREPROCESSOR__
+#endif
+
+static NETLIST_START(TTL_74279_DIP)
+{
+ TTL_74279B(A)
+ TTL_74279A(B)
+ TTL_74279B(C)
+ TTL_74279A(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+
+ DIPPINS( // +--------------+
+ A.R, A.VCC, // 1RQ |1 ++ 16| VCC
+ A.S1, D.S, // 1S1Q |2 15| 4SQ
+ A.S2, D.R, // 1S2Q |3 14| 4RQ
+ A.Q, D.Q, // 1Q |4 74279 13| 4Q
+ B.R, C.S2, // 2RQ |5 12| 3S2Q
+ B.S, C.S1, // 2SQ |6 11| 3S1Q
+ B.Q, C.R, // 2Q |7 10| 3RQ
+ A.GND, C.Q // GND |8 9| 3Q
+ // +--------------+
+ )
+}
+
+// FIXME: Documentation
+static NETLIST_START(TTL_74365_DIP)
+{
+ TTL_74365(A)
+
+ DIPPINS( // +--------------+
+ A.G1Q, A.VCC, // G1Q |1 ++ 16| VCC
+ A.A1, A.G2Q, // A1 |2 15| G2Q
+ A.Y1, A.A6, // Y1 |3 14| A6
+ A.A2, A.Y6, // A2 |4 74365 13| Y6
+ A.Y2, A.A5, // Y2 |5 12| A5
+ A.A3, A.Y5, // A3 |6 11| Y5
+ A.Y3, A.A4, // Y3 |7 10| A4
+ A.GND, A.Y4 // GND |8 9| Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74290_DIP
+//- Title: SN54290/SN74290, SN54LS290/SN74LS290 Decade Counter
+//- Pinalias: R91,NC,R92,QC,QB,NC,GND,QD,QA,CKA,CKB,R01,R02,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/27403/TI/SN74293.html
+//-
+//- BCD Count Sequence BCD Bi-Quinary
+//- +-------++----+----+----+----+ +-------++----+----+----+----+
+//- | Count || QD | QC | QB | QA | | Count || QD | QC | QB | QA |
+//- +=======++====+====+====+====+ +=======++====+====+====+====+
+//- | 0 || 0 | 0 | 0 | 0 | | 0 || 0 | 0 | 0 | 0 |
+//- | 1 || 0 | 0 | 0 | 1 | | 1 || 0 | 0 | 0 | 1 |
+//- | 2 || 0 | 0 | 1 | 0 | | 2 || 0 | 0 | 1 | 0 |
+//- | 3 || 0 | 0 | 1 | 1 | | 3 || 0 | 0 | 1 | 1 |
+//- | 4 || 0 | 1 | 0 | 0 | | 4 || 0 | 1 | 0 | 0 |
+//- | 5 || 0 | 1 | 0 | 1 | | 5 || 1 | 0 | 0 | 0 |
+//- | 6 || 0 | 1 | 1 | 0 | | 6 || 1 | 0 | 0 | 1 |
+//- | 7 || 0 | 1 | 1 | 1 | | 7 || 1 | 0 | 1 | 0 |
+//- | 8 || 1 | 0 | 0 | 0 | | 8 || 1 | 0 | 1 | 1 |
+//- | 9 || 1 | 0 | 0 | 1 | | 9 || 1 | 1 | 0 | 0 |
+//- +-------++----+----+----+----+ +-------++----+----+----+----+
+//-
+//- Reset/Count Function Table
+//- +-----+-----+-----+-----++----+----+----+----+
+//- | R01 | R02 | R91 | R92 || QD | QC | QB | QA |
+//- +=====+=====+=====+=====++====+====+====+====+
+//- | 1 | 1 | 0 | X || 0 | 0 | 0 | 0 |
+//- | 1 | 1 | X | 0 || 0 | 0 | 0 | 0 |
+//- | X | X | 1 | 1 || 1 | 0 | 0 | 1 |
+//- | X | 0 | X | 0 || COUNT |
+//- | 0 | X | 0 | X || COUNT |
+//- | 0 | X | X | 0 || COUNT |
+//- | X | 0 | 0 | X || COUNT |
+//- +-----+-----+-----+-----++----+----+----+----+
+//-
+static NETLIST_START(TTL_74290_DIP)
+{
+ TTL_7490(A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ A.R91, A.VCC, // R91 |1 ++ 14| VCC
+ NC.I, A.R2, // NC |2 13| R02
+ A.R92, A.R1, // R92 |3 12| R01
+ A.QC, A.B, // QC |4 74290 11| CKB
+ A.QB, A.A, // QB |5 10| CKA
+ NC.I, A.QA, // NC |6 9| QA
+ A.GND, A.QD // GND |7 8| QD
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74293_DIP
+//- Title: SN54293/SN74293, SN54LS293/SN74LS293 Binary Counters
+//- Pinalias: B,R01,R02,NC,VCC,NC,NC,QC,QB,GND,QD,QA,NC,A
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- Limitations: Internal resistor network currently fixed to 5k
+//- more limitations
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/27403/TI/SN74293.html
+//-
+//- Counter Sequence
+//-
+//- | COUNT || QD | QC | QB | QA |
+//- |------:||:--:|:--:|:--:|:--:|
+//- | 0 || 0 | 0 | 0 | 0 |
+//- | 1 || 0 | 0 | 0 | 1 |
+//- | 2 || 0 | 0 | 1 | 0 |
+//- | 3 || 0 | 0 | 1 | 1 |
+//- | 4 || 0 | 1 | 0 | 0 |
+//- | 5 || 0 | 1 | 0 | 1 |
+//- | 6 || 0 | 1 | 1 | 0 |
+//- | 7 || 0 | 1 | 1 | 1 |
+//- | 8 || 1 | 0 | 0 | 0 |
+//- | 9 || 1 | 0 | 0 | 1 |
+//- | 10 || 1 | 0 | 1 | 0 |
+//- | 11 || 1 | 0 | 1 | 1 |
+//- | 12 || 1 | 1 | 0 | 0 |
+//- | 13 || 1 | 1 | 0 | 1 |
+//- | 14 || 1 | 1 | 1 | 0 |
+//- | 15 || 1 | 1 | 1 | 1 |
+//-
+//- Note C Output QA is connected to input B
+//-
+//- Reset Count Function table
+//-
+//- | R01 | R02 | QD | QC | QB | QA |
+//- |:---:|:---:|:--:|:--:|:--:|:--:|
+//- | 1 | 1 | 0 | 0 | 0 | 0 |
+//- | 0 | X | COUNT ||||
+//- | X | 0 | COUNT ||||
+//-
+//-
+
+static NETLIST_START(TTL_74293_DIP)
+{
+ TTL_7493(A)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ NC.I, A.VCC, // NC |1 ++ 14| VCC
+ NC.I, A.R2, // NC |2 13| R02
+ NC.I, A.R1, // NC |3 12| R01
+ A.QC, A.CLKB, // QC |4 74293 11| CKB
+ A.QB, A.CLKA, // QB |5 10| CKA
+ NC.I, A.QA, // NC |6 9| QA
+ A.GND, A.QD // GND |7 8| QD
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74368_DIP
+//- Title: SN74368 Hex Inverting Buffers and Line Drivers With 3-State Outputs
+//- Pinalias: 1G,1A1,1Y1,1A2,1Y2,1A3,1Y3,Gnd,1Y4,1A4,2Y1,2A1,2Y2,2A2,2G,Vcc
+//- Package: DIP-16
+//- NamingConvention: Naming conventions follow Texas Instruments datasheet
+//- FunctionTable:
+//- https://www.ti.com/lit/ds/symlink/sn74hc368.pdf
+//- https://www.ti.com/lit/ds/symlink/sn74ls368a.pdf
+//-
+//- +----+---++---+
+//- | OE | A || Y |
+//- +====+===++===+
+//- | 1 | X || Z |
+//- | 0 | 1 || 0 |
+//- | 0 | 0 || 1 |
+//- +---+----++---+
+//-
+static NETLIST_START(TTL_74368_DIP)
+{
+ NET_REGISTER_DEV(TTL_74368_GATE, A)
+ NET_REGISTER_DEV(TTL_74368_GATE, B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ NET_C(A.A, B.A)
+ NET_C(A.B, B.B)
+
+ DIPPINS( // +--------------+
+ A.OE, A.VCC, // 1OE |1 ++ 16| VCC
+ A.A1, B.OE, // 1A1 |2 15| 2OE
+ A.Y1, B.A2, // 1Y1 |3 14| 2A2
+ A.A2, B.Y2, // 1A2 |4 74368 13| 2Y2
+ A.Y2, B.A1, // 1Y2 |5 12| 2A1
+ A.A3, B.Y1, // 1A3 |6 11| 2Y1
+ A.Y3, A.A4, // 1Y4 |7 10| 1A4
+ A.GND, A.Y4 // GND |8 9| 1Y4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74377_DIP
+//- Title: DM54LS377/DM74LS377 Octal D Flip-Flop with Common Enable and Clock
+//- Pinalias: EQ,Q0,D0,D1,Q1,Q2,D2,D3,Q3,GND,CP,Q4,D4,D5,Q5,Q6,D6,D7,Q7,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009785.PDF
+//-
+//- +----+-----+----++----+
+//- | EQ | CP | Dn || Qn |
+//- +====+=====+====++====+
+//- | 1 | X | X || Qn |
+//- | 0 | 0-1 | 1 || 1 |
+//- | 0 | 0-1 | 0 || 0 |
+//- +----+-----+----++----+
+//-
+static NETLIST_START(TTL_74377_DIP)
+{
+ TTL_74377_GATE(A)
+ TTL_74377_GATE(B)
+ TTL_74377_GATE(C)
+ TTL_74377_GATE(D)
+ TTL_74377_GATE(E)
+ TTL_74377_GATE(F)
+ TTL_74377_GATE(G)
+ TTL_74377_GATE(H)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC, G.VCC, H.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND, G.GND, H.GND)
+ NET_C(A.CP, B.CP, C.CP, D.CP, E.CP, F.CP, G.CP, H.CP)
+ NET_C(A.E, B.E, C.E, D.E, E.E, F.E, G.E, H.E)
+
+ HINT(A.QQ, NC)
+ HINT(B.QQ, NC)
+ HINT(C.QQ, NC)
+ HINT(D.QQ, NC)
+ HINT(E.QQ, NC)
+ HINT(F.QQ, NC)
+ HINT(G.QQ, NC)
+ HINT(H.QQ, NC)
+
+ DIPPINS( // +--------------+
+ A.E, A.VCC, // EQ |1 ++ 20| VCC
+ A.Q, H.Q, // Q0 |2 19| Q7
+ A.D, H.D, // D0 |3 18| D7
+ B.D, G.D, // D1 |4 74377 17| D6
+ B.Q, G.Q, // Q1 |5 16| Q6
+ C.Q, F.Q, // Q2 |6 15| Q5
+ C.D, F.D, // D2 |7 14| D5
+ D.D, E.D, // D3 |8 13| D4
+ D.Q, E.Q, // Q3 |9 12| Q4
+ A.GND, A.CP // GND |10 11| CP
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74378_DIP
+//- Title: DM54LS378/DM74LS378 Parallel D Register with Enable
+//- Pinalias: EQ,Q0,D0,D1,Q1,D2,Q2,GND,CP,Q3,D3,Q4,D4,D5,Q6,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009832.PDF
+//-
+//- +----+-----+----++----+
+//- | EQ | CP | Dn || Qn |
+//- +====+=====+====++====+
+//- | 1 | X | X || Qn |
+//- | 0 | 0-1 | 1 || 1 |
+//- | 0 | 0-1 | 0 || 0 |
+//- +----+-----+----++----+
+//-
+static NETLIST_START(TTL_74378_DIP)
+{
+ TTL_74377_GATE(A)
+ TTL_74377_GATE(B)
+ TTL_74377_GATE(C)
+ TTL_74377_GATE(D)
+ TTL_74377_GATE(E)
+ TTL_74377_GATE(F)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC, E.VCC, F.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND, E.GND, F.GND)
+ NET_C(A.CP, B.CP, C.CP, D.CP, E.CP, F.CP)
+ NET_C(A.E, B.E, C.E, D.E, E.E, F.E)
+
+ DIPPINS( // +--------------+
+ A.E, A.VCC, // EQ |1 ++ 16| VCC
+ A.Q, F.Q, // Q0 |2 15| Q5
+ A.D, F.D, // D0 |3 14| D5
+ B.D, E.D, // D1 |4 74378 13| D4
+ B.Q, E.Q, // Q1 |5 12| Q4
+ C.D, D.D, // D2 |6 11| D3
+ C.Q, D.Q, // Q2 |7 10| Q3
+ A.GND, A.CP // GND |8 9| CP
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74379_DIP
+//- Title: 54LS379/DM74LS379 Quad Parallel Register with Enable
+//- Pinalias: EEQ,Q0,QQ0,D0,QQ1,Q1,GND,CP,Q2,QQ2,D2,D3,QQ3,Q3,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS009832.PDF
+//-
+//- +----+-----+----++----+-----+
+//- | EQ | CP | Dn || Qn | QQn |
+//- +====+=====+====++====+=====+
+//- | 1 | X | X || Qn | QQn |
+//- | 0 | 0-1 | 1 || 1 | 0 |
+//- | 0 | 0-1 | 0 || 0 | 1 |
+//- +----+-----+----++----+-----+
+//-
+static NETLIST_START(TTL_74379_DIP)
+{
+ TTL_74377_GATE(A)
+ TTL_74377_GATE(B)
+ TTL_74377_GATE(C)
+ TTL_74377_GATE(D)
+
+ NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
+ NET_C(A.GND, B.GND, C.GND, D.GND)
+ NET_C(A.CP, B.CP, C.CP, D.CP)
+ NET_C(A.E, B.E, C.E, D.E)
+
+ DIPPINS( // +--------------+
+ A.E, A.VCC, // EQ |1 ++ 16| VCC
+ A.Q, D.Q, // Q0 |2 15| Q3
+ A.QQ, D.QQ, // QQ0 |3 14| QQ3
+ A.D, D.D, // D0 |4 74379 13| D3
+ B.D, C.D, // D1 |5 12| D2
+ B.QQ, C.QQ, // QQ1 |6 11| QQ2
+ B.Q, C.Q, // Q1 |7 10| Q2
+ A.GND, A.CP // GND |8 9| CP
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_74393_DIP
+//- Title: Dual 4-Bit Binary Counter
+//- Pinalias: 1A,1CLR,1QA,1QB,1QC,1QD,GND,2QD,2QC,2QB,2QA,2CLR,2A,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006434.PDF
+//-
+static NETLIST_START(TTL_74393_DIP)
+{
+ TTL_74393(A)
+ TTL_74393(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.CP, A.VCC, // 1A |1 ++ 14| VCC
+ A.MR, B.CP, // 1CLR |2 13| 2A
+ A.Q0, B.MR, // 1QA |3 12| 2CLR
+ A.Q1, B.Q0, // 1QB |4 74393 11| 2QA
+ A.Q2, B.Q1, // 1QC |5 10| 2QB
+ A.Q3, B.Q2, // 1QD |6 9| 2QC
+ A.GND, B.Q3 // GND |7 8| 2QD
+ // +--------------+
+ )
+}
+
+//- Identifier: SN74LS629_DIP
+//- Title: SN74LS629 VOLTAGE-CONTROLLED OSCILLATORS
+//- Pinalias: 2FC,1FC,1RNG,1CX1,1CX2,1ENQ,1Y,OSC_GND,GND,2Y,2ENQ,2CX2,2CX1,2RNG,OSC_VCC,VCC
+//- Package: DIP
+//- Param: A.CAP
+//- Capacitor value of capacitor connected to 1CX1 and 1CX2 pins
+//- Param: B.CAP
+//- Capacitor value of capacitor connected to 2CX1 and 2CX2 pins
+//- Limitations:
+//- The capacitor inputs are NC. Capacitor values need to be specified as
+//- ```
+//- SN74LS629_DIP(X)
+//- PARAM(X.A.CAP, CAP_U(1))
+//- PARAM(X.B.CAP, CAP_U(2))
+//- ```
+//-
+//- Example: 74ls629.cpp,74ls629_example
+//-
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheets/400/335051_DS.pdf
+//-
+static NETLIST_START(SN74LS629_DIP)
+{
+ SN74LS629(A, CAP_U(1))
+ SN74LS629(B, CAP_U(1))
+
+ NET_C(A.GND, B.GND)
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.OSCGND, B.OSCGND)
+ NET_C(A.OSCVCC, B.OSCVCC)
+ NC_PIN(NC)
+
+ DIPPINS( // +--------------+
+ B.FC, A.VCC, // 2FC |1 ++ 16| VCC
+ A.FC, A.OSCVCC, // 1FC |2 15| OSC VCC
+ A.RNG, B.RNG, // 1RNG |3 14| 2RNG
+ NC.I, NC.I, // 1CX1 |4 74LS629 13| 2CX1
+ NC.I, NC.I, // 1CX2 |5 12| 2CX2
+ A.ENQ, B.ENQ, // 1ENQ |6 11| 2ENQ
+ B.Y, B.Y, // 1Y |7 10| 2Y
+ A.OSCGND, A.GND // OSC GND |8 9| GND
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_9310_DIP
+//- Title: DM9310/DM8310 Synchronous 4-Bit Decade Counter
+//- Pinalias: CLEARQ,CLOCK,A,B,C,D,ENABLEP,GND,LOADQ,ENABLET,QD,QC,QB,QA,RC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- https://archive.org/download/bitsavers_nationaldaTTLDatabook_40452765/1976_National_TTL_Databook.pdf
+//-
+static NETLIST_START(TTL_9310_DIP)
+{
+ TTL_9310(A)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // /CLEAR |1 ++ 16| VCC
+ A.CLK, A.RC, // CLOCK |2 15| RC
+ A.A, A.QA, // A |3 14| QA
+ A.B, A.QB, // B |4 9310 13| QB
+ A.C, A.QC, // C |5 12| QC
+ A.D, A.QD, // D |6 11| QD
+ A.ENP, A.ENT, // Enable P |7 10| Enable T
+ A.GND, A.LOADQ // GND |8 9| /LOAD
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_9312_DIP
+//- Title: DM9312/DM8312 One of Eight Line Data Selectors/Multiplexers
+//- Pinalias: D0,D1,D2,D3,D4,D5,D6,GND,D7,G,A,B,C,YQ,Y,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DM9312.pdf
+//-
+//- +---+---+---+---++----+-----+
+//- | C | B | A | G || Y | YQ |
+//- +===+===+===+===++====+=====+
+//- | X | X | X | 1 || 0 | 1 |
+//- | 0 | 0 | 0 | 0 || D0 | D0Q |
+//- | 0 | 0 | 1 | 0 || D1 | D1Q |
+//- | 0 | 1 | 0 | 0 || D2 | D2Q |
+//- | 0 | 1 | 1 | 0 || D3 | D3Q |
+//- | 1 | 0 | 0 | 0 || D4 | D4Q |
+//- | 1 | 0 | 1 | 0 || D5 | D5Q |
+//- | 1 | 1 | 0 | 0 || D6 | D6Q |
+//- | 1 | 1 | 1 | 0 || D7 | D7Q |
+//- +---+---+---+---++----+-----+
+//-
+static NETLIST_START(TTL_9312_DIP)
+{
+ TTL_9312(A)
+
+ DIPPINS( // +--------------+
+ A.D0, A.VCC, // D0 |1 ++ 16| VCC
+ A.D1, A.Y, // D1 |2 15| Y
+ A.D2, A.YQ, // D2 |3 14| YQ
+ A.D3, A.C, // D3 |4 9312 13| C
+ A.D4, A.B, // D4 |5 12| B
+ A.D5, A.A, // D5 |6 11| A
+ A.D6, A.G, // Strobe // D6 |7 10| G
+ A.GND, A.D7 // GND |8 9| D7
+ // +--------------+
+ )
+}
+
+// FIXME: Documentation
+static NETLIST_START(TTL_9314_DIP)
+{
+ TTL_9314(A)
+
+ DIPPINS( // +--------------+
+ A.EQ, A.VCC, // /E |1 ++ 16| VCC
+ A.S0Q, A.Q0, // /S0 |2 15| Q0
+ A.D0, A.S1Q, // D0 |3 14| /S1
+ A.D1, A.Q1, // D1 |4 DM9314 13| Q1
+ A.S2Q, A.Q2, // /S2 |5 12| Q2
+ A.D2, A.S3Q, // D2 |6 11| /S3
+ A.D3, A.Q3, // D3 |7 10| Q3
+ A.GND, A.MRQ // GND |8 9| /MR
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_9316_DIP
+//- Title: DM9316/DM8316 Synchronous 4-Bit Counters
+//- Pinalias: CLEARQ,CLOCK,A,B,C,D,ENABLEP,GND,LOADQ,ENABLET,QD,QC,QB,QA,RC,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006606.PDF
+//-
+static NETLIST_START(TTL_9316_DIP)
+{
+ TTL_9316(A)
+
+ DIPPINS( // +--------------+
+ A.CLRQ, A.VCC, // CLEARQ |1 ++ 16| VCC
+ A.CLK, A.RC, // CLOCK |2 15| RC
+ A.A, A.QA, // A |3 14| QA
+ A.B, A.QB, // B |4 9316 13| QB
+ A.C, A.QC, // C |5 12| QC
+ A.D, A.QD, // D |6 11| QD
+ A.ENP, A.ENT, // Enable P |7 10| Enable T
+ A.GND, A.LOADQ // GND |8 9| LOADQ
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_9322_DIP
+//- Title: DM9322/DM8322 Quad 2-Line to 1-Line Data Selectors/Multiplexers
+//- Pinalias: SELECT,A1,B1,Y1,A2,B2,Y2,GND,Y3,B3,A3,Y4,B4,A4,STROBE,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//- FunctionTable:
+//- http://pdf.datasheetcatalog.com/datasheet/nationalsemiconductor/DS006606.PDF
+//-
+static NETLIST_START(TTL_9322_DIP)
+{
+ TTL_9322(A)
+
+ DIPPINS( // +--------------+
+ A.SELECT, A.VCC, // SELECT |1 ++ 16| VCC
+ A.A1, A.STROBE, // A1 |2 15| STROBE
+ A.B1, A.A4, // B1 |3 14| A4
+ A.Y1, A.B4, // Y1 |4 9322 13| B4
+ A.A2, A.Y4, // A2 |5 12| Y4
+ A.B2, A.A3, // B2 |6 11| A3
+ A.Y2, A.B3, // Y2 |7 10| B3
+ A.GND, A.Y3 // GND |8 9| Y3
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_9321_DIP
+//- Title: DM9321/DM8321 Dual 4-Line to 1-Line Data Selectors/Multiplexers
+//- Pinalias: AE,AA0,AA1,AD0,AD1,AD2,AD3,GND,BD3,BD2,BD1,BD0,BA1,BA0,BE,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow National Semiconductor datasheet
+//-
+static NETLIST_START(TTL_9321_DIP)
+{
+ TTL_9321(A)
+ TTL_9321(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.E, A.VCC, // /E |1 ++ 16| VCC
+ A.A0, B.E, // A0 |2 15| /E
+ A.A1, B.A0, // A1 |3 14| A0
+ A.D0, B.A1, // /D0 |4 9321 13| A1
+ A.D1, B.D0, // /D1 |5 12| /D0
+ A.D2, B.D1, // /D2 |6 11| /D1
+ A.D3, B.D2, // /D3 |7 10| /D2
+ A.GND, B.D3 // GND |8 9| /D3
+ // +--------------+
+ )
+}
+
+// FIXME: Documentation
+static NETLIST_START(TTL_9334_DIP)
+{
+ TTL_9334(A)
+
+ DIPPINS( // +--------------+
+ A.A0, A.VCC, // A0 |1 ++ 16| VCC
+ A.A1, A.CQ, // A1 |2 15| /C
+ A.A2, A.EQ, // A2 |3 14| /E
+ A.Q0, A.D, // Q0 |4 DM9334 13| D
+ A.Q1, A.Q7, // Q1 |5 12| Q7
+ A.Q2, A.Q6, // Q2 |6 11| Q6
+ A.Q3, A.Q5, // Q3 |7 10| Q5
+ A.GND, A.Q4 // GND |8 9| Q4
+ // +--------------+
+ )
+}
+
+//- Identifier: TTL_9602_DIP
+//- Title: DM9602/DM6802 Dual Retriggerable, Resettable One Shots
+//- Pinalias: C1,RC1,CLRQ1,B1,A1,Q1,QQ1,GND,QQ2,Q2,A2,B2,CLRQ2,RC2,C2,VCC
+//- Package: DIP
+//- NamingConvention: Naming conventions follow Fairchild Semiconductor datasheet
+//- Limitations:
+//- Timing inaccuracies may occur for capacitances < 1nF. Please consult datasheet
+//-
+//- Example: 74123.cpp,74123_example
+//-
+//- FunctionTable:
+//- https://pdf1.alldatasheet.com/datasheet-pdf/view/51137/FAIRCHILD/DM9602.html
+//-
+static NETLIST_START(TTL_9602_DIP)
+{
+ TTL_9602(A)
+ TTL_9602(B)
+
+ NET_C(A.VCC, B.VCC)
+ NET_C(A.GND, B.GND)
+
+ DIPPINS( // +--------------+
+ A.C, A.VCC, // C1 |1 ++ 16| VCC
+ A.RC, B.C, // RC1 |2 15| C2
+ A.CLRQ, B.RC, // CLRQ1 |3 14| RC2
+ A.B, B.CLRQ, // B1 |4 9602 13| CLRQ2
+ A.A, B.B, // A1 |5 12| B2
+ A.Q, B.A, // Q1 |6 11| A2
+ A.QQ, B.Q, // QQ1 |7 10| Q2
+ A.GND, B.QQ // GND |8 9| QQ2
+ // +--------------+
+ )
+}
+
+// FIXME: Documentation and naming
+static NETLIST_START(TTL_8277_DIP)
+{
+ TTL_8277(A)
+
+ DIPPINS( // +--------------+
+ A.RESET, A.VCC, // RESET |1 ++ 16| VCC
+ A.Q7QA, A.Q7QB, // /Q7A |2 15| /Q7B
+ A.Q7A, A.Q7B, // Q7A |3 14| Q7B
+ A.DSA, A.DSB, // DSA |4 8277 13| DSB
+ A.D1A, A.D1B, // D1A |5 12| D1B
+ A.D0A, A.D0B, // D0A |6 11| D0B
+ A.CLKA, A.CLKB, // CLKA |7 10| CLKB
+ A.GND, A.CLK // GND |8 9| CLK
+ // +--------------+
+ )
+}
+
+// FIXME: Documentation, add model, seems to be a CMOS device
+static NETLIST_START(TTL_AM2847_DIP)
+{
+ TTL_AM2847(A)
+
+ DIPPINS( // +--------------+
+ A.OUTA, A.VSS, // OUTA |1 ++ 16| VSS
+ A.RCA, A.IND, // RCA |2 15| IND
+ A.INA, A.RCD, // INA |3 14| RCD
+ A.OUTB, A.OUTD, // OUTB |4 Am2847 13| OUTD
+ A.RCB, A.VGG, // RCB |5 12| VGG
+ A.INB, A.CP, // INB |6 11| CP
+ A.OUTC, A.INC, // OUTC |7 10| INC
+ A.VDD, A.RCC // VDD |8 9| RCC
+ // +--------------+
+ )
+}
+
+static TRUTH_TABLE(TTL_7400_NAND, 2, 1, "+A,+B,@VCC,@GND")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,X|1|22")
+ TT_LINE("X,0|1|22")
+ TT_LINE("1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7402_NOR, 2, 1, "+A,+B,@VCC,@GND")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,0|1|22")
+ TT_LINE("X,1|0|15")
+ TT_LINE("1,X|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7404_INVERT, 1, 1, "+A,@VCC,@GND")
+{
+ TT_HEAD(" A | Q ")
+ TT_LINE(" 0 | 1 |22")
+ TT_LINE(" 1 | 0 |15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7406_GATE, 1, 1, "")
+{
+ TT_HEAD("A|Y ")
+ TT_LINE("0|1|15")
+ TT_LINE("1|0|23")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_7407_GATE, 1, 1, "")
+{
+ TT_HEAD("A|Y ")
+ TT_LINE("0|0|15")
+ TT_LINE("1|1|23")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_7408_GATE, 2, 1, "")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,X|0|15")
+ TT_LINE("X,0|0|15")
+ TT_LINE("1,1|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7408_AND, 2, 1, "+A,+B,@VCC,@GND")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,X|0|15")
+ TT_LINE("X,0|0|15")
+ TT_LINE("1,1|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7410_NAND, 3, 1, "+A,+B,+C,@VCC,@GND")
+{
+ TT_HEAD("A,B,C|Q ")
+ TT_LINE("0,X,X|1|22")
+ TT_LINE("X,0,X|1|22")
+ TT_LINE("X,X,0|1|22")
+ TT_LINE("1,1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7410_GATE, 3, 1, "")
+{
+ TT_HEAD("A,B,C|Q ")
+ TT_LINE("0,X,X|1|22")
+ TT_LINE("X,0,X|1|22")
+ TT_LINE("X,X,0|1|22")
+ TT_LINE("1,1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7411_AND, 3, 1, "+A,+B,+C,@VCC,@GND")
+{
+ TT_HEAD("A,B,C|Q ")
+ TT_LINE("0,X,X|0|15")
+ TT_LINE("X,0,X|0|15")
+ TT_LINE("X,X,0|0|15")
+ TT_LINE("1,1,1|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7411_GATE, 3, 1, "")
+{
+ TT_HEAD("A,B,C|Q ")
+ TT_LINE("0,X,X|0|15")
+ TT_LINE("X,0,X|0|15")
+ TT_LINE("X,X,0|0|15")
+ TT_LINE("1,1,1|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7416_GATE, 1, 1, "")
+{
+ TT_HEAD("A|Q")
+ TT_LINE("0|1|15")
+ TT_LINE("1|0|23")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_7417_GATE, 1, 1, "")
+{
+ TT_HEAD("A|Q")
+ TT_LINE("0|0|15")
+ TT_LINE("1|1|23")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_7420_NAND, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
+{
+ TT_HEAD("A,B,C,D|Q ")
+ TT_LINE("0,X,X,X|1|22")
+ TT_LINE("X,0,X,X|1|22")
+ TT_LINE("X,X,0,X|1|22")
+ TT_LINE("X,X,X,0|1|22")
+ TT_LINE("1,1,1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7421_AND, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
+{
+ TT_HEAD("A,B,C,D|Q ")
+ TT_LINE("0,X,X,X|0|22")
+ TT_LINE("X,0,X,X|0|22")
+ TT_LINE("X,X,0,X|0|22")
+ TT_LINE("X,X,X,0|0|22")
+ TT_LINE("1,1,1,1|1|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7425_NOR, 4, 1, "+A,+B,+C,+D,@VCC,@GND")
+{
+ TT_HEAD("A,B,C,D|Q ")
+ TT_LINE("1,X,X,X|0|15")
+ TT_LINE("X,1,X,X|0|15")
+ TT_LINE("X,X,1,X|0|15")
+ TT_LINE("X,X,X,1|0|15")
+ TT_LINE("0,0,0,0|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7427_NOR, 3, 1, "+A,+B,+C,@VCC,@GND")
+{
+ TT_HEAD("A,B,C|Q ")
+ TT_LINE("1,X,X|0|15")
+ TT_LINE("X,1,X|0|15")
+ TT_LINE("X,X,1|0|15")
+ TT_LINE("0,0,0|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7430_NAND, 8, 1, "+A,+B,+C,+D,+E,+F,+G,+H,@VCC,@GND")
+{
+ TT_HEAD("A,B,C,D,E,F,G,H|Q ")
+ TT_LINE("0,X,X,X,X,X,X,X|1|22")
+ TT_LINE("X,0,X,X,X,X,X,X|1|22")
+ TT_LINE("X,X,0,X,X,X,X,X|1|22")
+ TT_LINE("X,X,X,0,X,X,X,X|1|22")
+ TT_LINE("X,X,X,X,0,X,X,X|1|22")
+ TT_LINE("X,X,X,X,X,0,X,X|1|22")
+ TT_LINE("X,X,X,X,X,X,0,X|1|22")
+ TT_LINE("X,X,X,X,X,X,X,0|1|22")
+ TT_LINE("1,1,1,1,1,1,1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7432_OR, 2, 1, "+A,+B,@VCC,@GND")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("1,X|1|22")
+ TT_LINE("X,1|1|22")
+ TT_LINE("0,0|0|15")
+ TT_FAMILY("74XX")
+}
+
+/* FIXME: Same as 7400, but drains higher output currents.
+ * Netlist currently does not model over currents (should it ever?)
+ */
+
+static TRUTH_TABLE(TTL_7437_NAND, 2, 1, "+A,+B")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,X|1|22")
+ TT_LINE("X,0|1|22")
+ TT_LINE("1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_7438_NAND, 2, 1, "+A,+B")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,X|1|22")
+ TT_LINE("X,0|1|22")
+ TT_LINE("1,1|0|15")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_7442, 4, 10, "")
+{
+ TT_HEAD("D,C,B,A|0,1,2,3,4,5,6,7,8,9")
+ TT_LINE("0,0,0,0|0,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,0,0,1|1,0,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,0,1,0|1,1,0,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,0,1,1|1,1,1,0,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,1,0,0|1,1,1,1,0,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,1,0,1|1,1,1,1,1,0,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,1,1,0|1,1,1,1,1,1,0,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("0,1,1,1|1,1,1,1,1,1,1,0,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("1,0,0,0|1,1,1,1,1,1,1,1,0,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("1,0,0,1|1,1,1,1,1,1,1,1,1,0|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("1,0,1,X|1,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+ TT_LINE("1,1,X,X|1,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
+}
+
+static TRUTH_TABLE(TTL_7486_XOR, 2, 1, "+A,+B,@VCC,@GND")
+{
+ TT_HEAD("A,B|Q ")
+ TT_LINE("0,0|0|15")
+ TT_LINE("0,1|1|22")
+ TT_LINE("1,0|1|22")
+ TT_LINE("1,1|0|15")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74139_GATE, 3, 4, "")
+{
+ TT_HEAD("E,A,B|O0,O1,O2,O3")
+ TT_LINE("1,X,X|1,1,1,1|14")
+ TT_LINE("0,0,0|0,1,1,1|14")
+ TT_LINE("0,0,1|1,0,1,1|14")
+ TT_LINE("0,1,0|1,1,0,1|14")
+ TT_LINE("0,1,1|1,1,1,0|14")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74147_GATE, 9, 4, "")
+{
+ TT_HEAD("1,2,3,4,5,6,7,8,9|D,C,B,A")
+ TT_LINE("1,1,1,1,1,1,1,1,1|1,1,1,1|10")
+ TT_LINE("X,X,X,X,X,X,X,X,0|0,1,1,0|10")
+ TT_LINE("X,X,X,X,X,X,X,0,1|0,1,1,1|10")
+ TT_LINE("X,X,X,X,X,X,0,1,1|1,0,0,0|10")
+ TT_LINE("X,X,X,X,X,0,1,1,1|1,0,0,1|10")
+ TT_LINE("X,X,X,X,0,1,1,1,1|1,0,1,0|10")
+ TT_LINE("X,X,X,0,1,1,1,1,1|1,0,1,1|10")
+ TT_LINE("X,X,0,1,1,1,1,1,1|1,1,0,0|10")
+ TT_LINE("X,0,1,1,1,1,1,1,1|1,1,0,1|10")
+ TT_LINE("0,1,1,1,1,1,1,1,1|1,1,1,0|10")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74148_GATE, 9, 5, "")
+{
+ TT_HEAD("EI,0,1,2,3,4,5,6,7|A2,A1,A0,GS,EO")
+ TT_LINE( "1,X,X,X,X,X,X,X,X|1,1,1,1,1|10")
+ TT_LINE( "0,1,1,1,1,1,1,1,1|1,1,1,1,0|10")
+ TT_LINE( "0,X,X,X,X,X,X,X,0|0,0,0,0,1|10")
+ TT_LINE( "0,X,X,X,X,X,X,0,1|0,0,1,0,1|10")
+ TT_LINE( "0,X,X,X,X,X,0,1,1|0,1,0,0,1|10")
+ TT_LINE( "0,X,X,X,X,0,1,1,1|0,1,1,0,1|10")
+ TT_LINE( "0,X,X,X,0,1,1,1,1|1,0,0,0,1|10")
+ TT_LINE( "0,X,X,0,1,1,1,1,1|1,0,1,0,1|10")
+ TT_LINE( "0,X,0,1,1,1,1,1,1|1,1,0,0,1|10")
+ TT_LINE( "0,0,1,1,1,1,1,1,1|1,1,1,0,1|10")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74151_GATE, 12, 2, "")
+{
+ TT_HEAD("C,B,A,G,D0,D1,D2,D3,D4,D5,D6,D7|Y,W")
+ TT_LINE( "X,X,X,1,X,X,X,X,X,X,X,X|0,1|12,10")
+ TT_LINE( "0,0,0,0,1,X,X,X,X,X,X,X|1,0|12,10")
+ TT_LINE( "0,0,0,0,0,X,X,X,X,X,X,X|0,1|12,10")
+ TT_LINE( "0,0,1,0,X,1,X,X,X,X,X,X|1,0|12,10")
+ TT_LINE( "0,0,1,0,X,0,X,X,X,X,X,X|0,1|12,10")
+ TT_LINE( "0,1,0,0,X,X,1,X,X,X,X,X|1,0|12,10")
+ TT_LINE( "0,1,0,0,X,X,0,X,X,X,X,X|0,1|12,10")
+ TT_LINE( "0,1,1,0,X,X,X,1,X,X,X,X|1,0|12,10")
+ TT_LINE( "0,1,1,0,X,X,X,0,X,X,X,X|0,1|12,10")
+ TT_LINE( "1,0,0,0,X,X,X,X,1,X,X,X|1,0|12,10")
+ TT_LINE( "1,0,0,0,X,X,X,X,0,X,X,X|0,1|12,10")
+ TT_LINE( "1,0,1,0,X,X,X,X,X,1,X,X|1,0|12,10")
+ TT_LINE( "1,0,1,0,X,X,X,X,X,0,X,X|0,1|12,10")
+ TT_LINE( "1,1,0,0,X,X,X,X,X,X,1,X|1,0|12,10")
+ TT_LINE( "1,1,0,0,X,X,X,X,X,X,0,X|0,1|12,10")
+ TT_LINE( "1,1,1,0,X,X,X,X,X,X,X,1|1,0|12,10")
+ TT_LINE( "1,1,1,0,X,X,X,X,X,X,X,0|0,1|12,10")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74155A_GATE, 4, 4, "")
+{
+ TT_HEAD("B,A,G,C|Y0,Y1,Y2,Y3")
+ TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
+ TT_LINE("X,X,0,0|1,1,1,1|13,13,13,13")
+ TT_LINE("0,0,0,1|0,1,1,1|13,13,13,13")
+ TT_LINE("0,1,0,1|1,0,1,1|13,13,13,13")
+ TT_LINE("1,0,0,1|1,1,0,1|13,13,13,13")
+ TT_LINE("1,1,0,1|1,1,1,0|13,13,13,13")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74155B_GATE, 4, 4, "")
+{
+ TT_HEAD("B,A,G,C|Y0,Y1,Y2,Y3")
+ TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
+ TT_LINE("X,X,0,1|1,1,1,1|13,13,13,13")
+ TT_LINE("0,0,0,0|0,1,1,1|13,13,13,13")
+ TT_LINE("0,1,0,0|1,0,1,1|13,13,13,13")
+ TT_LINE("1,0,0,0|1,1,0,1|13,13,13,13")
+ TT_LINE("1,1,0,0|1,1,1,0|13,13,13,13")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74156A_GATE, 4, 4, "")
+{
+ TT_HEAD("B,A,G,C|Y0,Y1,Y2,Y3")
+ TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
+ TT_LINE("X,X,0,0|1,1,1,1|13,13,13,13")
+ TT_LINE("0,0,0,1|0,1,1,1|13,13,13,13")
+ TT_LINE("0,1,0,1|1,0,1,1|13,13,13,13")
+ TT_LINE("1,0,0,1|1,1,0,1|13,13,13,13")
+ TT_LINE("1,1,0,1|1,1,1,0|13,13,13,13")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_74156B_GATE, 4, 4, "")
+{
+ TT_HEAD("B,A,G,C|Y0,Y1,Y2,Y3")
+ TT_LINE("X,X,1,X|1,1,1,1|13,13,13,13")
+ TT_LINE("X,X,0,1|1,1,1,1|13,13,13,13")
+ TT_LINE("0,0,0,0|0,1,1,1|13,13,13,13")
+ TT_LINE("0,1,0,0|1,0,1,1|13,13,13,13")
+ TT_LINE("1,0,0,0|1,1,0,1|13,13,13,13")
+ TT_LINE("1,1,0,0|1,1,1,0|13,13,13,13")
+ // Open Collector
+ TT_FAMILY("74XXOC")
+}
+
+static TRUTH_TABLE(TTL_74157_GATE, 4, 1, "")
+{
+ TT_HEAD("E,S,I,J|O")
+ TT_LINE("1,X,X,X|0|14")
+ TT_LINE("0,1,X,0|0|14")
+ TT_LINE("0,1,X,1|1|14")
+ TT_LINE("0,0,0,X|0|14")
+ TT_LINE("0,0,1,X|1|14")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74260_NOR, 5, 1, "+A,+B,+C,+D,+E,@VCC,@GND")
+{
+ TT_HEAD("A,B,C,D,E|Q")
+ TT_LINE("0,0,0,0,0|1|10")
+ TT_LINE("X,X,X,X,1|0|12")
+ TT_LINE("X,X,X,1,X|0|12")
+ TT_LINE("X,X,1,X,X|0|12")
+ TT_LINE("X,1,X,X,X|0|12")
+ TT_LINE("1,X,X,X,X|0|12")
+ TT_FAMILY("74XX")
+}
+
+// FIXME: We need "private" devices
+static TRUTH_TABLE(TTL_74279A, 3, 1, "")
+{
+ TT_HEAD("S,R,_Q|Q")
+ TT_LINE("0,X,X|1|22")
+ TT_LINE("1,0,X|0|27")
+ TT_LINE("1,1,0|0|27")
+ TT_LINE("1,1,1|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74279B, 4, 1, "")
+{
+ TT_HEAD("S1,S2,R,_Q|Q")
+ TT_LINE("0,X,X,X|1|22")
+ TT_LINE("X,0,X,X|1|22")
+ TT_LINE("1,1,0,X|0|27")
+ TT_LINE("1,1,1,0|0|27")
+ TT_LINE("1,1,1,1|1|22")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_74368_GATE, 5, 4, "")
+{
+ TT_HEAD("OE,A1,A2,A3,A4|Y1,Y2,Y3,Y4")
+ TT_LINE("1,X,X,X,X|0,0,0,0|12")
+ TT_LINE("0,0,0,0,0|1,1,1,1|12")
+ TT_LINE("0,0,0,0,1|1,1,1,0|12")
+ TT_LINE("0,0,0,1,0|1,1,0,1|12")
+ TT_LINE("0,0,0,1,1|1,1,0,0|12")
+ TT_LINE("0,0,1,0,0|1,0,1,1|12")
+ TT_LINE("0,0,1,0,1|1,0,1,0|12")
+ TT_LINE("0,0,1,1,0|1,0,0,1|12")
+ TT_LINE("0,0,1,1,1|1,0,0,0|12")
+ TT_LINE("0,1,0,0,0|0,1,1,1|12")
+ TT_LINE("0,1,0,0,1|0,1,1,0|12")
+ TT_LINE("0,1,0,1,0|0,1,0,1|12")
+ TT_LINE("0,1,0,1,1|0,1,0,0|12")
+ TT_LINE("0,1,1,0,0|0,0,1,1|12")
+ TT_LINE("0,1,1,0,1|0,0,1,0|12")
+ TT_LINE("0,1,1,1,0|0,0,0,1|12")
+ TT_LINE("0,1,1,1,1|0,0,0,0|12")
+ TT_FAMILY("74XX")
+}
+
+static TRUTH_TABLE(TTL_9312, 12, 2,
+ "+A,+B,+C,+G,+D0,+D1,+D2,+D3,+D4,+D5,+D6,+D7,@VCC,@GND")
+{
+ TT_HEAD(" C, B, A, G,D0,D1,D2,D3,D4,D5,D6,D7| Y,YQ")
+ TT_LINE(" X, X, X, 1, X, X, X, X, X, X, X, X| 0, 1|33,19")
+ TT_LINE(" 0, 0, 0, 0, 0, X, X, X, X, X, X, X| 0, 1|33,28")
+ TT_LINE(" 0, 0, 0, 0, 1, X, X, X, X, X, X, X| 1, 0|33,28")
+ TT_LINE(" 0, 0, 1, 0, X, 0, X, X, X, X, X, X| 0, 1|33,28")
+ TT_LINE(" 0, 0, 1, 0, X, 1, X, X, X, X, X, X| 1, 0|33,28")
+ TT_LINE(" 0, 1, 0, 0, X, X, 0, X, X, X, X, X| 0, 1|33,28")
+ TT_LINE(" 0, 1, 0, 0, X, X, 1, X, X, X, X, X| 1, 0|33,28")
+ TT_LINE(" 0, 1, 1, 0, X, X, X, 0, X, X, X, X| 0, 1|33,28")
+ TT_LINE(" 0, 1, 1, 0, X, X, X, 1, X, X, X, X| 1, 0|33,28")
+ TT_LINE(" 1, 0, 0, 0, X, X, X, X, 0, X, X, X| 0, 1|33,28")
+ TT_LINE(" 1, 0, 0, 0, X, X, X, X, 1, X, X, X| 1, 0|33,28")
+ TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 0, X, X| 0, 1|33,28")
+ TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 1, X, X| 1, 0|33,28")
+ TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 0, X| 0, 1|33,28")
+ TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 1, X| 1, 0|33,28")
+ TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 0| 0, 1|33,28")
+ TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 1| 1, 0|33,28")
+ TT_FAMILY("74XX")
+}
+
+NETLIST_START(ttl74xx_lib)
+{
+ NET_MODEL(
+ "DM7414 SCHMITT_TRIGGER(VTP=1.7 VTM=0.9 VI=4.35 RI=6.15k VOH=3.5 ROH=120 VOL=0.1 ROL=37.5 TPLH=15 TPHL=15)")
+ NET_MODEL(
+ "TTL_7414_GATE SCHMITT_TRIGGER(VTP=1.7 VTM=0.9 VI=4.35 RI=6.15k VOH=3.5 ROH=120 VOL=0.1 ROL=37.5 TPLH=15 TPHL=15)")
+ NET_MODEL(
+ "DM74LS14 SCHMITT_TRIGGER(VTP=1.6 VTM=0.8 VI=4.4 RI=19.3k VOH=3.45 ROH=130 VOL=0.1 ROL=31.2 TPLH=15 TPHL=15)")
+ // NET_MODEL("DM7414 FAMILY(IVL=0.16 IVH=0.4 OVL=0.1 OVH=0.05 ORL=10.0
+ // ORH=1.0e8)")
+
+ TRUTHTABLE_ENTRY(TTL_7400_NAND)
+ TRUTHTABLE_ENTRY(TTL_7402_NOR)
+ TRUTHTABLE_ENTRY(TTL_7404_INVERT)
+ TRUTHTABLE_ENTRY(TTL_7406_GATE)
+ TRUTHTABLE_ENTRY(TTL_7407_GATE)
+ TRUTHTABLE_ENTRY(TTL_7408_GATE)
+ TRUTHTABLE_ENTRY(TTL_7408_AND)
+ TRUTHTABLE_ENTRY(TTL_7410_NAND)
+ TRUTHTABLE_ENTRY(TTL_7410_GATE)
+ TRUTHTABLE_ENTRY(TTL_7411_AND)
+ TRUTHTABLE_ENTRY(TTL_7411_GATE)
+ TRUTHTABLE_ENTRY(TTL_7416_GATE)
+ TRUTHTABLE_ENTRY(TTL_7417_GATE)
+ TRUTHTABLE_ENTRY(TTL_7420_NAND)
+ TRUTHTABLE_ENTRY(TTL_7421_AND)
+ TRUTHTABLE_ENTRY(TTL_7425_NOR)
+ TRUTHTABLE_ENTRY(TTL_7427_NOR)
+ TRUTHTABLE_ENTRY(TTL_7430_NAND)
+ TRUTHTABLE_ENTRY(TTL_7432_OR)
+ TRUTHTABLE_ENTRY(TTL_7437_NAND)
+ TRUTHTABLE_ENTRY(TTL_7438_NAND)
+ TRUTHTABLE_ENTRY(TTL_7442)
+ TRUTHTABLE_ENTRY(TTL_7486_XOR)
+ TRUTHTABLE_ENTRY(TTL_74139_GATE)
+ TRUTHTABLE_ENTRY(TTL_74147_GATE)
+ TRUTHTABLE_ENTRY(TTL_74148_GATE)
+ TRUTHTABLE_ENTRY(TTL_74151_GATE)
+ TRUTHTABLE_ENTRY(TTL_74155A_GATE)
+ TRUTHTABLE_ENTRY(TTL_74155B_GATE)
+ TRUTHTABLE_ENTRY(TTL_74156A_GATE)
+ TRUTHTABLE_ENTRY(TTL_74156B_GATE)
+ TRUTHTABLE_ENTRY(TTL_74157_GATE)
+ TRUTHTABLE_ENTRY(TTL_74260_NOR)
+ TRUTHTABLE_ENTRY(TTL_74279A)
+ TRUTHTABLE_ENTRY(TTL_74279B)
+ TRUTHTABLE_ENTRY(TTL_74368_GATE)
+ TRUTHTABLE_ENTRY(TTL_9312)
+
+ LOCAL_LIB_ENTRY(TTL_7400_DIP)
+ LOCAL_LIB_ENTRY(TTL_7402_DIP)
+ LOCAL_LIB_ENTRY(TTL_7404_DIP)
+ LOCAL_LIB_ENTRY(TTL_7406_DIP)
+ LOCAL_LIB_ENTRY(TTL_7407_DIP)
+ LOCAL_LIB_ENTRY(TTL_7408_DIP)
+ LOCAL_LIB_ENTRY(TTL_7410_DIP)
+ LOCAL_LIB_ENTRY(TTL_7411_DIP)
+ LOCAL_LIB_ENTRY(TTL_7414_GATE)
+ LOCAL_LIB_ENTRY(TTL_74LS14_GATE)
+ LOCAL_LIB_ENTRY(TTL_7414_DIP)
+ LOCAL_LIB_ENTRY(TTL_74LS14_DIP)
+ LOCAL_LIB_ENTRY(TTL_7416_DIP)
+ LOCAL_LIB_ENTRY(TTL_7417_DIP)
+ LOCAL_LIB_ENTRY(TTL_7420_DIP)
+ LOCAL_LIB_ENTRY(TTL_7421_DIP)
+ LOCAL_LIB_ENTRY(TTL_7425_DIP)
+ LOCAL_LIB_ENTRY(TTL_7427_DIP)
+ LOCAL_LIB_ENTRY(TTL_7430_DIP)
+ LOCAL_LIB_ENTRY(TTL_7432_DIP)
+ LOCAL_LIB_ENTRY(TTL_7437_DIP)
+ LOCAL_LIB_ENTRY(TTL_7438_DIP)
+ LOCAL_LIB_ENTRY(TTL_7442_DIP)
+ LOCAL_LIB_ENTRY(TTL_7448_DIP)
+ LOCAL_LIB_ENTRY(TTL_7450_DIP)
+ LOCAL_LIB_ENTRY(TTL_7473_DIP)
+ LOCAL_LIB_ENTRY(TTL_7473A_DIP)
+ LOCAL_LIB_ENTRY(TTL_7474_DIP)
+ LOCAL_LIB_ENTRY(TTL_7475_DIP)
+ LOCAL_LIB_ENTRY(TTL_7477_DIP)
+ LOCAL_LIB_ENTRY(TTL_7483_DIP)
+ LOCAL_LIB_ENTRY(TTL_7485_DIP)
+ LOCAL_LIB_ENTRY(TTL_7486_DIP)
+ LOCAL_LIB_ENTRY(TTL_7490_DIP)
+ LOCAL_LIB_ENTRY(TTL_7492_DIP)
+ LOCAL_LIB_ENTRY(TTL_7493_DIP)
+ LOCAL_LIB_ENTRY(TTL_7497_DIP)
+ LOCAL_LIB_ENTRY(TTL_74107_DIP)
+ LOCAL_LIB_ENTRY(TTL_74107A_DIP)
+ LOCAL_LIB_ENTRY(TTL_74113_DIP)
+ LOCAL_LIB_ENTRY(TTL_74113A_DIP)
+ LOCAL_LIB_ENTRY(TTL_74121_DIP)
+ LOCAL_LIB_ENTRY(TTL_74123_DIP)
+ LOCAL_LIB_ENTRY(TTL_9602_DIP)
+ LOCAL_LIB_ENTRY(TTL_74125_DIP)
+ LOCAL_LIB_ENTRY(TTL_74126_DIP)
+ LOCAL_LIB_ENTRY(TTL_74139_DIP)
+ LOCAL_LIB_ENTRY(TTL_74147_DIP)
+ LOCAL_LIB_ENTRY(TTL_74148_DIP)
+ LOCAL_LIB_ENTRY(TTL_74151_DIP)
+ LOCAL_LIB_ENTRY(TTL_74153_DIP)
+ LOCAL_LIB_ENTRY(TTL_74155_DIP)
+ LOCAL_LIB_ENTRY(TTL_74156_DIP)
+ LOCAL_LIB_ENTRY(TTL_74157_DIP)
+ LOCAL_LIB_ENTRY(TTL_74161_DIP)
+ LOCAL_LIB_ENTRY(TTL_74163_DIP)
+ LOCAL_LIB_ENTRY(TTL_74164_DIP)
+ LOCAL_LIB_ENTRY(TTL_74165_DIP)
+ LOCAL_LIB_ENTRY(TTL_74166_DIP)
+ LOCAL_LIB_ENTRY(TTL_74174_DIP)
+ LOCAL_LIB_ENTRY(TTL_74175_DIP)
+ LOCAL_LIB_ENTRY(TTL_74192_DIP)
+ LOCAL_LIB_ENTRY(TTL_74193_DIP)
+ LOCAL_LIB_ENTRY(TTL_74194_DIP)
+ LOCAL_LIB_ENTRY(TTL_74260_DIP)
+ LOCAL_LIB_ENTRY(TTL_74279_DIP)
+ LOCAL_LIB_ENTRY(TTL_74290_DIP)
+ LOCAL_LIB_ENTRY(TTL_74293_DIP)
+ LOCAL_LIB_ENTRY(TTL_74365_DIP)
+ LOCAL_LIB_ENTRY(TTL_74368_DIP)
+ LOCAL_LIB_ENTRY(TTL_74377_DIP)
+ LOCAL_LIB_ENTRY(TTL_74378_DIP)
+ LOCAL_LIB_ENTRY(TTL_74379_DIP)
+ LOCAL_LIB_ENTRY(TTL_74393_DIP)
+ LOCAL_LIB_ENTRY(SN74LS629_DIP)
+ LOCAL_LIB_ENTRY(TTL_9310_DIP)
+ LOCAL_LIB_ENTRY(TTL_9312_DIP)
+ LOCAL_LIB_ENTRY(TTL_9314_DIP)
+ LOCAL_LIB_ENTRY(TTL_9316_DIP)
+ LOCAL_LIB_ENTRY(TTL_9321_DIP)
+ LOCAL_LIB_ENTRY(TTL_9322_DIP)
+ LOCAL_LIB_ENTRY(TTL_9334_DIP)
+ LOCAL_LIB_ENTRY(TTL_8277_DIP)
+ LOCAL_LIB_ENTRY(TTL_AM2847_DIP)
+}