diff options
Diffstat (limited to 'src/lib/netlist/macro/nlm_ttl74xx.cpp')
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.cpp | 114 |
1 files changed, 83 insertions, 31 deletions
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp index ed74a8e305c..7cc32c573b0 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.cpp +++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp @@ -5,34 +5,6 @@ #include "devices/nld_truthtable.h" #include "devices/nld_system.h" -/* - * DM7416: Hex Inverting Buffers with - * High Voltage Open-Collector Outputs - * - */ - -NETLIST_START(TTL_7416_DIP) - TTL_7416_GATE(s1) - TTL_7416_GATE(s2) - TTL_7416_GATE(s3) - TTL_7416_GATE(s4) - TTL_7416_GATE(s5) - TTL_7416_GATE(s6) - - DUMMY_INPUT(GND) - DUMMY_INPUT(VCC) - - DIPPINS( /* +--------------+ */ - s1.A, /* A1 |1 ++ 14| VCC */ VCC.I, - s1.Q, /* Y1 |2 13| A6 */ s6.A, - s2.A, /* A2 |3 12| Y6 */ s6.Q, - s2.Q, /* Y2 |4 7416 11| A5 */ s5.A, - s3.A, /* A3 |5 10| Y5 */ s5.Q, - s3.Q, /* Y3 |6 9| A4 */ s4.A, - GND.I, /* GND |7 8| Y4 */ s4.Q - /* +--------------+ */ - ) -NETLIST_END() /* * DM7400: Quad 2-Input NAND Gates @@ -73,6 +45,73 @@ NETLIST_START(TTL_7400_DIP) ) NETLIST_END() +/* + * DM7404: Hex Inverting Gates + * _ + * Y = A + * +---++---+ + * | A || Y | + * +===++===+ + * | 0 || 1 | + * | 1 || 0 | + * +---++---+ + * + * Naming conventions follow National Semiconductor datasheet + * + */ + +NETLIST_START(TTL_7404_DIP) + TTL_7404_GATE(s1) + TTL_7404_GATE(s2) + TTL_7404_GATE(s3) + TTL_7404_GATE(s4) + TTL_7404_GATE(s5) + TTL_7404_GATE(s6) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + + DIPPINS( /* +--------------+ */ + s1.A, /* A1 |1 ++ 14| VCC */ VCC.I, + s1.Q, /* Y1 |2 13| A6 */ s6.A, + s2.A, /* A2 |3 12| Y6 */ s6.Q, + s2.Q, /* Y2 |4 7404 11| A5 */ s5.A, + s3.A, /* A3 |5 10| Y5 */ s5.Q, + s3.Q, /* Y3 |6 9| A4 */ s4.A, + GND.I, /* GND |7 8| Y4 */ s4.Q + /* +--------------+ */ + ) +NETLIST_END() + +/* + * DM7416: Hex Inverting Buffers with + * High Voltage Open-Collector Outputs + * + */ + +NETLIST_START(TTL_7416_DIP) + TTL_7416_GATE(s1) + TTL_7416_GATE(s2) + TTL_7416_GATE(s3) + TTL_7416_GATE(s4) + TTL_7416_GATE(s5) + TTL_7416_GATE(s6) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + + DIPPINS( /* +--------------+ */ + s1.A, /* A1 |1 ++ 14| VCC */ VCC.I, + s1.Q, /* Y1 |2 13| A6 */ s6.A, + s2.A, /* A2 |3 12| Y6 */ s6.Q, + s2.Q, /* Y2 |4 7416 11| A5 */ s5.A, + s3.A, /* A3 |5 10| Y5 */ s5.Q, + s3.Q, /* Y3 |6 9| A4 */ s4.A, + GND.I, /* GND |7 8| Y4 */ s4.Q + /* +--------------+ */ + ) +NETLIST_END() + NETLIST_START(TTL74XX_lib) TRUTHTABLE_START(TTL_7400_GATE, 2, 1, 0, "") @@ -80,7 +119,6 @@ NETLIST_START(TTL74XX_lib) TT_LINE("0,X|1|22") TT_LINE("X,0|1|22") TT_LINE("1,1|0|15") - /* Open Collector */ TT_FAMILY("74XX") TRUTHTABLE_END() @@ -89,7 +127,20 @@ NETLIST_START(TTL74XX_lib) TT_LINE("0,X|1|22") TT_LINE("X,0|1|22") TT_LINE("1,1|0|15") - /* Open Collector */ + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(TTL_7404_GATE, 1, 1, 0, "") + TT_HEAD(" A | Q ") + TT_LINE(" 0 | 1 |22") + TT_LINE(" 1 | 0 |15") + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(TTL_7404_INVERT, 1, 1, 0, "A") + TT_HEAD(" A | Q ") + TT_LINE(" 0 | 1 |22") + TT_LINE(" 1 | 0 |15") TT_FAMILY("74XX") TRUTHTABLE_END() @@ -101,6 +152,7 @@ NETLIST_START(TTL74XX_lib) TT_FAMILY("74XXOC") TRUTHTABLE_END() - LOCAL_LIB_ENTRY(TTL_7416_DIP) LOCAL_LIB_ENTRY(TTL_7400_DIP) + LOCAL_LIB_ENTRY(TTL_7404_DIP) + LOCAL_LIB_ENTRY(TTL_7416_DIP) NETLIST_END() |