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Diffstat (limited to 'src/lib/netlist/devices/nld_74164.cpp')
-rw-r--r--src/lib/netlist/devices/nld_74164.cpp158
1 files changed, 81 insertions, 77 deletions
diff --git a/src/lib/netlist/devices/nld_74164.cpp b/src/lib/netlist/devices/nld_74164.cpp
index ed401603181..878e333df0f 100644
--- a/src/lib/netlist/devices/nld_74164.cpp
+++ b/src/lib/netlist/devices/nld_74164.cpp
@@ -7,106 +7,110 @@
* implementing this was simple.
*
*/
+/*****************************************************************************
+
+ 5/74164 8-bit parallel-out serial shift registers
+
+***********************************************************************
+
+ Connection Diagram:
+ ___ ___
+ A 1 |* u | 14 Vcc
+ B 2 | | 13 QH
+ QA 3 | | 12 QG
+ QB 4 | | 11 QF
+ QC 5 | | 10 QE
+ QD 6 | | 9 *Clear
+ GND 7 |_______| 8 Clock
+
+***********************************************************************
+ Function Table:
+ +-------------------------+----------------+
+ | Inputs | Outputs* |
+ +-------+-------+---------+----------------+
+ | Clear | Clock | A B | QA QB ... QH |
+ +-------+-------+---------+----------------+
+ | L | X | X X | L L L |
+ | H | L | X X | QA0 QB0 QH0 |
+ | H | ^ | H H | H QAn QGn |
+ | H | ^ | L X | L QAn QGn |
+ | H | ^ | X L | L QAn QGn |
+ +-------+-------+---------+----------------+
+
+ H = High Level (steady state)
+ L = Low Level (steady state)
+ X = Don't Care
+ ^ = Transition from low to high level
+ QA0, QB0 ... QH0 = The level of QA, QB ... QH before the indicated steady-state input conditions were established.
+ QAn, QGn = The level of QA or QG before the most recent ^ transition of the clock; indicates a 1 bit shift.
+
+**********************************************************************/
+
+#include "nl_base.h"
+
+// FIXME: clk input to be separated - only falling edge relevant
+
+namespace netlist::devices {
-#include "nld_74164.h"
-#include "netlist/nl_base.h"
-#include "nlid_system.h"
-
-namespace netlist
-{
- namespace devices
- {
NETLIB_OBJECT(74164)
{
NETLIB_CONSTRUCTOR(74164)
- , m_A(*this, "A")
- , m_B(*this, "B")
- , m_CLRQ(*this, "CLRQ")
- , m_CLK(*this, "CLK")
+ , m_AB(*this, {"A", "B"}, NETLIB_DELEGATE(ab))
+ , m_CLRQ(*this, "CLRQ", NETLIB_DELEGATE(clrq))
+ , m_CLK(*this, "CLK", NETLIB_DELEGATE(clk))
, m_cnt(*this, "m_cnt", 0)
- , m_last_CLK(*this, "m_last_CLK", 0)
- , m_Q(*this, {{"QA", "QB", "QC", "QD", "QE", "QF", "QG", "QH"}})
+ , m_ab(*this, "m_ab", 0)
+ , m_Q(*this, {"QA", "QB", "QC", "QD", "QE", "QF", "QG", "QH"})
, m_power_pins(*this)
{
}
- NETLIB_RESETI();
- NETLIB_UPDATEI();
-
- protected:
- logic_input_t m_A;
- logic_input_t m_B;
- logic_input_t m_CLRQ;
- logic_input_t m_CLK;
-
- state_var<unsigned> m_cnt;
- state_var<unsigned> m_last_CLK;
-
- object_array_t<logic_output_t, 8> m_Q;
- nld_power_pins m_power_pins;
- };
-
- NETLIB_OBJECT_DERIVED(74164_dip, 74164)
- {
- NETLIB_CONSTRUCTOR_DERIVED(74164_dip, 74164)
- {
- register_subalias("1", m_A);
- register_subalias("2", m_B);
- register_subalias("3", m_Q[0]);
- register_subalias("4", m_Q[1]);
- register_subalias("5", m_Q[2]);
- register_subalias("6", m_Q[3]);
- register_subalias("7", "A.GND");
-
- register_subalias("8", m_CLK);
- register_subalias("9", m_CLRQ);
- register_subalias("10", m_Q[4]);
- register_subalias("11", m_Q[5]);
- register_subalias("12", m_Q[6]);
- register_subalias("13", m_Q[7]);
- register_subalias("14", "A.VCC");
-
- connect("A.GND", "B.GND");
- connect("A.VCC", "B.VCC");
-
- }
- };
-
- NETLIB_RESET(74164)
- {
- m_cnt = 0;
- m_last_CLK = 0;
- }
-
- NETLIB_UPDATE(74164)
- {
- if (!m_CLRQ())
+ private:
+ NETLIB_RESETI()
{
+ m_CLK.set_state(logic_t::STATE_INP_LH);
m_cnt = 0;
}
- else if (m_CLK() && !m_last_CLK)
+
+ NETLIB_HANDLERI(clrq)
{
- m_cnt = (m_cnt << 1) & 0xfe;
- if (m_A() && m_B())
+ if (m_CLRQ())
{
- m_cnt |= 0x01;
+ m_CLK.activate_lh();
}
else
{
- m_cnt &= 0xfe;
+ m_CLK.inactivate();
+ if (m_cnt != 0)
+ {
+ m_cnt = 0;
+ m_Q.push(0, NLTIME_FROM_NS(30));
+ }
}
}
- m_last_CLK = m_CLK();
+ NETLIB_HANDLERI(clk)
+ {
+ m_cnt = (m_cnt << 1) | m_ab;
+ m_Q.push(m_cnt, NLTIME_FROM_NS(30));
+ }
- for (std::size_t i=0; i<8; i++)
+ NETLIB_HANDLERI(ab)
{
- m_Q[i].push((m_cnt >> i) & 1, NLTIME_FROM_NS(30));
+ m_ab = static_cast<unsigned>((m_AB() == 3) ? 1 : 0);
}
- }
+
+ object_array_t<logic_input_t, 2> m_AB;
+ logic_input_t m_CLRQ;
+ logic_input_t m_CLK;
+
+ state_var<unsigned> m_cnt;
+ state_var<unsigned> m_ab;
+
+ object_array_t<logic_output_t, 8> m_Q;
+ nld_power_pins m_power_pins;
+ };
NETLIB_DEVICE_IMPL(74164, "TTL_74164", "+A,+B,+CLRQ,+CLK,@VCC,@GND")
- NETLIB_DEVICE_IMPL(74164_dip, "TTL_74164_DIP", "")
- } //namespace devices
-} // namespace netlist
+} // namespace netlist::devices