diff options
Diffstat (limited to 'src/emu')
33 files changed, 292 insertions, 299 deletions
diff --git a/src/emu/bus/a2bus/ezcgi.c b/src/emu/bus/a2bus/ezcgi.c index d7a9cf3d469..3c3a937b781 100644 --- a/src/emu/bus/a2bus/ezcgi.c +++ b/src/emu/bus/a2bus/ezcgi.c @@ -43,7 +43,7 @@ MACHINE_CONFIG_END #define MSX2_VISIBLE_YBORDER_PIXELS 14 * 2 MACHINE_CONFIG_FRAGMENT( ezcgi9938 ) - MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM + MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9938_device, tms_irq_w)) MCFG_SCREEN_ADD(SCREEN_TAG, RASTER) @@ -57,7 +57,7 @@ MACHINE_CONFIG_FRAGMENT( ezcgi9938 ) MACHINE_CONFIG_END MACHINE_CONFIG_FRAGMENT( ezcgi9958 ) - MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM + MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9958_device, tms_irq_w)) MCFG_SCREEN_ADD(SCREEN_TAG, RASTER) @@ -311,4 +311,3 @@ WRITE_LINE_MEMBER( a2bus_ezcgi_9958_device::tms_irq_w ) lower_slot_irq(); } } - diff --git a/src/emu/bus/scsi/omti5100.c b/src/emu/bus/scsi/omti5100.c index a3f00560f73..0d7ed1567ab 100644 --- a/src/emu/bus/scsi/omti5100.c +++ b/src/emu/bus/scsi/omti5100.c @@ -20,8 +20,8 @@ const rom_entry *omti5100_device::device_rom_region() const omti5100_device::omti5100_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : scsihd_device(mconfig, OMTI5100, "OMTI 5100", tag, owner, clock, "omti5100", __FILE__), - m_image0(*this, "image0"), - m_image1(*this, "image1") + m_image0(*this, "image0"), + m_image1(*this, "image1") { } diff --git a/src/emu/cpu/hmcs40/hmcs40.c b/src/emu/cpu/hmcs40/hmcs40.c index c279f07aec0..da878129069 100644 --- a/src/emu/cpu/hmcs40/hmcs40.c +++ b/src/emu/cpu/hmcs40/hmcs40.c @@ -187,7 +187,7 @@ void hmcs40_cpu_device::device_start() m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hmcs40_cpu_device::simple_timer_cb), this)); reset_prescaler(); - + m_read_r0.resolve_safe(0); m_read_r1.resolve_safe(0); m_read_r2.resolve_safe(0); @@ -196,7 +196,7 @@ void hmcs40_cpu_device::device_start() m_read_r5.resolve_safe(0); m_read_r6.resolve_safe(0); m_read_r7.resolve_safe(0); - + m_write_r0.resolve_safe(); m_write_r1.resolve_safe(); m_write_r2.resolve_safe(); @@ -290,15 +290,15 @@ void hmcs40_cpu_device::device_reset() { m_pc = m_pcmask; m_prev_op = m_op = 0; - + // clear i/o m_d = m_polarity; for (int i = 0; i < 16; i++) hmcs40_cpu_device::write_d(i, 0); - + for (int i = 0; i < 8; i++) hmcs40_cpu_device::write_r(i, 0); - + // clear interrupts m_cf = 0; m_ie = 0; @@ -316,7 +316,7 @@ UINT8 hmcs40_cpu_device::read_r(int index) { index &= 7; UINT8 inp = 0; - + switch (index) { case 0: inp = m_read_r0(index, 0xff); break; @@ -328,7 +328,7 @@ UINT8 hmcs40_cpu_device::read_r(int index) case 6: inp = m_read_r6(index, 0xff); break; case 7: inp = m_read_r7(index, 0xff); break; } - + return ((inp ^ m_polarity) | m_r[index]) & 0xf; } @@ -337,7 +337,7 @@ void hmcs40_cpu_device::write_r(int index, UINT8 data) index &= 7; data = (data ^ m_polarity) & 0xf; m_r[index] = data; - + switch (index) { case 0: m_write_r0(index, data, 0xff); break; @@ -354,7 +354,7 @@ void hmcs40_cpu_device::write_r(int index, UINT8 data) int hmcs40_cpu_device::read_d(int index) { index &= 15; - + return ((m_read_d(index, 0xffff) ^ m_polarity) | m_d) >> index & 1; } @@ -362,7 +362,7 @@ void hmcs40_cpu_device::write_d(int index, int state) { index &= 15; state = (((state) ? 1 : 0) ^ m_polarity) & 1; - + m_d = (m_d & ~(1 << index)) | state << index; m_write_d(index, m_d, 0xffff); } @@ -374,7 +374,7 @@ void hmcs40_cpu_device::write_d(int index, int state) UINT8 hmcs43_cpu_device::read_r(int index) { index &= 7; - + if (index >= 2) logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc); @@ -394,7 +394,7 @@ void hmcs43_cpu_device::write_r(int index, UINT8 data) int hmcs43_cpu_device::read_d(int index) { index &= 15; - + if (index >= 4) logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc); @@ -408,10 +408,10 @@ int hmcs43_cpu_device::read_d(int index) UINT8 hmcs44_cpu_device::read_r(int index) { index &= 7; - + if (index >= 6) logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc); - + return hmcs40_cpu_device::read_r(index); } @@ -432,10 +432,10 @@ void hmcs44_cpu_device::write_r(int index, UINT8 data) UINT8 hmcs45_cpu_device::read_r(int index) { index &= 7; - + if (index >= 6) logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc); - + return hmcs40_cpu_device::read_r(index); } @@ -460,10 +460,10 @@ void hmcs40_cpu_device::do_interrupt() m_icount--; push_stack(); m_ie = 0; - + // line 0/1 for external interrupt, let's use 2 for t/c interrupt int line = (m_iri) ? m_eint_line : 2; - + // vector $3f, on page 0(timer/counter), or page 1(external) // external interrupt has priority over t/c interrupt m_pc = 0x3f | (m_iri ? 0x40 : 0); @@ -480,7 +480,7 @@ void hmcs40_cpu_device::execute_set_input(int line, int state) if (line != 0 && line != 1) return; state = (state) ? 1 : 0; - + // external interrupt request on rising edge if (state && !m_int[line]) { @@ -490,12 +490,12 @@ void hmcs40_cpu_device::execute_set_input(int line, int state) m_iri = 1; m_if[line] = 1; } - + // clock tc if it is in counter mode if (m_cf && line == 1) increment_tc(); } - + m_int[line] = state; } @@ -511,7 +511,7 @@ TIMER_CALLBACK_MEMBER( hmcs40_cpu_device::simple_timer_cb ) // timer prescaler overflow if (!m_cf) increment_tc(); - + reset_prescaler(); } @@ -519,7 +519,7 @@ void hmcs40_cpu_device::increment_tc() { // increment timer/counter m_tc = (m_tc + 1) & 0xf; - + // timer interrupt request on overflow if (m_tc == 0 && !m_tf) { @@ -554,7 +554,7 @@ void hmcs40_cpu_device::execute_run() while (m_icount > 0) { m_icount--; - + // LPU is handled 1 cycle later if ((m_prev_op & 0x3e0) == 0x340) { @@ -571,7 +571,7 @@ void hmcs40_cpu_device::execute_run() // remember previous state m_prev_op = m_op; m_prev_pc = m_pc; - + // fetch next opcode debugger_instruction_hook(this, m_pc); m_op = m_program->read_word(m_pc << 1) & 0x3ff; @@ -582,7 +582,7 @@ void hmcs40_cpu_device::execute_run() switch (m_op) { /* 0x000 */ - + case 0x000: case 0x001: case 0x002: case 0x003: op_xsp(); break; case 0x004: case 0x005: case 0x006: case 0x007: @@ -602,7 +602,7 @@ void hmcs40_cpu_device::execute_run() op_am(); break; case 0x03c: op_lta(); break; - + case 0x040: op_lxa(); break; case 0x045: @@ -626,7 +626,7 @@ void hmcs40_cpu_device::execute_run() case 0x070: case 0x071: case 0x072: case 0x073: case 0x074: case 0x075: case 0x076: case 0x077: case 0x078: case 0x079: case 0x07a: case 0x07b: case 0x07c: case 0x07d: case 0x07e: case 0x07f: op_lai(); break; - + case 0x080: case 0x081: case 0x082: case 0x083: case 0x084: case 0x085: case 0x086: case 0x087: case 0x088: case 0x089: case 0x08a: case 0x08b: case 0x08c: case 0x08d: case 0x08e: case 0x08f: op_ai(); break; @@ -655,10 +655,10 @@ void hmcs40_cpu_device::execute_run() case 0x0f0: case 0x0f1: case 0x0f2: case 0x0f3: case 0x0f4: case 0x0f5: case 0x0f6: case 0x0f7: case 0x0f8: case 0x0f9: case 0x0fa: case 0x0fb: case 0x0fc: case 0x0fd: case 0x0fe: case 0x0ff: op_xamr(); break; - - + + /* 0x100 */ - + case 0x110: case 0x111: op_lmaiy(); break; case 0x114: case 0x115: @@ -682,7 +682,7 @@ void hmcs40_cpu_device::execute_run() case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177: case 0x178: case 0x179: case 0x17a: case 0x17b: case 0x17c: case 0x17d: case 0x17e: case 0x17f: op_lti(); break; - + case 0x1a0: op_tif1(); break; case 0x1a1: @@ -706,7 +706,7 @@ void hmcs40_cpu_device::execute_run() /* 0x200 */ - + case 0x200: case 0x201: case 0x202: case 0x203: op_tm(); break; case 0x204: case 0x205: case 0x206: case 0x207: @@ -728,7 +728,7 @@ void hmcs40_cpu_device::execute_run() op_alem(); break; case 0x23c: op_lat(); break; - + case 0x240: op_laspx(); break; case 0x244: @@ -804,8 +804,8 @@ void hmcs40_cpu_device::execute_run() case 0x3f0: case 0x3f1: case 0x3f2: case 0x3f3: case 0x3f4: case 0x3f5: case 0x3f6: case 0x3f7: case 0x3f8: case 0x3f9: case 0x3fa: case 0x3fb: case 0x3fc: case 0x3fd: case 0x3fe: case 0x3ff: op_cal(); break; - - + + default: op_illegal(); break; } /* big switch */ diff --git a/src/emu/cpu/hmcs40/hmcs40.h b/src/emu/cpu/hmcs40/hmcs40.h index 6dd5166df87..a7e34173306 100644 --- a/src/emu/cpu/hmcs40/hmcs40.h +++ b/src/emu/cpu/hmcs40/hmcs40.h @@ -182,7 +182,7 @@ protected: int m_eint_line; // which input_line caused an interrupt emu_timer *m_timer; int m_icount; - + UINT16 m_pc; // Program Counter UINT16 m_prev_pc; UINT8 m_page; // LPU prepared page @@ -213,7 +213,7 @@ protected: // misc internal helpers void increment_pc(); - + UINT8 ram_r(); void ram_w(UINT8 data); void pop_stack(); diff --git a/src/emu/cpu/hmcs40/hmcs40d.c b/src/emu/cpu/hmcs40/hmcs40d.c index e16fa8ed618..d01382e0b8d 100644 --- a/src/emu/cpu/hmcs40/hmcs40d.c +++ b/src/emu/cpu/hmcs40/hmcs40d.c @@ -3,7 +3,7 @@ /* Hitachi HMCS40 MCU family disassembler - + NOTE: start offset(basepc) is $3F, not 0 */ @@ -92,42 +92,42 @@ static const UINT8 hmcs40_mnemonic[0x400] = { /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ /* 0x000 */ - mNOP, mXSP, mXSP, mXSP, mSEM, mSEM, mSEM, mSEM, mLAM, mLAM, mLAM, mLAM, m, m, m, m, + mNOP, mXSP, mXSP, mXSP, mSEM, mSEM, mSEM, mSEM, mLAM, mLAM, mLAM, mLAM, m, m, m, m, mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY, - mLBM, mLBM, mLBM, mLBM, mBLEM, m, m, m, m, m, m, m, m, m, m, m, - mAMC, m, m, m, mAM, m, m, m, m, m, m, m, mLTA, m, m, m, + mLBM, mLBM, mLBM, mLBM, mBLEM, m, m, m, m, m, m, m, m, m, m, m, + mAMC, m, m, m, mAM, m, m, m, m, m, m, m, mLTA, m, m, m, /* 0x040 */ mLXA, m, m, m, m, mDAS, mDAA, m, m, m, m, m, mREC, m, m, mSEC, - mLYA, m, m, m, mIY, m, m, m, mAYY, m, m, m, m, m, m, m, - mLBA, m, m, m, mIB, m, m, m, m, m, m, m, m, m, m, m, + mLYA, m, m, m, mIY, m, m, m, mAYY, m, m, m, m, m, m, m, + mLBA, m, m, m, mIB, m, m, m, m, m, m, m, m, m, m, m, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, /* 0x080 */ mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, - mSED, m, m, m, mTD, m, m, m, m, m, m, m, m, m, m, m, - mSEIF1,mSECF, mSEIF0,m, mSEIE, mSETF, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mSED, m, m, m, mTD, m, m, m, m, m, m, m, m, m, m, m, + mSEIF1,mSECF, mSEIF0,m, mSEIE, mSETF, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x0c0 */ - mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, m, m, m, m, m, m, m, m, + mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, m, m, m, m, m, m, m, m, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, - mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, m, m, m, m, m, m, m, m, + mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, m, m, m, m, m, m, m, m, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ /* 0x100 */ - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - mLMAIY,mLMAIY,m, m, mLMADY,mLMADY,m, m, mLAY, m, m, m, m, m, m, m, - mOR, m, m, m, mANEM, m, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mLMAIY,mLMAIY,m, m, mLMADY,mLMADY,m, m, mLAY, m, m, m, m, m, m, m, + mOR, m, m, m, mANEM, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x140 */ mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, /* 0x180 */ - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - mTIF1, mTI1, mTIF0, mTI0, m, mTTF, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mTIF1, mTI1, mTIF0, mTI0, m, mTTF, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x1c0 */ mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, @@ -136,42 +136,42 @@ static const UINT8 hmcs40_mnemonic[0x400] = /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ /* 0x200 */ - mTM, mTM, mTM, mTM, mREM, mREM, mREM, mREM, mXMA, mXMA, mXMA, mXMA, m, m, m, m, + mTM, mTM, mTM, mTM, mREM, mREM, mREM, mREM, mXMA, mXMA, mXMA, mXMA, m, m, m, m, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, - mXMB, mXMB, mXMB, mXMB, mROTR, mROTL, m, m, m, m, m, m, m, m, m, m, - mSMC, m, m, m, mALEM, m, m, m, m, m, m, m, mLAT, m, m, m, + mXMB, mXMB, mXMB, mXMB, mROTR, mROTL, m, m, m, m, m, m, m, m, m, m, + mSMC, m, m, m, mALEM, m, m, m, m, m, m, m, mLAT, m, m, m, /* 0x240 */ mLASPX,m, m, m, mNEGA, m, m, m, m, m, m, m, m, m, m, mTC, - mLASPY,m, m, m, mDY, m, m, m, mSYY, m, m, m, m, m, m, m, - mLAB, m, m, m, m, m, m, mDB, m, m, m, m, m, m, m, m, + mLASPY,m, m, m, mDY, m, m, m, mSYY, m, m, m, m, m, m, m, + mLAB, m, m, m, m, m, m, mDB, m, m, m, m, m, m, m, m, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, /* 0x280 */ mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, - mRED, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - mREIF1,mRECF, mREIF0,m, mREIE, mRETF, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mRED, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mREIF1,mRECF, mREIF0,m, mREIE, mRETF, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x2c0 */ - mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, m, m, m, m, m, m, m, m, + mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, m, m, m, m, m, m, m, m, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, - mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */ /* 0x300 */ - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - mCOMB, m, m, m, mBNEM, m, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + mCOMB, m, m, m, mBNEM, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x340 */ mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mP, mP, mP, mP, mP, mP, mP, mP, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x380 */ - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, - m, m, m, m, mRTNI, m, m, mRTN, m, m, m, m, m, m, m, m, - m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, + m, m, m, m, mRTNI, m, m, mRTN, m, m, m, m, m, m, m, m, + m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, /* 0x3c0 */ mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, @@ -188,7 +188,7 @@ CPU_DISASSEMBLE(hmcs40) char *dst = buffer; UINT8 instr = hmcs40_mnemonic[op]; INT8 bits = s_bits[instr]; - + // special case for (XY) opcode if (bits == 99) { @@ -202,12 +202,12 @@ CPU_DISASSEMBLE(hmcs40) else { dst += sprintf(dst, "%-6s ", s_mnemonics[instr]); - + // opcode parameter if (bits != 0) { UINT8 param = op; - + // reverse bits if (bits < 0) { @@ -215,16 +215,16 @@ CPU_DISASSEMBLE(hmcs40) param >>= (8 + bits); bits = -bits; } - + param &= ((1 << bits) - 1); - + if (bits > 5) dst += sprintf(dst, "$%02X", param); else dst += sprintf(dst, "%d", param); } } - + int pos = s_next_pc[pc & 0x3f] & DASMFLAG_LENGTHMASK; return pos | s_flags[instr] | DASMFLAG_SUPPORTED; } diff --git a/src/emu/cpu/hmcs40/hmcs40op.inc b/src/emu/cpu/hmcs40/hmcs40op.inc index 9732d86f53f..1887c3c0105 100644 --- a/src/emu/cpu/hmcs40/hmcs40op.inc +++ b/src/emu/cpu/hmcs40/hmcs40op.inc @@ -73,19 +73,19 @@ void hmcs40_cpu_device::op_laspy() void hmcs40_cpu_device::op_xamr() { // XAMR m: Exchange A and MR(m) - + // determine MR(Memory Register) location UINT8 address = m_op & 0xf; - + // HMCS42: MR0 on file 0, MR4-MR15 on file 4 (there is no file 1-3) // HMCS43: MR0-MR3 on file 0-3, MR4-MR15 on file 4 if (m_family == FAMILY_HMCS42 || m_family == FAMILY_HMCS43) address |= (address < 4) ? (address << 4) : 0x40; - + // HMCS44/45/46/47: all on last file else address |= 0xf0; - + address &= m_datamask; UINT8 old_a = m_a; m_a = m_data->read_byte(address) & 0xf; @@ -657,7 +657,7 @@ void hmcs40_cpu_device::op_p() m_icount--; UINT16 address = m_a | m_b << 4 | m_c << 8 | (m_op & 7) << 9 | (m_pc & ~0x3f); UINT16 o = m_program->read_word((address & m_prgmask) << 1); - + // destination is determined by the 2 highest bits if (o & 0x100) { diff --git a/src/emu/cpu/i386/i386ops.h b/src/emu/cpu/i386/i386ops.h index c540a7d3c16..31f6b349721 100644 --- a/src/emu/cpu/i386/i386ops.h +++ b/src/emu/cpu/i386/i386ops.h @@ -333,7 +333,7 @@ const i386_device::X86_OPCODE i386_device::s_x86_opcode_table[] = { 0x3B, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false}, { 0x3C, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false}, { 0x3D, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false}, - { 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false}, + { 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false}, { 0x41, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, false}, { 0x42, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, false}, { 0x43, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovae_r16_rm16, &i386_device::pentium_cmovae_r32_rm32, false}, diff --git a/src/emu/cpu/i386/pentops.inc b/src/emu/cpu/i386/pentops.inc index c7a341d9ba7..f1b64aafb42 100644 --- a/src/emu/cpu/i386/pentops.inc +++ b/src/emu/cpu/i386/pentops.inc @@ -1065,10 +1065,10 @@ void i386_device::pentium_movnti_m32_r32() // Opcode 0f c3 void i386_device::i386_cyrix_special() // Opcode 0x0f 3a-3d { /* -0f 3a BB0_RESET (set BB0 pointer = base) -0f 3b BB1_RESET (set BB1 pointer = base) -0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax) -0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx]) +0f 3a BB0_RESET (set BB0 pointer = base) +0f 3b BB1_RESET (set BB1 pointer = base) +0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax) +0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx]) */ CYCLES(1); diff --git a/src/emu/cpu/nec/v53.c b/src/emu/cpu/nec/v53.c index 0019f5bd959..a99d3bad960 100644 --- a/src/emu/cpu/nec/v53.c +++ b/src/emu/cpu/nec/v53.c @@ -237,9 +237,8 @@ void v53_base_device::install_peripheral_io() if (m_SCTL & 0x02) // uPD71037 mode { - if (IOAG) // 8-bit + if (IOAG) // 8-bit { - } else { @@ -256,9 +255,8 @@ void v53_base_device::install_peripheral_io() UINT16 base = (m_OPHA << 8) | m_IULA; base &= 0xfffe; - if (IOAG) // 8-bit + if (IOAG) // 8-bit { - } else { @@ -272,9 +270,8 @@ void v53_base_device::install_peripheral_io() //printf("installing TCU to %04x\n", base); base &= 0xfffe; - if (IOAG) // 8-bit + if (IOAG) // 8-bit { - } else { @@ -290,9 +287,8 @@ void v53_base_device::install_peripheral_io() UINT16 base = (m_OPHA << 8) | m_SULA; base &= 0xfffe; - if (IOAG) // 8-bit + if (IOAG) // 8-bit { - } else { @@ -333,9 +329,9 @@ WRITE8_MEMBER(v53_base_device::tmu_tct2_w) { m_v53tcu->write(space, 2, data); } WRITE8_MEMBER(v53_base_device::tmu_tmd_w) { m_v53tcu->write(space, 3, data); } -READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); } -READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); } -READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); } +READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); } +READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); } +READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); } @@ -343,7 +339,7 @@ READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); } /*** DMA ***/ -// could be wrong / nonexistent +// could be wrong / nonexistent WRITE_LINE_MEMBER(v53_base_device::dreq0_w) { if (!(m_SCTL & 0x02)) @@ -409,20 +405,20 @@ WRITE_LINE_MEMBER(v53_base_device::hack_w) static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA) -// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2 -// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3 -// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4 -// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5 -// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6 -// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7 -// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8 +// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2 +// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3 +// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4 +// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5 +// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6 +// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7 +// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8 AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral) AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control -// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee -// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef +// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee +// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc. AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control @@ -430,7 +426,7 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control -// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7 +// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7 AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping @@ -438,7 +434,7 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common) AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping) -// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff +// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff ADDRESS_MAP_END @@ -486,7 +482,7 @@ static MACHINE_CONFIG_FRAGMENT( v53 ) MCFG_PIT8253_OUT0_HANDLER(WRITELINE( v53_base_device, tcu_out0_trampoline_cb )) MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb )) MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb )) - + MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000) MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb)) @@ -506,12 +502,12 @@ static MACHINE_CONFIG_FRAGMENT( v53 ) MCFG_AM9517A_OUT_DACK_2_CB(WRITELINE(v53_base_device, dma_dack2_trampoline_w)) MCFG_AM9517A_OUT_DACK_3_CB(WRITELINE(v53_base_device, dma_dack3_trampoline_w)) - + MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, internal_irq_w), VCC, READ8(v53_base_device,get_pic_ack)) - MCFG_DEVICE_ADD("v53scu", V53_SCU, 0) + MCFG_DEVICE_ADD("v53scu", V53_SCU, 0) MCFG_I8251_TXD_HANDLER(WRITELINE(v53_base_device, scu_txd_trampoline_cb)) MCFG_I8251_DTR_HANDLER(WRITELINE(v53_base_device, scu_dtr_trampoline_cb)) MCFG_I8251_RTS_HANDLER(WRITELINE(v53_base_device, scu_rts_trampoline_cb)) @@ -578,4 +574,3 @@ v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_ : v53_base_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", BYTE_XOR_LE(0), 6, 1, V33_TYPE) { } - diff --git a/src/emu/cpu/nec/v53.h b/src/emu/cpu/nec/v53.h index dbaa7778773..05611e5503f 100644 --- a/src/emu/cpu/nec/v53.h +++ b/src/emu/cpu/nec/v53.h @@ -131,7 +131,7 @@ public: UINT8 m_SCTL; UINT8 m_OPSEL; - + UINT8 m_SULA; UINT8 m_TULA; UINT8 m_IULA; @@ -151,10 +151,10 @@ public: template<class _Object> static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_syndet_handler.set_callback(object); } DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); } - DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); } + DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */ DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */ - DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); } + DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); } // TCU @@ -165,9 +165,9 @@ public: DECLARE_READ8_MEMBER(tmu_tst2_r); DECLARE_WRITE8_MEMBER(tmu_tct2_w); DECLARE_WRITE8_MEMBER(tmu_tmd_w); -// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; } -// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; } -// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; } +// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; } +// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; } +// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; } template<class _Object> static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out0_handler.set_callback(object); } template<class _Object> static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out1_handler.set_callback(object); } template<class _Object> static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out2_handler.set_callback(object); } @@ -195,7 +195,7 @@ public: DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); } DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); } DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); } - DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); } + DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); } DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); } DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); } DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); } @@ -204,10 +204,10 @@ public: DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); } DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); } DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); } - DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); } - DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); } - DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); } - DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); } + DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); } DECLARE_WRITE_LINE_MEMBER(dreq0_w); @@ -221,7 +221,7 @@ public: void install_peripheral_io(); const address_space_config m_io_space_config; - + const address_space_config *memory_space_config(address_spacenum spacenum) const { switch (spacenum) @@ -260,9 +260,9 @@ protected: devcb_write_line m_syndet_handler; // TCU -// double m_clk0; -// double m_clk1; -// double m_clk2; +// double m_clk0; +// double m_clk1; +// double m_clk2; devcb_write_line m_out0_handler; devcb_write_line m_out1_handler; devcb_write_line m_out2_handler; @@ -285,7 +285,7 @@ protected: devcb_write_line m_out_dack_1_cb; devcb_write_line m_out_dack_2_cb; devcb_write_line m_out_dack_3_cb; - + }; diff --git a/src/emu/cpu/pic16c5x/pic16c5x.c b/src/emu/cpu/pic16c5x/pic16c5x.c index 6820bad7c74..c39324a0a69 100644 --- a/src/emu/cpu/pic16c5x/pic16c5x.c +++ b/src/emu/cpu/pic16c5x/pic16c5x.c @@ -799,7 +799,7 @@ void pic16c5x_device::device_start() m_program = &space(AS_PROGRAM); m_direct = &m_program->direct(); m_data = &space(AS_DATA); - + m_read_a.resolve_safe(0); m_read_b.resolve_safe(0); m_read_c.resolve_safe(0); diff --git a/src/emu/cpu/pic16c5x/pic16c5x.h b/src/emu/cpu/pic16c5x/pic16c5x.h index 92a62d3f207..779d7a12a5d 100644 --- a/src/emu/cpu/pic16c5x/pic16c5x.h +++ b/src/emu/cpu/pic16c5x/pic16c5x.h @@ -81,7 +81,7 @@ public: * the value if known (available in HEX dumps of the ROM). */ void pic16c5x_set_config(UINT16 data); - + // or with a macro static void set_config_static(device_t &device, UINT16 data) { downcast<pic16c5x_device &>(device).m_temp_config = data; } @@ -155,7 +155,7 @@ private: address_space *m_program; direct_read_data *m_direct; address_space *m_data; - + // i/o handlers devcb_read8 m_read_a; devcb_read8 m_read_b; diff --git a/src/emu/cpu/z80/kl5c80a12.c b/src/emu/cpu/z80/kl5c80a12.c index 4be701168f3..ddf40bd8612 100644 --- a/src/emu/cpu/z80/kl5c80a12.c +++ b/src/emu/cpu/z80/kl5c80a12.c @@ -1,13 +1,13 @@ /*************************************************************************** - Kawasaki LSI - KL5C80A12 CPU (KL5C80A12CFP on hng64.c) + Kawasaki LSI + KL5C80A12 CPU (KL5C80A12CFP on hng64.c) - Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz - Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller + Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz + Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller - (is this different enough to need it's own core?) - (todo: everything, some code currently lives in machine/hng64_net.c but not much) + (is this different enough to need it's own core?) + (todo: everything, some code currently lives in machine/hng64_net.c but not much) ***************************************************************************/ diff --git a/src/emu/cpu/z80/kl5c80a12.h b/src/emu/cpu/z80/kl5c80a12.h index 14fa9cc86dc..6f6683ecb59 100644 --- a/src/emu/cpu/z80/kl5c80a12.h +++ b/src/emu/cpu/z80/kl5c80a12.h @@ -1,13 +1,13 @@ /*************************************************************************** - Kawasaki LSI - KL5C80A12 CPU (KL5C80A12CFP on hng64.c) + Kawasaki LSI + KL5C80A12 CPU (KL5C80A12CFP on hng64.c) - Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz - Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller + Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz + Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller - (is this different enough to need it's own core?) - (todo: everything, some code currently lives in machine/hng64_net.c but not much) + (is this different enough to need it's own core?) + (todo: everything, some code currently lives in machine/hng64_net.c but not much) ***************************************************************************/ diff --git a/src/emu/machine/am9517a.c b/src/emu/machine/am9517a.c index 0104ff077d6..15dafeb0362 100644 --- a/src/emu/machine/am9517a.c +++ b/src/emu/machine/am9517a.c @@ -3,15 +3,15 @@ /*************************************************************************** AMD AM9517A - Intel 8237A - NEC uPD71037 + Intel 8237A + NEC uPD71037 - NEC uPD71071 (extended version of above) + NEC uPD71071 (extended version of above) - a variant is used in the V53 CPU which offers subsets of both the - uPD71071 and uPD71037 functionality depending on a mode bit. - - Multimode DMA Controller emulation + a variant is used in the V53 CPU which offers subsets of both the + uPD71071 and uPD71037 functionality depending on a mode bit. + + Multimode DMA Controller emulation Copyright the MESS Team. Visit http://mamedev.org for licensing and usage restrictions. @@ -28,17 +28,17 @@ /* - When the V53 operates in uPD71071 compatible mode there are the following - differences from a real uPD71071 + When the V53 operates in uPD71071 compatible mode there are the following + differences from a real uPD71071 - V53 Real uPD71071 - Software Reqs No Yes - Memory-to-Memory DMA No Yes - DMARQ active level High programmable - DMAAK active level Low programmable - Bus Cycle 4 4 or 3 + V53 Real uPD71071 + Software Reqs No Yes + Memory-to-Memory DMA No Yes + DMARQ active level High programmable + DMAAK active level Low programmable + Bus Cycle 4 4 or 3 - we don't currently handle the differences + we don't currently handle the differences */ @@ -1158,7 +1158,7 @@ READ8_MEMBER(upd71071_v53_device::read) ret = m_command & 0xff; break; case 0x09: // Device control (high) // UPD71071 only? - ret = m_command_high & 0xff; + ret = m_command_high & 0xff; break; case 0x0b: // Status ret = m_status; @@ -1187,14 +1187,14 @@ READ8_MEMBER(upd71071_v53_device::read) WRITE8_MEMBER(upd71071_v53_device::write) { int channel = m_selected_channel; - + switch (offset) { case 0x00: // Initialise // TODO: reset (bit 0) //m_buswidth = data & 0x02; //if (data & 0x01) - // soft_reset(); + // soft_reset(); logerror("DMA: Initialise [%02x]\n", data); break; case 0x01: // Channel @@ -1279,4 +1279,4 @@ WRITE8_MEMBER(upd71071_v53_device::write) } trigger(1); -}
\ No newline at end of file +} diff --git a/src/emu/machine/am9517a.h b/src/emu/machine/am9517a.h index 3a0eb2a6432..3ba47c35f96 100644 --- a/src/emu/machine/am9517a.h +++ b/src/emu/machine/am9517a.h @@ -172,7 +172,7 @@ protected: virtual void device_start(); virtual void device_reset(); - int m_selected_channel; + int m_selected_channel; int m_base; UINT8 m_command_high; diff --git a/src/emu/machine/i8251.c b/src/emu/machine/i8251.c index 59da201a4d5..622605453ca 100644 --- a/src/emu/machine/i8251.c +++ b/src/emu/machine/i8251.c @@ -3,10 +3,10 @@ i8251.c Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter code - NEC uPD71051 is a clone + NEC uPD71051 is a clone - The V53/V53A use a customized version with only the Asynchronous mode - and a split command / mode register + The V53/V53A use a customized version with only the Asynchronous mode + and a split command / mode register @@ -428,29 +428,29 @@ WRITE8_MEMBER(i8251_device::command_w) /* bit 7: - 0 = normal operation - 1 = hunt mode - bit 6: - 0 = normal operation - 1 = internal reset - bit 5: - 0 = /RTS set to 1 - 1 = /RTS set to 0 - bit 4: - 0 = normal operation - 1 = reset error flag - bit 3: - 0 = normal operation - 1 = send break character - bit 2: - 0 = receive disable - 1 = receive enable - bit 1: - 0 = /DTR set to 1 - 1 = /DTR set to 0 - bit 0: - 0 = transmit disable - 1 = transmit enable + 0 = normal operation + 1 = hunt mode + bit 6: + 0 = normal operation + 1 = internal reset + bit 5: + 0 = /RTS set to 1 + 1 = /RTS set to 0 + bit 4: + 0 = normal operation + 1 = reset error flag + bit 3: + 0 = normal operation + 1 = send break character + bit 2: + 0 = receive disable + 1 = receive enable + bit 1: + 0 = /DTR set to 1 + 1 = /DTR set to 0 + bit 0: + 0 = transmit disable + 1 = transmit enable */ m_rts_handler(!BIT(data, 5)); @@ -484,28 +484,28 @@ WRITE8_MEMBER(i8251_device::mode_w) { /* Asynchronous - bit 7,6: stop bit length - 0 = inhibit - 1 = 1 bit - 2 = 1.5 bits - 3 = 2 bits - bit 5: parity type - 0 = parity odd - 1 = parity even - bit 4: parity test enable - 0 = disable - 1 = enable - bit 3,2: character length - 0 = 5 bits - 1 = 6 bits - 2 = 7 bits - 3 = 8 bits - bit 1,0: baud rate factor - 0 = defines command byte for synchronous or asynchronous - 1 = x1 - 2 = x16 - 3 = x64 - */ + bit 7,6: stop bit length + 0 = inhibit + 1 = 1 bit + 2 = 1.5 bits + 3 = 2 bits + bit 5: parity type + 0 = parity odd + 1 = parity even + bit 4: parity test enable + 0 = disable + 1 = enable + bit 3,2: character length + 0 = 5 bits + 1 = 6 bits + 2 = 7 bits + 3 = 8 bits + bit 1,0: baud rate factor + 0 = defines command byte for synchronous or asynchronous + 1 = x1 + 2 = x16 + 3 = x64 + */ LOG(("I8251: Asynchronous operation\n")); @@ -597,24 +597,24 @@ WRITE8_MEMBER(i8251_device::mode_w) else { /* bit 7: Number of sync characters - 0 = 1 character - 1 = 2 character - bit 6: Synchronous mode - 0 = Internal synchronisation - 1 = External synchronisation - bit 5: parity type - 0 = parity odd - 1 = parity even - bit 4: parity test enable - 0 = disable - 1 = enable - bit 3,2: character length - 0 = 5 bits - 1 = 6 bits - 2 = 7 bits - 3 = 8 bits - bit 1,0 = 0 - */ + 0 = 1 character + 1 = 2 character + bit 6: Synchronous mode + 0 = Internal synchronisation + 1 = External synchronisation + bit 5: parity type + 0 = parity odd + 1 = parity even + bit 4: parity test enable + 0 = disable + 1 = enable + bit 3,2: character length + 0 = 5 bits + 1 = 6 bits + 2 = 7 bits + 3 = 8 bits + bit 1,0 = 0 + */ LOG(("I8251: Synchronous operation\n")); /* setup for sync byte(s) */ diff --git a/src/emu/machine/i8257.c b/src/emu/machine/i8257.c index 791a040295f..404e3066b15 100644 --- a/src/emu/machine/i8257.c +++ b/src/emu/machine/i8257.c @@ -79,7 +79,7 @@ inline void i8257_device::dma_request(int channel, int state) } else { - m_request &= ~(1 << channel); + m_request &= ~(1 << channel); } trigger(1); } diff --git a/src/emu/machine/mcf5206e.c b/src/emu/machine/mcf5206e.c index d7b99c42483..f19684f71a0 100644 --- a/src/emu/machine/mcf5206e.c +++ b/src/emu/machine/mcf5206e.c @@ -860,7 +860,7 @@ void mcf5206e_peripheral_device::device_start() init_regs(true); m_timer1 = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( mcf5206e_peripheral_device::timer1_callback ), this) ); - + save_item(NAME(m_ICR)); save_item(NAME(m_CSAR)); save_item(NAME(m_CSMR)); diff --git a/src/emu/machine/tmp68301.c b/src/emu/machine/tmp68301.c index 9795e075b4a..4594ea0397f 100644 --- a/src/emu/machine/tmp68301.c +++ b/src/emu/machine/tmp68301.c @@ -123,7 +123,7 @@ void tmp68301_device::device_start() m_in_parallel_cb.resolve_safe(0); m_out_parallel_cb.resolve_safe(); - + save_item(NAME(m_regs)); save_item(NAME(m_IE)); save_item(NAME(m_irq_vector)); diff --git a/src/emu/machine/upd71071.c b/src/emu/machine/upd71071.c index 62214ef9e91..0a4484b607f 100644 --- a/src/emu/machine/upd71071.c +++ b/src/emu/machine/upd71071.c @@ -1,7 +1,7 @@ /* - am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it + am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it NEC uPD71071 DMA Controller Used on the Fujitsu FM-Towns @@ -31,8 +31,8 @@ Self-explanatory, I hope. :) NOTE: Datasheet clearly shows this as 24-bit, with register 7 unused. But the FM-Towns definitely uses reg 7 as bits 24-31. - The documentation on the V53A manual doesn't show these bits either, maybe it's - an external connection on the FMT? might be worth checking overflow behavior etc. + The documentation on the V53A manual doesn't show these bits either, maybe it's + an external connection on the FMT? might be worth checking overflow behavior etc. 0x08: 0x09: Device Control register (16-bit) @@ -77,8 +77,8 @@ 0x0f: Mask register bit 0-3: DMARQ mask bits 1 and 0 only in MTM transfers - - Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways + + Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways diff --git a/src/emu/machine/vrc4373.c b/src/emu/machine/vrc4373.c index b1e5c6e8928..e91c2f2a8c4 100644 --- a/src/emu/machine/vrc4373.c +++ b/src/emu/machine/vrc4373.c @@ -111,7 +111,7 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_ if (LOG_NILE) logerror("%s: map_extra Master Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci2_laddr); } - // PCI IO Window + // PCI IO Window if (m_cpu_regs[NREG_PCIMIOW]&0x1000) { winStart = m_cpu_regs[NREG_PCIMIOW]&0xff000000; winEnd = winStart | (~(0x80000000 | (((m_cpu_regs[NREG_PCIMIOW]>>13)&0x7f)<<24))); @@ -122,7 +122,7 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_ logerror("%s: map_extra IO Window start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci_io_laddr); } // PCI Target Window 1 - if (m_cpu_regs[NREG_PCITW1]&0x1000) { + if (m_cpu_regs[NREG_PCITW1]&0x1000) { winStart = m_cpu_regs[NREG_PCITW1]&0xffe00000; winEnd = winStart | (~(0xf0000000 | (((m_cpu_regs[NREG_PCITW1]>>13)&0x7f)<<21))); winSize = winEnd - winStart + 1; @@ -242,7 +242,7 @@ WRITE32_MEMBER (vrc4373_device::target2_w) logerror("%06X:nile target2 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask); } -// CPU I/F +// CPU I/F READ32_MEMBER (vrc4373_device::cpu_if_r) { UINT32 result = m_cpu_regs[offset]; @@ -290,7 +290,7 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w) case NREG_PCICAR: // Bits in reserved area are used for device selection of type 0 config transactions // Assuming 23:11 get mapped into device number for configuration - if ((data&0x3) == 0x0) { + if ((data&0x3) == 0x0) { // Type 0 transaction modData = 0; // Select the device based on one hot bit @@ -341,4 +341,3 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w) } } - diff --git a/src/emu/machine/vrc4373.h b/src/emu/machine/vrc4373.h index 17fa5de7e9c..998bea71832 100644 --- a/src/emu/machine/vrc4373.h +++ b/src/emu/machine/vrc4373.h @@ -10,13 +10,13 @@ downcast<vrc4373_device *>(device)->set_cpu_tag(_cpu_tag); #define VRC4373_PAGESHIFT 12 - + /* NILE 3 registers 0x000-0x0ff */ -#define NREG_BMCR (0x000/4) -#define NREG_SIMM1 (0x004/4) -#define NREG_SIMM2 (0x008/4) -#define NREG_SIMM3 (0x00C/4) -#define NREG_SIMM4 (0x010/4) +#define NREG_BMCR (0x000/4) +#define NREG_SIMM1 (0x004/4) +#define NREG_SIMM2 (0x008/4) +#define NREG_SIMM3 (0x00C/4) +#define NREG_SIMM4 (0x010/4) #define NREG_PCIMW1 (0x014/4) #define NREG_PCIMW2 (0x018/4) #define NREG_PCITW1 (0x01C/4) @@ -57,7 +57,7 @@ public: void set_cpu_tag(const char *tag); virtual DECLARE_ADDRESS_MAP(config_map, 32); - + DECLARE_READ32_MEMBER( pcictrl_r); DECLARE_WRITE32_MEMBER( pcictrl_w); //cpu bus registers @@ -76,7 +76,7 @@ public: virtual DECLARE_ADDRESS_MAP(target1_map, 32); DECLARE_READ32_MEMBER (target1_r); DECLARE_WRITE32_MEMBER(target1_w); - + virtual DECLARE_ADDRESS_MAP(target2_map, 32); DECLARE_READ32_MEMBER (target2_r); DECLARE_WRITE32_MEMBER(target2_w); diff --git a/src/emu/mame.c b/src/emu/mame.c index 3d8380d8666..b2df26d661b 100644 --- a/src/emu/mame.c +++ b/src/emu/mame.c @@ -286,11 +286,11 @@ void CLIB_DECL popmessage(const char *format, ...) // pop it in the UI machine_manager::instance()->machine()->ui().popup_time(temp.len() / 40 + 2, "%s", temp.cstr()); - + /* // also write to error.log logerror("popmessage: %s\n", temp.cstr()); - + #ifdef MAME_DEBUG // and to command-line in a DEBUG build osd_printf_info("popmessage: %s\n", temp.cstr()); diff --git a/src/emu/render.c b/src/emu/render.c index 46ae77e8909..af95b896cf5 100644 --- a/src/emu/render.c +++ b/src/emu/render.c @@ -2494,13 +2494,13 @@ float render_manager::ui_aspect(render_container *rc) orient = orientation_add(m_ui_target->orientation(), m_ui_container->orientation()); // based on the orientation of the target, compute height/width or width/height if (!(orient & ORIENTATION_SWAP_XY)) - aspect = (float)m_ui_target->height() / (float)m_ui_target->width(); + aspect = (float)m_ui_target->height() / (float)m_ui_target->width(); else - aspect = (float)m_ui_target->width() / (float)m_ui_target->height(); + aspect = (float)m_ui_target->width() / (float)m_ui_target->height(); // if we have a valid pixel aspect, apply that and return if (m_ui_target->pixel_aspect() != 0.0f) - return (aspect / m_ui_target->pixel_aspect()); + return (aspect / m_ui_target->pixel_aspect()); } else { // single screen container diff --git a/src/emu/sound/es1373.h b/src/emu/sound/es1373.h index b2ee13f1feb..46a2e4180d3 100644 --- a/src/emu/sound/es1373.h +++ b/src/emu/sound/es1373.h @@ -9,26 +9,26 @@ MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371) /* Ensonic ES1373 registers 0x00-0x3f */ -#define ES_INT_CS_CTRL (0x00/4) -#define ES_INT_CS_STATUS (0x04/4) -#define ES_UART_DATA (0x08/4) -#define ES_UART_STATUS (0x09/4) -#define ES_UART_CTRL (0x09/4) -#define ES_UART_RSVD (0x0A/4) -#define ES_MEM_PAGE (0x0C/4) -#define ES_SRC_IF (0x10/4) -#define ES_CODEC (0x14/4) -#define ES_LEGACY (0x18/4) -#define ES_CHAN_CTRL (0x1C/4) -#define ES_SERIAL_CTRL (0x20/4) -#define ES_DAC1_CNT (0x24/4) -#define ES_DAC2_CNT (0x28/4) -#define ES_ADC_CNT (0x2C/4) -#define ES_ADC_CNT (0x2C/4) -#define ES_HOST_IF0 (0x30/4) -#define ES_HOST_IF1 (0x34/4) -#define ES_HOST_IF2 (0x38/4) -#define ES_HOST_IF3 (0x3C/4) +#define ES_INT_CS_CTRL (0x00/4) +#define ES_INT_CS_STATUS (0x04/4) +#define ES_UART_DATA (0x08/4) +#define ES_UART_STATUS (0x09/4) +#define ES_UART_CTRL (0x09/4) +#define ES_UART_RSVD (0x0A/4) +#define ES_MEM_PAGE (0x0C/4) +#define ES_SRC_IF (0x10/4) +#define ES_CODEC (0x14/4) +#define ES_LEGACY (0x18/4) +#define ES_CHAN_CTRL (0x1C/4) +#define ES_SERIAL_CTRL (0x20/4) +#define ES_DAC1_CNT (0x24/4) +#define ES_DAC2_CNT (0x28/4) +#define ES_ADC_CNT (0x2C/4) +#define ES_ADC_CNT (0x2C/4) +#define ES_HOST_IF0 (0x30/4) +#define ES_HOST_IF1 (0x34/4) +#define ES_HOST_IF2 (0x38/4) +#define ES_HOST_IF3 (0x3C/4) struct frame_reg { UINT32 pci_addr; diff --git a/src/emu/sound/flt_rc.c b/src/emu/sound/flt_rc.c index 806792ccc17..cec4ebd6bc4 100644 --- a/src/emu/sound/flt_rc.c +++ b/src/emu/sound/flt_rc.c @@ -37,7 +37,7 @@ void filter_rc_device::device_start() { m_stream = stream_alloc(1, 1, machine().sample_rate()); recalc(); - + save_item(NAME(m_k)); save_item(NAME(m_memory)); save_item(NAME(m_type)); diff --git a/src/emu/sound/okim9810.c b/src/emu/sound/okim9810.c index 3370ee460e8..b18894e71a3 100644 --- a/src/emu/sound/okim9810.c +++ b/src/emu/sound/okim9810.c @@ -115,11 +115,11 @@ void okim9810_device::device_start() save_item(NAME(m_global_volume)); save_item(NAME(m_filter_type)); save_item(NAME(m_output_level)); - + for (int i = 0; i < OKIM9810_VOICES; i++) { okim_voice *voice = get_voice(i); - + save_item(NAME(voice->m_adpcm.m_signal), i); save_item(NAME(voice->m_adpcm.m_step), i); save_item(NAME(voice->m_adpcm2.m_signal), i); diff --git a/src/emu/sound/okim9810.h b/src/emu/sound/okim9810.h index 823a8e25f59..4d1f3da7b71 100644 --- a/src/emu/sound/okim9810.h +++ b/src/emu/sound/okim9810.h @@ -135,7 +135,7 @@ protected: }; okim_voice *get_voice(int which); - + // internal state const address_space_config m_space_config; diff --git a/src/emu/video.c b/src/emu/video.c index 11dc4545540..f332e75eac7 100644 --- a/src/emu/video.c +++ b/src/emu/video.c @@ -153,7 +153,7 @@ video_manager::video_manager(running_machine &machine) filename = machine.options().avi_write(); if (filename[0] != 0) begin_recording(filename, MF_AVI); - + #ifdef MAME_DEBUG m_dummy_recording = machine.options().dummy_write(); #endif diff --git a/src/emu/video.h b/src/emu/video.h index c5ca9c9e27b..31e115870ef 100644 --- a/src/emu/video.h +++ b/src/emu/video.h @@ -176,9 +176,9 @@ private: attotime m_avi_frame_period; // period of a single movie frame attotime m_avi_next_frame_time; // time of next frame UINT32 m_avi_frame; // current movie frame number - + // movie recording - dummy - bool m_dummy_recording; // indicates if snapshot should be created of every frame + bool m_dummy_recording; // indicates if snapshot should be created of every frame static const UINT8 s_skiptable[FRAMESKIP_LEVELS][FRAMESKIP_LEVELS]; diff --git a/src/emu/video/tms34061.c b/src/emu/video/tms34061.c index ffcb01d99ad..2e1667d991f 100644 --- a/src/emu/video/tms34061.c +++ b/src/emu/video/tms34061.c @@ -60,7 +60,7 @@ void tms34061_device::device_start() /* allocate memory for VRAM */ m_vram = auto_alloc_array_clear(machine(), UINT8, m_vramsize + 256 * 2); - + /* allocate memory for latch RAM */ m_latchram = auto_alloc_array_clear(machine(), UINT8, m_vramsize + 256 * 2); @@ -93,7 +93,7 @@ void tms34061_device::device_start() /* start vertical interrupt timer */ m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tms34061_device::interrupt), this)); - + save_item(NAME(m_regs)); save_item(NAME(m_xmask)); save_item(NAME(m_yshift)); diff --git a/src/emu/video/voodoo_pci.c b/src/emu/video/voodoo_pci.c index 2b7a6f07433..e1e02e2260e 100644 --- a/src/emu/video/voodoo_pci.c +++ b/src/emu/video/voodoo_pci.c @@ -56,7 +56,7 @@ void voodoo_pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_wind return; if(UINT32(bi.adr) == UINT32(~(bi.size - 1))) return; - + UINT64 start; address_space *space; if(bi.flags & M_IO) { |
