diff options
Diffstat (limited to 'src/emu/cpu')
| -rw-r--r-- | src/emu/cpu/sh4/sh3comn.c | 16 | ||||
| -rw-r--r-- | src/emu/cpu/sh4/sh4.c | 506 |
2 files changed, 261 insertions, 261 deletions
diff --git a/src/emu/cpu/sh4/sh3comn.c b/src/emu/cpu/sh4/sh3comn.c index 29a4cbdfdf6..e364ebb50e4 100644 --- a/src/emu/cpu/sh4/sh3comn.c +++ b/src/emu/cpu/sh4/sh3comn.c @@ -299,7 +299,7 @@ READ32_HANDLER( sh3_internal_r ) logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); return sh4->m_sh3internal_lower[offset]; } - + if (mem_mask & 0x0000ff00) { logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); @@ -315,7 +315,7 @@ READ32_HANDLER( sh3_internal_r ) logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); return sh4->m_sh3internal_lower[offset]; } - + if (mem_mask & 0x0000ff00) { logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); @@ -331,7 +331,7 @@ READ32_HANDLER( sh3_internal_r ) logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); return sh4->m_sh3internal_lower[offset]; } - + if (mem_mask & 0x0000ff00) { logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); @@ -347,7 +347,7 @@ READ32_HANDLER( sh3_internal_r ) logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); return sh4->m_sh3internal_lower[offset]; } - + if (mem_mask & 0x0000ffff) { logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); @@ -622,7 +622,7 @@ WRITE32_HANDLER( sh3_internal_w ) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } - + if (mem_mask & 0x0000ff00) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); @@ -636,7 +636,7 @@ WRITE32_HANDLER( sh3_internal_w ) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } - + if (mem_mask & 0x0000ff00) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); @@ -650,7 +650,7 @@ WRITE32_HANDLER( sh3_internal_w ) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } - + if (mem_mask & 0x0000ff00) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); @@ -664,7 +664,7 @@ WRITE32_HANDLER( sh3_internal_w ) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); } - + if (mem_mask & 0x0000ffff) { logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c index e7183843875..dfa4ae55166 100644 --- a/src/emu/cpu/sh4/sh4.c +++ b/src/emu/cpu/sh4/sh4.c @@ -207,8 +207,8 @@ const void ADDI(sh4_state *sh4, UINT16 opcode) * ADDC Rm,Rn */ const void ADDC(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 tmp0, tmp1; tmp1 = sh4->r[n] + sh4->r[m]; @@ -228,7 +228,7 @@ const void ADDC(sh4_state *sh4, UINT16 opcode) */ const void ADDV(sh4_state *sh4, UINT16 opcode) { - UINT32 m = Rm; UINT32 n = Rn; + UINT32 m = Rm; UINT32 n = Rn; INT32 dest, src, ans; if ((INT32) sh4->r[n] >= 0) @@ -262,7 +262,7 @@ const void ADDV(sh4_state *sh4, UINT16 opcode) * AND Rm,Rn */ const void AND(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] &= sh4->r[Rm]; } @@ -354,7 +354,7 @@ const void BRA(sh4_state *sh4, UINT16 d) * BRAF Rm */ const void BRAF(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->delay = sh4->pc; sh4->pc += sh4->r[Rn] + 2; sh4->sh4_icount--; @@ -380,7 +380,7 @@ const void BSR(sh4_state *sh4, UINT16 d) * BSRF Rm */ const void BSRF(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->pr = sh4->pc + 2; sh4->delay = sh4->pc; sh4->pc += sh4->r[Rn] + 2; @@ -444,7 +444,7 @@ const void CLRT(sh4_state *sh4, UINT16 opcode) * CMP_EQ Rm,Rn */ const void CMPEQ(sh4_state *sh4, UINT16 opcode) -{ +{ if (sh4->r[Rn] == sh4->r[Rm]) sh4->sr |= T; else @@ -456,7 +456,7 @@ const void CMPEQ(sh4_state *sh4, UINT16 opcode) * CMP_GE Rm,Rn */ const void CMPGE(sh4_state *sh4, UINT16 opcode) -{ +{ if ((INT32) sh4->r[Rn] >= (INT32) sh4->r[Rm]) sh4->sr |= T; else @@ -468,7 +468,7 @@ const void CMPGE(sh4_state *sh4, UINT16 opcode) * CMP_GT Rm,Rn */ const void CMPGT(sh4_state *sh4, UINT16 opcode) -{ +{ if ((INT32) sh4->r[Rn] > (INT32) sh4->r[Rm]) sh4->sr |= T; else @@ -480,7 +480,7 @@ const void CMPGT(sh4_state *sh4, UINT16 opcode) * CMP_HI Rm,Rn */ const void CMPHI(sh4_state *sh4, UINT16 opcode) -{ +{ if ((UINT32) sh4->r[Rn] > (UINT32) sh4->r[Rm]) sh4->sr |= T; else @@ -492,7 +492,7 @@ const void CMPHI(sh4_state *sh4, UINT16 opcode) * CMP_HS Rm,Rn */ const void CMPHS(sh4_state *sh4, UINT16 opcode) -{ +{ if ((UINT32) sh4->r[Rn] >= (UINT32) sh4->r[Rm]) sh4->sr |= T; else @@ -505,7 +505,7 @@ const void CMPHS(sh4_state *sh4, UINT16 opcode) * CMP_PL Rn */ const void CMPPL(sh4_state *sh4, UINT16 opcode) -{ +{ if ((INT32) sh4->r[Rn] > 0) sh4->sr |= T; else @@ -517,7 +517,7 @@ const void CMPPL(sh4_state *sh4, UINT16 opcode) * CMP_PZ Rn */ const void CMPPZ(sh4_state *sh4, UINT16 opcode) -{ +{ if ((INT32) sh4->r[Rn] >= 0) sh4->sr |= T; else @@ -529,7 +529,7 @@ const void CMPPZ(sh4_state *sh4, UINT16 opcode) * CMP_STR Rm,Rn */ const void CMPSTR(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 temp; INT32 HH, HL, LH, LL; temp = sh4->r[Rn] ^ sh4->r[Rm]; @@ -565,8 +565,8 @@ const void CMPIM(sh4_state *sh4, UINT16 i) * DIV0S Rm,Rn */ const void DIV0S(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if ((sh4->r[n] & 0x80000000) == 0) sh4->sr &= ~Q; @@ -596,8 +596,8 @@ const void DIV0U(sh4_state *sh4, UINT16 opcode) * DIV1 Rm,Rn */ const void DIV1(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 tmp0; UINT32 old_q; @@ -690,8 +690,8 @@ const void DIV1(sh4_state *sh4, UINT16 opcode) /* DMULS.L Rm,Rn */ const void DMULS(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; @@ -741,8 +741,8 @@ const void DMULS(sh4_state *sh4, UINT16 opcode) /* DMULU.L Rm,Rn */ const void DMULU(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; @@ -771,8 +771,8 @@ const void DMULU(sh4_state *sh4, UINT16 opcode) /* DT Rn */ const void DT(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n]--; if (sh4->r[n] == 0) @@ -799,38 +799,38 @@ const void DT(sh4_state *sh4, UINT16 opcode) /* EXTS.B Rm,Rn */ const void EXTSB(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = ((INT32)sh4->r[Rm] << 24) >> 24; } /* EXTS.W Rm,Rn */ const void EXTSW(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = ((INT32)sh4->r[Rm] << 16) >> 16; } /* EXTU.B Rm,Rn */ const void EXTUB(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->r[Rm] & 0x000000ff; } /* EXTU.W Rm,Rn */ const void EXTUW(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->r[Rm] & 0x0000ffff; } /* JMP @Rm */ const void JMP(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->delay = sh4->pc; sh4->pc = sh4->ea = sh4->r[Rn]; } /* JSR @Rm */ const void JSR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->delay = sh4->pc; sh4->pr = sh4->pc + 2; sh4->pc = sh4->ea = sh4->r[Rn]; @@ -840,7 +840,7 @@ const void JSR(sh4_state *sh4, UINT16 opcode) /* LDC Rm,SR */ const void LDCSR(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 reg; reg = sh4->r[Rn]; @@ -854,19 +854,19 @@ const void LDCSR(sh4_state *sh4, UINT16 opcode) /* LDC Rm,GBR */ const void LDCGBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->gbr = sh4->r[Rn]; } /* LDC Rm,VBR */ const void LDCVBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->vbr = sh4->r[Rn]; } /* LDC.L @Rm+,SR */ const void LDCMSR(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 old; old = sh4->sr; @@ -883,7 +883,7 @@ const void LDCMSR(sh4_state *sh4, UINT16 opcode) /* LDC.L @Rm+,GBR */ const void LDCMGBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->gbr = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -892,7 +892,7 @@ const void LDCMGBR(sh4_state *sh4, UINT16 opcode) /* LDC.L @Rm+,VBR */ const void LDCMVBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->vbr = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -900,26 +900,26 @@ const void LDCMVBR(sh4_state *sh4, UINT16 opcode) } /* LDS Rm,MACH */ -const void LDSMACH(sh4_state *sh4, UINT16 opcode) +const void LDSMACH(sh4_state *sh4, UINT16 opcode) { sh4->mach = sh4->r[Rn]; } /* LDS Rm,MACL */ const void LDSMACL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->macl = sh4->r[Rn]; } /* LDS Rm,PR */ const void LDSPR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->pr = sh4->r[Rn]; } /* LDS.L @Rm+,MACH */ const void LDSMMACH(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->mach = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -927,7 +927,7 @@ const void LDSMMACH(sh4_state *sh4, UINT16 opcode) /* LDS.L @Rm+,MACL */ const void LDSMMACL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->macl = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -935,7 +935,7 @@ const void LDSMMACL(sh4_state *sh4, UINT16 opcode) /* LDS.L @Rm+,PR */ const void LDSMPR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->pr = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -943,8 +943,8 @@ const void LDSMPR(sh4_state *sh4, UINT16 opcode) /* MAC.L @Rm+,@Rn+ */ const void MAC_L(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; @@ -1023,7 +1023,7 @@ const void MAC_L(sh4_state *sh4, UINT16 opcode) /* MAC.W @Rm+,@Rn+ */ const void MAC_W(sh4_state *sh4, UINT16 opcode) { - UINT32 m = Rm; UINT32 n = Rn; + UINT32 m = Rm; UINT32 n = Rn; INT32 tempm, tempn, dest, src, ans; UINT32 templ; @@ -1076,55 +1076,55 @@ const void MAC_W(sh4_state *sh4, UINT16 opcode) /* MOV Rm,Rn */ const void MOV(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->r[Rm]; } /* MOV.B Rm,@Rn */ const void MOVBS(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; WB(sh4, sh4->ea, sh4->r[Rm] & 0x000000ff); } /* MOV.W Rm,@Rn */ const void MOVWS(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; WW(sh4, sh4->ea, sh4->r[Rm] & 0x0000ffff); } /* MOV.L Rm,@Rn */ const void MOVLS(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; WL(sh4, sh4->ea, sh4->r[Rm] ); } /* MOV.B @Rm,Rn */ const void MOVBL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rm]; sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); } /* MOV.W @Rm,Rn */ const void MOVWL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rm]; sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @Rm,Rn */ const void MOVLL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rm]; sh4->r[Rn] = RL(sh4, sh4->ea ); } /* MOV.B Rm,@-Rn */ const void MOVBM(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 data = sh4->r[Rm] & 0x000000ff; sh4->r[Rn] -= 1; @@ -1133,7 +1133,7 @@ const void MOVBM(sh4_state *sh4, UINT16 opcode) /* MOV.W Rm,@-Rn */ const void MOVWM(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 data = sh4->r[Rm] & 0x0000ffff; sh4->r[Rn] -= 2; @@ -1142,7 +1142,7 @@ const void MOVWM(sh4_state *sh4, UINT16 opcode) /* MOV.L Rm,@-Rn */ const void MOVLM(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 data = sh4->r[Rm]; sh4->r[Rn] -= 4; @@ -1151,8 +1151,8 @@ const void MOVLM(sh4_state *sh4, UINT16 opcode) /* MOV.B @Rm+,Rn */ const void MOVBP(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->r[m] ); if (n != m) @@ -1161,8 +1161,8 @@ const void MOVBP(sh4_state *sh4, UINT16 opcode) /* MOV.W @Rm+,Rn */ const void MOVWP(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->r[m] ); if (n != m) @@ -1171,8 +1171,8 @@ const void MOVWP(sh4_state *sh4, UINT16 opcode) /* MOV.L @Rm+,Rn */ const void MOVLP(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; sh4->r[n] = RL(sh4, sh4->r[m] ); if (n != m) @@ -1181,42 +1181,42 @@ const void MOVLP(sh4_state *sh4, UINT16 opcode) /* MOV.B Rm,@(R0,Rn) */ const void MOVBS0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn] + sh4->r[0]; WB(sh4, sh4->ea, sh4->r[Rm] & 0x000000ff ); } /* MOV.W Rm,@(R0,Rn) */ const void MOVWS0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn] + sh4->r[0]; WW(sh4, sh4->ea, sh4->r[Rm] & 0x0000ffff ); } /* MOV.L Rm,@(R0,Rn) */ const void MOVLS0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn] + sh4->r[0]; WL(sh4, sh4->ea, sh4->r[Rm] ); } /* MOV.B @(R0,Rm),Rn */ const void MOVBL0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rm] + sh4->r[0]; sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); } /* MOV.W @(R0,Rm),Rn */ const void MOVWL0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rm] + sh4->r[0]; sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); } /* MOV.L @(R0,Rm),Rn */ const void MOVLL0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rm] + sh4->r[0]; sh4->r[Rn] = RL(sh4, sh4->ea ); } @@ -1351,38 +1351,38 @@ const void MOVA(sh4_state *sh4, UINT16 d) /* MOVT Rn */ const void MOVT(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->sr & T; } /* MUL.L Rm,Rn */ const void MULL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->macl = sh4->r[Rn] * sh4->r[Rm]; sh4->sh4_icount--; } /* MULS Rm,Rn */ const void MULS(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->macl = (INT16) sh4->r[Rn] * (INT16) sh4->r[Rm]; } /* MULU Rm,Rn */ const void MULU(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->macl = (UINT16) sh4->r[Rn] * (UINT16) sh4->r[Rm]; } /* NEG Rm,Rn */ const void NEG(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = 0 - sh4->r[Rm]; } /* NEGC Rm,Rn */ const void NEGC(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 temp; temp = sh4->r[Rm]; @@ -1400,13 +1400,13 @@ const void NOP(sh4_state *sh4, UINT16 opcode) /* NOT Rm,Rn */ const void NOT(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = ~sh4->r[Rm]; } /* OR Rm,Rn */ const void OR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] |= sh4->r[Rm]; } @@ -1432,8 +1432,8 @@ const void ORM(sh4_state *sh4, UINT16 i) /* ROTCL Rn */ const void ROTCL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; UINT32 temp; @@ -1444,8 +1444,8 @@ const void ROTCL(sh4_state *sh4, UINT16 opcode) /* ROTCR Rn */ const void ROTCR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; UINT32 temp; temp = (sh4->sr & T) << 31; @@ -1458,8 +1458,8 @@ const void ROTCR(sh4_state *sh4, UINT16 opcode) /* ROTL Rn */ const void ROTL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); sh4->r[n] = (sh4->r[n] << 1) | (sh4->r[n] >> 31); @@ -1467,8 +1467,8 @@ const void ROTL(sh4_state *sh4, UINT16 opcode) /* ROTR Rn */ const void ROTR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); sh4->r[n] = (sh4->r[n] >> 1) | (sh4->r[n] << 31); @@ -1504,8 +1504,8 @@ const void SETT(sh4_state *sh4, UINT16 opcode) /* SHAL Rn (same as SHLL) */ const void SHAL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); sh4->r[n] <<= 1; @@ -1513,8 +1513,8 @@ const void SHAL(sh4_state *sh4, UINT16 opcode) /* SHAR Rn */ const void SHAR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); sh4->r[n] = (UINT32)((INT32)sh4->r[n] >> 1); @@ -1522,8 +1522,8 @@ const void SHAR(sh4_state *sh4, UINT16 opcode) /* SHLL Rn (same as SHAL) */ const void SHLL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); sh4->r[n] <<= 1; @@ -1531,26 +1531,26 @@ const void SHLL(sh4_state *sh4, UINT16 opcode) /* SHLL2 Rn */ const void SHLL2(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] <<= 2; } /* SHLL8 Rn */ const void SHLL8(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] <<= 8; } /* SHLL16 Rn */ const void SHLL16(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] <<= 16; } /* SHLR Rn */ const void SHLR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); sh4->r[n] >>= 1; @@ -1558,19 +1558,19 @@ const void SHLR(sh4_state *sh4, UINT16 opcode) /* SHLR2 Rn */ const void SHLR2(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] >>= 2; } /* SHLR8 Rn */ const void SHLR8(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] >>= 8; } /* SHLR16 Rn */ const void SHLR16(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] >>= 16; } @@ -1592,26 +1592,26 @@ const void SLEEP(sh4_state *sh4, UINT16 opcode) /* STC SR,Rn */ const void STCSR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->sr; } /* STC GBR,Rn */ const void STCGBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->gbr; } /* STC VBR,Rn */ const void STCVBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->vbr; } /* STC.L SR,@-Rn */ const void STCMSR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1621,8 +1621,8 @@ const void STCMSR(sh4_state *sh4, UINT16 opcode) /* STC.L GBR,@-Rn */ const void STCMGBR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1632,8 +1632,8 @@ const void STCMGBR(sh4_state *sh4, UINT16 opcode) /* STC.L VBR,@-Rn */ const void STCMVBR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1643,26 +1643,26 @@ const void STCMVBR(sh4_state *sh4, UINT16 opcode) /* STS MACH,Rn */ const void STSMACH(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->mach; } /* STS MACL,Rn */ const void STSMACL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->macl; } /* STS PR,Rn */ const void STSPR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->pr; } /* STS.L MACH,@-Rn */ const void STSMMACH(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1671,8 +1671,8 @@ const void STSMMACH(sh4_state *sh4, UINT16 opcode) /* STS.L MACL,@-Rn */ const void STSMMACL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1681,8 +1681,8 @@ const void STSMMACL(sh4_state *sh4, UINT16 opcode) /* STS.L PR,@-Rn */ const void STSMPR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1691,14 +1691,14 @@ const void STSMPR(sh4_state *sh4, UINT16 opcode) /* SUB Rm,Rn */ const void SUB(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] -= sh4->r[Rm]; } /* SUBC Rm,Rn */ const void SUBC(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 tmp0, tmp1; @@ -1715,8 +1715,8 @@ const void SUBC(sh4_state *sh4, UINT16 opcode) /* SUBV Rm,Rn */ const void SUBV(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; INT32 dest, src, ans; @@ -1748,8 +1748,8 @@ const void SUBV(sh4_state *sh4, UINT16 opcode) /* SWAP.B Rm,Rn */ const void SWAPB(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 temp0, temp1; @@ -1761,8 +1761,8 @@ const void SWAPB(sh4_state *sh4, UINT16 opcode) /* SWAP.W Rm,Rn */ const void SWAPW(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 temp; @@ -1772,8 +1772,8 @@ const void SWAPW(sh4_state *sh4, UINT16 opcode) /* TAS.B @Rn */ const void TAS(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; UINT32 temp; sh4->ea = sh4->r[n]; @@ -1834,7 +1834,7 @@ const void TRAPA(sh4_state *sh4, UINT16 i) /* TST Rm,Rn */ const void TST(sh4_state *sh4, UINT16 opcode) -{ +{ if ((sh4->r[Rn] & sh4->r[Rm]) == 0) sh4->sr |= T; else @@ -1867,7 +1867,7 @@ const void TSTM(sh4_state *sh4, UINT16 i) /* XOR Rm,Rn */ const void XOR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] ^= sh4->r[Rm]; } @@ -1893,8 +1893,8 @@ const void XORM(sh4_state *sh4, UINT16 i) /* XTRCT Rm,Rn */ const void XTRCT(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; UINT32 temp; @@ -1905,43 +1905,43 @@ const void XTRCT(sh4_state *sh4, UINT16 opcode) /* STC SSR,Rn */ const void STCSSR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->ssr; } /* STC SPC,Rn */ const void STCSPC(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->spc; } /* STC SGR,Rn */ const void STCSGR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->sgr; } /* STS FPUL,Rn */ const void STSFPUL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->fpul; } /* STS FPSCR,Rn */ const void STSFPSCR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->fpscr & 0x003FFFFF; } /* STC DBR,Rn */ const void STCDBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->r[Rn] = sh4->dbr; } /* STCRBANK Rm_BANK,Rn */ const void STCRBANK(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 m = Rm; sh4->r[Rn] = sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7]; @@ -1949,8 +1949,8 @@ const void STCRBANK(sh4_state *sh4, UINT16 opcode) /* STCMRBANK Rm_BANK,@-Rn */ const void STCMRBANK(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1960,7 +1960,7 @@ const void STCMRBANK(sh4_state *sh4, UINT16 opcode) /* MOVCA.L R0,@Rn */ const void MOVCAL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; WL(sh4, sh4->ea, sh4->r[0] ); } @@ -1977,8 +1977,8 @@ const void SETS(sh4_state *sh4, UINT16 opcode) /* STS.L SGR,@-Rn */ const void STCMSGR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1987,8 +1987,8 @@ const void STCMSGR(sh4_state *sh4, UINT16 opcode) /* STS.L FPUL,@-Rn */ const void STSMFPUL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -1997,8 +1997,8 @@ const void STSMFPUL(sh4_state *sh4, UINT16 opcode) /* STS.L FPSCR,@-Rn */ const void STSMFPSCR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -2007,8 +2007,8 @@ const void STSMFPSCR(sh4_state *sh4, UINT16 opcode) /* STC.L DBR,@-Rn */ const void STCMDBR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -2017,8 +2017,8 @@ const void STCMDBR(sh4_state *sh4, UINT16 opcode) /* STC.L SSR,@-Rn */ const void STCMSSR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -2027,8 +2027,8 @@ const void STCMSSR(sh4_state *sh4, UINT16 opcode) /* STC.L SPC,@-Rn */ const void STCMSPC(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; sh4->r[n] -= 4; sh4->ea = sh4->r[n]; @@ -2065,7 +2065,7 @@ const void LDSMFPSCR(sh4_state *sh4, UINT16 opcode) /* LDC.L @Rm+,DBR */ const void LDCMDBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->dbr = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -2073,8 +2073,8 @@ const void LDCMDBR(sh4_state *sh4, UINT16 opcode) /* LDC.L @Rn+,Rm_BANK */ const void LDCMRBANK(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; sh4->ea = sh4->r[n]; sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = RL(sh4, sh4->ea ); @@ -2083,7 +2083,7 @@ const void LDCMRBANK(sh4_state *sh4, UINT16 opcode) /* LDC.L @Rm+,SSR */ const void LDCMSSR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->ssr = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -2091,7 +2091,7 @@ const void LDCMSSR(sh4_state *sh4, UINT16 opcode) /* LDC.L @Rm+,SPC */ const void LDCMSPC(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ea = sh4->r[Rn]; sh4->spc = RL(sh4, sh4->ea ); sh4->r[Rn] += 4; @@ -2099,13 +2099,13 @@ const void LDCMSPC(sh4_state *sh4, UINT16 opcode) /* LDS Rm,FPUL */ const void LDSFPUL(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->fpul = sh4->r[Rn]; } /* LDS Rm,FPSCR */ const void LDSFPSCR(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 s; s = sh4->fpscr; @@ -2122,14 +2122,14 @@ const void LDSFPSCR(sh4_state *sh4, UINT16 opcode) /* LDC Rm,DBR */ const void LDCDBR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->dbr = sh4->r[Rn]; } /* SHAD Rm,Rn */ const void SHAD(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if ((sh4->r[m] & 0x80000000) == 0) sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F); @@ -2144,8 +2144,8 @@ const void SHAD(sh4_state *sh4, UINT16 opcode) /* SHLD Rm,Rn */ const void SHLD(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if ((sh4->r[m] & 0x80000000) == 0) sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F); @@ -2157,7 +2157,7 @@ const void SHLD(sh4_state *sh4, UINT16 opcode) /* LDCRBANK Rn,Rm_BANK */ const void LDCRBANK(sh4_state *sh4, UINT16 opcode) -{ +{ UINT32 m = Rm; sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = sh4->r[Rn]; @@ -2165,19 +2165,19 @@ const void LDCRBANK(sh4_state *sh4, UINT16 opcode) /* LDC Rm,SSR */ const void LDCSSR(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->ssr = sh4->r[Rn]; } /* LDC Rm,SPC */ const void LDCSPC(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->spc = sh4->r[Rn]; } /* PREF @Rn */ const void PREFM(sh4_state *sh4, UINT16 opcode) -{ +{ int a; UINT32 addr,dest,sq; @@ -2255,8 +2255,8 @@ const void PREFM(sh4_state *sh4, UINT16 opcode) /* FMOV @Rm+,XDn PR=0 SZ=1 1111nnn1mmmm1001 */ /* FMOV @Rm+,XDn PR=1 1111nnn1mmmm1001 */ const void FMOVMRIFR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2293,8 +2293,8 @@ const void FMOVMRIFR(sh4_state *sh4, UINT16 opcode) /* FMOV XDm,@Rn PR=0 SZ=1 1111nnnnmmm11010 */ /* FMOV XDm,@Rn PR=1 1111nnnnmmm11010 */ const void FMOVFRMR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ m= m & 14; @@ -2325,8 +2325,8 @@ const void FMOVFRMR(sh4_state *sh4, UINT16 opcode) /* FMOV XDm,@-Rn PR=0 SZ=1 1111nnnnmmm11011 */ /* FMOV XDm,@-Rn PR=1 1111nnnnmmm11011 */ const void FMOVFRMDR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ m= m & 14; @@ -2361,8 +2361,8 @@ const void FMOVFRMDR(sh4_state *sh4, UINT16 opcode) /* FMOV XDm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm10111 */ /* FMOV XDm,@(R0,Rn) PR=1 1111nnnnmmm10111 */ const void FMOVFRS0(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ m= m & 14; @@ -2393,8 +2393,8 @@ const void FMOVFRS0(sh4_state *sh4, UINT16 opcode) /* FMOV @(R0,Rm),XDn PR=0 SZ=1 1111nnn1mmmm0110 */ /* FMOV @(R0,Rm),XDn PR=1 1111nnn1mmmm0110 */ const void FMOVS0FR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n= n & 14; @@ -2426,8 +2426,8 @@ const void FMOVS0FR(sh4_state *sh4, UINT16 opcode) /* FMOV @Rm,XDn PR=1 1111nnn1mmmm1000 */ /* FMOV @Rm,DRn PR=1 1111nnn0mmmm1000 */ const void FMOVMRFR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ if (n & 1) { @@ -2467,8 +2467,8 @@ const void FMOVMRFR(sh4_state *sh4, UINT16 opcode) /* FMOV DRm,XDn PR=1 DRm -> XDn 1111nnn1mmm01100 */ /* FMOV XDm,XDn PR=1 XDm -> XDn 1111nnn1mmm11100 */ const void FMOVFR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if ((sh4->fpu_sz == 0) && (sh4->fpu_pr == 0)) /* SZ = 0 */ sh4->fr[n] = sh4->fr[m]; @@ -2495,13 +2495,13 @@ const void FMOVFR(sh4_state *sh4, UINT16 opcode) /* FLDI1 FRn 1111nnnn10011101 */ const void FLDI1(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->fr[Rn] = 0x3F800000; } /* FLDI0 FRn 1111nnnn10001101 */ const void FLDI0(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->fr[Rn] = 0; } @@ -2513,7 +2513,7 @@ const void FLDS(sh4_state *sh4, UINT16 opcode) /* FSTS FPUL,FRn 1111nnnn00001101 */ const void FSTS(sh4_state *sh4, UINT16 opcode) -{ +{ sh4->fr[Rn] = sh4->fpul; } @@ -2534,8 +2534,8 @@ const void FSCHG(sh4_state *sh4) /* FTRC FRm,FPUL PR=0 1111mmmm00111101 */ /* FTRC DRm,FPUL PR=1 1111mmm000111101 */ const void FTRC(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2549,8 +2549,8 @@ const void FTRC(sh4_state *sh4, UINT16 opcode) /* FLOAT FPUL,FRn PR=0 1111nnnn00101101 */ /* FLOAT FPUL,DRn PR=1 1111nnn000101101 */ const void FLOAT(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2563,8 +2563,8 @@ const void FLOAT(sh4_state *sh4, UINT16 opcode) /* FNEG FRn PR=0 1111nnnn01001101 */ /* FNEG DRn PR=1 1111nnn001001101 */ const void FNEG(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ FP_RFD(n) = -FP_RFD(n); @@ -2576,8 +2576,8 @@ const void FNEG(sh4_state *sh4, UINT16 opcode) /* FABS FRn PR=0 1111nnnn01011101 */ /* FABS DRn PR=1 1111nnn001011101 */ const void FABS(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ #ifdef LSB_FIRST @@ -2595,8 +2595,8 @@ const void FABS(sh4_state *sh4, UINT16 opcode) /* FCMP/EQ FRm,FRn PR=0 1111nnnnmmmm0100 */ /* FCMP/EQ DRm,DRn PR=1 1111nnn0mmm00100 */ const void FCMP_EQ(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2616,8 +2616,8 @@ const void FCMP_EQ(sh4_state *sh4, UINT16 opcode) /* FCMP/GT FRm,FRn PR=0 1111nnnnmmmm0101 */ /* FCMP/GT DRm,DRn PR=1 1111nnn0mmm00101 */ const void FCMP_GT(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2636,8 +2636,8 @@ const void FCMP_GT(sh4_state *sh4, UINT16 opcode) /* FCNVDS DRm,FPUL PR=1 1111mmm010111101 */ const void FCNVDS(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2649,8 +2649,8 @@ const void FCNVDS(sh4_state *sh4, UINT16 opcode) /* FCNVSD FPUL, DRn PR=1 1111nnn010101101 */ const void FCNVSD(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2661,8 +2661,8 @@ const void FCNVSD(sh4_state *sh4, UINT16 opcode) /* FADD FRm,FRn PR=0 1111nnnnmmmm0000 */ /* FADD DRm,DRn PR=1 1111nnn0mmm00000 */ const void FADD(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2676,8 +2676,8 @@ const void FADD(sh4_state *sh4, UINT16 opcode) /* FSUB FRm,FRn PR=0 1111nnnnmmmm0001 */ /* FSUB DRm,DRn PR=1 1111nnn0mmm00001 */ const void FSUB(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2692,8 +2692,8 @@ const void FSUB(sh4_state *sh4, UINT16 opcode) /* FMUL FRm,FRn PR=0 1111nnnnmmmm0010 */ /* FMUL DRm,DRn PR=1 1111nnn0mmm00010 */ const void FMUL(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2707,8 +2707,8 @@ const void FMUL(sh4_state *sh4, UINT16 opcode) /* FDIV FRm,FRn PR=0 1111nnnnmmmm0011 */ /* FDIV DRm,DRn PR=1 1111nnn0mmm00011 */ const void FDIV(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2725,8 +2725,8 @@ const void FDIV(sh4_state *sh4, UINT16 opcode) /* FMAC FR0,FRm,FRn PR=0 1111nnnnmmmm1110 */ const void FMAC(sh4_state *sh4, UINT16 opcode) -{ - UINT32 m = Rm; UINT32 n = Rn; +{ + UINT32 m = Rm; UINT32 n = Rn; if (sh4->fpu_pr == 0) { /* PR = 0 */ FP_RFS(n) = (FP_RFS(0) * FP_RFS(m)) + FP_RFS(n); @@ -2736,8 +2736,8 @@ const void FMAC(sh4_state *sh4, UINT16 opcode) /* FSQRT FRn PR=0 1111nnnn01101101 */ /* FSQRT DRn PR=1 1111nnnn01101101 */ const void FSQRT(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (sh4->fpu_pr) { /* PR = 1 */ n = n & 14; @@ -2753,8 +2753,8 @@ const void FSQRT(sh4_state *sh4, UINT16 opcode) /* FSRRA FRn PR=0 1111nnnn01111101 */ const void FSRRA(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; if (FP_RFS(n) < 0) return; @@ -2763,8 +2763,8 @@ const void FSRRA(sh4_state *sh4, UINT16 opcode) /* FSSCA FPUL,FRn PR=0 1111nnn011111101 */ const void FSSCA(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; float angle; @@ -2775,8 +2775,8 @@ float angle; /* FIPR FVm,FVn PR=0 1111nnmm11101101 */ const void FIPR(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; UINT32 m; float ml[4]; @@ -2791,8 +2791,8 @@ int a; /* FTRV XMTRX,FVn PR=0 1111nn0111111101 */ const void FTRV(sh4_state *sh4, UINT16 opcode) -{ - UINT32 n = Rn; +{ + UINT32 n = Rn; int i,j; float sum[4]; @@ -2971,52 +2971,52 @@ static CPU_RESET( sh4 ) sh4ophandler op1000_handler[] = { - MOVBS4, MOVWS4, NOP, NOP, MOVBL4, MOVWL4, NOP, NOP, CMPIM, BT, NOP, BF, NOP, BTS, NOP, BFS + MOVBS4, MOVWS4, NOP, NOP, MOVBL4, MOVWL4, NOP, NOP, CMPIM, BT, NOP, BF, NOP, BTS, NOP, BFS }; - + sh4ophandler op1100_handler[] = { - MOVBSG, MOVWSG, MOVLSG, TRAPA, MOVBLG, MOVWLG, MOVLLG, MOVA, TSTI, ANDI, XORI, ORI, TSTM, ANDM, XORM, ORM + MOVBSG, MOVWSG, MOVLSG, TRAPA, MOVBLG, MOVWLG, MOVLLG, MOVA, TSTI, ANDI, XORI, ORI, TSTM, ANDM, XORM, ORM }; sh4ophandler op0000_handlers[] = { - NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, - NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, + NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, + NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, STCSR, STCGBR, STCVBR, STCSSR, STCSPC, NOP, NOP, NOP, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, BSRF, NOP, BRAF, NOP, NOP, NOP, NOP, NOP, PREFM, TODO, TODO, TODO, MOVCAL, NOP, NOP, NOP, - MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, - MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, - MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, - MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, + MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, + MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, + MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, + MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, CLRT, SETT, CLRMAC, TODO, CLRS, SETS, NOP, NOP, CLRT, SETT, CLRMAC, TODO, CLRS, SETS, NOP, NOP, - NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, - STSMACH, STSMACL, STSPR, STCSGR, NOP, STSFPUL, STSFPSCR, STCDBR, STSMACH, STSMACL, STSPR, STCSGR, NOP, STSFPUL, STSFPSCR, STCDBR, - RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, - MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, - MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, - MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, - MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, + NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, + STSMACH, STSMACL, STSPR, STCSGR, NOP, STSFPUL, STSFPSCR, STCDBR, STSMACH, STSMACL, STSPR, STCSGR, NOP, STSFPUL, STSFPSCR, STCDBR, + RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, + MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, + MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, + MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, + MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, }; sh4ophandler op0100_handlers[] = { - SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, + SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLR, CMPPZ, SHAR, NOP, SHLR, CMPPZ, SHAR, NOP, SHLR, CMPPZ, SHAR, NOP, SHLR, CMPPZ, SHAR, NOP, STSMMACH, STSMMACL, STSMPR, STCMSGR, NOP, STSMFPUL, STSMFPSCR, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, STCMDBR, STCMSR, STCMGBR, STCMVBR, STCMSSR, STCMSPC, NOP, NOP, NOP, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, - ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, - ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, + ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, + ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, LDSMMACH, LDSMMACL, LDSMPR, NOP, NOP, LDSMFPUL, LDSMFPSCR, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, LDCMDBR, LDCMSR, LDCMGBR, LDCMVBR, LDCMSSR, LDCMSPC, NOP, NOP, NOP, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, - SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, - SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, + SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, + SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, LDSMACH, LDSMACL, LDSPR, NOP, NOP, LDSFPUL, LDSFPSCR, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, LDCDBR, - JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, - SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, - SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, + JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, + SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, + SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, LDCSR, LDCGBR, LDCVBR, LDCSSR, LDCSPC, NOP, NOP, NOP, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, - MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, + MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, }; @@ -3024,7 +3024,7 @@ sh4ophandler upper4bits[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* j = 0x0000 - uses op0000_handlers*/ MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, /* j = 0x1000 */ - MOVBS, MOVWS, MOVLS, NOP, MOVBM, MOVWM, MOVLM, DIV0S, TST, AND, XOR, OR, CMPSTR, XTRCT, MULU, MULS, /* j = 0x2000 */ + MOVBS, MOVWS, MOVLS, NOP, MOVBM, MOVWM, MOVLM, DIV0S, TST, AND, XOR, OR, CMPSTR, XTRCT, MULU, MULS, /* j = 0x2000 */ CMPEQ, NOP, CMPHS, CMPGE, DIV1, DMULU, CMPHI, CMPGT, SUB, NOP, SUBC, SUBV, ADD, DMULS, ADDC, ADDV, /* j = 0x3000 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* j = 0x4000 - uses op0100_handlers*/ MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, /* j = 0x5000 */ @@ -3063,7 +3063,7 @@ void sh4_build_optable(sh4_state *sh4) //for (j = 0; j<0x10000;j+=0x1000) { for (y = 0; y<0x1000;y+=0x100) - { + { for (x=0; x<0x100;x+=0x10) { for (z=0;z<0x10;z++) @@ -3073,12 +3073,12 @@ void sh4_build_optable(sh4_state *sh4) } } } - + j = 0x4000; //for (j = 0; j<0x10000;j+=0x1000) { for (y = 0; y<0x1000;y+=0x100) - { + { for (x=0; x<0x100;x+=0x10) { for (z=0;z<0x10;z++) @@ -3088,13 +3088,13 @@ void sh4_build_optable(sh4_state *sh4) } } } - + j = 0x8000; //for (j = 0; j<0x10000;j+=0x1000) { for (y = 0; y<0x1000;y+=0x100) - { + { for (x=0; x<0x100;x+=0x10) { for (z=0;z<0x10;z++) @@ -3109,7 +3109,7 @@ void sh4_build_optable(sh4_state *sh4) //for (j = 0; j<0x10000;j+=0x1000) { for (y = 0; y<0x1000;y+=0x100) - { + { for (x=0; x<0x100;x+=0x10) { for (z=0;z<0x10;z++) |
