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-rw-r--r--src/emu/cpu/drcbex86.c12
-rw-r--r--src/emu/cpu/i386/i386op16.c2
-rw-r--r--src/emu/cpu/pic16c62x/16c62xdsm.c6
-rw-r--r--src/emu/cpu/pic16c62x/pic16c62x.c12
-rw-r--r--src/emu/cpu/pic16c62x/pic16c62x.h2
-rw-r--r--src/emu/cpu/rsp/rspdrc.c90
-rw-r--r--src/emu/cpu/x86emit.h2
7 files changed, 63 insertions, 63 deletions
diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c
index beafe283055..d35c5132b82 100644
--- a/src/emu/cpu/drcbex86.c
+++ b/src/emu/cpu/drcbex86.c
@@ -528,7 +528,7 @@ INLINE void emit_combine_z_shl_flags(x86code **dst)
/*-------------------------------------------------
- reset_last_upper_lower_reg - reset the last
+ reset_last_upper_lower_reg - reset the last
upper/lower register state
-------------------------------------------------*/
@@ -575,7 +575,7 @@ INLINE void set_last_upper_reg(drcbe_state *drcbe, x86code *dst, const drcuml_pa
INLINE int can_skip_lower_load(drcbe_state *drcbe, x86code *dst, UINT32 *memptr, UINT8 reglo)
{
-// return FALSE;
+// return FALSE;
return (dst == drcbe->last_lower_pc && memptr == drcbe->last_lower_addr && reglo == drcbe->last_lower_reg);
}
@@ -587,7 +587,7 @@ INLINE int can_skip_lower_load(drcbe_state *drcbe, x86code *dst, UINT32 *memptr,
INLINE int can_skip_upper_load(drcbe_state *drcbe, x86code *dst, UINT32 *memptr, UINT8 reghi)
{
-// return FALSE;
+// return FALSE;
return (dst == drcbe->last_upper_pc && memptr == drcbe->last_upper_addr && reghi == drcbe->last_upper_reg);
}
@@ -5658,7 +5658,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
else if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov dsthi,0
}
-
+
/* AND with immediate 0xffffffff00000000 */
else if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value == U64(0xffffffff00000000) && inst->flags == 0)
{
@@ -5672,7 +5672,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
else if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value), 0); // mov dstlo,0
}
-
+
/* AND with immediate <= 0xffffffff */
else if (src2p.type == DRCUML_PTYPE_IMMEDIATE && src2p.value <= 0xffffffff && inst->flags == 0)
{
@@ -5684,7 +5684,7 @@ static x86code *op_and(drcbe_state *drcbe, x86code *dst, const drcuml_instructio
else if (dstp.type == DRCUML_PTYPE_MEMORY)
emit_mov_m32_imm(&dst, MABS(dstp.value + 4), 0); // mov dsthi,0
}
-
+
/* general case */
else
{
diff --git a/src/emu/cpu/i386/i386op16.c b/src/emu/cpu/i386/i386op16.c
index 66bc15587d9..1d32a623410 100644
--- a/src/emu/cpu/i386/i386op16.c
+++ b/src/emu/cpu/i386/i386op16.c
@@ -3110,7 +3110,7 @@ static void I386OP(lsl_r16_rm16)(i386_state *cpustate) // Opcode 0x0f 0x03
UINT8 modrm = FETCH(cpustate);
UINT32 limit;
I386_SREG seg;
-
+
if(PROTECTED_MODE)
{
memset(&seg, 0, sizeof(seg));
diff --git a/src/emu/cpu/pic16c62x/16c62xdsm.c b/src/emu/cpu/pic16c62x/16c62xdsm.c
index 6f18d73e60f..0ef3fe1351f 100644
--- a/src/emu/cpu/pic16c62x/16c62xdsm.c
+++ b/src/emu/cpu/pic16c62x/16c62xdsm.c
@@ -52,9 +52,9 @@ static const char *const regfile[32] = { "Reg$00 (INDF)", "Reg$01 (TMR0/OPTIO
"Reg$18", "Reg$19", "Reg$1A", "Reg$1B", "Reg$1C", "Reg$1D", "Reg$1E", "Reg$1F (CMCON/VRCON)" };
/* Registers bank 1 */
/*static const char *const regfile1[32] = { "Reg$00 (INDF)", "Reg$01 (OPTION)", "Reg$02 (PCL)", "Reg$03 (STATUS)", "Reg$04 (FSR)", "Reg$05 (TRISA)", "Reg$06 (TRISB)", "Reg$07",
- "Reg$08", "Reg$09", "Reg$0A (PCLATH)", "Reg$0B (INTCON)", "Reg$0C (PIE1)", "Reg$0D", "Reg$0E (PCON)", "Reg$0F",
- "Reg$10", "Reg$11", "Reg$12", "Reg$13", "Reg$14", "Reg$15", "Reg$16", "Reg$17",
- "Reg$18", "Reg$19", "Reg$1A", "Reg$1B", "Reg$1C", "Reg$1D", "Reg$1E", "Reg$1F (VRCON)" };
+ "Reg$08", "Reg$09", "Reg$0A (PCLATH)", "Reg$0B (INTCON)", "Reg$0C (PIE1)", "Reg$0D", "Reg$0E (PCON)", "Reg$0F",
+ "Reg$10", "Reg$11", "Reg$12", "Reg$13", "Reg$14", "Reg$15", "Reg$16", "Reg$17",
+ "Reg$18", "Reg$19", "Reg$1A", "Reg$1B", "Reg$1C", "Reg$1D", "Reg$1E", "Reg$1F (VRCON)" };
static const char **regfile[2] = { regfile0, regfile1 };*/
static const char *const dest[2] = { "W", "Reg" };
diff --git a/src/emu/cpu/pic16c62x/pic16c62x.c b/src/emu/cpu/pic16c62x/pic16c62x.c
index 24c7a2c3eb8..ec3d986d5b7 100644
--- a/src/emu/cpu/pic16c62x/pic16c62x.c
+++ b/src/emu/cpu/pic16c62x/pic16c62x.c
@@ -99,7 +99,7 @@ INLINE pic16c62x_state *get_safe_token(const device_config *device)
assert(device->type == CPU);
assert(cpu_get_type(device) == CPU_PIC16C620 ||
cpu_get_type(device) == CPU_PIC16C620A ||
-// cpu_get_type(device) == CPU_PIC16CR620A ||
+// cpu_get_type(device) == CPU_PIC16CR620A ||
cpu_get_type(device) == CPU_PIC16C621 ||
cpu_get_type(device) == CPU_PIC16C621A ||
cpu_get_type(device) == CPU_PIC16C622 ||
@@ -391,7 +391,7 @@ INLINE void STORE_REGFILE(pic16c62x_state *cpustate, offs_t addr, UINT8 data) /*
M_WRTRAM(0x81, data);
break;
case 0x85: if (cpustate->TRISA != data)
- {
+ {
cpustate->TRISA = data | 0xf0;
P_OUT(2,cpustate->TRISA);
P_OUT(0,cpustate->PORTA & (UINT8)(~cpustate->TRISA) & 0x0f);
@@ -399,11 +399,11 @@ INLINE void STORE_REGFILE(pic16c62x_state *cpustate, offs_t addr, UINT8 data) /*
}
break;
case 0x86: if (cpustate->TRISB != data)
- {
- cpustate->TRISB = data;
+ {
+ cpustate->TRISB = data;
P_OUT(3,cpustate->TRISB);
- P_OUT(1,cpustate->PORTB & (UINT8)(~cpustate->TRISB));
- M_WRTRAM(addr, data);
+ P_OUT(1,cpustate->PORTB & (UINT8)(~cpustate->TRISB));
+ M_WRTRAM(addr, data);
}
break;
default: M_WRTRAM(addr, data);
diff --git a/src/emu/cpu/pic16c62x/pic16c62x.h b/src/emu/cpu/pic16c62x/pic16c62x.h
index 712ff9c1452..1b591e28df3 100644
--- a/src/emu/cpu/pic16c62x/pic16c62x.h
+++ b/src/emu/cpu/pic16c62x/pic16c62x.h
@@ -34,7 +34,7 @@ enum
PIC16C62x_STK3, PIC16C62x_STK4, PIC16C62x_STK5, PIC16C62x_STK6,
PIC16C62x_STK7, PIC16C62x_FSR, PIC16C62x_W, PIC16C62x_ALU,
PIC16C62x_STR, PIC16C62x_OPT, PIC16C62x_TMR0, PIC16C62x_PRTA,
- PIC16C62x_PRTB, PIC16C62x_WDT, PIC16C62x_TRSA, PIC16C62x_TRSB,
+ PIC16C62x_PRTB, PIC16C62x_WDT, PIC16C62x_TRSA, PIC16C62x_TRSB,
PIC16C62x_PSCL
};
diff --git a/src/emu/cpu/rsp/rspdrc.c b/src/emu/cpu/rsp/rspdrc.c
index 5a65a76c2fa..c3dd4ac1c7d 100644
--- a/src/emu/cpu/rsp/rspdrc.c
+++ b/src/emu/cpu/rsp/rspdrc.c
@@ -2,8 +2,8 @@
rspdrc.c
- Universal machine language-based Nintendo/SGI RSP emulator.
- Written by Harmony of the MESS team.
+ Universal machine language-based Nintendo/SGI RSP emulator.
+ Written by Harmony of the MESS team.
Copyright the MESS team.
Released for general non-commercial use under the MAME license
@@ -2394,41 +2394,41 @@ INLINE void rsp_vcr(rsp_state *rsp, UINT32 op, INT16 *vres)
WRITEBACK_RESULT();
}
-// switch(EL)
-// {
-// case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */
-// break;
-// case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */
-// break;
-// case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */
-// break;
-// case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */
-// break;
-// case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */
-// break;
-// case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */
-// break;
-// case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */
-// break;
-// case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */
-// break;
-// case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */
-// break;
-// case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */
-// break;
-// case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */
-// break;
-// case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */
-// break;
-// case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */
-// break;
-// case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */
-// break;
-// case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */
-// break;
-// case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */
-// break;
-// }
+// switch(EL)
+// {
+// case 0: /* 0, 1, 2, 3, 4, 5, 6, 7 - none */ /* 0, 1, 2, 3, 4, 5, 6, 7 - none */
+// break;
+// case 1: /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */ /* 0, 1, 2, 3, 4, 5, 6, 7 - ??? */
+// break;
+// case 2: /* 1, 3, 5, 7, 0, 2, 4, 6 - 0q */ /* 0, 0, 2, 2, 4, 4, 6, 6 - 0q */
+// break;
+// case 3: /* 0, 2, 4, 6, 1, 3, 5, 7 - 1q */ /* 1, 1, 3, 3, 5, 5, 7, 7 - 1q */
+// break;
+// case 4: /* 1, 2, 3, 5, 6, 7, 0, 4 - 0h */ /* 0, 0, 0, 0, 4, 4, 4, 4 - 0h */
+// break;
+// case 5: /* 0, 2, 3, 4, 6, 7, 1, 5 - 1h */ /* 1, 1, 1, 1, 5, 5, 5, 5 - 1h */
+// break;
+// case 6: /* 0, 1, 3, 4, 5, 7, 2, 6 - 2h */ /* 2, 2, 2, 2, 6, 6, 6, 6 - 2h */
+// break;
+// case 7: /* 0, 1, 2, 4, 5, 6, 3, 7 - 3h */ /* 3, 3, 3, 3, 7, 7, 7, 7 - 3h */
+// break;
+// case 8: /* 1, 2, 3, 4, 5, 6, 7, 0 - 0 */ /* 0, 0, 0, 0, 0, 0, 0, 0 - 0 */
+// break;
+// case 9: /* 0, 2, 3, 4, 5, 6, 7, 1 - 1 */ /* 1, 1, 1, 1, 1, 1, 1, 1 - 0 */
+// break;
+// case 10:/* 0, 1, 3, 4, 5, 6, 7, 2 - 2 */ /* 2, 2, 2, 2, 2, 2, 2, 2 - 0 */
+// break;
+// case 11:/* 0, 1, 2, 4, 5, 6, 7, 3 - 3 */ /* 3, 3, 3, 3, 3, 3, 3, 3 - 0 */
+// break;
+// case 12:/* 0, 1, 2, 3, 5, 6, 7, 4 - 4 */ /* 4, 4, 4, 4, 4, 4, 4, 4 - 0 */
+// break;
+// case 13:/* 0, 1, 2, 3, 4, 6, 7, 5 - 5 */ /* 5, 5, 5, 5, 5, 5, 5, 5 - 0 */
+// break;
+// case 14:/* 0, 1, 2, 3, 4, 5, 7, 6 - 6 */ /* 6, 6, 6, 6, 6, 6, 6, 6 - 0 */
+// break;
+// case 15:/* 0, 1, 2, 3, 4, 5, 6, 7 - 7 */ /* 7, 7, 7, 7, 7, 7, 7, 7 - 0 */
+// break;
+// }
#define RSP_VMRG(E10, E11, E12, E13, E14, E15, E16, E17, E20, E21, E22, E23, E24, E25, E26, E27) \
if (COMPARE_FLAG(E10)) \
@@ -3622,7 +3622,7 @@ static void code_compile_block(rsp_state *rsp, offs_t pc)
int override = FALSE;
drcuml_block *block;
jmp_buf errorbuf;
-
+
profiler_mark_start(PROFILER_DRC_COMPILE);
/* get a description of this sequence */
@@ -3893,7 +3893,7 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit
UML_DLOAD(block, IREG(3), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i3,dmem,i0,qword_x1
UML_DROL(block, IREG(3), IREG(3), IREG(2)); // drol i3,i3,i2
UML_DAND(block, IREG(1), IREG(1), IMM(0xffff)); // dand i1,i1,0xffff
- UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffffffff0000))); // dand i3,i3,~0xffff
+ UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffffffff0000))); // dand i3,i3,~0xffff
UML_DOR(block, IREG(1), IREG(1), IREG(3)); // dor i1,i1,i3
UML_DROR(block, IREG(1), IREG(1), IREG(2)); // dror i1,i1,i2
UML_DSTORE(block, rsp->impstate->dmem, IREG(0), IREG(1), QWORD_x1); // dstore dmem,i0,i1,qword_x1
@@ -3915,7 +3915,7 @@ static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrit
UML_DLOAD(block, IREG(3), rsp->impstate->dmem, IREG(0), QWORD_x1); // dload i3,dmem,i0,qword_x1
UML_DROL(block, IREG(3), IREG(3), IREG(2)); // drol i3,i3,i2
UML_DAND(block, IREG(1), IREG(1), IMM(0xffffffff)); // dand i1,i1,0xffffffff
- UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffff00000000))); // dand i3,i3,~0xffffffff
+ UML_DAND(block, IREG(3), IREG(3), IMM(U64(0xffffffff00000000))); // dand i3,i3,~0xffffffff
UML_DOR(block, IREG(1), IREG(1), IREG(3)); // dor i1,i1,i3
UML_DROR(block, IREG(1), IREG(1), IREG(2)); // dror i1,i1,i2
UML_DSTORE(block, rsp->impstate->dmem, IREG(0), IREG(1), QWORD_x1); // dstore dmem,i0,i1,qword_x1
@@ -4076,9 +4076,9 @@ static void generate_sequence_instruction(rsp_state *rsp, drcuml_block *block, c
/* if we hit an unmapped address, fatal error */
//if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
//{
- // UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc
- // save_fast_iregs(rsp, block);
- // UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE
+ // UML_MOV(block, MEM(&rsp->pc), IMM(desc->pc)); // mov [pc],desc->pc
+ // save_fast_iregs(rsp, block);
+ // UML_EXIT(block, IMM(EXECUTE_UNMAPPED_CODE)); // exit EXECUTE_UNMAPPED_CODE
//}
/* otherwise, unless this is a virtual no-op, it's a regular instruction */
@@ -4587,7 +4587,7 @@ static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *co
{
UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_mfc2, rsp); // callc cfunc_mfc2
- //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword
+ //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword
}
return TRUE;
@@ -4596,7 +4596,7 @@ static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *co
{
UML_MOV(block, MEM(&rsp->impstate->arg0), IMM(desc->opptr.l[0])); // mov [arg0],desc->opptr.l
UML_CALLC(block, cfunc_cfc2, rsp); // callc cfunc_cfc2
- //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword
+ //UML_SEXT(block, R32(RTREG), IREG(0), DWORD); // dsext <rtreg>,i0,dword
}
return TRUE;
diff --git a/src/emu/cpu/x86emit.h b/src/emu/cpu/x86emit.h
index 10395c52d4a..007d3600c1a 100644
--- a/src/emu/cpu/x86emit.h
+++ b/src/emu/cpu/x86emit.h
@@ -1900,7 +1900,7 @@ INLINE void emit_movsx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) {
INLINE void emit_movsx_r32_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, MEMPARAMS); }
INLINE void emit_movsx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, sreg); }
INLINE void emit_movsx_r32_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, MEMPARAMS); }
-INLINE void emit_movzx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
+INLINE void emit_movzx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
{
#ifndef PTR64
if (sreg >= 4)