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-rw-r--r--src/emu/cpu/asap/asap.c2
-rw-r--r--src/emu/cpu/avr8/avr8.c2
-rw-r--r--src/emu/cpu/drcbex64.c8
-rw-r--r--src/emu/cpu/drcbex86.c6
-rw-r--r--src/emu/cpu/es5510/es5510.c2
-rw-r--r--src/emu/cpu/h83002/h8speriph.c28
-rw-r--r--src/emu/cpu/i386/i386dasm.c2
-rw-r--r--src/emu/cpu/nec/necdasm.c2
-rw-r--r--src/emu/cpu/powerpc/ppccom.c4
-rw-r--r--src/emu/cpu/rsp/rspdrc.c2
-rw-r--r--src/emu/cpu/tms32031/dis32031.c2
-rw-r--r--src/emu/cpu/tms32031/tms32031.c6
-rw-r--r--src/emu/cpu/tms34010/tms34010.c4
13 files changed, 44 insertions, 26 deletions
diff --git a/src/emu/cpu/asap/asap.c b/src/emu/cpu/asap/asap.c
index cb6fcba1df7..ffa58a598cc 100644
--- a/src/emu/cpu/asap/asap.c
+++ b/src/emu/cpu/asap/asap.c
@@ -27,7 +27,7 @@ const UINT32 PS_NFLAG = 0x00000008;
const UINT32 PS_IFLAG = 0x00000010;
const UINT32 PS_PFLAG = 0x00000020;
-const int EXCEPTION_RESET = 0;
+//const int EXCEPTION_RESET = 0;
const int EXCEPTION_TRAP0 = 1;
const int EXCEPTION_TRAPF = 2;
const int EXCEPTION_INTERRUPT = 3;
diff --git a/src/emu/cpu/avr8/avr8.c b/src/emu/cpu/avr8/avr8.c
index 4c9892a3695..36b3c87edc6 100644
--- a/src/emu/cpu/avr8/avr8.c
+++ b/src/emu/cpu/avr8/avr8.c
@@ -165,7 +165,7 @@ enum
WGM5_FAST_PWM_OCR
};
-static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' };
+//static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' };
#define SREG_R(b) ((m_r[AVR8_REGIDX_SREG] & (1 << (b))) >> (b))
#define SREG_W(b,v) m_r[AVR8_REGIDX_SREG] = (m_r[AVR8_REGIDX_SREG] & ~(1 << (b))) | ((v) << (b))
diff --git a/src/emu/cpu/drcbex64.c b/src/emu/cpu/drcbex64.c
index d13d46abc5f..532c493619e 100644
--- a/src/emu/cpu/drcbex64.c
+++ b/src/emu/cpu/drcbex64.c
@@ -198,8 +198,8 @@ const UINT32 PTYPE_M = 1 << parameter::PTYPE_MEMORY;
const UINT32 PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE;
const UINT32 PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER;
const UINT32 PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER;
-const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I;
-const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I;
+//const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I;
+//const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MR = PTYPE_M | PTYPE_R;
const UINT32 PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F;
@@ -248,7 +248,7 @@ inline x86_memref drcbe_x64::MABS(const void *ptr)
drcbe_x64::opcode_generate_func drcbe_x64::s_opcode_table[OP_MAX];
// size-to-mask table
-static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) };
+//static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) };
// register mapping tables
static const UINT8 int_register_map[REG_I_COUNT] =
@@ -286,6 +286,7 @@ static const UINT8 condition_map[uml::COND_MAX - uml::COND_Z] =
x64emit::COND_GE, // COND_GE, requires SV
};
+#if 0
// rounding mode mapping table
static const UINT8 fprnd_map[4] =
{
@@ -294,6 +295,7 @@ static const UINT8 fprnd_map[4] =
FPRND_UP, // ROUND_CEIL, round up
FPRND_DOWN // ROUND_FLOOR round down
};
+#endif
diff --git a/src/emu/cpu/drcbex86.c b/src/emu/cpu/drcbex86.c
index 5ba18d6bf4c..0575c92a673 100644
--- a/src/emu/cpu/drcbex86.c
+++ b/src/emu/cpu/drcbex86.c
@@ -108,8 +108,8 @@ const UINT32 PTYPE_M = 1 << parameter::PTYPE_MEMORY;
const UINT32 PTYPE_I = 1 << parameter::PTYPE_IMMEDIATE;
const UINT32 PTYPE_R = 1 << parameter::PTYPE_INT_REGISTER;
const UINT32 PTYPE_F = 1 << parameter::PTYPE_FLOAT_REGISTER;
-const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I;
-const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I;
+//const UINT32 PTYPE_MI = PTYPE_M | PTYPE_I;
+//const UINT32 PTYPE_RI = PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MR = PTYPE_M | PTYPE_R;
const UINT32 PTYPE_MRI = PTYPE_M | PTYPE_R | PTYPE_I;
const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F;
@@ -137,7 +137,7 @@ const UINT32 PTYPE_MF = PTYPE_M | PTYPE_F;
drcbe_x86::opcode_generate_func drcbe_x86::s_opcode_table[OP_MAX];
// size-to-mask table
-static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) };
+//static const UINT64 size_to_mask[] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0, U64(0xffffffffffffffff) };
// register mapping tables
static const UINT8 int_register_map[REG_I_COUNT] =
diff --git a/src/emu/cpu/es5510/es5510.c b/src/emu/cpu/es5510/es5510.c
index 060ed8394e4..82a9c048cad 100644
--- a/src/emu/cpu/es5510/es5510.c
+++ b/src/emu/cpu/es5510/es5510.c
@@ -26,7 +26,7 @@ static const INT64 MAX_48 = (S64(1) << 47) - 1;
static inline INT32 SX(INT32 x) { return IS_NEGATIVE(x) ? x | 0xff000000 : x & 0x00ffffff; }
static inline INT32 SC(INT32 x) { return x & 0x00ffffff; }
static inline INT64 SX64(INT64 x) { return (x & S64(0x0000800000000000)) ? x | S64(0xffff000000000000) : x & S64(0x0000ffffffffffff); }
-static inline INT64 SC64(INT64 x) { return x & S64(0x0000ffffffffffff); }
+//static inline INT64 SC64(INT64 x) { return x & S64(0x0000ffffffffffff); }
#define VERBOSE 0
#define VERBOSE_EXEC 0
diff --git a/src/emu/cpu/h83002/h8speriph.c b/src/emu/cpu/h83002/h8speriph.c
index 933cde525ca..20dc048c533 100644
--- a/src/emu/cpu/h83002/h8speriph.c
+++ b/src/emu/cpu/h83002/h8speriph.c
@@ -228,15 +228,15 @@ const int TPU_3_DIV[] = { 1, 4, 16, 64, 0, 1024, 256, 4096 };
const int TPU_4_DIV[] = { 1, 4, 16, 64, 0, 0, 1024, 0 };
const int TPU_5_DIV[] = { 1, 4, 16, 64, 0, 0, 256, 0 };
-const int H8S_IO_SMR[] = { H8S_IO_SMR0, H8S_IO_SMR1, H8S_IO_SMR2 };
-const int H8S_IO_BRR[] = { H8S_IO_BRR0, H8S_IO_BRR1, H8S_IO_BRR2 };
-const int H8S_IO_SCR[] = { H8S_IO_SCR0, H8S_IO_SCR1, H8S_IO_SCR2 };
-const int H8S_IO_TDR[] = { H8S_IO_TDR0, H8S_IO_TDR1, H8S_IO_TDR2 };
-const int H8S_IO_SSR[] = { H8S_IO_SSR0, H8S_IO_SSR1, H8S_IO_SSR2 };
-const int H8S_IO_RDR[] = { H8S_IO_RDR0, H8S_IO_RDR1, H8S_IO_RDR2 };
+//const int H8S_IO_SMR[] = { H8S_IO_SMR0, H8S_IO_SMR1, H8S_IO_SMR2 };
+//const int H8S_IO_BRR[] = { H8S_IO_BRR0, H8S_IO_BRR1, H8S_IO_BRR2 };
+//const int H8S_IO_SCR[] = { H8S_IO_SCR0, H8S_IO_SCR1, H8S_IO_SCR2 };
+//const int H8S_IO_TDR[] = { H8S_IO_TDR0, H8S_IO_TDR1, H8S_IO_TDR2 };
+//const int H8S_IO_SSR[] = { H8S_IO_SSR0, H8S_IO_SSR1, H8S_IO_SSR2 };
+//const int H8S_IO_RDR[] = { H8S_IO_RDR0, H8S_IO_RDR1, H8S_IO_RDR2 };
-const int H8S_INT_TXI[] = { H8S_INT_TXI0, H8S_INT_TXI1, H8S_INT_TXI2 };
-const int H8S_INT_RXI[] = { H8S_INT_RXI0, H8S_INT_RXI1, H8S_INT_RXI2 };
+//const int H8S_INT_TXI[] = { H8S_INT_TXI0, H8S_INT_TXI1, H8S_INT_TXI2 };
+//const int H8S_INT_RXI[] = { H8S_INT_RXI0, H8S_INT_RXI1, H8S_INT_RXI2 };
const int H8S_IO_TCORA[] = { H8S_IO_TCORA0, H8S_IO_TCORA1 };
const int H8S_IO_TCORB[] = { H8S_IO_TCORB0, H8S_IO_TCORB1 };
@@ -249,15 +249,15 @@ const int H8S_INT_CMIA[] = { H8S_INT_CMIA0, H8S_INT_CMIA1 };
const int H8S_INT_CMIB[] = { H8S_INT_CMIB0, H8S_INT_CMIB1 };
const int H8S_IO_TGRA_H[] = { H8S_IO_TGR0A_H, H8S_IO_TGR1A_H, H8S_IO_TGR2A_H, H8S_IO_TGR3A_H, H8S_IO_TGR4A_H, H8S_IO_TGR5A_H };
-const int H8S_IO_TGRA_L[] = { H8S_IO_TGR0A_L, H8S_IO_TGR1A_L, H8S_IO_TGR2A_L, H8S_IO_TGR3A_L, H8S_IO_TGR4A_L, H8S_IO_TGR5A_L };
+//const int H8S_IO_TGRA_L[] = { H8S_IO_TGR0A_L, H8S_IO_TGR1A_L, H8S_IO_TGR2A_L, H8S_IO_TGR3A_L, H8S_IO_TGR4A_L, H8S_IO_TGR5A_L };
const int H8S_IO_TGRB_H[] = { H8S_IO_TGR0B_H, H8S_IO_TGR1B_H, H8S_IO_TGR2B_H, H8S_IO_TGR3B_H, H8S_IO_TGR4B_H, H8S_IO_TGR5B_H };
-const int H8S_IO_TGRB_L[] = { H8S_IO_TGR0B_L, H8S_IO_TGR1B_L, H8S_IO_TGR2B_L, H8S_IO_TGR3B_L, H8S_IO_TGR4B_L, H8S_IO_TGR5B_L };
+//const int H8S_IO_TGRB_L[] = { H8S_IO_TGR0B_L, H8S_IO_TGR1B_L, H8S_IO_TGR2B_L, H8S_IO_TGR3B_L, H8S_IO_TGR4B_L, H8S_IO_TGR5B_L };
const int H8S_IO_TGRC_H[] = { H8S_IO_TGR0C_H, 0, 0, H8S_IO_TGR3C_H, 0, 0 };
-const int H8S_IO_TGRC_L[] = { H8S_IO_TGR0C_L, 0, 0, H8S_IO_TGR3C_L, 0, 0 };
+//const int H8S_IO_TGRC_L[] = { H8S_IO_TGR0C_L, 0, 0, H8S_IO_TGR3C_L, 0, 0 };
const int H8S_IO_TGRD_H[] = { H8S_IO_TGR0D_H, 0, 0, H8S_IO_TGR3D_H, 0, 0 };
-const int H8S_IO_TGRD_L[] = { H8S_IO_TGR0D_L, 0, 0, H8S_IO_TGR3D_L, 0, 0 };
+//const int H8S_IO_TGRD_L[] = { H8S_IO_TGR0D_L, 0, 0, H8S_IO_TGR3D_L, 0, 0 };
const int H8S_IO_TCNT_H[] = { H8S_IO_TCNT0_H, H8S_IO_TCNT1_H, H8S_IO_TCNT2_H, H8S_IO_TCNT3_H, H8S_IO_TCNT4_H, H8S_IO_TCNT5_H };
-const int H8S_IO_TCNT_L[] = { H8S_IO_TCNT0_L, H8S_IO_TCNT1_L, H8S_IO_TCNT2_L, H8S_IO_TCNT3_L, H8S_IO_TCNT4_L, H8S_IO_TCNT5_L };
+//const int H8S_IO_TCNT_L[] = { H8S_IO_TCNT0_L, H8S_IO_TCNT1_L, H8S_IO_TCNT2_L, H8S_IO_TCNT3_L, H8S_IO_TCNT4_L, H8S_IO_TCNT5_L };
const int H8S_IO_TIOR_H[] = { H8S_IO_TIOR0_H, H8S_IO_TIOR1, H8S_IO_TIOR2, H8S_IO_TIOR3_H, H8S_IO_TIOR4, H8S_IO_TIOR5 };
const int H8S_IO_TIOR_L[] = { H8S_IO_TIOR0_L, 0, 0, H8S_IO_TIOR3_L, 0, 0 };
const int H8S_IO_TTCR[] = { H8S_IO_TTCR0, H8S_IO_TTCR1, H8S_IO_TTCR2, H8S_IO_TTCR3, H8S_IO_TTCR4, H8S_IO_TTCR5 };
@@ -265,7 +265,7 @@ const int H8S_IO_TIER[] = { H8S_IO_TIER0, H8S_IO_TIER1, H8S_IO_TIER2, H8S_IO_T
const int H8S_IO_TSR[] = { H8S_IO_TSR0, H8S_IO_TSR1, H8S_IO_TSR2, H8S_IO_TSR3, H8S_IO_TSR4, H8S_IO_TSR5 };
const int H8S_INT_TCIV[] = { H8S_INT_TCI0V, H8S_INT_TCI1V, H8S_INT_TCI2V, H8S_INT_TCI3V, H8S_INT_TCI4V, H8S_INT_TCI5V };
-const int H8S_INT_TCIU[] = { 0, H8S_INT_TCI1U, H8S_INT_TCI2U, 0, H8S_INT_TCI4U, H8S_INT_TCI5U };
+//const int H8S_INT_TCIU[] = { 0, H8S_INT_TCI1U, H8S_INT_TCI2U, 0, H8S_INT_TCI4U, H8S_INT_TCI5U };
const int H8S_INT_TGIA[] = { H8S_INT_TGI0A, H8S_INT_TGI1A, H8S_INT_TGI2A, H8S_INT_TGI3A, H8S_INT_TGI4A, H8S_INT_TGI5A };
const int H8S_INT_TGIB[] = { H8S_INT_TGI0B, H8S_INT_TGI1B, H8S_INT_TGI2B, H8S_INT_TGI3B, H8S_INT_TGI4B, H8S_INT_TGI5B };
const int H8S_INT_TGIC[] = { H8S_INT_TGI0C, 0, 0, H8S_INT_TGI3C, 0, 0 };
diff --git a/src/emu/cpu/i386/i386dasm.c b/src/emu/cpu/i386/i386dasm.c
index 82423552ac3..be98380d726 100644
--- a/src/emu/cpu/i386/i386dasm.c
+++ b/src/emu/cpu/i386/i386dasm.c
@@ -1960,6 +1960,7 @@ INLINE UINT8 FETCH(void)
return *opcode_ptr++;
}
+#if 0
INLINE UINT16 FETCH16(void)
{
UINT16 d;
@@ -1970,6 +1971,7 @@ INLINE UINT16 FETCH16(void)
pc += 2;
return d;
}
+#endif
INLINE UINT32 FETCH32(void)
{
diff --git a/src/emu/cpu/nec/necdasm.c b/src/emu/cpu/nec/necdasm.c
index 23a763614fc..4c89a67b678 100644
--- a/src/emu/cpu/nec/necdasm.c
+++ b/src/emu/cpu/nec/necdasm.c
@@ -881,6 +881,7 @@ INLINE UINT8 FETCH(void)
return *opcode_ptr++;
}
+#if 0
INLINE UINT16 FETCH16(void)
{
UINT16 d;
@@ -891,6 +892,7 @@ INLINE UINT16 FETCH16(void)
pc += 2;
return d;
}
+#endif
INLINE UINT8 FETCHD(void)
{
diff --git a/src/emu/cpu/powerpc/ppccom.c b/src/emu/cpu/powerpc/ppccom.c
index a61214130f7..4565b7b912c 100644
--- a/src/emu/cpu/powerpc/ppccom.c
+++ b/src/emu/cpu/powerpc/ppccom.c
@@ -204,6 +204,7 @@ INLINE void set_decrementer(powerpc_state *ppc, UINT32 newdec)
}
+#if 0
/*-------------------------------------------------
is_nan_double - is a double value a NaN
-------------------------------------------------*/
@@ -214,6 +215,7 @@ INLINE int is_nan_double(double x)
return( ((xi & DOUBLE_EXP) == DOUBLE_EXP) &&
((xi & DOUBLE_FRAC) != DOUBLE_ZERO) );
}
+#endif
/*-------------------------------------------------
@@ -230,6 +232,7 @@ INLINE int is_qnan_double(double x)
}
+#if 0
/*-------------------------------------------------
is_snan_double - is a double value a
signaling NaN
@@ -242,6 +245,7 @@ INLINE int is_snan_double(double x)
((xi & DOUBLE_FRAC) != DOUBLE_ZERO) &&
((xi & U64(0x0008000000000000)) == DOUBLE_ZERO) );
}
+#endif
/*-------------------------------------------------
diff --git a/src/emu/cpu/rsp/rspdrc.c b/src/emu/cpu/rsp/rspdrc.c
index 5d209a0990e..a78b5aa814b 100644
--- a/src/emu/cpu/rsp/rspdrc.c
+++ b/src/emu/cpu/rsp/rspdrc.c
@@ -2116,6 +2116,7 @@ INLINE UINT16 SATURATE_ACCUM1(rsp_state *rsp, int accum, UINT16 negative, UINT16
return 0;
}
+#if 0
INLINE UINT16 C_SATURATE_ACCUM1(UINT16 *h, UINT16 *m, int accum, UINT16 negative, UINT16 positive)
{
// Return negative if H<0 && (H!=0xffff || M >= 0)
@@ -2161,6 +2162,7 @@ INLINE UINT16 C_SATURATE_ACCUM1(UINT16 *h, UINT16 *m, int accum, UINT16 negative
return 0;
}
+#endif
#if USE_SIMD
#define WRITEBACK_RESULT() { \
diff --git a/src/emu/cpu/tms32031/dis32031.c b/src/emu/cpu/tms32031/dis32031.c
index 3cd7afe437d..56e3533e474 100644
--- a/src/emu/cpu/tms32031/dis32031.c
+++ b/src/emu/cpu/tms32031/dis32031.c
@@ -30,6 +30,7 @@
CODE CODE
***************************************************************************/
+#if 0
INLINE char *signed_16bit(INT16 val)
{
static char temp[10];
@@ -39,6 +40,7 @@ INLINE char *signed_16bit(INT16 val)
sprintf(temp, "$%x", val);
return temp;
}
+#endif
static const char *const regname[32] =
{
diff --git a/src/emu/cpu/tms32031/tms32031.c b/src/emu/cpu/tms32031/tms32031.c
index 3e85f2ffe10..3ad69d45df9 100644
--- a/src/emu/cpu/tms32031/tms32031.c
+++ b/src/emu/cpu/tms32031/tms32031.c
@@ -67,9 +67,9 @@ const int LVFLAG = 0x0020;
const int LUFFLAG = 0x0040;
const int OVMFLAG = 0x0080;
const int RMFLAG = 0x0100;
-const int CFFLAG = 0x0400;
-const int CEFLAG = 0x0800;
-const int CCFLAG = 0x1000;
+//const int CFFLAG = 0x0400;
+//const int CEFLAG = 0x0800;
+//const int CCFLAG = 0x1000;
const int GIEFLAG = 0x2000;
diff --git a/src/emu/cpu/tms34010/tms34010.c b/src/emu/cpu/tms34010/tms34010.c
index 81077435393..635de9fea48 100644
--- a/src/emu/cpu/tms34010/tms34010.c
+++ b/src/emu/cpu/tms34010/tms34010.c
@@ -1169,6 +1169,7 @@ UINT32 tms34010_device::tms340x0_rgb32(screen_device &screen, bitmap_rgb32 &bitm
I/O REGISTER WRITES
***************************************************************************/
+#if 0
static const char *const ioreg_name[] =
{
"HESYNC", "HEBLNK", "HSBLNK", "HTOTAL",
@@ -1181,6 +1182,7 @@ static const char *const ioreg_name[] =
"RESERVED", "RESERVED", "RESERVED", "DPYTAP",
"HCOUNT", "VCOUNT", "DPYADR", "REFCNT"
};
+#endif
WRITE16_HANDLER( tms34010_io_register_w )
{
@@ -1302,6 +1304,7 @@ WRITE16_HANDLER( tms34010_io_register_w )
}
+#if 0
static const char *const ioreg020_name[] =
{
"VESYNC", "HESYNC", "VEBLNK", "HEBLNK",
@@ -1324,6 +1327,7 @@ static const char *const ioreg020_name[] =
"IHOST1L", "IHOST1H", "IHOST2L", "IHOST2H",
"IHOST3L", "IHOST3H", "IHOST4L", "IHOST4H"
};
+#endif
WRITE16_HANDLER( tms34020_io_register_w )
{