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-rw-r--r--src/emu/cpu/alph8201/alph8201.c1
-rw-r--r--src/emu/cpu/am29000/am29000.c25
-rw-r--r--src/emu/cpu/apexc/apexc.c3
-rw-r--r--src/emu/cpu/apexc/apexc.h2
-rw-r--r--src/emu/cpu/arm/arm.c17
-rw-r--r--src/emu/cpu/arm/arm.h4
-rw-r--r--src/emu/cpu/arm7/arm7.c23
-rw-r--r--src/emu/cpu/arm7/arm7.h2
-rw-r--r--src/emu/cpu/arm7/arm7core.c1
-rw-r--r--src/emu/cpu/arm7/arm7drc.c8
-rw-r--r--src/emu/cpu/arm7/arm7ops.c4
-rw-r--r--src/emu/cpu/arm7/arm7tdrc.c1
-rw-r--r--src/emu/cpu/ccpu/ccpu.c4
-rw-r--r--src/emu/cpu/cop400/cop400.c1
-rw-r--r--src/emu/cpu/cop400/cop400.h2
-rw-r--r--src/emu/cpu/cp1610/cp1610.c2
-rw-r--r--src/emu/cpu/cpu.mak2
-rw-r--r--src/emu/cpu/dsp16/dsp16.c204
-rw-r--r--src/emu/cpu/dsp16/dsp16.h16
-rw-r--r--src/emu/cpu/dsp16/dsp16ops.c78
-rw-r--r--src/emu/cpu/es5510/es5510.c14
-rw-r--r--src/emu/cpu/es5510/es5510.h2
-rw-r--r--src/emu/cpu/hcd62121/hcd62121.c3
-rw-r--r--src/emu/cpu/i386/i386ops.h78
-rw-r--r--src/emu/cpu/i386/pentops.c20
-rw-r--r--src/emu/cpu/i4004/i4004.c6
-rw-r--r--src/emu/cpu/lr35902/lr35902.h4
-rw-r--r--src/emu/cpu/m68000/m68000.h18
-rw-r--r--src/emu/cpu/m68000/m68kcpu.c145
-rw-r--r--src/emu/cpu/mcs48/mcs48.h2
-rw-r--r--src/emu/cpu/rsp/rspdrc.c136
-rw-r--r--src/emu/cpu/tms0980/tms0980.c11
-rw-r--r--src/emu/cpu/tms0980/tms0980.h6
-rw-r--r--src/emu/cpu/tms32082/dis32082.c376
-rw-r--r--src/emu/cpu/tms32082/mp_ops.c186
-rw-r--r--src/emu/cpu/tms32082/tms32082.c8
-rw-r--r--src/emu/cpu/tms32082/tms32082.h4
37 files changed, 691 insertions, 728 deletions
diff --git a/src/emu/cpu/alph8201/alph8201.c b/src/emu/cpu/alph8201/alph8201.c
index b575728ed8f..63fa0c66818 100644
--- a/src/emu/cpu/alph8201/alph8201.c
+++ b/src/emu/cpu/alph8201/alph8201.c
@@ -645,4 +645,3 @@ offs_t alpha8201_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const U
extern CPU_DISASSEMBLE( alpha8201 );
return CPU_DISASSEMBLE_NAME(alpha8201)(this, buffer, pc, oprom, opram, options);
}
-
diff --git a/src/emu/cpu/am29000/am29000.c b/src/emu/cpu/am29000/am29000.c
index ae8ebe8d7d4..f8f025c2578 100644
--- a/src/emu/cpu/am29000/am29000.c
+++ b/src/emu/cpu/am29000/am29000.c
@@ -196,9 +196,9 @@ void am29000_cpu_device::device_start()
state_add( AM29000_IPB, "IPB", m_ipb ).formatstr("%08X");
state_add( AM29000_Q, "Q", m_q ).formatstr("%08X");
state_add( AM29000_ALU, "ALU", m_alu ).formatstr("%08X");
-// state_add( AM29000_BP, "BP", GET_ALU_BP).formatstr("%08X");
-// state_add( AM29000_FC, "FC", GET_ALU_FC).formatstr("%08X");
-// state_add( AM29000_CR, "CR", GET_CHC_CR).formatstr("%08X");
+// state_add( AM29000_BP, "BP", GET_ALU_BP).formatstr("%08X");
+// state_add( AM29000_FC, "FC", GET_ALU_FC).formatstr("%08X");
+// state_add( AM29000_CR, "CR", GET_CHC_CR).formatstr("%08X");
state_add( AM29000_FPE, "FPE", m_fpe ).formatstr("%08X");
state_add( AM29000_INTE, "INTE", m_inte ).formatstr("%08X");
state_add( AM29000_FPS, "FPS", m_fps ).formatstr("%08X");
@@ -409,15 +409,15 @@ void am29000_cpu_device::state_string_export(const device_state_entry &entry, as
{
case STATE_GENFLAGS:
string.printf("%c%c%c%c%c%c%c%c%c|%3d", m_alu & ALU_V ? 'V' : '.',
- m_alu & ALU_Z ? 'Z' : '.',
- m_alu & ALU_N ? 'N' : '.',
- m_alu & ALU_C ? 'C' : '.',
- m_cps & CPS_IP ? 'I' : '.',
- m_cps & CPS_FZ ? 'F' : '.',
- m_cps & CPS_SM ? 'S' : 'U',
- m_cps & CPS_DI ? 'I' : '.',
- m_cps & CPS_DA ? 'D' : '.',
- (m_r[1] >> 2) & 0x7f);
+ m_alu & ALU_Z ? 'Z' : '.',
+ m_alu & ALU_N ? 'N' : '.',
+ m_alu & ALU_C ? 'C' : '.',
+ m_cps & CPS_IP ? 'I' : '.',
+ m_cps & CPS_FZ ? 'F' : '.',
+ m_cps & CPS_SM ? 'S' : 'U',
+ m_cps & CPS_DI ? 'I' : '.',
+ m_cps & CPS_DA ? 'D' : '.',
+ (m_r[1] >> 2) & 0x7f);
break;
}
}
@@ -675,4 +675,3 @@ offs_t am29000_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UIN
extern CPU_DISASSEMBLE( am29000 );
return CPU_DISASSEMBLE_NAME(am29000)(this, buffer, pc, oprom, opram, options);
}
-
diff --git a/src/emu/cpu/apexc/apexc.c b/src/emu/cpu/apexc/apexc.c
index b802ed38b05..8ec78c15e74 100644
--- a/src/emu/cpu/apexc/apexc.c
+++ b/src/emu/cpu/apexc/apexc.c
@@ -825,7 +825,7 @@ void apexc_cpu_device::device_reset()
/* next two lines are just the product of my bold fantasy */
m_cr = 0; /* first instruction executed will be a stop */
m_running = TRUE; /* this causes the CPU to load the instruction at 0/0,
- which enables easy booting (just press run on the panel) */
+ which enables easy booting (just press run on the panel) */
m_a = 0;
m_r = 0;
m_pc = 0;
@@ -854,4 +854,3 @@ offs_t apexc_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
extern CPU_DISASSEMBLE( apexc );
return CPU_DISASSEMBLE_NAME(apexc)(this, buffer, pc, oprom, opram, options);
}
-
diff --git a/src/emu/cpu/apexc/apexc.h b/src/emu/cpu/apexc/apexc.h
index 9a1d5a92ed1..1f18757dd51 100644
--- a/src/emu/cpu/apexc/apexc.h
+++ b/src/emu/cpu/apexc/apexc.h
@@ -73,7 +73,7 @@ protected:
int m_current_word; /* current word position within track (0-31) */
int m_running; /* 1 flag: */
- /* running: flag implied by the existence of the stop instruction */
+ /* running: flag implied by the existence of the stop instruction */
UINT32 m_pc; /* address of next instruction for the disassembler */
address_space *m_program;
diff --git a/src/emu/cpu/arm/arm.c b/src/emu/cpu/arm/arm.c
index a8e1b83d31d..6463f7c2c18 100644
--- a/src/emu/cpu/arm/arm.c
+++ b/src/emu/cpu/arm/arm.c
@@ -320,7 +320,7 @@ void arm_cpu_device::device_reset()
m_coproRegister[i] = 0;
}
m_pendingIrq = 0;
- m_pendingFiq = 0;
+ m_pendingFiq = 0;
/* start up in SVC mode with interrupts disabled. */
R15 = eARM_MODE_SVC|I_MASK|F_MASK;
@@ -549,13 +549,13 @@ void arm_cpu_device::state_string_export(const device_state_entry &entry, astrin
{
case STATE_GENFLAGS:
string.printf("%c%c%c%c%c%c %s",
- (m_sArmRegister[15] & N_MASK) ? 'N' : '-',
- (m_sArmRegister[15] & Z_MASK) ? 'Z' : '-',
- (m_sArmRegister[15] & C_MASK) ? 'C' : '-',
- (m_sArmRegister[15] & V_MASK) ? 'V' : '-',
- (m_sArmRegister[15] & I_MASK) ? 'I' : '-',
- (m_sArmRegister[15] & F_MASK) ? 'F' : '-',
- s[m_sArmRegister[15] & 3] );
+ (m_sArmRegister[15] & N_MASK) ? 'N' : '-',
+ (m_sArmRegister[15] & Z_MASK) ? 'Z' : '-',
+ (m_sArmRegister[15] & C_MASK) ? 'C' : '-',
+ (m_sArmRegister[15] & V_MASK) ? 'V' : '-',
+ (m_sArmRegister[15] & I_MASK) ? 'I' : '-',
+ (m_sArmRegister[15] & F_MASK) ? 'F' : '-',
+ s[m_sArmRegister[15] & 3] );
break;
}
}
@@ -1470,4 +1470,3 @@ offs_t arm_be_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT
extern CPU_DISASSEMBLE( arm_be );
return CPU_DISASSEMBLE_NAME(arm_be)(this, buffer, pc, oprom, opram, options);
}
-
diff --git a/src/emu/cpu/arm/arm.h b/src/emu/cpu/arm/arm.h
index 44a15e31978..5cfde924337 100644
--- a/src/emu/cpu/arm/arm.h
+++ b/src/emu/cpu/arm/arm.h
@@ -95,8 +95,8 @@ protected:
class arm_be_cpu_device : public arm_cpu_device
{
public:
- // construction/destruction
- arm_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ // construction/destruction
+ arm_be_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
diff --git a/src/emu/cpu/arm7/arm7.c b/src/emu/cpu/arm7/arm7.c
index 759716bc2c3..a58b8655392 100644
--- a/src/emu/cpu/arm7/arm7.c
+++ b/src/emu/cpu/arm7/arm7.c
@@ -132,7 +132,7 @@ sa1110_cpu_device::sa1110_cpu_device(const machine_config &mconfig, const char *
}
-void arm7_cpu_device::set_cpsr(UINT32 val)
+void arm7_cpu_device::set_cpsr(UINT32 val)
{
if (m_archFlags & eARM_ARCHFLAGS_MODE26)
{
@@ -558,7 +558,7 @@ void arm7_cpu_device::device_start()
state_add( ARM7_UR14, "UR14", m_r[eR14_UND] ).formatstr("%08X");
state_add( ARM7_USPSR, "UR16", m_r[eSPSR_UND]).formatstr("%08X");
- state_add(STATE_GENFLAGS, "GENFLAGS", m_r[eCPSR]).formatstr("%13s").noshow();
+ state_add(STATE_GENFLAGS, "GENFLAGS", m_r[eCPSR]).formatstr("%13s").noshow();
}
@@ -579,15 +579,15 @@ void arm7_cpu_device::state_string_export(const device_state_entry &entry, astri
{
case STATE_GENFLAGS:
string.printf("%c%c%c%c%c%c%c%c %s",
- (ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
- (ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
- (ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
- (ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
- (ARM7REG(eCPSR) & Q_MASK) ? 'Q' : '-',
- (ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
- (ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
- (ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
- GetModeText(ARM7REG(eCPSR)) );
+ (ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
+ (ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
+ (ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
+ (ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
+ (ARM7REG(eCPSR) & Q_MASK) ? 'Q' : '-',
+ (ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
+ (ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
+ (ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
+ GetModeText(ARM7REG(eCPSR)) );
break;
}
}
@@ -1219,4 +1219,3 @@ UINT8 arm7_cpu_device::arm7_cpu_read8(UINT32 addr)
}
#include "arm7drc.c"
-
diff --git a/src/emu/cpu/arm7/arm7.h b/src/emu/cpu/arm7/arm7.h
index f7e82632a48..81fbbf14c2d 100644
--- a/src/emu/cpu/arm7/arm7.h
+++ b/src/emu/cpu/arm7/arm7.h
@@ -131,7 +131,7 @@ protected:
UINT8 m_archFlags; // architecture flags
//#if ARM7_MMU_ENABLE_HACK
-// UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
+// UINT32 mmu_enable_addr; // workaround for "MMU is enabled when PA != VA" problem
//#endif
UINT32 m_copro_id;
diff --git a/src/emu/cpu/arm7/arm7core.c b/src/emu/cpu/arm7/arm7core.c
index a00fe88cf3d..9b4f02f868e 100644
--- a/src/emu/cpu/arm7/arm7core.c
+++ b/src/emu/cpu/arm7/arm7core.c
@@ -228,4 +228,3 @@ void arm7_cpu_device::arm7_check_irq_state()
return;
}
}
-
diff --git a/src/emu/cpu/arm7/arm7drc.c b/src/emu/cpu/arm7/arm7drc.c
index d418c1b4380..2086f2238d1 100644
--- a/src/emu/cpu/arm7/arm7drc.c
+++ b/src/emu/cpu/arm7/arm7drc.c
@@ -358,8 +358,8 @@ void arm7_cpu_device::code_compile_block(UINT8 mode, offs_t pc)
/* get a description of this sequence */
// TODO FIXME
const opcode_desc *desclist = NULL; //m_impstate.drcfe->describe_code(pc); // TODO
-// if (LOG_UML || LOG_NATIVE)
-// log_opcode_desc(drcuml, desclist, 0);
+// if (LOG_UML || LOG_NATIVE)
+// log_opcode_desc(drcuml, desclist, 0);
/* if we get an error back, flush the cache and try again */
bool succeeded = false;
@@ -1281,8 +1281,8 @@ void arm7_cpu_device::generate_sequence_instruction(drcuml_block *block, compile
/* add an entry for the log */
// TODO FIXME
-// if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
-// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
+// if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
+// log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
/* set the PC map variable */
//expc = (desc->flags & OPFLAG_IN_DELAY_SLOT) ? desc->pc - 3 : desc->pc;
diff --git a/src/emu/cpu/arm7/arm7ops.c b/src/emu/cpu/arm7/arm7ops.c
index 6aeb0c035ba..808c254f599 100644
--- a/src/emu/cpu/arm7/arm7ops.c
+++ b/src/emu/cpu/arm7/arm7ops.c
@@ -22,8 +22,8 @@ INT64 arm7_cpu_device::saturate_qbit_overflow(INT64 res)
void arm7_cpu_device::SwitchMode(UINT32 cpsr_mode_val)
{
- UINT32 cspr = m_r[eCPSR] & ~MODE_FLAG;
- set_cpsr(cspr | cpsr_mode_val);
+ UINT32 cspr = m_r[eCPSR] & ~MODE_FLAG;
+ set_cpsr(cspr | cpsr_mode_val);
}
diff --git a/src/emu/cpu/arm7/arm7tdrc.c b/src/emu/cpu/arm7/arm7tdrc.c
index 9163326269d..148ebcb099b 100644
--- a/src/emu/cpu/arm7/arm7tdrc.c
+++ b/src/emu/cpu/arm7/arm7tdrc.c
@@ -1589,4 +1589,3 @@ void arm7_cpu_device::drctg0f_1(drcuml_block *block, compiler_state *compiler, c
UML_OR(block, DRC_REG(14), DRC_REG(14), 1);
UML_MOV(block, DRC_PC, uml::I0);
}
-
diff --git a/src/emu/cpu/ccpu/ccpu.c b/src/emu/cpu/ccpu/ccpu.c
index 7a7bbbb8703..5570ce55def 100644
--- a/src/emu/cpu/ccpu/ccpu.c
+++ b/src/emu/cpu/ccpu/ccpu.c
@@ -142,7 +142,7 @@ void ccpu_cpu_device::state_string_export(const device_state_entry &entry, astri
switch (entry.index())
{
case STATE_GENFLAGS:
- string.printf("%c%c%c%c%c%c",
+ string.printf("%c%c%c%c%c%c",
TEST_A0 ? '0' : 'o',
TEST_NC ? 'N' : 'n',
TEST_LT ? 'L' : 'l',
@@ -685,5 +685,3 @@ offs_t ccpu_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
extern CPU_DISASSEMBLE( ccpu );
return CPU_DISASSEMBLE_NAME(ccpu)(this, buffer, pc, oprom, opram, options);
}
-
-
diff --git a/src/emu/cpu/cop400/cop400.c b/src/emu/cpu/cop400/cop400.c
index f77c5a15e8f..c7cbd8c5c4c 100644
--- a/src/emu/cpu/cop400/cop400.c
+++ b/src/emu/cpu/cop400/cop400.c
@@ -1270,4 +1270,3 @@ offs_t cop400_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT
return CPU_DISASSEMBLE_NAME(cop410)(this, buffer, pc, oprom, opram, options);
}
-
diff --git a/src/emu/cpu/cop400/cop400.h b/src/emu/cpu/cop400/cop400.h
index 6e594133ee2..957038c73e2 100644
--- a/src/emu/cpu/cop400/cop400.h
+++ b/src/emu/cpu/cop400/cop400.h
@@ -131,7 +131,7 @@ protected:
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
{
return (spacenum == AS_PROGRAM) ? &m_program_config :
- ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
+ ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
}
// device_state_interface overrides
diff --git a/src/emu/cpu/cp1610/cp1610.c b/src/emu/cpu/cp1610/cp1610.c
index 9e38476a9e6..7e0870aec93 100644
--- a/src/emu/cpu/cp1610/cp1610.c
+++ b/src/emu/cpu/cp1610/cp1610.c
@@ -3442,5 +3442,3 @@ offs_t cp1610_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT
extern CPU_DISASSEMBLE( cp1610 );
return CPU_DISASSEMBLE_NAME(cp1610)(this, buffer, pc, oprom, opram, options);
}
-
-
diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak
index c5e107d8309..519f15a04ea 100644
--- a/src/emu/cpu/cpu.mak
+++ b/src/emu/cpu/cpu.mak
@@ -566,7 +566,7 @@ $(CPUOBJ)/sh2/sh2fe.o: $(CPUSRC)/sh2/sh2fe.c \
#-------------------------------------------------
# Hitachi SH4
-#@src/emu/cpu/sh4/sh4.h,CPUS += SH4
+#@src/emu/cpu/sh4/sh4.h,CPUS += SH4
#-------------------------------------------------
ifneq ($(filter SH4,$(CPUS)),)
diff --git a/src/emu/cpu/dsp16/dsp16.c b/src/emu/cpu/dsp16/dsp16.c
index 411496ec88b..3ceb0e26014 100644
--- a/src/emu/cpu/dsp16/dsp16.c
+++ b/src/emu/cpu/dsp16/dsp16.c
@@ -18,7 +18,7 @@
// * Handle virtual shift addressing using RB & RE (when RE is enabled) (page 2-6)
// * The ALU sign-extends 32-bit operands from y or p to 36 bits and produces a 36-bit output
// * Interrupt lines (page 2-15)
-//
+//
//**************************************************************************
// DEVICE INTERFACE
@@ -176,13 +176,13 @@ void dsp16_device::device_reset()
m_pc = 0x0000;
m_pi = 0x0000;
m_sioc = 0x0000; // (page 5-4)
-
+
// SRTA is unaltered by reset
m_pioc = 0x0008;
m_rb = 0x0000;
m_re = 0x0000;
-
- // AUC is not affected by reset
+
+ // AUC is not affected by reset
m_ppc = m_pc;
// Hacky cache emulation.
@@ -202,8 +202,8 @@ void dsp16_device::device_reset()
const address_space_config *dsp16_device::memory_space_config(address_spacenum spacenum) const
{
return (spacenum == AS_PROGRAM) ? &m_program_config :
- (spacenum == AS_DATA) ? &m_data_config :
- NULL;
+ (spacenum == AS_DATA) ? &m_data_config :
+ NULL;
}
@@ -220,101 +220,101 @@ void dsp16_device::state_string_export(const device_state_entry &entry, astring
string.printf("(below)");
break;
- case DSP16_AUC:
- {
- astring alignString;
- const UINT8 align = m_auc & 0x03;
- switch (align)
- {
- case 0x00: alignString.printf("xy"); break;
- case 0x01: alignString.printf("/4"); break;
- case 0x02: alignString.printf("x4"); break;
- case 0x03: alignString.printf(",,"); break;
- }
- string.printf("%c%c%c%c%c%s",
- m_auc & 0x40 ? 'Y':'.',
- m_auc & 0x20 ? '1':'.',
- m_auc & 0x10 ? '0':'.',
- m_auc & 0x08 ? '1':'.',
- m_auc & 0x04 ? '0':'.',
- alignString.cstr());
- break;
- }
-
- case DSP16_PSW:
- string.printf("%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
- m_psw & 0x8000 ? 'M':'.',
- m_psw & 0x4000 ? 'E':'.',
- m_psw & 0x2000 ? 'L':'.',
- m_psw & 0x1000 ? 'V':'.',
- m_psw & 0x0800 ? ',':',',
- m_psw & 0x0400 ? ',':',',
- m_psw & 0x0200 ? 'O':'.',
- m_psw & 0x0100 ? '1':'.',
- m_psw & 0x0080 ? '1':'.',
- m_psw & 0x0040 ? '1':'.',
- m_psw & 0x0020 ? '1':'.',
- m_psw & 0x0010 ? 'O':'.',
- m_psw & 0x0008 ? '1':'.',
- m_psw & 0x0004 ? '1':'.',
- m_psw & 0x0002 ? '1':'.',
- m_psw & 0x0001 ? '1':'.');
- break;
-
- case DSP16_PIOC:
- {
- astring strobeString;
- const UINT8 strobe = (m_pioc & 0x6000) >> 13;
- switch (strobe)
- {
- case 0x00: strobeString.printf("1T"); break;
- case 0x01: strobeString.printf("2T"); break;
- case 0x02: strobeString.printf("3T"); break;
- case 0x03: strobeString.printf("4T"); break;
- }
- string.printf("%c%s%c%c%c%c%c%c%c%c%c%c%c%c%c",
- m_pioc & 0x8000 ? 'I':'.',
- strobeString.cstr(),
- m_pioc & 0x1000 ? 'O':'I',
- m_pioc & 0x0800 ? 'O':'I',
- m_pioc & 0x0400 ? 'S':'.',
- m_pioc & 0x0200 ? 'I':'.',
- m_pioc & 0x0100 ? 'O':'.',
- m_pioc & 0x0080 ? 'P':'.',
- m_pioc & 0x0040 ? 'P':'.',
- m_pioc & 0x0020 ? 'I':'.',
- m_pioc & 0x0010 ? 'I':'.',
- m_pioc & 0x0008 ? 'O':'.',
- m_pioc & 0x0004 ? 'P':'.',
- m_pioc & 0x0002 ? 'P':'.',
- m_pioc & 0x0001 ? 'I':'.');
- break;
- }
-
+ case DSP16_AUC:
+ {
+ astring alignString;
+ const UINT8 align = m_auc & 0x03;
+ switch (align)
+ {
+ case 0x00: alignString.printf("xy"); break;
+ case 0x01: alignString.printf("/4"); break;
+ case 0x02: alignString.printf("x4"); break;
+ case 0x03: alignString.printf(",,"); break;
+ }
+ string.printf("%c%c%c%c%c%s",
+ m_auc & 0x40 ? 'Y':'.',
+ m_auc & 0x20 ? '1':'.',
+ m_auc & 0x10 ? '0':'.',
+ m_auc & 0x08 ? '1':'.',
+ m_auc & 0x04 ? '0':'.',
+ alignString.cstr());
+ break;
+ }
+
+ case DSP16_PSW:
+ string.printf("%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ m_psw & 0x8000 ? 'M':'.',
+ m_psw & 0x4000 ? 'E':'.',
+ m_psw & 0x2000 ? 'L':'.',
+ m_psw & 0x1000 ? 'V':'.',
+ m_psw & 0x0800 ? ',':',',
+ m_psw & 0x0400 ? ',':',',
+ m_psw & 0x0200 ? 'O':'.',
+ m_psw & 0x0100 ? '1':'.',
+ m_psw & 0x0080 ? '1':'.',
+ m_psw & 0x0040 ? '1':'.',
+ m_psw & 0x0020 ? '1':'.',
+ m_psw & 0x0010 ? 'O':'.',
+ m_psw & 0x0008 ? '1':'.',
+ m_psw & 0x0004 ? '1':'.',
+ m_psw & 0x0002 ? '1':'.',
+ m_psw & 0x0001 ? '1':'.');
+ break;
+
+ case DSP16_PIOC:
+ {
+ astring strobeString;
+ const UINT8 strobe = (m_pioc & 0x6000) >> 13;
+ switch (strobe)
+ {
+ case 0x00: strobeString.printf("1T"); break;
+ case 0x01: strobeString.printf("2T"); break;
+ case 0x02: strobeString.printf("3T"); break;
+ case 0x03: strobeString.printf("4T"); break;
+ }
+ string.printf("%c%s%c%c%c%c%c%c%c%c%c%c%c%c%c",
+ m_pioc & 0x8000 ? 'I':'.',
+ strobeString.cstr(),
+ m_pioc & 0x1000 ? 'O':'I',
+ m_pioc & 0x0800 ? 'O':'I',
+ m_pioc & 0x0400 ? 'S':'.',
+ m_pioc & 0x0200 ? 'I':'.',
+ m_pioc & 0x0100 ? 'O':'.',
+ m_pioc & 0x0080 ? 'P':'.',
+ m_pioc & 0x0040 ? 'P':'.',
+ m_pioc & 0x0020 ? 'I':'.',
+ m_pioc & 0x0010 ? 'I':'.',
+ m_pioc & 0x0008 ? 'O':'.',
+ m_pioc & 0x0004 ? 'P':'.',
+ m_pioc & 0x0002 ? 'P':'.',
+ m_pioc & 0x0001 ? 'I':'.');
+ break;
+ }
+
// Placeholder for a better view later (TODO)
case DSP16_SIOC:
- {
- astring clkString;
- const UINT8 clk = (m_sioc & 0x0180) >> 7;
- switch (clk)
- {
- case 0x00: clkString.printf("/4"); break;
- case 0x01: clkString.printf("12"); break;
- case 0x02: clkString.printf("16"); break;
- case 0x03: clkString.printf("20"); break;
- }
- string.printf("%c%s%c%c%c%c%c%c%c",
- m_sioc & 0x0200 ? 'I':'O',
- clkString.cstr(),
- m_sioc & 0x0040 ? 'L':'M',
- m_sioc & 0x0020 ? 'I':'O',
- m_sioc & 0x0010 ? 'I':'O',
- m_sioc & 0x0008 ? 'I':'O',
- m_sioc & 0x0004 ? 'I':'O',
- m_sioc & 0x0002 ? '2':'1',
- m_sioc & 0x0001 ? '2':'1');
- break;
- }
+ {
+ astring clkString;
+ const UINT8 clk = (m_sioc & 0x0180) >> 7;
+ switch (clk)
+ {
+ case 0x00: clkString.printf("/4"); break;
+ case 0x01: clkString.printf("12"); break;
+ case 0x02: clkString.printf("16"); break;
+ case 0x03: clkString.printf("20"); break;
+ }
+ string.printf("%c%s%c%c%c%c%c%c%c",
+ m_sioc & 0x0200 ? 'I':'O',
+ clkString.cstr(),
+ m_sioc & 0x0040 ? 'L':'M',
+ m_sioc & 0x0020 ? 'I':'O',
+ m_sioc & 0x0010 ? 'I':'O',
+ m_sioc & 0x0008 ? 'I':'O',
+ m_sioc & 0x0004 ? 'I':'O',
+ m_sioc & 0x0002 ? '2':'1',
+ m_sioc & 0x0001 ? '2':'1');
+ break;
+ }
}
}
@@ -441,9 +441,9 @@ void dsp16_device::execute_run()
m_pc += pcAdvance;
m_icount -= cycles;
- // The 16 bit PI "shadow" register gets set to PC on each instruction except
- // when an interrupt service routine is active (TODO: Interrupt check) (page 2-4)
- m_pi = m_pc;
+ // The 16 bit PI "shadow" register gets set to PC on each instruction except
+ // when an interrupt service routine is active (TODO: Interrupt check) (page 2-4)
+ m_pi = m_pc;
} while (m_icount > 0);
}
diff --git a/src/emu/cpu/dsp16/dsp16.h b/src/emu/cpu/dsp16/dsp16.h
index b32f564e9dc..8ab6834bec2 100644
--- a/src/emu/cpu/dsp16/dsp16.h
+++ b/src/emu/cpu/dsp16/dsp16.h
@@ -60,7 +60,7 @@ protected:
UINT16 m_pt;
UINT16 m_pr;
UINT16 m_pi;
-
+
// RAM Address Arithmetic Unit (YAAU) (page 2-6)
UINT16 m_j; // Signed
UINT16 m_k; // Signed
@@ -70,8 +70,8 @@ protected:
UINT16 m_r1;
UINT16 m_r2;
UINT16 m_r3;
-
- // Data Arithmetic Unit (DAU) (page 2-6)
+
+ // Data Arithmetic Unit (DAU) (page 2-6)
UINT16 m_x;
UINT32 m_y;
UINT32 m_p;
@@ -82,8 +82,8 @@ protected:
UINT8 m_c0;
UINT8 m_c1;
UINT8 m_c2;
-
- // Serial and parallel interfaces (TODO: More here (page 2-13))
+
+ // Serial and parallel interfaces (TODO: More here (page 2-13))
UINT16 m_sioc;
UINT16 m_srta;
UINT16 m_sdx;
@@ -133,12 +133,12 @@ protected:
void* addressYL();
void writeRegister(void* reg, const UINT16& value);
bool conditionTest(const UINT8& CON);
-
+
// flags
bool lmi();
bool leq();
- bool llv();
- bool lmv();
+ bool llv();
+ bool lmv();
};
diff --git a/src/emu/cpu/dsp16/dsp16ops.c b/src/emu/cpu/dsp16/dsp16ops.c
index 8386c506d88..ffa7d008168 100644
--- a/src/emu/cpu/dsp16/dsp16ops.c
+++ b/src/emu/cpu/dsp16/dsp16ops.c
@@ -4,19 +4,19 @@
// TODO:
// * AUC has a CLR field for writing to A0 & A1 + sign extension + psw + zero lower bits
-// implement as a clean function (page 2-7)
+// implement as a clean function (page 2-7)
// * Implement saturation overflow (SAT on AUC) (page 2-8)
// * Implement p alignment (ALIGN on AUC) (page 2-9)
-// * When a register is used as a memory pointer. its value is compared with re. If its value is
-// equal to the contents of re and the postincrement is +1, then the value in rb is copied into
+// * When a register is used as a memory pointer. its value is compared with re. If its value is
+// equal to the contents of re and the postincrement is +1, then the value in rb is copied into
// the register after the memory access is complete. See Section 4.2.3.
// * CPU flags go to the PSW & conditionTest() works on that (Page 3-4)
// * Some instructions are not interruptible.
-//
+//
// NOTES:
-// When y is used in an assembly-language instruction, the DSPI6/DSPI6A device will read
+// When y is used in an assembly-language instruction, the DSPI6/DSPI6A device will read
// or write the high half (bits 16-31) of the y register (page 2-7)
// The YL register is the lower half of the 32 bit Y register
@@ -34,17 +34,17 @@ bool dsp16_device::lmi()
bool dsp16_device::leq()
{
- return m_psw & 0x4000;
+ return m_psw & 0x4000;
}
bool dsp16_device::llv()
{
- return m_psw & 0x2000;
+ return m_psw & 0x2000;
}
bool dsp16_device::lmv()
{
- return m_psw & 0x1000;
+ return m_psw & 0x1000;
}
@@ -78,7 +78,7 @@ void dsp16_device::writeRegister(void* reg, const UINT16 &value)
}
else if (reg == &m_y)
{
- // Y register
+ // Y register
// TODO - Automatic clearing of yl may be selected (according to the CLR field of the auc register) (page 2-7)
m_y = (value << 16) | (m_y & 0x0000ffff);
}
@@ -119,9 +119,9 @@ bool dsp16_device::conditionTest(const UINT8& CON)
case 0x11: return (lmi() || leq()); // le (result <= 0)
default: logerror("Unrecognized condition at PC=0x%04x\n", m_pc); break;
}
-
+
// Testing each of these conditions (*) increments the respective counter being tested (page 3-5)
-
+
return false;
}
@@ -187,7 +187,7 @@ void* dsp16_device::registerFromRTable(const UINT8 &R)
void dsp16_device::executeF1Field(const UINT8& F1, const UINT8& D, const UINT8& S)
{
// TODO: I'm pretty sure we need to feed X into these as well - Double check
-
+
// Note these instructions read right-to-left, so act accordingly (page 3-6)
// y & p are sign extended (page 3-9)
// implementation details (page 3-9)
@@ -223,7 +223,7 @@ void dsp16_device::executeF1Field(const UINT8& F1, const UINT8& D, const UINT8&
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x01:
+ case 0x01:
{
// Ad = aS+p p = x*y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
@@ -238,112 +238,112 @@ void dsp16_device::executeF1Field(const UINT8& F1, const UINT8& D, const UINT8&
justATest = true;
break;
}
- case 0x03:
+ case 0x03:
{
// Ad = aS-p p = x*y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x04:
+ case 0x04:
{
// Ad = p
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x05:
+ case 0x05:
{
// Ad = aS+p
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x06:
+ case 0x06:
{
// nop
justATest = true;
break;
}
- case 0x07:
+ case 0x07:
{
// Ad = aS-p
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x08:
+ case 0x08:
{
// Ad = aS|y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x09:
+ case 0x09:
{
// Ad = aS^y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x0a:
+ case 0x0a:
{
// aS&y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
justATest = true;
break;
}
- case 0x0b:
+ case 0x0b:
{
// aS-y
INT64 aS = *sourceReg;
if (aS & U64(0x800000000))
aS |= U64(0xfffffff000000000);
-
+
INT64 y = (m_y & 0xffff0000) >> 16;
if (y & 0x8000)
y |= U64(0xffffffffffff0000);
-
+
result = aS-y;
justATest = true;
break;
}
- case 0x0c:
+ case 0x0c:
{
// Ad = y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x0d:
+ case 0x0d:
{
// Ad = aS+y
INT64 aS = *sourceReg;
- if (aS & U64(0x800000000))
+ if (aS & U64(0x800000000))
aS |= U64(0xfffffff000000000);
-
+
INT64 y = (m_y & 0xffff0000) >> 16;
- if (y & 0x8000)
+ if (y & 0x8000)
y |= U64(0xffffffffffff0000);
-
+
result = aS+y;
break;
}
- case 0x0e:
+ case 0x0e:
{
// Ad = aS&y
printf("UNIMPLEMENTED F1 operation @ PC 0x%04x (%d)\n", m_pc, __LINE__);
break;
}
- case 0x0f:
+ case 0x0f:
{
// Ad = aS-y
INT64 aS = *sourceReg;
if (aS & U64(0x800000000))
aS |= U64(0xfffffff000000000);
-
+
INT64 y = (m_y & 0xffff0000) >> 16;
- if (y & 0x8000)
+ if (y & 0x8000)
y |= U64(0xffffffffffff0000);
-
+
result = aS-y;
break;
}
}
-
+
// CPU Flags (page 3-4)
// LMI (logical minus)
if (result & U64(0x800000000))
@@ -359,7 +359,7 @@ void dsp16_device::executeF1Field(const UINT8& F1, const UINT8& D, const UINT8&
// LLV (logical overflow)
// TODO
-
+
// LMV (mathematical overflow)
if ((result | U64(0xf00000000)) != U64(0xf00000000) &&
(result | U64(0xf00000000)) != U64(0x000000000))
@@ -369,7 +369,7 @@ void dsp16_device::executeF1Field(const UINT8& F1, const UINT8& D, const UINT8&
// If it was a real operation, make sure the data goes where it should
if (!justATest)
- *destinationReg = (UINT64)result & U64(0x0000000fffffffff);
+ *destinationReg = (UINT64)result & U64(0x0000000fffffffff);
}
@@ -570,7 +570,7 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance
case 0x14:
{
DSP_LINE("3-53")
- // F1, Y = y[l] : (page 3-53)
+ // F1, Y = y[l] : (page 3-53)
const UINT8 Y = (op & 0x000f);
const UINT8 X = (op & 0x0010) >> 4;
const UINT8 S = (op & 0x0200) >> 9;
diff --git a/src/emu/cpu/es5510/es5510.c b/src/emu/cpu/es5510/es5510.c
index d101ead70d9..bfe0e4dfef9 100644
--- a/src/emu/cpu/es5510/es5510.c
+++ b/src/emu/cpu/es5510/es5510.c
@@ -559,7 +559,7 @@ void es5510_device::execute_set_input(int linenum, int state) {
void es5510_device::list_program(void(p)(const char *, ...)) {
LOG(("ES5501: Starting!\n"));
-
+
UINT8 addr;
char buf[1024];
for (addr = 0; addr < 0xa0; addr++) {
@@ -802,14 +802,14 @@ void es5510_device::run_once()
{
// turn HALT off
set_HALT(false);
-
- // run for one instruction
+
+ // run for one instruction
icount = 1;
execute_run();
-
- // turn HALT on again
+
+ // turn HALT on again
set_HALT(true);
-
+
// run ESP to the end of its program, a few instructions at a time
while (state != STATE_HALTED) {
icount = 1;
@@ -898,7 +898,7 @@ void es5510_device::write_to_dol(INT32 value) {
}
void es5510_device::alu_operation_end() {
- // Handle the END instruction separately
+ // Handle the END instruction separately
LOG(("ES5510: END\n"));
// sample the HALT line
if (halt_asserted) {
diff --git a/src/emu/cpu/es5510/es5510.h b/src/emu/cpu/es5510/es5510.h
index 8120d204081..20fec32cc11 100644
--- a/src/emu/cpu/es5510/es5510.h
+++ b/src/emu/cpu/es5510/es5510.h
@@ -104,7 +104,7 @@ public:
ram_cycle_t cycle; // cycle type
};
- // direct access to the 'HALT' pin - not just through the
+ // direct access to the 'HALT' pin - not just through the
void set_HALT(bool halt) { halt_asserted = halt; }
bool get_HALT() { return halt_asserted; }
diff --git a/src/emu/cpu/hcd62121/hcd62121.c b/src/emu/cpu/hcd62121/hcd62121.c
index 832c3e37c2a..de8b5ff3b2c 100644
--- a/src/emu/cpu/hcd62121/hcd62121.c
+++ b/src/emu/cpu/hcd62121/hcd62121.c
@@ -287,7 +287,7 @@ int hcd62121_cpu_device::check_cond( UINT8 op )
void hcd62121_cpu_device::device_start()
{
-// m_irq_callback = irqcallback;
+// m_irq_callback = irqcallback;
m_program = &space(AS_PROGRAM);
m_io = &space(AS_IO);
@@ -519,4 +519,3 @@ offs_t hcd62121_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UI
extern CPU_DISASSEMBLE( hcd62121 );
return CPU_DISASSEMBLE_NAME(hcd62121)(this, buffer, pc, oprom, opram, options);
}
-
diff --git a/src/emu/cpu/i386/i386ops.h b/src/emu/cpu/i386/i386ops.h
index 8fdfe9b509d..00a6528cd06 100644
--- a/src/emu/cpu/i386/i386ops.h
+++ b/src/emu/cpu/i386/i386ops.h
@@ -321,26 +321,26 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0x2c, OP_2BYTE|OP_SSE, SSEOP(cvttps2pi_r64_r128m64), SSEOP(cvttps2pi_r64_r128m64),},
{ 0x2d, OP_2BYTE|OP_SSE, SSEOP(cvtps2pi_r64_r128m64), SSEOP(cvtps2pi_r64_r128m64),},
{ 0x2e, OP_2BYTE|OP_SSE, SSEOP(ucomiss_r128_r128m32), SSEOP(ucomiss_r128_r128m32),},
- { 0x2f, OP_2BYTE|OP_SSE, SSEOP(comiss_r128_r128m32), SSEOP(comiss_r128_r128m32), },
+ { 0x2f, OP_2BYTE|OP_SSE, SSEOP(comiss_r128_r128m32), SSEOP(comiss_r128_r128m32), },
{ 0x30, OP_2BYTE|OP_PENTIUM, PENTIUMOP(wrmsr), PENTIUMOP(wrmsr), },
{ 0x31, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdtsc), PENTIUMOP(rdtsc), },
{ 0x32, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdmsr), PENTIUMOP(rdmsr), },
- { 0x40, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovo_r16_rm16), PENTIUMOP(cmovo_r32_rm32), },
- { 0x41, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovno_r16_rm16), PENTIUMOP(cmovno_r32_rm32), },
- { 0x42, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovb_r16_rm16), PENTIUMOP(cmovb_r32_rm32), },
- { 0x43, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovae_r16_rm16), PENTIUMOP(cmovae_r32_rm32), },
- { 0x44, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmove_r16_rm16), PENTIUMOP(cmove_r32_rm32), },
- { 0x45, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovne_r16_rm16), PENTIUMOP(cmovne_r32_rm32), },
- { 0x46, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovbe_r16_rm16), PENTIUMOP(cmovbe_r32_rm32), },
- { 0x47, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmova_r16_rm16), PENTIUMOP(cmova_r32_rm32), },
- { 0x48, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovs_r16_rm16), PENTIUMOP(cmovs_r32_rm32), },
- { 0x49, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovns_r16_rm16), PENTIUMOP(cmovns_r32_rm32), },
- { 0x4a, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovp_r16_rm16), PENTIUMOP(cmovp_r32_rm32), },
- { 0x4b, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovnp_r16_rm16), PENTIUMOP(cmovnp_r32_rm32), },
- { 0x4c, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovl_r16_rm16), PENTIUMOP(cmovl_r32_rm32), },
- { 0x4d, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovge_r16_rm16), PENTIUMOP(cmovge_r32_rm32), },
- { 0x4e, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovle_r16_rm16), PENTIUMOP(cmovle_r32_rm32), },
- { 0x4f, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovg_r16_rm16), PENTIUMOP(cmovg_r32_rm32), },
+ { 0x40, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovo_r16_rm16), PENTIUMOP(cmovo_r32_rm32), },
+ { 0x41, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovno_r16_rm16), PENTIUMOP(cmovno_r32_rm32), },
+ { 0x42, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovb_r16_rm16), PENTIUMOP(cmovb_r32_rm32), },
+ { 0x43, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovae_r16_rm16), PENTIUMOP(cmovae_r32_rm32), },
+ { 0x44, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmove_r16_rm16), PENTIUMOP(cmove_r32_rm32), },
+ { 0x45, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovne_r16_rm16), PENTIUMOP(cmovne_r32_rm32), },
+ { 0x46, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovbe_r16_rm16), PENTIUMOP(cmovbe_r32_rm32), },
+ { 0x47, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmova_r16_rm16), PENTIUMOP(cmova_r32_rm32), },
+ { 0x48, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovs_r16_rm16), PENTIUMOP(cmovs_r32_rm32), },
+ { 0x49, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovns_r16_rm16), PENTIUMOP(cmovns_r32_rm32), },
+ { 0x4a, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovp_r16_rm16), PENTIUMOP(cmovp_r32_rm32), },
+ { 0x4b, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovnp_r16_rm16), PENTIUMOP(cmovnp_r32_rm32), },
+ { 0x4c, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovl_r16_rm16), PENTIUMOP(cmovl_r32_rm32), },
+ { 0x4d, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovge_r16_rm16), PENTIUMOP(cmovge_r32_rm32), },
+ { 0x4e, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovle_r16_rm16), PENTIUMOP(cmovle_r32_rm32), },
+ { 0x4f, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovg_r16_rm16), PENTIUMOP(cmovg_r32_rm32), },
{ 0x50, OP_2BYTE|OP_SSE, SSEOP(movmskps_r16_r128), SSEOP(movmskps_r32_r128), },
{ 0x51, OP_2BYTE|OP_SSE, SSEOP(sqrtps_r128_rm128), SSEOP(sqrtps_r128_rm128), },
{ 0x52, OP_2BYTE|OP_SSE, SSEOP(rsqrtps_r128_rm128), SSEOP(rsqrtps_r128_rm128), },
@@ -363,8 +363,8 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0x63, OP_2BYTE|OP_MMX, MMXOP(packsswb_r64_rm64), MMXOP(packsswb_r64_rm64), },
{ 0x64, OP_2BYTE|OP_MMX, MMXOP(pcmpgtb_r64_rm64), MMXOP(pcmpgtb_r64_rm64), },
{ 0x65, OP_2BYTE|OP_MMX, MMXOP(pcmpgtw_r64_rm64), MMXOP(pcmpgtw_r64_rm64), },
- { 0x66, OP_2BYTE|OP_MMX, MMXOP(pcmpgtd_r64_rm64), MMXOP(pcmpgtd_r64_rm64), },
- { 0x67, OP_2BYTE|OP_MMX, MMXOP(packuswb_r64_rm64), MMXOP(packuswb_r64_rm64), },
+ { 0x66, OP_2BYTE|OP_MMX, MMXOP(pcmpgtd_r64_rm64), MMXOP(pcmpgtd_r64_rm64), },
+ { 0x67, OP_2BYTE|OP_MMX, MMXOP(packuswb_r64_rm64), MMXOP(packuswb_r64_rm64), },
{ 0x68, OP_2BYTE|OP_MMX, MMXOP(punpckhbw_r64_rm64), MMXOP(punpckhbw_r64_rm64), },
{ 0x69, OP_2BYTE|OP_MMX, MMXOP(punpckhwd_r64_rm64), MMXOP(punpckhwd_r64_rm64), },
{ 0x6a, OP_2BYTE|OP_MMX, MMXOP(punpckhdq_r64_rm64), MMXOP(punpckhdq_r64_rm64), },
@@ -444,8 +444,8 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0xBF, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movsx_r32_rm16), },
{ 0xC0, OP_2BYTE|OP_I486, I486OP(xadd_rm8_r8), I486OP(xadd_rm8_r8), },
{ 0xC1, OP_2BYTE|OP_I486, I486OP(xadd_rm16_r16), I486OP(xadd_rm32_r32), },
- { 0xC2, OP_2BYTE|OP_SSE, SSEOP(cmpps_r128_rm128_i8), SSEOP(cmpps_r128_rm128_i8), },
- { 0xC3, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movnti_m16_r16), PENTIUMOP(movnti_m32_r32), },
+ { 0xC2, OP_2BYTE|OP_SSE, SSEOP(cmpps_r128_rm128_i8), SSEOP(cmpps_r128_rm128_i8), },
+ { 0xC3, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movnti_m16_r16), PENTIUMOP(movnti_m32_r32), },
{ 0xC4, OP_2BYTE|OP_SSE, SSEOP(pinsrw_r64_r16m16_i8), SSEOP(pinsrw_r64_r32m16_i8),},
{ 0xC5, OP_2BYTE|OP_SSE, SSEOP(pextrw_r16_r64_i8), SSEOP(pextrw_r32_r64_i8), },
{ 0xC6, OP_2BYTE|OP_SSE, SSEOP(shufps), SSEOP(shufps), },
@@ -502,30 +502,30 @@ static const X86_OPCODE x86_opcode_table[] =
{ 0xFD, OP_2BYTE|OP_MMX, MMXOP(paddw_r64_rm64), MMXOP(paddw_r64_rm64), },
{ 0xFE, OP_2BYTE|OP_MMX, MMXOP(paddd_r64_rm64), MMXOP(paddd_r64_rm64), },
/* F3 0F ?? */
- { 0x10, OP_3BYTEF3|OP_SSE, SSEOP(movss_r128_rm128), SSEOP(movss_r128_rm128), },
- { 0x11, OP_3BYTEF3|OP_SSE, SSEOP(movss_rm128_r128), SSEOP(movss_rm128_r128), },
- { 0x12, OP_3BYTEF3|OP_SSE, SSEOP(movsldup_r128_rm128), SSEOP(movsldup_r128_rm128), },
- { 0x16, OP_3BYTEF3|OP_SSE, SSEOP(movshdup_r128_rm128), SSEOP(movshdup_r128_rm128), },
+ { 0x10, OP_3BYTEF3|OP_SSE, SSEOP(movss_r128_rm128), SSEOP(movss_r128_rm128), },
+ { 0x11, OP_3BYTEF3|OP_SSE, SSEOP(movss_rm128_r128), SSEOP(movss_rm128_r128), },
+ { 0x12, OP_3BYTEF3|OP_SSE, SSEOP(movsldup_r128_rm128), SSEOP(movsldup_r128_rm128), },
+ { 0x16, OP_3BYTEF3|OP_SSE, SSEOP(movshdup_r128_rm128), SSEOP(movshdup_r128_rm128), },
{ 0x2A, OP_3BYTEF3|OP_SSE, SSEOP(cvtsi2ss_r128_rm32), SSEOP(cvtsi2ss_r128_rm32), },
{ 0x2C, OP_3BYTEF3|OP_SSE, SSEOP(cvttss2si_r32_r128m32), SSEOP(cvttss2si_r32_r128m32),},
- { 0x2D, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2si_r32_r128m32), SSEOP(cvtss2si_r32_r128m32),},
- { 0x51, OP_3BYTEF3|OP_SSE, SSEOP(sqrtss_r128_r128m32), SSEOP(sqrtss_r128_r128m32), },
- { 0x52, OP_3BYTEF3|OP_SSE, SSEOP(rsqrtss_r128_r128m32), SSEOP(rsqrtss_r128_r128m32),},
+ { 0x2D, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2si_r32_r128m32), SSEOP(cvtss2si_r32_r128m32),},
+ { 0x51, OP_3BYTEF3|OP_SSE, SSEOP(sqrtss_r128_r128m32), SSEOP(sqrtss_r128_r128m32), },
+ { 0x52, OP_3BYTEF3|OP_SSE, SSEOP(rsqrtss_r128_r128m32), SSEOP(rsqrtss_r128_r128m32),},
{ 0x53, OP_3BYTEF3|OP_SSE, SSEOP(rcpss_r128_r128m32), SSEOP(rcpss_r128_r128m32), },
{ 0x58, OP_3BYTEF3|OP_SSE, SSEOP(addss), SSEOP(addss), },
{ 0x59, OP_3BYTEF3|OP_SSE, SSEOP(mulss), SSEOP(mulss), },
- { 0x5A, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2sd_r128_r128m32), SSEOP(cvtss2sd_r128_r128m32),},
- { 0x5B, OP_3BYTEF3|OP_SSE, SSEOP(cvttps2dq_r128_rm128), SSEOP(cvttps2dq_r128_rm128),},
+ { 0x5A, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2sd_r128_r128m32), SSEOP(cvtss2sd_r128_r128m32),},
+ { 0x5B, OP_3BYTEF3|OP_SSE, SSEOP(cvttps2dq_r128_rm128), SSEOP(cvttps2dq_r128_rm128),},
{ 0x5C, OP_3BYTEF3|OP_SSE, SSEOP(subss), SSEOP(subss), },
{ 0x5D, OP_3BYTEF3|OP_SSE, SSEOP(minss_r128_r128m32), SSEOP(minss_r128_r128m32), },
{ 0x5E, OP_3BYTEF3|OP_SSE, SSEOP(divss), SSEOP(divss), },
- { 0x5F, OP_3BYTEF3|OP_SSE, SSEOP(maxss_r128_r128m32), SSEOP(maxss_r128_r128m32), },
- { 0x6F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_r128_rm128), SSEOP(movdqu_r128_rm128), },
- { 0x70, OP_3BYTEF3|OP_SSE, SSEOP(pshufhw_r128_rm128_i8), SSEOP(pshufhw_r128_rm128_i8),},
- { 0x7E, OP_3BYTEF3|OP_SSE, SSEOP(movq_r128_r128m64), SSEOP(movq_r128_r128m64), },
- { 0x7F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_rm128_r128), SSEOP(movdqu_rm128_r128), },
- { 0xB8, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(popcnt_r16_rm16), PENTIUMOP(popcnt_r32_rm32), },
- { 0xC2, OP_3BYTEF3|OP_SSE, SSEOP(cmpss_r128_r128m32_i8), SSEOP(cmpss_r128_r128m32_i8),},
- { 0xD6, OP_3BYTEF3|OP_SSE, SSEOP(movq2dq_r128_r64), SSEOP(movq2dq_r128_r64), },
- { 0xE6, OP_3BYTEF3|OP_SSE, SSEOP(cvtdq2pd_r128_r128m64), SSEOP(cvtdq2pd_r128_r128m64)}
+ { 0x5F, OP_3BYTEF3|OP_SSE, SSEOP(maxss_r128_r128m32), SSEOP(maxss_r128_r128m32), },
+ { 0x6F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_r128_rm128), SSEOP(movdqu_r128_rm128), },
+ { 0x70, OP_3BYTEF3|OP_SSE, SSEOP(pshufhw_r128_rm128_i8), SSEOP(pshufhw_r128_rm128_i8),},
+ { 0x7E, OP_3BYTEF3|OP_SSE, SSEOP(movq_r128_r128m64), SSEOP(movq_r128_r128m64), },
+ { 0x7F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_rm128_r128), SSEOP(movdqu_rm128_r128), },
+ { 0xB8, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(popcnt_r16_rm16), PENTIUMOP(popcnt_r32_rm32), },
+ { 0xC2, OP_3BYTEF3|OP_SSE, SSEOP(cmpss_r128_r128m32_i8), SSEOP(cmpss_r128_r128m32_i8),},
+ { 0xD6, OP_3BYTEF3|OP_SSE, SSEOP(movq2dq_r128_r64), SSEOP(movq2dq_r128_r64), },
+ { 0xE6, OP_3BYTEF3|OP_SSE, SSEOP(cvtdq2pd_r128_r128m64), SSEOP(cvtdq2pd_r128_r128m64)}
};
diff --git a/src/emu/cpu/i386/pentops.c b/src/emu/cpu/i386/pentops.c
index 9cd2119eff3..146dc4f006e 100644
--- a/src/emu/cpu/i386/pentops.c
+++ b/src/emu/cpu/i386/pentops.c
@@ -1467,17 +1467,17 @@ static void MMXOP(pmaddwd_r64_rm64)(i386_state *cpustate) // Opcode 0f f5
UINT8 modrm = FETCH(cpustate);
if( modrm >= 0xc0 ) {
MMX((modrm >> 3) & 0x7).i[0]=(INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)MMX(modrm & 7).s[0]+
- (INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)MMX(modrm & 7).s[1];
+ (INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)MMX(modrm & 7).s[1];
MMX((modrm >> 3) & 0x7).i[1]=(INT32)MMX((modrm >> 3) & 0x7).s[2]*(INT32)MMX(modrm & 7).s[2]+
- (INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)MMX(modrm & 7).s[3];
+ (INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)MMX(modrm & 7).s[3];
} else {
MMX_REG s;
UINT32 ea = GetEA(cpustate, modrm, 0);
READMMX(cpustate, ea, s);
MMX((modrm >> 3) & 0x7).i[0]=(INT32)MMX((modrm >> 3) & 0x7).s[0]*(INT32)s.s[0]+
- (INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)s.s[1];
+ (INT32)MMX((modrm >> 3) & 0x7).s[1]*(INT32)s.s[1];
MMX((modrm >> 3) & 0x7).i[1]=(INT32)MMX((modrm >> 3) & 0x7).s[2]*(INT32)s.s[2]+
- (INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)s.s[3];
+ (INT32)MMX((modrm >> 3) & 0x7).s[3]*(INT32)s.s[3];
}
CYCLES(cpustate,1); // TODO: correct cycle count
}
@@ -2772,11 +2772,11 @@ static void SSEOP(subps)(i386_state *cpustate) // Opcode 0f 5c
INLINE float sse_min_single(float src1, float src2)
{
/*if ((src1 == 0) && (src2 == 0))
- return src2;
+ return src2;
if (src1 = SNaN)
- return src2;
+ return src2;
if (src2 = SNaN)
- return src2;*/
+ return src2;*/
if (src1 < src2)
return src1;
return src2;
@@ -2825,11 +2825,11 @@ static void SSEOP(divps)(i386_state *cpustate) // Opcode 0f 5e
INLINE float sse_max_single(float src1, float src2)
{
/*if ((src1 == 0) && (src2 == 0))
- return src2;
+ return src2;
if (src1 = SNaN)
- return src2;
+ return src2;
if (src2 = SNaN)
- return src2;*/
+ return src2;*/
if (src1 > src2)
return src1;
return src2;
diff --git a/src/emu/cpu/i4004/i4004.c b/src/emu/cpu/i4004/i4004.c
index 753e4607f70..7d508d4e36e 100644
--- a/src/emu/cpu/i4004/i4004.c
+++ b/src/emu/cpu/i4004/i4004.c
@@ -501,8 +501,8 @@ void i4004_cpu_device::state_export(const device_state_entry &entry)
{
case STATE_GENFLAGS:
m_flags = ((m_A == 0) ? 0x04 : 0x00) |
- (m_C ? 0x02 : 0x00) |
- (m_TEST ? 0x01 : 0x00);
+ (m_C ? 0x02 : 0x00) |
+ (m_TEST ? 0x01 : 0x00);
break;
}
}
@@ -526,4 +526,4 @@ offs_t i4004_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
return CPU_DISASSEMBLE_NAME(i4004)(this, buffer, pc, oprom, opram, options);
}
-// case CPUINFO_IS_OCTAL: info->i = true; break;
+// case CPUINFO_IS_OCTAL: info->i = true; break;
diff --git a/src/emu/cpu/lr35902/lr35902.h b/src/emu/cpu/lr35902/lr35902.h
index e33af3038a5..ab07b658555 100644
--- a/src/emu/cpu/lr35902/lr35902.h
+++ b/src/emu/cpu/lr35902/lr35902.h
@@ -77,7 +77,7 @@ protected:
protected:
address_space_config m_program_config;
-
+
UINT8 m_A;
UINT8 m_F;
UINT8 m_B;
@@ -110,7 +110,7 @@ protected:
UINT8 m_features;
const UINT16 *c_regs;
const struct lr35902_config *m_config;
-
+
/* Flag bit definitions */
static const UINT8 LR35902_FLAG_Z = 0x80;
static const UINT8 LR35902_FLAG_N = 0x40;
diff --git a/src/emu/cpu/m68000/m68000.h b/src/emu/cpu/m68000/m68000.h
index 38f7b315981..2cffb1058a7 100644
--- a/src/emu/cpu/m68000/m68000.h
+++ b/src/emu/cpu/m68000/m68000.h
@@ -182,7 +182,7 @@ public:
UINT32 cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
-// UINT32 dasm_type; /* disassembly type */
+// UINT32 dasm_type; /* disassembly type */
UINT32 dar[16]; /* Data and Address Registers */
UINT32 ppc; /* Previous program counter */
UINT32 pc; /* Program Counter */
@@ -272,8 +272,8 @@ public:
typedef delegate<void (offs_t, UINT16)> m68k_write16_delegate;
typedef delegate<void (offs_t, UINT32)> m68k_write32_delegate;
-// class m68k_memory_interface
-// {
+// class m68k_memory_interface
+// {
public:
void init8(address_space &space);
void init16(address_space &space);
@@ -312,15 +312,15 @@ public:
UINT32 readlong_d32_hmmu(offs_t address);
void writelong_d32_hmmu(offs_t address, UINT32 data);
-// m68000_base_device *m_cpustate;
-// };
+// m68000_base_device *m_cpustate;
+// };
public:
-// m68k_memory_interface memory;
+// m68k_memory_interface memory;
address_space *m_space;
direct_read_data *m_direct;
-
+
offs_t encrypted_start;
offs_t encrypted_end;
@@ -390,7 +390,7 @@ public:
void reset_cpu(void);
inline void cpu_execute(void);
-
+
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry);
virtual void state_export(const device_state_entry &entry);
@@ -720,7 +720,7 @@ class fscpu32_device : public m68000_base_device
public:
// construction/destruction
fscpu32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
fscpu32_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source);
diff --git a/src/emu/cpu/m68000/m68kcpu.c b/src/emu/cpu/m68000/m68kcpu.c
index 24f74cce3a4..94526192d7d 100644
--- a/src/emu/cpu/m68000/m68kcpu.c
+++ b/src/emu/cpu/m68000/m68kcpu.c
@@ -774,7 +774,7 @@ inline void m68000_base_device::cpu_execute(void)
m_address_error = 0;
try {
m68ki_exception_address_error(this);
- }
+ }
catch(int error)
{
if (error==10)
@@ -1199,7 +1199,7 @@ void m68000_base_device::init8(address_space &space)
{
m_space = &space;
m_direct = &space.direct();
-// m_cpustate = this;
+// m_cpustate = this;
opcode_xor = 0;
readimm16 = m68k_readimm16_delegate(FUNC(m68000_base_device::m68008_read_immediate_16), this);
@@ -1698,8 +1698,8 @@ void m68000_base_device::init_cpu_m68000(void)
init_cpu_common();
cpu_type = CPU_TYPE_000;
-// dasm_type = M68K_CPU_TYPE_68000;
-
+// dasm_type = M68K_CPU_TYPE_68000;
+
init16(*program);
sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[0];
@@ -1725,12 +1725,11 @@ void m68000_base_device::init_cpu_m68000(void)
void m68000_base_device::init_cpu_m68008(void)
{
-
init_cpu_common();
cpu_type = CPU_TYPE_008;
-// dasm_type = M68K_CPU_TYPE_68008;
-
+// dasm_type = M68K_CPU_TYPE_68008;
+
init8(*program);
sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[0];
@@ -1755,11 +1754,10 @@ void m68000_base_device::init_cpu_m68008(void)
void m68000_base_device::init_cpu_m68010(void)
{
-
init_cpu_common();
cpu_type = CPU_TYPE_010;
-// dasm_type = M68K_CPU_TYPE_68010;
-
+// dasm_type = M68K_CPU_TYPE_68010;
+
init16(*program);
sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[1];
@@ -1785,8 +1783,8 @@ void m68000_base_device::init_cpu_m68020(void)
{
init_cpu_common();
cpu_type = CPU_TYPE_020;
-// dasm_type = M68K_CPU_TYPE_68020;
-
+// dasm_type = M68K_CPU_TYPE_68020;
+
init32(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[2];
@@ -1813,7 +1811,7 @@ void m68000_base_device::init_cpu_m68020pmmu(void)
has_pmmu = 1;
has_fpu = 1;
-
+
init32mmu(*program);
}
@@ -1826,7 +1824,7 @@ void m68000_base_device::init_cpu_m68020hmmu(void)
has_hmmu = 1;
has_fpu = 1;
-
+
init32hmmu(*program);
}
@@ -1835,9 +1833,9 @@ void m68000_base_device::init_cpu_m68ec020(void)
init_cpu_common();
cpu_type = CPU_TYPE_EC020;
-// dasm_type = M68K_CPU_TYPE_68EC020;
+// dasm_type = M68K_CPU_TYPE_68EC020;
+
-
init32(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[2];
@@ -1864,9 +1862,9 @@ void m68000_base_device::init_cpu_m68030(void)
init_cpu_common();
cpu_type = CPU_TYPE_030;
-// dasm_type = M68K_CPU_TYPE_68030;
+// dasm_type = M68K_CPU_TYPE_68030;
+
-
init32mmu(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[3];
@@ -1892,11 +1890,11 @@ void m68000_base_device::init_cpu_m68030(void)
void m68000_base_device::init_cpu_m68ec030(void)
{
init_cpu_common();
-
+
cpu_type = CPU_TYPE_EC030;
-// dasm_type = M68K_CPU_TYPE_68EC030;
+// dasm_type = M68K_CPU_TYPE_68EC030;
+
-
init32(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[3];
@@ -1924,9 +1922,9 @@ void m68000_base_device::init_cpu_m68040(void)
init_cpu_common();
cpu_type = CPU_TYPE_040;
-// dasm_type = M68K_CPU_TYPE_68040;
+// dasm_type = M68K_CPU_TYPE_68040;
+
-
init32mmu(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[4];
@@ -1953,9 +1951,9 @@ void m68000_base_device::init_cpu_m68ec040(void)
init_cpu_common();
cpu_type = CPU_TYPE_EC040;
-// dasm_type = M68K_CPU_TYPE_68EC040;
+// dasm_type = M68K_CPU_TYPE_68EC040;
+
-
init32(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[4];
@@ -1982,9 +1980,9 @@ void m68000_base_device::init_cpu_m68lc040(void)
init_cpu_common();
cpu_type = CPU_TYPE_LC040;
-// dasm_type = M68K_CPU_TYPE_68LC040;
+// dasm_type = M68K_CPU_TYPE_68LC040;
+
-
init32mmu(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[4];
@@ -2018,9 +2016,9 @@ void m68000_base_device::init_cpu_fscpu32(void)
init_cpu_common();
cpu_type = CPU_TYPE_FSCPU32;
-// dasm_type = M68K_CPU_TYPE_FSCPU32;
+// dasm_type = M68K_CPU_TYPE_FSCPU32;
+
-
init32(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[5];
@@ -2044,11 +2042,11 @@ void m68000_base_device::init_cpu_fscpu32(void)
void m68000_base_device::init_cpu_coldfire(void)
{
init_cpu_common();
-
+
cpu_type = CPU_TYPE_COLDFIRE;
-// dasm_type = M68K_CPU_TYPE_COLDFIRE;
+// dasm_type = M68K_CPU_TYPE_COLDFIRE;
+
-
init32(*program);
sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
jump_table = m68ki_instruction_jump_table[6];
@@ -2073,25 +2071,25 @@ void m68000_base_device::init_cpu_coldfire(void)
/*
- case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
- case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
+ case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
+ case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
- case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
- case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
+ case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break;
+ case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
- case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; // there is no level 0
- case CPUINFO_INT_INPUT_STATE + 1: info->i = (m68k->virq_state >> 1) & 1; break;
- case CPUINFO_INT_INPUT_STATE + 2: info->i = (m68k->virq_state >> 2) & 1; break;
- case CPUINFO_INT_INPUT_STATE + 3: info->i = (m68k->virq_state >> 3) & 1; break;
- case CPUINFO_INT_INPUT_STATE + 4: info->i = (m68k->virq_state >> 4) & 1; break;
- case CPUINFO_INT_INPUT_STATE + 5: info->i = (m68k->virq_state >> 5) & 1; break;
- case CPUINFO_INT_INPUT_STATE + 6: info->i = (m68k->virq_state >> 6) & 1; break;
- case CPUINFO_INT_INPUT_STATE + 7: info->i = (m68k->virq_state >> 7) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 0: info->i = 0; // there is no level 0
+ case CPUINFO_INT_INPUT_STATE + 1: info->i = (m68k->virq_state >> 1) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 2: info->i = (m68k->virq_state >> 2) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 3: info->i = (m68k->virq_state >> 3) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 4: info->i = (m68k->virq_state >> 4) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 5: info->i = (m68k->virq_state >> 5) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 6: info->i = (m68k->virq_state >> 6) & 1; break;
+ case CPUINFO_INT_INPUT_STATE + 7: info->i = (m68k->virq_state >> 7) & 1; break;
- case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
- case CPUINFO_STR_VERSION: strcpy(info->s, "4.95"); break;
- case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
- case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO+OG)"); break;
+ case CPUINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
+ case CPUINFO_STR_VERSION: strcpy(info->s, "4.95"); break;
+ case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
+ case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO+OG)"); break;
*/
@@ -2196,7 +2194,7 @@ void m68000_base_device::m68ki_exception_interrupt(m68000_base_device *m68k, UIN
/* Acknowledge the interrupt */
vector = (*int_ack_callback)(this, int_level);
-
+
/* Get the interrupt vector */
if(vector == M68K_INT_ACK_AUTOVECTOR)
/* Use the autovectors. This is the most commonly used implementation */
@@ -2273,7 +2271,7 @@ m68000_base_device::m68000_base_device(const machine_config &mconfig, const char
void m68000_base_device::clear_all()
{
cpu_type= 0;
-// dasm_type= 0;
+// dasm_type= 0;
for (int i=0;i<16;i++)
dar[i]= 0;
ppc= 0;
@@ -2286,8 +2284,8 @@ void m68000_base_device::clear_all()
cacr= 0;
caar= 0;
ir= 0;
-// for (int i=0;i<8;i++)
-// fpr[i]= 0;
+// for (int i=0;i<8;i++)
+// fpr[i]= 0;
fpiar= 0;
fpsr= 0;
fpcr= 0;
@@ -2352,13 +2350,13 @@ void m68000_base_device::clear_all()
program = 0;
opcode_xor = 0;
-// readimm16 = 0;
-// read8 = 0;
-// read16 = 0;
-// read32 = 0;
-// write8 = 0;
-// write16 = 0;
-// write32 = 0;
+// readimm16 = 0;
+// read8 = 0;
+// read16 = 0;
+// read32 = 0;
+// write8 = 0;
+// write16 = 0;
+// write32 = 0;
m_space = 0;
m_direct = 0;
@@ -2383,7 +2381,7 @@ void m68000_base_device::clear_all()
for (int i=0; i<MMU_ATC_ENTRIES;i++)
mmu_atc_tag[i] = mmu_atc_data[i] = 0;
-
+
mmu_atc_rr = 0;
mmu_tt0 = mmu_tt1 = 0;
mmu_itt0 = mmu_itt1 = mmu_dtt0 = mmu_dtt1 = 0;
@@ -2398,7 +2396,7 @@ void m68000_base_device::clear_all()
for (int i=0;i<M68K_IC_SIZE;i++)
ic_address[i] = 0;
-
+
for (int i=0;i<M68K_IC_SIZE;i++)
ic_data[i] = 0;
@@ -2415,7 +2413,6 @@ void m68000_base_device::execute_run()
void m68000_base_device::device_start()
{
-
}
void m68000_base_device::device_reset()
@@ -2425,7 +2422,6 @@ void m68000_base_device::device_reset()
void m68000_base_device::device_stop()
{
-
}
@@ -2491,7 +2487,6 @@ const device_type MCF5206E = &device_creator<mcf5206e_device>;
m68000_device::m68000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68000", tag, owner, clock, M68000, 16,24, "m68000", __FILE__)
{
-
}
void m68000_device::device_start()
@@ -2503,7 +2498,6 @@ m68000_device::m68000_device(const machine_config &mconfig, const char *name, co
const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source)
: m68000_base_device(mconfig, name, tag, owner, clock, type, prg_data_width, prg_address_bits, internal_map, shortname, source)
{
-
}
@@ -2513,7 +2507,6 @@ m68000_device::m68000_device(const machine_config &mconfig, const char *name, co
m68301_device::m68301_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68301", tag, owner, clock, M68301, 16,24, "m68301", __FILE__)
{
-
}
@@ -2532,7 +2525,6 @@ void m68301_device::device_start()
m68008_device::m68008_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68008", tag, owner, clock, M68008, 8,20, "m68008", __FILE__)
{
-
}
void m68008_device::device_start()
@@ -2544,7 +2536,6 @@ void m68008_device::device_start()
m68008plcc_device::m68008plcc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68008PLCC", tag, owner, clock, M68008, 8,22, "m68008plcc", __FILE__)
{
-
}
void m68008plcc_device::device_start()
@@ -2557,7 +2548,6 @@ void m68008plcc_device::device_start()
m68010_device::m68010_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68010", tag, owner, clock, M68010, 16,24, "m68010", __FILE__)
{
-
}
void m68010_device::device_start()
@@ -2570,7 +2560,6 @@ void m68010_device::device_start()
m68020_device::m68020_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68020", tag, owner, clock, M68020, 32,32, "m68020", __FILE__)
{
-
}
void m68020_device::device_start()
@@ -2582,7 +2571,6 @@ void m68020_device::device_start()
m68020pmmu_device::m68020pmmu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68020PMMU", tag, owner, clock, M68020PMMU, 32,32, "m68020pmmu", __FILE__)
{
-
}
void m68020pmmu_device::device_start()
@@ -2605,11 +2593,10 @@ bool m68020hmmu_device::memory_translate(address_spacenum space, int intention,
// 68020 with Apple HMMU & 68881 FPU
-// case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(m68khmmu); break;
+// case CPUINFO_FCT_TRANSLATE: info->translate = CPU_TRANSLATE_NAME(m68khmmu); break;
m68020hmmu_device::m68020hmmu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68020HMMU", tag, owner, clock, M68020HMMU, 32,32, "m68020hmmu", __FILE__)
{
-
}
void m68020hmmu_device::device_start()
@@ -2621,7 +2608,6 @@ void m68020hmmu_device::device_start()
m68ec020_device::m68ec020_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68EC020", tag, owner, clock, M68EC020, 32,24, "m68ec020", __FILE__)
{
-
}
void m68ec020_device::device_start()
@@ -2632,7 +2618,6 @@ void m68ec020_device::device_start()
m68030_device::m68030_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68030", tag, owner, clock, M68030, 32,32, "m68030", __FILE__)
{
-
}
void m68030_device::device_start()
@@ -2643,7 +2628,6 @@ void m68030_device::device_start()
m68ec030_device::m68ec030_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68EC030", tag, owner, clock, M68EC030, 32,32, "m68ec030", __FILE__)
{
-
}
void m68ec030_device::device_start()
@@ -2654,7 +2638,6 @@ void m68ec030_device::device_start()
m68040_device::m68040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68040", tag, owner, clock, M68040, 32,32, "m68040", __FILE__)
{
-
}
@@ -2668,7 +2651,6 @@ void m68040_device::device_start()
m68ec040_device::m68ec040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68EC040", tag, owner, clock, M68EC040, 32,32, "m68ec040", __FILE__)
{
-
}
void m68ec040_device::device_start()
@@ -2681,7 +2663,6 @@ void m68ec040_device::device_start()
m68lc040_device::m68lc040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "M68LC040", tag, owner, clock, M68LC040, 32,32, "m68lc040", __FILE__)
{
-
}
void m68lc040_device::device_start()
@@ -2693,7 +2674,6 @@ void m68lc040_device::device_start()
scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "SCC68070", tag, owner, clock, SCC68070, 16,32, "scc68070", __FILE__)
{
-
}
void scc68070_device::device_start()
@@ -2705,14 +2685,12 @@ void scc68070_device::device_start()
fscpu32_device::fscpu32_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "Freescale CPU32 Core", tag, owner, clock, FSCPU32, 32,32, "fscpu32", __FILE__)
{
-
}
fscpu32_device::fscpu32_device(const machine_config &mconfig, const char *name, const char *tag, device_t *owner, UINT32 clock,
const device_type type, UINT32 prg_data_width, UINT32 prg_address_bits, address_map_constructor internal_map, const char *shortname, const char *source)
: m68000_base_device(mconfig, name, tag, owner, clock, type, prg_data_width, prg_address_bits, internal_map, shortname, source)
{
-
}
@@ -2726,10 +2704,9 @@ void fscpu32_device::device_start()
mcf5206e_device::mcf5206e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: m68000_base_device(mconfig, "MCF5206E", tag, owner, clock, MCF5206E, 32,32, "mcf5206e", __FILE__)
{
-
}
void mcf5206e_device::device_start()
{
init_cpu_coldfire();
-} \ No newline at end of file
+}
diff --git a/src/emu/cpu/mcs48/mcs48.h b/src/emu/cpu/mcs48/mcs48.h
index 52a32815bda..590eb7f9152 100644
--- a/src/emu/cpu/mcs48/mcs48.h
+++ b/src/emu/cpu/mcs48/mcs48.h
@@ -88,7 +88,7 @@ enum
***************************************************************************/
#define MCS48_LC_CLOCK(_L, _C) \
- (1 / (2 * 3.14159265358979323846 * sqrt(_L * _C)))
+ (1 / (2 * 3.14159265358979323846 * sqrt(_L * _C)))
#define MCS48_ALE_CLOCK(_clock) \
attotime::from_hz(_clock/(3*5))
diff --git a/src/emu/cpu/rsp/rspdrc.c b/src/emu/cpu/rsp/rspdrc.c
index 0d75a8fdda8..1c9a8c5e188 100644
--- a/src/emu/cpu/rsp/rspdrc.c
+++ b/src/emu/cpu/rsp/rspdrc.c
@@ -238,9 +238,9 @@ static void log_add_disasm_comment(rsp_state *rsp, drcuml_block *block, UINT32 p
}
-#define VREG_B(reg, offset) rsp->v[(reg)].b[(offset)^1]
-#define W_VREG_S(reg, offset) rsp->v[(reg)].s[(offset)]
-#define VREG_S(reg, offset) (INT16)rsp->v[(reg)].s[(offset)]
+#define VREG_B(reg, offset) rsp->v[(reg)].b[(offset)^1]
+#define W_VREG_S(reg, offset) rsp->v[(reg)].s[(offset)]
+#define VREG_S(reg, offset) (INT16)rsp->v[(reg)].s[(offset)]
#define VEC_EL_2(x,z) (vector_elements_2[(x)][(z)])
@@ -1192,7 +1192,7 @@ static void cfunc_rsp_lwv(void *param)
#if USE_SIMD
rsp->xv[dest] = _mm_set_epi8(val[15], val[14], val[13], val[12], val[11], val[10], val[ 9], val[ 8],
- val[ 7], val[ 6], val[ 5], val[ 4], val[ 3], val[ 2], val[ 1], val[ 0]);
+ val[ 7], val[ 6], val[ 5], val[ 4], val[ 3], val[ 2], val[ 1], val[ 0]);
#endif
}
@@ -2850,67 +2850,67 @@ INLINE void cfunc_rsp_vmadh(void *param)
vres[i] = C_SATURATE_ACCUM1(caccumh, caccumm, i, 0x8000, 0x7fff);*/
}
-/* printf("%08x\n", rsp->pc);
- for (int i = 0; i < 8; i++)
- {
- if ((UINT16)vres[i] != vresult[i])
- {
- printf("Result mismatch:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vres[0], vres[1], vres[2], vres[3], vres[4], vres[5], vres[6], vres[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", vresult[0], vresult[1], vresult[2], vresult[3], vresult[4], vresult[5], vresult[6], vresult[7]);
- printf("High accumulator:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumh[0], caccumh[1], caccumh[2], caccumh[3], caccumh[4], caccumh[5], caccumh[6], caccumh[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
- printf("Mid accumulator:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumm[0], caccumm[1], caccumm[2], caccumm[3], caccumm[4], caccumm[5], caccumm[6], caccumm[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
- printf("VS1:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs1[0], vs1[1], vs1[2], vs1[3], vs1[4], vs1[5], vs1[6], vs1[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs1[0], svs1[1], svs1[2], svs1[3], svs1[4], svs1[5], svs1[6], svs1[7]);
- printf("VS2:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs2[0], vs2[1], vs2[2], vs2[3], vs2[4], vs2[5], vs2[6], vs2[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs2[0], svs2[1], svs2[2], svs2[3], svs2[4], svs2[5], svs2[6], svs2[7]);
- fatalerror("asdf");
- }
- if (caccumh[i] != (UINT16)ACCUM_H(i))
- {
- printf("Result:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vres[0], vres[1], vres[2], vres[3], vres[4], vres[5], vres[6], vres[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", vresult[0], vresult[1], vresult[2], vresult[3], vresult[4], vresult[5], vresult[6], vresult[7]);
- printf("High accumulator mismatch:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumh[0], caccumh[1], caccumh[2], caccumh[3], caccumh[4], caccumh[5], caccumh[6], caccumh[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
- printf("Mid accumulator:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumm[0], caccumm[1], caccumm[2], caccumm[3], caccumm[4], caccumm[5], caccumm[6], caccumm[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
- printf("VS1:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs1[0], vs1[1], vs1[2], vs1[3], vs1[4], vs1[5], vs1[6], vs1[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs1[0], svs1[1], svs1[2], svs1[3], svs1[4], svs1[5], svs1[6], svs1[7]);
- printf("VS2:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs2[0], vs2[1], vs2[2], vs2[3], vs2[4], vs2[5], vs2[6], vs2[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs2[0], svs2[1], svs2[2], svs2[3], svs2[4], svs2[5], svs2[6], svs2[7]);
- fatalerror("asdf");
- }
- if (caccumm[i] != (UINT16)ACCUM_M(i))
- {
- printf("Result:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vres[0], vres[1], vres[2], vres[3], vres[4], vres[5], vres[6], vres[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", vresult[0], vresult[1], vresult[2], vresult[3], vresult[4], vresult[5], vresult[6], vresult[7]);
- printf("High accumulator:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumh[0], caccumh[1], caccumh[2], caccumh[3], caccumh[4], caccumh[5], caccumh[6], caccumh[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
- printf("Mid accumulator mismatch:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumm[0], caccumm[1], caccumm[2], caccumm[3], caccumm[4], caccumm[5], caccumm[6], caccumm[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
- printf("VS1:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs1[0], vs1[1], vs1[2], vs1[3], vs1[4], vs1[5], vs1[6], vs1[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs1[0], svs1[1], svs1[2], svs1[3], svs1[4], svs1[5], svs1[6], svs1[7]);
- printf("VS2:\n");
- printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs2[0], vs2[1], vs2[2], vs2[3], vs2[4], vs2[5], vs2[6], vs2[7]);
- printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs2[0], svs2[1], svs2[2], svs2[3], svs2[4], svs2[5], svs2[6], svs2[7]);
- fatalerror("asdf");
- }
- }*/
+/* printf("%08x\n", rsp->pc);
+ for (int i = 0; i < 8; i++)
+ {
+ if ((UINT16)vres[i] != vresult[i])
+ {
+ printf("Result mismatch:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vres[0], vres[1], vres[2], vres[3], vres[4], vres[5], vres[6], vres[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", vresult[0], vresult[1], vresult[2], vresult[3], vresult[4], vresult[5], vresult[6], vresult[7]);
+ printf("High accumulator:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumh[0], caccumh[1], caccumh[2], caccumh[3], caccumh[4], caccumh[5], caccumh[6], caccumh[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
+ printf("Mid accumulator:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumm[0], caccumm[1], caccumm[2], caccumm[3], caccumm[4], caccumm[5], caccumm[6], caccumm[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
+ printf("VS1:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs1[0], vs1[1], vs1[2], vs1[3], vs1[4], vs1[5], vs1[6], vs1[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs1[0], svs1[1], svs1[2], svs1[3], svs1[4], svs1[5], svs1[6], svs1[7]);
+ printf("VS2:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs2[0], vs2[1], vs2[2], vs2[3], vs2[4], vs2[5], vs2[6], vs2[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs2[0], svs2[1], svs2[2], svs2[3], svs2[4], svs2[5], svs2[6], svs2[7]);
+ fatalerror("asdf");
+ }
+ if (caccumh[i] != (UINT16)ACCUM_H(i))
+ {
+ printf("Result:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vres[0], vres[1], vres[2], vres[3], vres[4], vres[5], vres[6], vres[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", vresult[0], vresult[1], vresult[2], vresult[3], vresult[4], vresult[5], vresult[6], vresult[7]);
+ printf("High accumulator mismatch:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumh[0], caccumh[1], caccumh[2], caccumh[3], caccumh[4], caccumh[5], caccumh[6], caccumh[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
+ printf("Mid accumulator:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumm[0], caccumm[1], caccumm[2], caccumm[3], caccumm[4], caccumm[5], caccumm[6], caccumm[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
+ printf("VS1:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs1[0], vs1[1], vs1[2], vs1[3], vs1[4], vs1[5], vs1[6], vs1[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs1[0], svs1[1], svs1[2], svs1[3], svs1[4], svs1[5], svs1[6], svs1[7]);
+ printf("VS2:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs2[0], vs2[1], vs2[2], vs2[3], vs2[4], vs2[5], vs2[6], vs2[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs2[0], svs2[1], svs2[2], svs2[3], svs2[4], svs2[5], svs2[6], svs2[7]);
+ fatalerror("asdf");
+ }
+ if (caccumm[i] != (UINT16)ACCUM_M(i))
+ {
+ printf("Result:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vres[0], vres[1], vres[2], vres[3], vres[4], vres[5], vres[6], vres[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", vresult[0], vresult[1], vresult[2], vresult[3], vresult[4], vresult[5], vresult[6], vresult[7]);
+ printf("High accumulator:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumh[0], caccumh[1], caccumh[2], caccumh[3], caccumh[4], caccumh[5], caccumh[6], caccumh[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_H(0), ACCUM_H(1), ACCUM_H(2), ACCUM_H(3), ACCUM_H(4), ACCUM_H(5), ACCUM_H(6), ACCUM_H(7));
+ printf("Mid accumulator mismatch:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", caccumm[0], caccumm[1], caccumm[2], caccumm[3], caccumm[4], caccumm[5], caccumm[6], caccumm[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", ACCUM_M(0), ACCUM_M(1), ACCUM_M(2), ACCUM_M(3), ACCUM_M(4), ACCUM_M(5), ACCUM_M(6), ACCUM_M(7));
+ printf("VS1:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs1[0], vs1[1], vs1[2], vs1[3], vs1[4], vs1[5], vs1[6], vs1[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs1[0], svs1[1], svs1[2], svs1[3], svs1[4], svs1[5], svs1[6], svs1[7]);
+ printf("VS2:\n");
+ printf(" C: %04x %04x %04x %04x %04x %04x %04x %04x\n", vs2[0], vs2[1], vs2[2], vs2[3], vs2[4], vs2[5], vs2[6], vs2[7]);
+ printf("SIMD: %04x %04x %04x %04x %04x %04x %04x %04x\n", svs2[0], svs2[1], svs2[2], svs2[3], svs2[4], svs2[5], svs2[6], svs2[7]);
+ fatalerror("asdf");
+ }
+ }*/
WRITEBACK_RESULT();
#endif
}
@@ -2930,7 +2930,7 @@ INLINE void cfunc_rsp_vadd(void *param)
__m128i shuffled = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
__m128i unsat = rsp->xv[VS1REG];
__m128i carry = _mm_set_epi16(CARRY_FLAG(7), CARRY_FLAG(6), CARRY_FLAG(5), CARRY_FLAG(4),
- CARRY_FLAG(3), CARRY_FLAG(2), CARRY_FLAG(1), CARRY_FLAG(0));
+ CARRY_FLAG(3), CARRY_FLAG(2), CARRY_FLAG(1), CARRY_FLAG(0));
unsat = _mm_add_epi16(unsat, shuffled);
unsat = _mm_add_epi16(unsat, carry);
@@ -3011,7 +3011,7 @@ INLINE void cfunc_rsp_vsub(void *param)
__m128i shuffled = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
__m128i unsat = rsp->xv[VS1REG];
__m128i carry = _mm_set_epi16(CARRY_FLAG(7), CARRY_FLAG(6), CARRY_FLAG(5), CARRY_FLAG(4),
- CARRY_FLAG(3), CARRY_FLAG(2), CARRY_FLAG(1), CARRY_FLAG(0));
+ CARRY_FLAG(3), CARRY_FLAG(2), CARRY_FLAG(1), CARRY_FLAG(0));
unsat = _mm_sub_epi16(unsat, shuffled);
unsat = _mm_sub_epi16(unsat, carry);
@@ -3142,7 +3142,7 @@ INLINE void cfunc_rsp_vaddc(void *param)
#if USE_SIMD
__m128i shuf2 = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
- __m128i vec7531 = _mm_and_si128(rsp->xv[VS1REG], vec_lomask);
+ __m128i vec7531 = _mm_and_si128(rsp->xv[VS1REG], vec_lomask);
__m128i vec6420 = _mm_srli_epi32(rsp->xv[VS1REG], 16);
__m128i shuf7531 = _mm_and_si128(shuf2, vec_lomask);
__m128i shuf6420 = _mm_srli_epi32(shuf2, 16);
diff --git a/src/emu/cpu/tms0980/tms0980.c b/src/emu/cpu/tms0980/tms0980.c
index 82a2684a1e0..bf95bccca8d 100644
--- a/src/emu/cpu/tms0980/tms0980.c
+++ b/src/emu/cpu/tms0980/tms0980.c
@@ -1042,7 +1042,7 @@ void tms1100_cpu_device::state_string_export(const device_state_entry &entry, as
tms0980_cpu_device::tms0980_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: tms1xxx_cpu_device( mconfig, TMS0980, "TMS0980", tag, owner, clock, tms0980_decode, 0x00ff, 0x07ff, 7, 9, 4
- , 12, ADDRESS_MAP_NAME( tms0980_internal_rom ), 7, ADDRESS_MAP_NAME( tms0980_internal_ram ), "tms0980", __FILE__)
+ , 12, ADDRESS_MAP_NAME( tms0980_internal_rom ), 7, ADDRESS_MAP_NAME( tms0980_internal_ram ), "tms0980", __FILE__)
{
}
@@ -1056,14 +1056,14 @@ offs_t tms0980_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UIN
tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: tms1xxx_cpu_device( mconfig, TMS1000, "TMS1000", tag, owner, clock, tms1000_default_decode, 0x00ff, 0x07ff, 6, 8, 2
- , 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_7bit ), "tms1000", __FILE__)
+ , 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_7bit ), "tms1000", __FILE__)
{
}
tms1000_cpu_device::tms1000_cpu_device(const machine_config &mconfig, device_type type, const char*name, const char *tag, device_t *owner, UINT32 clock, UINT16 o_mask, UINT16 r_mask, const char *shortname, const char *source)
: tms1xxx_cpu_device( mconfig, type, name, tag, owner, clock, tms1000_default_decode, o_mask, r_mask, 6, 8, 2
- , 10, ADDRESS_MAP_NAME( program_10bit_8 ), 6, ADDRESS_MAP_NAME( data_6bit ), shortname, source )
+ , 10, ADDRESS_MAP_NAME( program_10bit_8 ), 6, ADDRESS_MAP_NAME( data_6bit ), shortname, source )
{
}
@@ -1095,14 +1095,14 @@ tms1270_cpu_device::tms1270_cpu_device(const machine_config &mconfig, const char
tms1100_cpu_device::tms1100_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: tms1xxx_cpu_device( mconfig, TMS1100, "TMS1100", tag, owner, clock, tms1100_default_decode, 0x00ff, 0x07ff, 6, 8, 3
- , 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_7bit ), "tms1100", __FILE__ )
+ , 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_7bit ), "tms1100", __FILE__ )
{
}
tms1100_cpu_device::tms1100_cpu_device(const machine_config &mconfig, device_type type, const char*name, const char *tag, device_t *owner, UINT32 clock, UINT16 o_mask, UINT16 r_mask, const char *shortname, const char *source)
: tms1xxx_cpu_device( mconfig, type, name, tag, owner, clock, tms1100_default_decode, o_mask, r_mask, 6, 8, 3
- , 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_7bit ), shortname, source )
+ , 11, ADDRESS_MAP_NAME( program_11bit_8 ), 7, ADDRESS_MAP_NAME( data_7bit ), shortname, source )
{
}
@@ -1118,4 +1118,3 @@ tms1300_cpu_device::tms1300_cpu_device(const machine_config &mconfig, const char
: tms1100_cpu_device( mconfig, TMS1300, "TMS1300", tag, owner, clock, 0x00ff, 0xffff, "tms1300", __FILE__ )
{
}
-
diff --git a/src/emu/cpu/tms0980/tms0980.h b/src/emu/cpu/tms0980/tms0980.h
index 3a76d7e16c2..c600d81b44f 100644
--- a/src/emu/cpu/tms0980/tms0980.h
+++ b/src/emu/cpu/tms0980/tms0980.h
@@ -27,8 +27,8 @@ class tms1xxx_cpu_device : public cpu_device
public:
// construction/destruction
tms1xxx_cpu_device( const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock
- , const UINT32* decode_table, UINT16 o_mask, UINT16 r_mask, UINT8 pc_size, UINT8 byte_size, UINT8 x_bits
- , int program_addrbus_width, address_map_constructor program, int data_addrbus_width, address_map_constructor data, const char *shortname, const char *source)
+ , const UINT32* decode_table, UINT16 o_mask, UINT16 r_mask, UINT8 pc_size, UINT8 byte_size, UINT8 x_bits
+ , int program_addrbus_width, address_map_constructor program, int data_addrbus_width, address_map_constructor data, const char *shortname, const char *source)
: cpu_device( mconfig, type, name, tag, owner, clock, shortname, source)
, m_program_config("program", ENDIANNESS_BIG, byte_size > 8 ? 16 : 8, program_addrbus_width, 0, program )
, m_data_config("data", ENDIANNESS_BIG, 8, data_addrbus_width, 0, data )
@@ -72,7 +72,7 @@ protected:
void set_cki_bus();
address_space_config m_program_config;
- address_space_config m_data_config;
+ address_space_config m_data_config;
UINT8 m_prev_pc; /* previous program counter */
UINT8 m_prev_pa; /* previous page address register */
diff --git a/src/emu/cpu/tms32082/dis32082.c b/src/emu/cpu/tms32082/dis32082.c
index 98b1fa3a82b..fc9f3e0e1d5 100644
--- a/src/emu/cpu/tms32082/dis32082.c
+++ b/src/emu/cpu/tms32082/dis32082.c
@@ -7,10 +7,10 @@
static const char *BCND_CONDITION[32] =
{
- "nev.b", "gt0.b", "eq0.b", "ge0.b", "lt0.b", "ne0.b", "le0.b", "alw.b",
- "nev.h", "gt0.h", "eq0.h", "ge0.h", "lt0.h", "ne0.h", "le0.h", "alw.h",
- "nev.w", "gt0.w", "eq0.w", "ge0.w", "lt0.w", "ne0.w", "le0.w", "alw.w",
- "nev.d", "gt0.d", "eq0.d", "ge0.d", "lt0.d", "ne0.d", "le0.d", "alw.d",
+ "nev.b", "gt0.b", "eq0.b", "ge0.b", "lt0.b", "ne0.b", "le0.b", "alw.b",
+ "nev.h", "gt0.h", "eq0.h", "ge0.h", "lt0.h", "ne0.h", "le0.h", "alw.h",
+ "nev.w", "gt0.w", "eq0.w", "ge0.w", "lt0.w", "ne0.w", "le0.w", "alw.w",
+ "nev.d", "gt0.d", "eq0.d", "ge0.d", "lt0.d", "ne0.d", "le0.d", "alw.d",
};
static char *output;
@@ -40,33 +40,33 @@ static char* get_creg_name(UINT32 reg)
switch (reg)
{
- case 0x0000: sprintf(buffer, "EPC"); break;
- case 0x0001: sprintf(buffer, "EIP"); break;
- case 0x0002: sprintf(buffer, "CONFIG"); break;
- case 0x0004: sprintf(buffer, "INTPEN"); break;
- case 0x0006: sprintf(buffer, "IE"); break;
- case 0x0008: sprintf(buffer, "FPST"); break;
- case 0x000a: sprintf(buffer, "PPERROR"); break;
- case 0x000d: sprintf(buffer, "PKTREQ"); break;
- case 0x000e: sprintf(buffer, "TCOUNT"); break;
- case 0x000f: sprintf(buffer, "TSCALE"); break;
- case 0x0010: sprintf(buffer, "FLTOP"); break;
- case 0x0011: sprintf(buffer, "FLTADR"); break;
- case 0x0012: sprintf(buffer, "FLTTAG"); break;
- case 0x0013: sprintf(buffer, "FLTDTL"); break;
- case 0x0014: sprintf(buffer, "FLTDTH"); break;
- case 0x0020: sprintf(buffer, "SYSSTK"); break;
- case 0x0021: sprintf(buffer, "SYSTMP"); break;
- case 0x0030: sprintf(buffer, "MPC"); break;
- case 0x0031: sprintf(buffer, "MIP"); break;
- case 0x0033: sprintf(buffer, "ECOMCNTL"); break;
- case 0x0034: sprintf(buffer, "ANASTAT"); break;
- case 0x0039: sprintf(buffer, "BRK1"); break;
- case 0x003a: sprintf(buffer, "BRK2"); break;
- case 0x4000: sprintf(buffer, "IN0P"); break;
- case 0x4001: sprintf(buffer, "IN1P"); break;
- case 0x4002: sprintf(buffer, "OUTP"); break;
- default: sprintf(buffer, "CR %04X\n", reg);
+ case 0x0000: sprintf(buffer, "EPC"); break;
+ case 0x0001: sprintf(buffer, "EIP"); break;
+ case 0x0002: sprintf(buffer, "CONFIG"); break;
+ case 0x0004: sprintf(buffer, "INTPEN"); break;
+ case 0x0006: sprintf(buffer, "IE"); break;
+ case 0x0008: sprintf(buffer, "FPST"); break;
+ case 0x000a: sprintf(buffer, "PPERROR"); break;
+ case 0x000d: sprintf(buffer, "PKTREQ"); break;
+ case 0x000e: sprintf(buffer, "TCOUNT"); break;
+ case 0x000f: sprintf(buffer, "TSCALE"); break;
+ case 0x0010: sprintf(buffer, "FLTOP"); break;
+ case 0x0011: sprintf(buffer, "FLTADR"); break;
+ case 0x0012: sprintf(buffer, "FLTTAG"); break;
+ case 0x0013: sprintf(buffer, "FLTDTL"); break;
+ case 0x0014: sprintf(buffer, "FLTDTH"); break;
+ case 0x0020: sprintf(buffer, "SYSSTK"); break;
+ case 0x0021: sprintf(buffer, "SYSTMP"); break;
+ case 0x0030: sprintf(buffer, "MPC"); break;
+ case 0x0031: sprintf(buffer, "MIP"); break;
+ case 0x0033: sprintf(buffer, "ECOMCNTL"); break;
+ case 0x0034: sprintf(buffer, "ANASTAT"); break;
+ case 0x0039: sprintf(buffer, "BRK1"); break;
+ case 0x003a: sprintf(buffer, "BRK2"); break;
+ case 0x4000: sprintf(buffer, "IN0P"); break;
+ case 0x4001: sprintf(buffer, "IN1P"); break;
+ case 0x4002: sprintf(buffer, "OUTP"); break;
+ default: sprintf(buffer, "CR %04X\n", reg);
}
return buffer;
@@ -92,36 +92,36 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
switch ((op >> 20) & 3)
{
- case 0: case 1: case 2: // Short immediate
+ case 0: case 1: case 2: // Short immediate
{
int subop = (op >> 15) & 0x7f;
switch (subop)
{
- case 0x00: print("illop0 "); break;
- case 0x01: print("trap %d", UIMM15(uimm15)); break;
- case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break;
- case 0x04: print("rdcr R%d, %s", rd, get_creg_name(UIMM15(uimm15))); break;
- case 0x05: print("swcr %s, R%d, R%d", get_creg_name(UIMM15(uimm15)), rs, rd); break;
- case 0x06: print("brcr 0x%04X", UIMM15(uimm15)); break;
- case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x09: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x0a: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x0b: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x0c: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x0d: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x0e: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x0f: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x11: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
- case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x00: print("illop0 "); break;
+ case 0x01: print("trap %d", UIMM15(uimm15)); break;
+ case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break;
+ case 0x04: print("rdcr R%d, %s", rd, get_creg_name(UIMM15(uimm15))); break;
+ case 0x05: print("swcr %s, R%d, R%d", get_creg_name(UIMM15(uimm15)), rs, rd); break;
+ case 0x06: print("brcr 0x%04X", UIMM15(uimm15)); break;
+ case 0x08: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x09: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x0a: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x0b: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x0c: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x0d: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x0e: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x0f: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x11: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
+ case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x24: case 0x20:
print("ld.b 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
@@ -155,76 +155,76 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
print("st.d R%d, 0x%04X(R%d)", rd, UIMM15(uimm15), rs);
break;
- case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
- case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
- case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
- case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
- case 0x48: print("bbz 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
- case 0x49: print("bbz.a 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
- case 0x4a: print("bbo 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
- case 0x4b: print("bbo.a 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
- case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
- case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
- case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
- case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
- case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
- case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
- case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
+ case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
+ case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
+ case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
+ case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
+ case 0x48: print("bbz 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
+ case 0x49: print("bbz.a 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
+ case 0x4a: print("bbo 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
+ case 0x4b: print("bbo.a 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
+ case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
+ case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
+ case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
+ case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
+ case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
+ case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
+ case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
}
break;
}
- case 3: // Register / Long immediate
+ case 3: // Register / Long immediate
{
int subop = (op >> 12) & 0xff;
UINT32 imm32 = 0;
- if (op & (1 << 12)) // fetch 32-bit immediate if needed
+ if (op & (1 << 12)) // fetch 32-bit immediate if needed
imm32 = fetch();
switch (subop)
{
- case 0x02: print("trap %d", src1); break;
- case 0x03: print("trap %d", imm32); break;
- case 0x04: print("cmnd R%d", src1); break;
- case 0x05: print("cmnd 0x%08X", imm32); break;
- case 0x08: print("rdcr R%d, R%d", rd, src1); break;
- case 0x09: print("rdcr R%d, %s", rd, get_creg_name(imm32)); break;
- case 0x0a: print("swcr R%d, R%d, R%d", src1, rs, rd); break;
- case 0x0b: print("swcr %s, R%d, R%d", get_creg_name(imm32), rs, rd); break;
- case 0x0c: print("brcr R%d", src1); break;
- case 0x0d: print("brcr 0x%08X", imm32); break;
-
- case 0x10: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x12: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x14: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x16: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x18: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x1a: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x1c: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
- case 0x1e: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
-
- case 0x22: print("and R%d, R%d, R%d", src1, rs, rd); break;
- case 0x23: print("and 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x24: print("and.tf R%d, R%d, R%d", src1, rs, rd); break;
- case 0x25: print("and.tf 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x28: print("and.ft R%d, R%d, R%d", src1, rs, rd); break;
- case 0x29: print("and.ft 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x2c: print("xor R%d, R%d, R%d", src1, rs, rd); break;
- case 0x2d: print("xor 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x2e: print("or R%d, R%d, R%d", src1, rs, rd); break;
- case 0x2f: print("or 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x30: print("and.ff R%d, R%d, R%d", src1, rs, rd); break;
- case 0x31: print("and.ff 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x32: print("xnor R%d, R%d, R%d", src1, rs, rd); break;
- case 0x33: print("xnor 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x36: print("or.tf R%d, R%d, R%d", src1, rs, rd); break;
- case 0x37: print("or.tf 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x3a: print("or.ft R%d, R%d, R%d", src1, rs, rd); break;
- case 0x3b: print("or.ft 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0x3c: print("or.ff R%d, R%d, R%d", src1, rs, rd); break;
- case 0x3d: print("or.ff 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x02: print("trap %d", src1); break;
+ case 0x03: print("trap %d", imm32); break;
+ case 0x04: print("cmnd R%d", src1); break;
+ case 0x05: print("cmnd 0x%08X", imm32); break;
+ case 0x08: print("rdcr R%d, R%d", rd, src1); break;
+ case 0x09: print("rdcr R%d, %s", rd, get_creg_name(imm32)); break;
+ case 0x0a: print("swcr R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x0b: print("swcr %s, R%d, R%d", get_creg_name(imm32), rs, rd); break;
+ case 0x0c: print("brcr R%d", src1); break;
+ case 0x0d: print("brcr 0x%08X", imm32); break;
+
+ case 0x10: print("shift%s.dz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x12: print("shift%s.dm %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x14: print("shift%s.ds %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x16: print("shift%s.ez %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x18: print("shift%s.em %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x1a: print("shift%s.es %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x1c: print("shift%s.iz %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+ case 0x1e: print("shift%s.im %d, %d, R%d, R%d", (op & (1 << 10)) ? "r" : "l", rotate, endmask, rs, rd); break;
+
+ case 0x22: print("and R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x23: print("and 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x24: print("and.tf R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x25: print("and.tf 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x28: print("and.ft R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x29: print("and.ft 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x2c: print("xor R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x2d: print("xor 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x2e: print("or R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x2f: print("or 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x30: print("and.ff R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x31: print("and.ff 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x32: print("xnor R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x33: print("xnor 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x36: print("or.tf R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x37: print("or.tf 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x3a: print("or.ft R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x3b: print("or.ft 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x3c: print("or.ff R%d, R%d, R%d", src1, rs, rd); break;
+ case 0x3d: print("or.ff 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x48: case 0x40:
print("ld.b R%d(R%d), R%d", src1, rs, rd);
@@ -232,22 +232,22 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
case 0x49: case 0x41:
print("ld.b 0x%08X(R%d), R%d", imm32, rs, rd);
break;
- case 0x4a: case 0x42:
+ case 0x4a: case 0x42:
print("ld.h R%d(R%d), R%d", src1, rs, rd);
break;
- case 0x4b: case 0x43:
+ case 0x4b: case 0x43:
print("ld.h 0x%08X(R%d), R%d", imm32, rs, rd);
break;
- case 0x4c: case 0x44:
+ case 0x4c: case 0x44:
print("ld R%d(R%d), R%d", src1, rs, rd);
break;
- case 0x4d: case 0x45:
+ case 0x4d: case 0x45:
print("ld 0x%08X(R%d), R%d", imm32, rs, rd);
break;
- case 0x4e: case 0x46:
+ case 0x4e: case 0x46:
print("ld.d R%d(R%d), R%d", src1, rs, rd);
break;
- case 0x4f: case 0x47:
+ case 0x4f: case 0x47:
print("ld.d 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x58: case 0x50:
@@ -256,7 +256,7 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
case 0x59: case 0x51:
print("ld.ub 0x%08X(R%d), R%d", imm32, rs, rd);
break;
- case 0x5a: case 0x52:
+ case 0x5a: case 0x52:
print("ld.uh R%d(R%d), R%d", src1, rs, rd);
break;
case 0x5b: case 0x53:
@@ -272,66 +272,66 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
case 0x6a: case 0x62:
print("st.h R%d, R%d(R%d)", rd, src1, rs);
break;
- case 0x6b: case 0x63:
+ case 0x6b: case 0x63:
print("st.h R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
- case 0x6c: case 0x64:
+ case 0x6c: case 0x64:
print("st R%d, R%d(R%d)", rd, src1, rs);
break;
- case 0x6d: case 0x65:
+ case 0x6d: case 0x65:
print("st R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
case 0x6e: case 0x66:
print("st.d R%d, R%d(R%d)", rd, src1, rs);
break;
- case 0x6f: case 0x67:
+ case 0x6f: case 0x67:
print("st.d R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
case 0x78: case 0x70:
print("dcache R%d(R%d)", src1, rs);
break;
- case 0x79: case 0x71:
+ case 0x79: case 0x71:
print("dcache 0x%08X(R%d)", imm32, rs);
break;
- case 0x80: print("bsr R%d, R%d", src1, link); break;
- case 0x81: print("bsr 0x%08X, R%d", imm32, link); break;
- case 0x82: print("bsr.a R%d, R%d", src1, rd); break;
- case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break;
- case 0x88: print("jsr R%d, R%d", src1, link); break;
- case 0x89: print("jsr 0x%08X, R%d", imm32, link); break;
- case 0x8a: print("jsr.a R%d, R%d", src1, link); break;
- case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break;
- case 0x90: print("bbz R%d, R%d, #%d", src1, rs, bitnum); break;
- case 0x91: print("bbz 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
- case 0x92: print("bbz.a R%d, R%d, #%d", src1, rs, bitnum); break;
- case 0x93: print("bbz.a 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
- case 0x94: print("bbo R%d, R%d, #%d", src1, rs, bitnum); break;
- case 0x95: print("bbo 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
- case 0x96: print("bbo.a R%d, R%d, #%d", src1, rs, bitnum); break;
- case 0x97: print("bbo.a 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
- case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
- case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
- case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
- case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
- case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break;
- case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break;
- case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break;
- case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break;
- case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break;
- case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break;
-
- case 0xc0: print("vadd R%d, R%d, R%d", src1, rs, rd); break;
- case 0xc1: print("vadd 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xc2: print("vsub R%d, R%d, R%d", src1, rs, rd); break;
- case 0xc3: print("vsub 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xc4: print("vmpy R%d, R%d, R%d", src1, rs, rd); break;
- case 0xc5: print("vmpy 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0x80: print("bsr R%d, R%d", src1, link); break;
+ case 0x81: print("bsr 0x%08X, R%d", imm32, link); break;
+ case 0x82: print("bsr.a R%d, R%d", src1, rd); break;
+ case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break;
+ case 0x88: print("jsr R%d, R%d", src1, link); break;
+ case 0x89: print("jsr 0x%08X, R%d", imm32, link); break;
+ case 0x8a: print("jsr.a R%d, R%d", src1, link); break;
+ case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break;
+ case 0x90: print("bbz R%d, R%d, #%d", src1, rs, bitnum); break;
+ case 0x91: print("bbz 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
+ case 0x92: print("bbz.a R%d, R%d, #%d", src1, rs, bitnum); break;
+ case 0x93: print("bbz.a 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
+ case 0x94: print("bbo R%d, R%d, #%d", src1, rs, bitnum); break;
+ case 0x95: print("bbo 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
+ case 0x96: print("bbo.a R%d, R%d, #%d", src1, rs, bitnum); break;
+ case 0x97: print("bbo.a 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
+ case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
+ case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
+ case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
+ case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
+ case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break;
+
+ case 0xc0: print("vadd R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xc1: print("vadd 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xc2: print("vsub R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xc3: print("vsub 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xc4: print("vmpy R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xc5: print("vmpy 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xd6: case 0xc6:
print("vmsub R%d, R%d, R%d", src1, rs, rd);
@@ -342,34 +342,34 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
case 0xd8: case 0xc8:
print("vrnd R%d, R%d, R%d", src1, rs, rd);
break;
- case 0xd9: case 0xc9:
+ case 0xd9: case 0xc9:
print("vrnd 0x%08X, R%d, R%d", imm32, rs, rd);
break;
- case 0xca: print("vrnd R%d, R%d, R%d", src1, rs, rd); break;
- case 0xcb: print("vrnd 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xcc: print("vmac R%d, R%d, R%d", src1, rs, rd); break;
- case 0xcd: print("vmac 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xce: print("vmsc R%d, R%d, R%d", src1, rs, rd); break;
- case 0xcf: print("vmsc 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xe0: print("fadd R%d, R%d, R%d", src1, rs, rd); break;
- case 0xe1: print("fadd 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xe2: print("fsub R%d, R%d, R%d", src1, rs, rd); break;
- case 0xe3: print("fsub 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xe4: print("fmpy R%d, R%d, R%d", src1, rs, rd); break;
- case 0xe5: print("fmpy 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xe6: print("fdiv R%d, R%d, R%d", src1, rs, rd); break;
- case 0xe7: print("fdiv 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xe8: print("frndx R%d, R%d", src1, rd); break;
- case 0xe9: print("frndx 0x%08X, R%d", imm32, rd); break;
- case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break;
- case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
- case 0xee: print("fsqrt R%d, R%d", src1, rd); break;
- case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break;
- case 0xf0: print("lmo R%d, R%d", rs, rd); break;
- case 0xf2: print("rmo R%d, R%d", rs, rd); break;
- case 0xfc: print("estop "); break;
-
+ case 0xca: print("vrnd R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xcb: print("vrnd 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xcc: print("vmac R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xcd: print("vmac 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xce: print("vmsc R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xcf: print("vmsc 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xe0: print("fadd R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xe1: print("fadd 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xe2: print("fsub R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xe3: print("fsub 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xe4: print("fmpy R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xe5: print("fmpy 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xe6: print("fdiv R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xe7: print("fdiv 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xe8: print("frndx R%d, R%d", src1, rd); break;
+ case 0xe9: print("frndx 0x%08X, R%d", imm32, rd); break;
+ case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break;
+ case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
+ case 0xee: print("fsqrt R%d, R%d", src1, rd); break;
+ case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break;
+ case 0xf0: print("lmo R%d, R%d", rs, rd); break;
+ case 0xf2: print("rmo R%d, R%d", rs, rd); break;
+ case 0xfc: print("estop "); break;
+
case 0xfe: case 0xff:
print("illopF ");
break;
@@ -384,4 +384,4 @@ static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
CPU_DISASSEMBLE(tms32082_mp)
{
return tms32082_disasm_mp(buffer, pc, oprom);
-} \ No newline at end of file
+}
diff --git a/src/emu/cpu/tms32082/mp_ops.c b/src/emu/cpu/tms32082/mp_ops.c
index 03292557cd3..404f9e8a32d 100644
--- a/src/emu/cpu/tms32082/mp_ops.c
+++ b/src/emu/cpu/tms32082/mp_ops.c
@@ -18,15 +18,15 @@
#define ROTATE_L(x, r) ((x << r) | (x >> (32-r)))
#define ROTATE_R(x, r) ((x >> r) | (x << (32-r)))
-#define CMP_OVERFLOW32(r, s, d) ((((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0)
-#define CMP_OVERFLOW16(r, s, d) ((((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0)
-#define CMP_OVERFLOW8(r, s, d) ((((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0)
-#define CARRY32(x) (((x) & (((UINT64)1) << 32)) ? 1 : 0)
-#define CARRY16(x) (((x) & 0x10000) ? 1 : 0)
-#define CARRY8(x) (((x) & 0x100) ? 1 : 0)
-#define SIGN32(x) (((x) & 0x80000000) ? 1 : 0)
-#define SIGN16(x) (((x) & 0x8000) ? 1 : 0)
-#define SIGN8(x) (((x) & 0x80) ? 1 : 0)
+#define CMP_OVERFLOW32(r, s, d) ((((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0)
+#define CMP_OVERFLOW16(r, s, d) ((((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0)
+#define CMP_OVERFLOW8(r, s, d) ((((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0)
+#define CARRY32(x) (((x) & (((UINT64)1) << 32)) ? 1 : 0)
+#define CARRY16(x) (((x) & 0x10000) ? 1 : 0)
+#define CARRY8(x) (((x) & 0x100) ? 1 : 0)
+#define SIGN32(x) (((x) & 0x80000000) ? 1 : 0)
+#define SIGN16(x) (((x) & 0x8000) ? 1 : 0)
+#define SIGN8(x) (((x) & 0x80) ? 1 : 0)
@@ -34,31 +34,31 @@ bool tms32082_mp_device::test_condition(int condition, UINT32 value)
{
switch (condition)
{
- case 0x00: return false; // never, byte
- case 0x01: return (INT8)(value) > 0; // greater than zero, byte
- case 0x02: return (INT8)(value) == 0; // equals zero, byte
- case 0x03: return (INT8)(value) >= 0; // greater than or equal to zero, byte
- case 0x04: return (INT8)(value) < 0; // less than zero, byte
- case 0x05: return (INT8)(value) != 0; // not equal to zero, byte
- case 0x06: return (INT8)(value) <= 0; // less than or equal to zero, byte
- case 0x07: return true; // always, byte
- case 0x08: return false; // never, word
- case 0x09: return (INT16)(value) > 0; // greater than zero, word
- case 0x0a: return (INT16)(value) == 0; // equals zero, word
- case 0x0b: return (INT16)(value) >= 0; // greater than or equal to zero, word
- case 0x0c: return (INT16)(value) < 0; // less than zero, word
- case 0x0d: return (INT16)(value) != 0; // not equal to zero, word
- case 0x0e: return (INT16)(value) <= 0; // less than or equal to zero, word
- case 0x0f: return true; // always, word
- case 0x10: return false; // never, dword
- case 0x11: return (INT32)(value) > 0; // greater than zero, dword
- case 0x12: return (INT32)(value) == 0; // equals zero, dword
- case 0x13: return (INT32)(value) >= 0; // greater than or equal to zero, dword
- case 0x14: return (INT32)(value) < 0; // less than zero, dword
- case 0x15: return (INT32)(value) != 0; // not equal to zero, dword
- case 0x16: return (INT32)(value) <= 0; // less than or equal to zero, dword
- case 0x17: return true; // always, dword
- default: return false; // reserved
+ case 0x00: return false; // never, byte
+ case 0x01: return (INT8)(value) > 0; // greater than zero, byte
+ case 0x02: return (INT8)(value) == 0; // equals zero, byte
+ case 0x03: return (INT8)(value) >= 0; // greater than or equal to zero, byte
+ case 0x04: return (INT8)(value) < 0; // less than zero, byte
+ case 0x05: return (INT8)(value) != 0; // not equal to zero, byte
+ case 0x06: return (INT8)(value) <= 0; // less than or equal to zero, byte
+ case 0x07: return true; // always, byte
+ case 0x08: return false; // never, word
+ case 0x09: return (INT16)(value) > 0; // greater than zero, word
+ case 0x0a: return (INT16)(value) == 0; // equals zero, word
+ case 0x0b: return (INT16)(value) >= 0; // greater than or equal to zero, word
+ case 0x0c: return (INT16)(value) < 0; // less than zero, word
+ case 0x0d: return (INT16)(value) != 0; // not equal to zero, word
+ case 0x0e: return (INT16)(value) <= 0; // less than or equal to zero, word
+ case 0x0f: return true; // always, word
+ case 0x10: return false; // never, dword
+ case 0x11: return (INT32)(value) > 0; // greater than zero, dword
+ case 0x12: return (INT32)(value) == 0; // equals zero, dword
+ case 0x13: return (INT32)(value) >= 0; // greater than or equal to zero, dword
+ case 0x14: return (INT32)(value) < 0; // less than zero, dword
+ case 0x15: return (INT32)(value) != 0; // not equal to zero, dword
+ case 0x16: return (INT32)(value) <= 0; // less than or equal to zero, dword
+ case 0x17: return true; // always, dword
+ default: return false; // reserved
}
}
@@ -66,7 +66,7 @@ void tms32082_mp_device::execute_short_imm()
{
switch ((m_ir >> 15) & 0x7f)
{
- case 0x04: // rdcr
+ case 0x04: // rdcr
{
int rd = OP_RD();
INT32 imm = OP_SIMM15();
@@ -78,7 +78,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x05: // swcr
+ case 0x05: // swcr
{
int rd = OP_RD();
int rs = OP_RS();
@@ -92,7 +92,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x0b: // shift.ez
+ case 0x0b: // shift.ez
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@@ -109,11 +109,11 @@ void tms32082_mp_device::execute_short_imm()
UINT32 compmask = endmask & shiftmask;
UINT32 res = 0;
- if (r) // right
+ if (r) // right
{
res = ROTATE_R(source, rot) & compmask;
}
- else // left
+ else // left
{
res = ROTATE_L(source, rot) & compmask;
}
@@ -123,7 +123,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x0e: // shift.iz
+ case 0x0e: // shift.iz
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@@ -139,11 +139,11 @@ void tms32082_mp_device::execute_short_imm()
UINT32 compmask = endmask & ~shiftmask;
UINT32 res = 0;
- if (r) // right
+ if (r) // right
{
res = ROTATE_R(source, rot) & compmask;
}
- else // left
+ else // left
{
res = ROTATE_L(source, rot) & compmask;
}
@@ -153,7 +153,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x11: // and
+ case 0x11: // and
{
int rd = OP_RD();
int rs = OP_RS();
@@ -164,7 +164,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x17: // or
+ case 0x17: // or
{
int rd = OP_RD();
int rs = OP_RS();
@@ -176,7 +176,7 @@ void tms32082_mp_device::execute_short_imm()
}
case 0x36:
- case 0x32: // st
+ case 0x32: // st
{
int rd = OP_RD();
int base = OP_BASE();
@@ -192,7 +192,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x49: // bbz.a
+ case 0x49: // bbz.a
{
int bitnum = OP_BITNUM();
INT32 offset = OP_SIMM15();
@@ -205,7 +205,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x4b: // bbo.a
+ case 0x4b: // bbo.a
{
int bitnum = OP_BITNUM();
INT32 offset = OP_SIMM15();
@@ -218,7 +218,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x4d: // bcnd.a
+ case 0x4d: // bcnd.a
{
INT32 offset = OP_SIMM15();
int code = OP_RD();
@@ -231,7 +231,7 @@ void tms32082_mp_device::execute_short_imm()
break;
}
- case 0x50: // cmp
+ case 0x50: // cmp
{
UINT32 src1 = OP_SIMM15();
UINT32 src2 = m_reg[OP_RS()];
@@ -262,45 +262,45 @@ void tms32082_mp_device::execute_short_imm()
UINT32 flags = 0;
// 32-bits (bits 20-29)
- flags |= ((c32) & 1) << 29; // higher than or same (C)
- flags |= ((~c32) & 1) << 28; // lower than (~C)
- flags |= ((~c32|z32) & 1) << 27; // lower than or same (~C|Z)
- flags |= ((c32&~z32) & 1) << 26; // higher than (C&~Z)
- flags |= (((n32&v32)|(~n32&~v32)) & 1) << 25; // greater than or equal (N&V)|(~N&~V)
- flags |= (((n32&~v32)|(~n32&v32)) & 1) << 24; // less than (N&~V)|(~N&V)
- flags |= (((n32&~v32)|(~n32&v32)|(z32)) & 1) << 23; // less than or equal (N&~V)|(~N&V)|Z
- flags |= (((n32&v32&~z32)|(~n32&~v32&~z32)) & 1) << 22; // greater than (N&V&~Z)|(~N&~V&~Z)
- flags |= ((~z32) & 1) << 21; // not equal (~Z)
- flags |= ((z32) & 1) << 20; // equal (Z)
+ flags |= ((c32) & 1) << 29; // higher than or same (C)
+ flags |= ((~c32) & 1) << 28; // lower than (~C)
+ flags |= ((~c32|z32) & 1) << 27; // lower than or same (~C|Z)
+ flags |= ((c32&~z32) & 1) << 26; // higher than (C&~Z)
+ flags |= (((n32&v32)|(~n32&~v32)) & 1) << 25; // greater than or equal (N&V)|(~N&~V)
+ flags |= (((n32&~v32)|(~n32&v32)) & 1) << 24; // less than (N&~V)|(~N&V)
+ flags |= (((n32&~v32)|(~n32&v32)|(z32)) & 1) << 23; // less than or equal (N&~V)|(~N&V)|Z
+ flags |= (((n32&v32&~z32)|(~n32&~v32&~z32)) & 1) << 22; // greater than (N&V&~Z)|(~N&~V&~Z)
+ flags |= ((~z32) & 1) << 21; // not equal (~Z)
+ flags |= ((z32) & 1) << 20; // equal (Z)
// 16-bits (bits 10-19)
- flags |= ((c16) & 1) << 19; // higher than or same (C)
- flags |= ((~c16) & 1) << 18; // lower than (~C)
- flags |= ((~c16|z16) & 1) << 17; // lower than or same (~C|Z)
- flags |= ((c16&~z16) & 1) << 16; // higher than (C&~Z)
- flags |= (((n16&v16)|(~n16&~v16)) & 1) << 15; // greater than or equal (N&V)|(~N&~V)
- flags |= (((n16&~v16)|(~n16&v16)) & 1) << 14; // less than (N&~V)|(~N&V)
- flags |= (((n16&~v16)|(~n16&v16)|(z16)) & 1) << 13; // less than or equal (N&~V)|(~N&V)|Z
- flags |= (((n16&v16&~z16)|(~n16&~v16&~z16)) & 1) << 12; // greater than (N&V&~Z)|(~N&~V&~Z)
- flags |= ((~z16) & 1) << 11; // not equal (~Z)
- flags |= ((z16) & 1) << 10; // equal (Z)
+ flags |= ((c16) & 1) << 19; // higher than or same (C)
+ flags |= ((~c16) & 1) << 18; // lower than (~C)
+ flags |= ((~c16|z16) & 1) << 17; // lower than or same (~C|Z)
+ flags |= ((c16&~z16) & 1) << 16; // higher than (C&~Z)
+ flags |= (((n16&v16)|(~n16&~v16)) & 1) << 15; // greater than or equal (N&V)|(~N&~V)
+ flags |= (((n16&~v16)|(~n16&v16)) & 1) << 14; // less than (N&~V)|(~N&V)
+ flags |= (((n16&~v16)|(~n16&v16)|(z16)) & 1) << 13; // less than or equal (N&~V)|(~N&V)|Z
+ flags |= (((n16&v16&~z16)|(~n16&~v16&~z16)) & 1) << 12; // greater than (N&V&~Z)|(~N&~V&~Z)
+ flags |= ((~z16) & 1) << 11; // not equal (~Z)
+ flags |= ((z16) & 1) << 10; // equal (Z)
// 8-bits (bits 0-9)
- flags |= ((c8) & 1) << 9; // higher than or same (C)
- flags |= ((~c8) & 1) << 8; // lower than (~C)
- flags |= ((~c8|z8) & 1) << 7; // lower than or same (~C|Z)
- flags |= ((c8&~z8) & 1) << 6; // higher than (C&~Z)
- flags |= (((n8&v8)|(~n8&~v8)) & 1) << 5; // greater than or equal (N&V)|(~N&~V)
- flags |= (((n8&~v8)|(~n8&v8)) & 1) << 4; // less than (N&~V)|(~N&V)
- flags |= (((n8&~v8)|(~n8&v8)|(z8)) & 1) << 3; // less than or equal (N&~V)|(~N&V)|Z
- flags |= (((n8&v8&~z8)|(~n8&~v8&~z8)) & 1) << 2; // greater than (N&V&~Z)|(~N&~V&~Z)
- flags |= ((~z8) & 1) << 1; // not equal (~Z)
- flags |= ((z8) & 1) << 0; // equal (Z)
+ flags |= ((c8) & 1) << 9; // higher than or same (C)
+ flags |= ((~c8) & 1) << 8; // lower than (~C)
+ flags |= ((~c8|z8) & 1) << 7; // lower than or same (~C|Z)
+ flags |= ((c8&~z8) & 1) << 6; // higher than (C&~Z)
+ flags |= (((n8&v8)|(~n8&~v8)) & 1) << 5; // greater than or equal (N&V)|(~N&~V)
+ flags |= (((n8&~v8)|(~n8&v8)) & 1) << 4; // less than (N&~V)|(~N&V)
+ flags |= (((n8&~v8)|(~n8&v8)|(z8)) & 1) << 3; // less than or equal (N&~V)|(~N&V)|Z
+ flags |= (((n8&v8&~z8)|(~n8&~v8&~z8)) & 1) << 2; // greater than (N&V&~Z)|(~N&~V&~Z)
+ flags |= ((~z8) & 1) << 1; // not equal (~Z)
+ flags |= ((z8) & 1) << 0; // equal (Z)
if (rd)
m_reg[rd] = flags;
break;
}
- case 0x59: // addu
+ case 0x59: // addu
{
INT32 imm = OP_SIMM15();
int rd = OP_RD();
@@ -327,7 +327,7 @@ void tms32082_mp_device::execute_reg_long_imm()
switch ((m_ir >> 12) & 0xff)
{
- case 0x04: // cmnd
+ case 0x04: // cmnd
{
UINT32 data = has_imm ? imm32 : m_reg[OP_SRC1()];
@@ -335,7 +335,7 @@ void tms32082_mp_device::execute_reg_long_imm()
break;
}
- case 0x16: // shift.ez
+ case 0x16: // shift.ez
{
int r = (m_ir & (1 << 10));
int inv = (m_ir & (1 << 11));
@@ -352,11 +352,11 @@ void tms32082_mp_device::execute_reg_long_imm()
UINT32 compmask = endmask & shiftmask;
UINT32 res = 0;
- if (r) // right
+ if (r) // right
{
res = ROTATE_R(source, rot) & compmask;
}
- else // left
+ else // left
{
res = ROTATE_L(source, rot) & compmask;
}
@@ -367,7 +367,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x24:
- case 0x25: // and.tf
+ case 0x25: // and.tf
{
int rd = OP_RD();
int rs = OP_RS();
@@ -379,7 +379,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x2e:
- case 0x2f: // or
+ case 0x2f: // or
{
int rd = OP_RD();
int rs = OP_RS();
@@ -389,7 +389,7 @@ void tms32082_mp_device::execute_reg_long_imm()
break;
}
- case 0x43: // ld.h
+ case 0x43: // ld.h
case 0x4b:
{
int shift = (m_ir & (1 << 11)) ? 1 : 0;
@@ -401,7 +401,7 @@ void tms32082_mp_device::execute_reg_long_imm()
UINT32 address = m_reg[base] + ((has_imm ? imm32 : m_reg[OP_SRC1()]) << shift);
UINT32 r = m_program->read_word(address);
if (r & 0x8000) r |= 0xffff0000;
-
+
if (rd)
m_reg[rd] = r;
@@ -411,7 +411,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x6d:
- case 0x65: // st
+ case 0x65: // st
{
int shift = (m_ir & (1 << 11)) ? 2 : 0;
int m = m_ir & (1 << 15);
@@ -427,7 +427,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x88:
- case 0x89: // jsr
+ case 0x89: // jsr
{
int link = OP_LINK();
int base = OP_BASE();
@@ -445,7 +445,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0x8a:
- case 0x8b: // jsr.a
+ case 0x8b: // jsr.a
{
int link = OP_LINK();
int base = OP_BASE();
@@ -458,7 +458,7 @@ void tms32082_mp_device::execute_reg_long_imm()
}
case 0xb2:
- case 0xb3: // addu
+ case 0xb3: // addu
{
int rd = OP_RD();
int rs = OP_RS();
@@ -488,4 +488,4 @@ void tms32082_mp_device::execute()
execute_reg_long_imm();
break;
}
-} \ No newline at end of file
+}
diff --git a/src/emu/cpu/tms32082/tms32082.c b/src/emu/cpu/tms32082/tms32082.c
index 9c8996e6ff5..dfffe66c501 100644
--- a/src/emu/cpu/tms32082/tms32082.c
+++ b/src/emu/cpu/tms32082/tms32082.c
@@ -1,7 +1,7 @@
/*
- Texas Instruments TMS320C82 DSP Emulator
+ Texas Instruments TMS320C82 DSP Emulator
- Written by Ville Linde
+ Written by Ville Linde
*/
@@ -213,7 +213,7 @@ UINT32 tms32082_mp_device::read_creg(int reg)
{
switch (reg)
{
- case 0xa: // PPERROR
+ case 0xa: // PPERROR
return 0;
default:
@@ -258,4 +258,4 @@ void tms32082_mp_device::execute_run()
};
return;
-} \ No newline at end of file
+}
diff --git a/src/emu/cpu/tms32082/tms32082.h b/src/emu/cpu/tms32082/tms32082.h
index 28fcfb36f59..890729fb77e 100644
--- a/src/emu/cpu/tms32082/tms32082.h
+++ b/src/emu/cpu/tms32082/tms32082.h
@@ -64,7 +64,7 @@ protected:
virtual UINT32 execute_max_cycles() const { return 1; }
virtual UINT32 execute_input_lines() const { return 0; }
virtual void execute_run();
-
+
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
{
@@ -114,4 +114,4 @@ protected:
extern const device_type TMS32082_MP;
-#endif /* __TMS32082_H__ */ \ No newline at end of file
+#endif /* __TMS32082_H__ */