summaryrefslogtreecommitdiffstatshomepage
path: root/src/emu/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/emu/cpu')
-rw-r--r--src/emu/cpu/cpu.mak6
-rw-r--r--src/emu/cpu/g65816/g65816.c4
-rw-r--r--src/emu/cpu/jaguar/jaguar.c4
-rw-r--r--src/emu/cpu/m6502/m3745x.c185
-rw-r--r--src/emu/cpu/m6502/m3745x.h30
-rw-r--r--src/emu/cpu/m6502/m740.c10
-rw-r--r--src/emu/cpu/m6502/m740.h32
-rw-r--r--src/emu/cpu/m6502/om740.lst1
-rw-r--r--src/emu/cpu/m6809/hd6309.c266
-rw-r--r--src/emu/cpu/m6809/hd6309.h29
-rw-r--r--src/emu/cpu/m6809/konami.c74
-rw-r--r--src/emu/cpu/m6809/konami.h2
-rw-r--r--src/emu/cpu/m6809/m6809.c78
-rw-r--r--src/emu/cpu/m6809/m6809.h190
-rw-r--r--src/emu/cpu/m6809/m6809inl.h68
-rw-r--r--src/emu/cpu/sh2/sh2drc.c28
16 files changed, 502 insertions, 505 deletions
diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak
index 53cfe7a72bc..7eb9a7f3dce 100644
--- a/src/emu/cpu/cpu.mak
+++ b/src/emu/cpu/cpu.mak
@@ -1222,15 +1222,15 @@ $(CPUOBJ)/m6809/konami.o: $(CPUSRC)/m6809/konami.c \
$(CPUSRC)/m6809/m6809inl.h \
$(CPUOBJ)/m6809/konami.inc
-$(CPUOBJ)/m6809/m6809.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/m6809.ops $(CPUSRC)/m6809/base6x09.ops
+$(CPUOBJ)/m6809/m6809.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/m6809.ops $(CPUSRC)/m6809/base6x09.ops
@echo Generating m6809 source file...
$(PYTHON) $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/m6809.ops > $@
-$(CPUOBJ)/m6809/hd6309.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/hd6309.ops $(CPUSRC)/m6809/base6x09.ops
+$(CPUOBJ)/m6809/hd6309.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/hd6309.ops $(CPUSRC)/m6809/base6x09.ops
@echo Generating hd6309 source file...
$(PYTHON) $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/hd6309.ops > $@
-$(CPUOBJ)/m6809/konami.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/konami.ops $(CPUSRC)/m6809/base6x09.ops
+$(CPUOBJ)/m6809/konami.inc: $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/konami.ops $(CPUSRC)/m6809/base6x09.ops
@echo Generating konami source file...
$(PYTHON) $(CPUSRC)/m6809/m6809make.py $(CPUSRC)/m6809/konami.ops > $@
diff --git a/src/emu/cpu/g65816/g65816.c b/src/emu/cpu/g65816/g65816.c
index 4e49f0678f4..47cfad6ae15 100644
--- a/src/emu/cpu/g65816/g65816.c
+++ b/src/emu/cpu/g65816/g65816.c
@@ -681,9 +681,9 @@ void set_5a22_map(legacy_cpu_device &cpu)
cpu.space(AS_PROGRAM).install_legacy_write_handler(0x4204, 0x4204, 0, 0xbf0000, FUNC(wrdivl_w));
cpu.space(AS_PROGRAM).install_legacy_write_handler(0x4205, 0x4205, 0, 0xbf0000, FUNC(wrdivh_w));
cpu.space(AS_PROGRAM).install_legacy_write_handler(0x4206, 0x4206, 0, 0xbf0000, FUNC(wrdvdd_w));
-
+
cpu.space(AS_PROGRAM).install_legacy_write_handler(0x420d, 0x420d, 0, 0xbf0000, FUNC(memsel_w));
-
+
cpu.space(AS_PROGRAM).install_legacy_read_handler(0x4214, 0x4214, 0, 0xbf0000, FUNC(rddivl_r));
cpu.space(AS_PROGRAM).install_legacy_read_handler(0x4215, 0x4215, 0, 0xbf0000, FUNC(rddivh_r));
cpu.space(AS_PROGRAM).install_legacy_read_handler(0x4216, 0x4216, 0, 0xbf0000, FUNC(rdmpyl_r));
diff --git a/src/emu/cpu/jaguar/jaguar.c b/src/emu/cpu/jaguar/jaguar.c
index 20ad81fe031..10843a961b8 100644
--- a/src/emu/cpu/jaguar/jaguar.c
+++ b/src/emu/cpu/jaguar/jaguar.c
@@ -103,8 +103,8 @@ struct jaguar_cpu_state
address_space *program;
direct_read_data *direct;
- UINT32 internal_ram_start;
- UINT32 internal_ram_end;
+ UINT32 internal_ram_start;
+ UINT32 internal_ram_end;
};
diff --git a/src/emu/cpu/m6502/m3745x.c b/src/emu/cpu/m6502/m3745x.c
index 87ecd7b5b25..bc3851ddb1e 100644
--- a/src/emu/cpu/m6502/m3745x.c
+++ b/src/emu/cpu/m6502/m3745x.c
@@ -11,16 +11,16 @@
// Interrupt control bits (interpolated from C68 program; need 7450 Group manual badly)
-#define IRQ1_INT1 (0x04)
-#define IRQ1_INT2 (0x08) // guess, not used in C68
-#define IRQ1_INT3 (0x10) // guess, not used in C68
+#define IRQ1_INT1 (0x04)
+#define IRQ1_INT2 (0x08) // guess, not used in C68
+#define IRQ1_INT3 (0x10) // guess, not used in C68
-#define IRQ2_SERIALRX (0x08)
-#define IRQ2_SERIALTX (0x10)
-#define IRQ2_ADC (0x20)
+#define IRQ2_SERIALRX (0x08)
+#define IRQ2_SERIALTX (0x10)
+#define IRQ2_ADC (0x20)
-#define ADCTRL_CH_MASK (0x07) // AD ctrl reg. channel mask
-#define ADCTRL_COMPLETE (0x08) // AD ctrl "start"/"complete" bit
+#define ADCTRL_CH_MASK (0x07) // AD ctrl reg. channel mask
+#define ADCTRL_COMPLETE (0x08) // AD ctrl "start"/"complete" bit
//**************************************************************************
// DEVICE DEFINITIONS
@@ -75,7 +75,7 @@ void m3745x_device::device_start()
write_p3.resolve_safe();
write_p4.resolve_safe();
write_p5.resolve_safe();
- write_p6.resolve_safe();
+ write_p6.resolve_safe();
read_ad_0.resolve_safe(0);
read_ad_1.resolve_safe(0);
read_ad_2.resolve_safe(0);
@@ -109,7 +109,7 @@ void m3745x_device::device_reset()
{
m740_device::device_reset();
- SP = 0x01ff; // we have the "traditional" stack in page 1, not 0 like some M740 derivatives
+ SP = 0x01ff; // we have the "traditional" stack in page 1, not 0 like some M740 derivatives
for (int i = 0; i < NUM_TIMERS; i++)
{
@@ -179,7 +179,7 @@ void m3745x_device::execute_set_input(int inputnum, int state)
}
break;
- case M3745X_SET_OVERFLOW: // the base 740 class can handle this
+ case M3745X_SET_OVERFLOW: // the base 740 class can handle this
m740_device::execute_set_input(M740_SET_OVERFLOW, state);
break;
}
@@ -190,7 +190,7 @@ void m3745x_device::execute_set_input(int inputnum, int state)
void m3745x_device::recalc_irqs()
{
UINT16 all_ints = 0;
- int static const irq_lines[16] =
+ int static const irq_lines[16] =
{
-1, -1, -1, M740_INT11_LINE, M740_INT12_LINE, M740_INT13_LINE, -1, -1,
-1, -1, M740_INT2_LINE, M740_INT3_LINE, M740_INT4_LINE, -1, -1, -1
@@ -199,7 +199,7 @@ void m3745x_device::recalc_irqs()
all_ints = (m_intreq1 & m_intctrl1) << 8;
all_ints |= (m_intreq2 & m_intctrl2);
-// printf("recalc_irqs: last_all_ints = %04x last_ints = %04x (req1 %02x ctrl1 %02x req2 %02x ctrl2 %02x)\n", all_ints, m_last_all_ints, m_intreq1, m_intctrl1, m_intreq2, m_intctrl2);
+// printf("recalc_irqs: last_all_ints = %04x last_ints = %04x (req1 %02x ctrl1 %02x req2 %02x ctrl2 %02x)\n", all_ints, m_last_all_ints, m_intreq1, m_intctrl1, m_intreq2, m_intctrl2);
// check all 16 IRQ bits for changes
for (int i = 0; i < 16; i++)
@@ -210,19 +210,19 @@ void m3745x_device::recalc_irqs()
// and wasn't last time
if (!(m_last_all_ints & (1 << i)))
{
-// printf(" asserting irq %d (%d)\n", i, irq_lines[i]);
+// printf(" asserting irq %d (%d)\n", i, irq_lines[i]);
if (irq_lines[i] != -1)
{
m740_device::execute_set_input(irq_lines[i], ASSERT_LINE);
}
}
}
- else // bit is clear now
+ else // bit is clear now
{
// ...and wasn't clear last time
if (m_last_all_ints & (1 << i))
{
-// printf(" clearing irq %d (%d)\n", i, irq_lines[i]);
+// printf(" clearing irq %d (%d)\n", i, irq_lines[i]);
if (irq_lines[i] != -1)
{
m740_device::execute_set_input(irq_lines[i], CLEAR_LINE);
@@ -258,103 +258,103 @@ void m3745x_device::send_port(address_space &space, UINT8 offset, UINT8 data)
UINT8 m3745x_device::read_port(UINT8 offset)
{
- UINT8 incoming = 0;
+ UINT8 incoming = 0;
- switch (offset)
- {
- case 0:
- incoming = read_p3();
- break;
+ switch (offset)
+ {
+ case 0:
+ incoming = read_p3();
+ break;
- case 1:
- incoming = read_p4();
- break;
+ case 1:
+ incoming = read_p4();
+ break;
- case 2:
- incoming = read_p5();
- break;
+ case 2:
+ incoming = read_p5();
+ break;
- case 3:
- incoming = read_p6();
- break;
- }
+ case 3:
+ incoming = read_p6();
+ break;
+ }
- // apply data direction registers
- incoming &= (m_ddrs[offset] ^ 0xff);
- // OR in ddr-masked version of port writes
- incoming |= (m_ports[offset] & m_ddrs[offset]);
+ // apply data direction registers
+ incoming &= (m_ddrs[offset] ^ 0xff);
+ // OR in ddr-masked version of port writes
+ incoming |= (m_ports[offset] & m_ddrs[offset]);
- return incoming;
+ return incoming;
}
READ8_MEMBER(m3745x_device::ports_r)
{
- switch (offset)
- {
- case 0:
- return read_port(0);
+ switch (offset)
+ {
+ case 0:
+ return read_port(0);
- case 1:
- return m_ddrs[0];
+ case 1:
+ return m_ddrs[0];
- case 2:
- return read_port(1);
+ case 2:
+ return read_port(1);
- case 4:
- return read_port(2);
+ case 4:
+ return read_port(2);
- case 5:
- return m_ddrs[2];
+ case 5:
+ return m_ddrs[2];
- case 6:
- return read_port(3);
+ case 6:
+ return read_port(3);
- case 7:
- return m_ddrs[3];
- }
+ case 7:
+ return m_ddrs[3];
+ }
- return 0xff;
+ return 0xff;
}
WRITE8_MEMBER(m3745x_device::ports_w)
{
- switch (offset)
- {
- case 0: // p3
- send_port(space, 0, data & m_ddrs[0]);
- m_ports[0] = data;
- break;
-
- case 1: // p3 ddr
- send_port(space, 0, m_ports[0] & data);
- m_ddrs[0] = data;
- break;
-
- case 2: // p4
- send_port(space, 1, data & m_ddrs[1]);
- m_ports[1] = data;
- break;
-
- case 4: // p5
- send_port(space, 2, data & m_ddrs[2]);
- m_ports[2] = data;
- break;
-
- case 5: // p5 ddr
- send_port(space, 2, m_ports[2] & data);
- m_ddrs[2] = data;
- break;
-
- case 6: // p6
- send_port(space, 3, data & m_ddrs[3]);
- m_ports[3] = data;
- break;
-
- case 7: // p6 ddr
- send_port(space, 3, m_ports[3] & data);
- m_ddrs[3] = data;
- break;
- }
+ switch (offset)
+ {
+ case 0: // p3
+ send_port(space, 0, data & m_ddrs[0]);
+ m_ports[0] = data;
+ break;
+
+ case 1: // p3 ddr
+ send_port(space, 0, m_ports[0] & data);
+ m_ddrs[0] = data;
+ break;
+
+ case 2: // p4
+ send_port(space, 1, data & m_ddrs[1]);
+ m_ports[1] = data;
+ break;
+
+ case 4: // p5
+ send_port(space, 2, data & m_ddrs[2]);
+ m_ports[2] = data;
+ break;
+
+ case 5: // p5 ddr
+ send_port(space, 2, m_ports[2] & data);
+ m_ddrs[2] = data;
+ break;
+
+ case 6: // p6
+ send_port(space, 3, data & m_ddrs[3]);
+ m_ports[3] = data;
+ break;
+
+ case 7: // p6 ddr
+ send_port(space, 3, m_ports[3] & data);
+ m_ddrs[3] = data;
+ break;
+ }
}
READ8_MEMBER(m3745x_device::intregs_r)
@@ -495,4 +495,3 @@ m37450_device::m37450_device(const machine_config &mconfig, device_type type, co
m3745x_device(mconfig, type, name, tag, owner, clock, ADDRESS_MAP_NAME(m37450_map))
{
}
-
diff --git a/src/emu/cpu/m6502/m3745x.h b/src/emu/cpu/m6502/m3745x.h
index 43798a5b83a..83178649083 100644
--- a/src/emu/cpu/m6502/m3745x.h
+++ b/src/emu/cpu/m6502/m3745x.h
@@ -63,31 +63,31 @@ public:
const address_space_config m_program_config;
- template<class _read, class _write> void set_p3_callbacks(_read rd, _write wr)
+ template<class _read, class _write> void set_p3_callbacks(_read rd, _write wr)
{
read_p3.set_callback(rd);
write_p3.set_callback(wr);
}
- template<class _read, class _write> void set_p4_callbacks(_read rd, _write wr)
+ template<class _read, class _write> void set_p4_callbacks(_read rd, _write wr)
{
read_p4.set_callback(rd);
write_p4.set_callback(wr);
}
- template<class _read, class _write> void set_p5_callbacks(_read rd, _write wr)
+ template<class _read, class _write> void set_p5_callbacks(_read rd, _write wr)
{
read_p5.set_callback(rd);
write_p5.set_callback(wr);
}
- template<class _read, class _write> void set_p6_callbacks(_read rd, _write wr)
+ template<class _read, class _write> void set_p6_callbacks(_read rd, _write wr)
{
read_p6.set_callback(rd);
write_p6.set_callback(wr);
}
- template<class _read, class _read2, class _read3, class _read4> void set_ad14_callbacks(_read rd, _read2 rd2, _read3 rd3, _read4 rd4)
+ template<class _read, class _read2, class _read3, class _read4> void set_ad14_callbacks(_read rd, _read2 rd2, _read3 rd3, _read4 rd4)
{
read_ad_0.set_callback(rd);
read_ad_1.set_callback(rd2);
@@ -95,7 +95,7 @@ public:
read_ad_3.set_callback(rd4);
}
- template<class _read, class _read2, class _read3, class _read4> void set_ad58_callbacks(_read rd, _read2 rd2, _read3 rd3, _read4 rd4)
+ template<class _read, class _read2, class _read3, class _read4> void set_ad58_callbacks(_read rd, _read2 rd2, _read3 rd3, _read4 rd4)
{
read_ad_4.set_callback(rd);
read_ad_5.set_callback(rd2);
@@ -108,12 +108,12 @@ public:
devcb2_read8 read_ad_0, read_ad_1, read_ad_2, read_ad_3;
devcb2_read8 read_ad_4, read_ad_5, read_ad_6, read_ad_7;
- DECLARE_READ8_MEMBER(ports_r);
- DECLARE_WRITE8_MEMBER(ports_w);
- DECLARE_READ8_MEMBER(adc_r);
- DECLARE_WRITE8_MEMBER(adc_w);
- DECLARE_READ8_MEMBER(intregs_r);
- DECLARE_WRITE8_MEMBER(intregs_w);
+ DECLARE_READ8_MEMBER(ports_r);
+ DECLARE_WRITE8_MEMBER(ports_w);
+ DECLARE_READ8_MEMBER(adc_r);
+ DECLARE_WRITE8_MEMBER(adc_w);
+ DECLARE_READ8_MEMBER(intregs_r);
+ DECLARE_WRITE8_MEMBER(intregs_w);
bool are_port_bits_output(UINT8 port, UINT8 mask) { return ((m_ddrs[port] & mask) == mask) ? true : false; }
@@ -127,11 +127,11 @@ protected:
virtual const address_space_config *memory_space_config(address_spacenum spacenum) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
void send_port(address_space &space, UINT8 offset, UINT8 data);
- UINT8 read_port(UINT8 offset);
+ UINT8 read_port(UINT8 offset);
void recalc_irqs();
- UINT8 m_ports[6], m_ddrs[6];
+ UINT8 m_ports[6], m_ddrs[6];
UINT8 m_intreq1, m_intreq2, m_intctrl1, m_intctrl2;
UINT8 m_adctrl;
UINT16 m_last_all_ints;
@@ -140,7 +140,7 @@ private:
emu_timer *m_timers[NUM_TIMERS];
};
-class m37450_device : public m3745x_device
+class m37450_device : public m3745x_device
{
public:
m37450_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
diff --git a/src/emu/cpu/m6502/m740.c b/src/emu/cpu/m6502/m740.c
index 9aa42f13c37..f6035794c1e 100644
--- a/src/emu/cpu/m6502/m740.c
+++ b/src/emu/cpu/m6502/m740.c
@@ -88,12 +88,12 @@ UINT8 m740_device::do_seb(UINT8 in, UINT8 bit)
// doesn't affect the flags
UINT8 m740_device::do_rrf(UINT8 in)
{
- return ((in&0xf)<<4) | ((in&0xf0)>>4);
+ return ((in&0xf)<<4) | ((in&0xf0)>>4);
}
void m740_device::execute_set_input(int inputnum, int state)
{
- switch(inputnum)
+ switch(inputnum)
{
case M740_INT0_LINE:
case M740_INT1_LINE:
@@ -109,9 +109,9 @@ void m740_device::execute_set_input(int inputnum, int state)
case M740_INT11_LINE:
case M740_INT12_LINE:
case M740_INT13_LINE:
- case M740_INT14_LINE: // 37450 has 15 IRQ lines, no other known variant has that many
+ case M740_INT14_LINE: // 37450 has 15 IRQ lines, no other known variant has that many
set_irq_line(inputnum - M740_INT0_LINE, state);
- break;
+ break;
case V_LINE:
if(!v_state && state == ASSERT_LINE)
@@ -151,7 +151,7 @@ void m740_device::set_irq_line(int line, int state)
}
}
-// printf("M740 single IRQ state is %d (MPX %08x, vector %x)\n", irq_state, m_irq_multiplex, m_irq_vector);
+// printf("M740 single IRQ state is %d (MPX %08x, vector %x)\n", irq_state, m_irq_multiplex, m_irq_vector);
}
#include "cpu/m6502/m740.inc"
diff --git a/src/emu/cpu/m6502/m740.h b/src/emu/cpu/m6502/m740.h
index 4e085f95cda..cdf738956c2 100644
--- a/src/emu/cpu/m6502/m740.h
+++ b/src/emu/cpu/m6502/m740.h
@@ -46,16 +46,16 @@ class m740_device : public m6502_device {
public:
enum
{
- M740_INT0_LINE = INPUT_LINE_IRQ0, // (fffc)
- M740_INT1_LINE, // (fffa)
- M740_INT2_LINE, // (fff8)
- M740_INT3_LINE, // (fff6)
- M740_INT4_LINE, // (fff4)
- M740_INT5_LINE, // (fff2)
- M740_INT6_LINE, // (fff0)
- M740_INT7_LINE, // (ffee)
- M740_INT8_LINE, // (ffec)
- M740_INT9_LINE, // (ffea)
+ M740_INT0_LINE = INPUT_LINE_IRQ0, // (fffc)
+ M740_INT1_LINE, // (fffa)
+ M740_INT2_LINE, // (fff8)
+ M740_INT3_LINE, // (fff6)
+ M740_INT4_LINE, // (fff4)
+ M740_INT5_LINE, // (fff2)
+ M740_INT6_LINE, // (fff0)
+ M740_INT7_LINE, // (ffee)
+ M740_INT8_LINE, // (ffec)
+ M740_INT9_LINE, // (ffea)
M740_INT10_LINE, // (ffe8)
M740_INT11_LINE, // (ffe6)
M740_INT12_LINE, // (ffe4)
@@ -68,14 +68,14 @@ public:
m740_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
m740_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
- virtual void device_reset();
+ virtual void device_reset();
- static const disasm_entry disasm_entries[0x100];
+ static const disasm_entry disasm_entries[0x100];
- virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
- virtual void do_exec_full();
- virtual void do_exec_partial();
- virtual void execute_set_input(int inputnum, int state);
+ virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
+ virtual void do_exec_full();
+ virtual void do_exec_partial();
+ virtual void execute_set_input(int inputnum, int state);
protected:
#define O(o) void o ## _full(); void o ## _partial()
diff --git a/src/emu/cpu/m6502/om740.lst b/src/emu/cpu/m6502/om740.lst
index 49f9c4a782b..048fa1304ea 100644
--- a/src/emu/cpu/m6502/om740.lst
+++ b/src/emu/cpu/m6502/om740.lst
@@ -143,4 +143,3 @@ brk740_imp
P |= F_I; // Do *not* move after the prefetch
prefetch();
inst_state = -1;
-
diff --git a/src/emu/cpu/m6809/hd6309.c b/src/emu/cpu/m6809/hd6309.c
index bc7362b5721..5fbb2a9fa78 100644
--- a/src/emu/cpu/m6809/hd6309.c
+++ b/src/emu/cpu/m6809/hd6309.c
@@ -26,7 +26,7 @@
History:
March 2013 NPW:
- Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
+ Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
070614 ZV:
Fixed N flag setting in DIV overflow
@@ -140,12 +140,12 @@ void hd6309_device::device_start()
super::device_start();
// register our state for the debugger
- state_add(HD6309_E, "E", m_w.b.h).mask(0xff);
- state_add(HD6309_F, "F", m_w.b.l).mask(0xff);
- state_add(HD6309_W, "W", m_w.w).mask(0xffff);
- state_add(HD6309_V, "V", m_w.w).mask(0xffff);
- state_add(HD6309_MD, "MD", m_md).mask(0xff);
-
+ state_add(HD6309_E, "E", m_w.b.h).mask(0xff);
+ state_add(HD6309_F, "F", m_w.b.l).mask(0xff);
+ state_add(HD6309_W, "W", m_w.w).mask(0xffff);
+ state_add(HD6309_V, "V", m_w.w).mask(0xffff);
+ state_add(HD6309_MD, "MD", m_md).mask(0xff);
+
// initialize variables
m_w.w = 0x0000;
m_v.w = 0x0000;
@@ -220,13 +220,13 @@ ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand()
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: return read_memory(m_ea.w);
- case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
- case ADDRESSING_MODE_REGISTER_A: return m_d.b.h;
- case ADDRESSING_MODE_REGISTER_B: return m_d.b.l;
- case ADDRESSING_MODE_REGISTER_E: return m_w.b.h;
- case ADDRESSING_MODE_REGISTER_F: return m_w.b.l;
- default: fatalerror("Unexpected"); return 0x00;
+ case ADDRESSING_MODE_EA: return read_memory(m_ea.w);
+ case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
+ case ADDRESSING_MODE_REGISTER_A: return m_d.b.h;
+ case ADDRESSING_MODE_REGISTER_B: return m_d.b.l;
+ case ADDRESSING_MODE_REGISTER_E: return m_w.b.h;
+ case ADDRESSING_MODE_REGISTER_F: return m_w.b.l;
+ default: fatalerror("Unexpected"); return 0x00;
}
}
@@ -239,18 +239,18 @@ ATTR_FORCE_INLINE UINT8 hd6309_device::read_operand(int ordinal)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
- case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
- case ADDRESSING_MODE_REGISTER_D: return (ordinal & 1) ? m_d.b.l : m_d.b.h;
- case ADDRESSING_MODE_REGISTER_W: return (ordinal & 1) ? m_w.b.l : m_w.b.h;
- case ADDRESSING_MODE_REGISTER_X: return (ordinal & 1) ? m_x.b.l : m_x.b.h;
- case ADDRESSING_MODE_REGISTER_Y: return (ordinal & 1) ? m_y.b.l : m_y.b.h;
- case ADDRESSING_MODE_REGISTER_U: return (ordinal & 1) ? m_u.b.l : m_u.b.h;
- case ADDRESSING_MODE_REGISTER_S: return (ordinal & 1) ? m_s.b.l : m_s.b.h;
- case ADDRESSING_MODE_REGISTER_V: return (ordinal & 1) ? m_v.b.l : m_v.b.h;
- case ADDRESSING_MODE_REGISTER_PC: return (ordinal & 1) ? m_pc.b.l : m_pc.b.h;
- case ADDRESSING_MODE_ZERO: return 0x00;
- default: fatalerror("Unexpected"); return 0x00;
+ case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
+ case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
+ case ADDRESSING_MODE_REGISTER_D: return (ordinal & 1) ? m_d.b.l : m_d.b.h;
+ case ADDRESSING_MODE_REGISTER_W: return (ordinal & 1) ? m_w.b.l : m_w.b.h;
+ case ADDRESSING_MODE_REGISTER_X: return (ordinal & 1) ? m_x.b.l : m_x.b.h;
+ case ADDRESSING_MODE_REGISTER_Y: return (ordinal & 1) ? m_y.b.l : m_y.b.h;
+ case ADDRESSING_MODE_REGISTER_U: return (ordinal & 1) ? m_u.b.l : m_u.b.h;
+ case ADDRESSING_MODE_REGISTER_S: return (ordinal & 1) ? m_s.b.l : m_s.b.h;
+ case ADDRESSING_MODE_REGISTER_V: return (ordinal & 1) ? m_v.b.l : m_v.b.h;
+ case ADDRESSING_MODE_REGISTER_PC: return (ordinal & 1) ? m_pc.b.l : m_pc.b.h;
+ case ADDRESSING_MODE_ZERO: return 0x00;
+ default: fatalerror("Unexpected"); return 0x00;
}
}
@@ -263,13 +263,13 @@ ATTR_FORCE_INLINE void hd6309_device::write_operand(UINT8 data)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: write_memory(m_ea.w, data); break;
- case ADDRESSING_MODE_REGISTER_A: m_d.b.h = data; break;
- case ADDRESSING_MODE_REGISTER_B: m_d.b.l = data; break;
- case ADDRESSING_MODE_REGISTER_E: m_w.b.h = data; break;
- case ADDRESSING_MODE_REGISTER_F: m_w.b.l = data; break;
- case ADDRESSING_MODE_ZERO: break;
- default: fatalerror("Unexpected"); break;
+ case ADDRESSING_MODE_EA: write_memory(m_ea.w, data); break;
+ case ADDRESSING_MODE_REGISTER_A: m_d.b.h = data; break;
+ case ADDRESSING_MODE_REGISTER_B: m_d.b.l = data; break;
+ case ADDRESSING_MODE_REGISTER_E: m_w.b.h = data; break;
+ case ADDRESSING_MODE_REGISTER_F: m_w.b.l = data; break;
+ case ADDRESSING_MODE_ZERO: break;
+ default: fatalerror("Unexpected"); break;
}
}
@@ -282,17 +282,17 @@ ATTR_FORCE_INLINE void hd6309_device::write_operand(int ordinal, UINT8 data)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
- case ADDRESSING_MODE_REGISTER_D: *((ordinal & 1) ? &m_d.b.l : &m_d.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_W: *((ordinal & 1) ? &m_w.b.l : &m_w.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_X: *((ordinal & 1) ? &m_x.b.l : &m_x.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_Y: *((ordinal & 1) ? &m_y.b.l : &m_y.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_U: *((ordinal & 1) ? &m_u.b.l : &m_u.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_S: *((ordinal & 1) ? &m_s.b.l : &m_s.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_V: *((ordinal & 1) ? &m_v.b.l : &m_v.b.h) = data; break;
- case ADDRESSING_MODE_REGISTER_PC: *((ordinal & 1) ? &m_pc.b.l : &m_pc.b.h) = data; break;
- case ADDRESSING_MODE_ZERO: break;
- default: fatalerror("Unexpected"); break;
+ case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
+ case ADDRESSING_MODE_REGISTER_D: *((ordinal & 1) ? &m_d.b.l : &m_d.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_W: *((ordinal & 1) ? &m_w.b.l : &m_w.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_X: *((ordinal & 1) ? &m_x.b.l : &m_x.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_Y: *((ordinal & 1) ? &m_y.b.l : &m_y.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_U: *((ordinal & 1) ? &m_u.b.l : &m_u.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_S: *((ordinal & 1) ? &m_s.b.l : &m_s.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_V: *((ordinal & 1) ? &m_v.b.l : &m_v.b.h) = data; break;
+ case ADDRESSING_MODE_REGISTER_PC: *((ordinal & 1) ? &m_pc.b.l : &m_pc.b.h) = data; break;
+ case ADDRESSING_MODE_ZERO: break;
+ default: fatalerror("Unexpected"); break;
}
}
@@ -305,10 +305,10 @@ ATTR_FORCE_INLINE UINT8 &hd6309_device::bittest_register()
{
switch(m_temp_im & 0xC0)
{
- case 0x00: return m_cc;
- case 0x40: return m_d.b.h;
- case 0x80: return m_d.b.l;
- default: return m_temp.b.l;
+ case 0x00: return m_cc;
+ case 0x40: return m_d.b.h;
+ case 0x80: return m_d.b.l;
+ default: return m_temp.b.l;
}
}
@@ -357,22 +357,22 @@ ATTR_FORCE_INLINE m6809_base_device::exgtfr_register hd6309_device::read_exgtfr_
switch(reg & 0x0F)
{
- case 0: value = m_d.w; break; // D
- case 1: value = m_x.w; break; // X
- case 2: value = m_y.w; break; // Y
- case 3: value = m_u.w; break; // U
- case 4: value = m_s.w; break; // S
- case 5: value = m_pc.w; break; // PC
- case 6: value = m_w.w; break; // W
- case 7: value = m_v.w; break; // V
- case 8: value = ((UINT16) m_d.b.h) << 8 | m_d.b.h; break; // A
- case 9: value = ((UINT16) m_d.b.l) << 8 | m_d.b.l; break; // B
- case 10: value = ((UINT16) m_cc) << 8 | m_cc; break; // CC
- case 11: value = ((UINT16) m_dp) << 8 | m_dp; break; // DP
- case 12: value = 0; break; // 0
- case 13: value = 0; break; // 0
- case 14: value = ((UINT16) m_w.b.h) << 8 | m_w.b.h; break; // E
- case 15: value = ((UINT16) m_w.b.l) << 8 | m_w.b.l; break; // F
+ case 0: value = m_d.w; break; // D
+ case 1: value = m_x.w; break; // X
+ case 2: value = m_y.w; break; // Y
+ case 3: value = m_u.w; break; // U
+ case 4: value = m_s.w; break; // S
+ case 5: value = m_pc.w; break; // PC
+ case 6: value = m_w.w; break; // W
+ case 7: value = m_v.w; break; // V
+ case 8: value = ((UINT16) m_d.b.h) << 8 | m_d.b.h; break; // A
+ case 9: value = ((UINT16) m_d.b.l) << 8 | m_d.b.l; break; // B
+ case 10: value = ((UINT16) m_cc) << 8 | m_cc; break; // CC
+ case 11: value = ((UINT16) m_dp) << 8 | m_dp; break; // DP
+ case 12: value = 0; break; // 0
+ case 13: value = 0; break; // 0
+ case 14: value = ((UINT16) m_w.b.h) << 8 | m_w.b.h; break; // E
+ case 15: value = ((UINT16) m_w.b.l) << 8 | m_w.b.l; break; // F
default:
fatalerror("Should not reach here");
break;
@@ -394,22 +394,22 @@ ATTR_FORCE_INLINE void hd6309_device::write_exgtfr_register(UINT8 reg, m6809_bas
{
switch(reg & 0x0F)
{
- case 0: m_d.w = value.word_value; break; // D
- case 1: m_x.w = value.word_value; break; // X
- case 2: m_y.w = value.word_value; break; // Y
- case 3: m_u.w = value.word_value; break; // U
- case 4: m_s.w = value.word_value; break; // S
- case 5: m_pc.w = value.word_value; break; // PC
- case 6: m_w.w = value.word_value; break; // W
- case 7: m_v.w = value.word_value; break; // V
- case 8: m_d.b.h = (UINT8) (value.word_value >> 8); break; // A
- case 9: m_d.b.l = (UINT8) (value.word_value >> 0); break; // B
- case 10: m_cc = (UINT8) (value.word_value >> 0); break; // CC
- case 11: m_dp = (UINT8) (value.word_value >> 8); break; // DP
- case 12: break; // 0
- case 13: break; // 0
- case 14: m_w.b.h = (UINT8) (value.word_value >> 8); break; // E
- case 15: m_w.b.l = (UINT8) (value.word_value >> 0); break; // F
+ case 0: m_d.w = value.word_value; break; // D
+ case 1: m_x.w = value.word_value; break; // X
+ case 2: m_y.w = value.word_value; break; // Y
+ case 3: m_u.w = value.word_value; break; // U
+ case 4: m_s.w = value.word_value; break; // S
+ case 5: m_pc.w = value.word_value; break; // PC
+ case 6: m_w.w = value.word_value; break; // W
+ case 7: m_v.w = value.word_value; break; // V
+ case 8: m_d.b.h = (UINT8) (value.word_value >> 8); break; // A
+ case 9: m_d.b.l = (UINT8) (value.word_value >> 0); break; // B
+ case 10: m_cc = (UINT8) (value.word_value >> 0); break; // CC
+ case 11: m_dp = (UINT8) (value.word_value >> 8); break; // DP
+ case 12: break; // 0
+ case 13: break; // 0
+ case 14: m_w.b.h = (UINT8) (value.word_value >> 8); break; // E
+ case 15: m_w.b.l = (UINT8) (value.word_value >> 0); break; // F
default:
fatalerror("Should not reach here");
break;
@@ -428,22 +428,22 @@ ATTR_FORCE_INLINE bool hd6309_device::tfr_read(UINT8 opcode, UINT8 arg, UINT8 &d
switch(arg & 0xF0)
{
- case 0x00: reg = &m_d; break;
- case 0x10: reg = &m_x; break;
- case 0x20: reg = &m_y; break;
- case 0x30: reg = &m_u; break;
- case 0x40: reg = &m_s; break;
- default: return false;
+ case 0x00: reg = &m_d; break;
+ case 0x10: reg = &m_x; break;
+ case 0x20: reg = &m_y; break;
+ case 0x30: reg = &m_u; break;
+ case 0x40: reg = &m_s; break;
+ default: return false;
}
data = read_memory(reg->w);
switch(opcode & 0x03)
{
- case 0x00: reg->w++; break; // TFM R0+,R1+
- case 0x01: reg->w--; break; // TFM R0-,R1-
- case 0x02: reg->w++; break; // TFM R0+,R1
- case 0x03: break; // TFM R0,R1+
+ case 0x00: reg->w++; break; // TFM R0+,R1+
+ case 0x01: reg->w--; break; // TFM R0-,R1-
+ case 0x02: reg->w++; break; // TFM R0+,R1
+ case 0x03: break; // TFM R0,R1+
}
return true;
@@ -461,22 +461,22 @@ ATTR_FORCE_INLINE bool hd6309_device::tfr_write(UINT8 opcode, UINT8 arg, UINT8 d
switch(arg & 0x0F)
{
- case 0x00: reg = &m_d; break;
- case 0x01: reg = &m_x; break;
- case 0x02: reg = &m_y; break;
- case 0x03: reg = &m_u; break;
- case 0x04: reg = &m_s; break;
- default: return false;
+ case 0x00: reg = &m_d; break;
+ case 0x01: reg = &m_x; break;
+ case 0x02: reg = &m_y; break;
+ case 0x03: reg = &m_u; break;
+ case 0x04: reg = &m_s; break;
+ default: return false;
}
write_memory(reg->w, data);
switch(opcode & 0x03)
{
- case 0x00: reg->w++; break; // TFM R0+,R1+
- case 0x01: reg->w--; break; // TFM R0-,R1-
- case 0x02: break; // TFM R0+,R1
- case 0x03: reg->w++; break; // TFM R0,R1+
+ case 0x00: reg->w++; break; // TFM R0+,R1+
+ case 0x01: reg->w--; break; // TFM R0-,R1-
+ case 0x02: break; // TFM R0+,R1
+ case 0x03: reg->w++; break; // TFM R0,R1+
}
return true;
@@ -501,22 +501,22 @@ void hd6309_device::register_register_op()
// set destination
switch((operand >> 0) & 0x0F)
{
- case 0: set_regop16(m_d); break; // D
- case 1: set_regop16(m_x); break; // X
- case 2: set_regop16(m_y); break; // Y
- case 3: set_regop16(m_u); break; // U
- case 4: set_regop16(m_s); break; // S
- case 5: set_regop16(m_pc); break; // PC
- case 6: set_regop16(m_w); break; // W
- case 7: set_regop16(m_v); break; // V
- case 8: if (promote) set_regop16(m_d); else set_regop8(m_d.b.h); break; // A
- case 9: if (promote) set_regop16(m_d); else set_regop8(m_d.b.l); break; // B
- case 10: if (promote) set_regop16(m_temp); else set_regop8(m_cc); break; // CC
- case 11: if (promote) set_regop16(m_temp); else set_regop8(m_dp); break; // DP
- case 12: if (promote) set_regop16(m_temp); else set_regop8(m_temp.b.l); break; // 0
- case 13: if (promote) set_regop16(m_temp); else set_regop8(m_temp.b.l); break; // 0
- case 14: if (promote) set_regop16(m_w); else set_regop8(m_w.b.h); break; // E
- case 15: if (promote) set_regop16(m_w); else set_regop8(m_w.b.l); break; // F
+ case 0: set_regop16(m_d); break; // D
+ case 1: set_regop16(m_x); break; // X
+ case 2: set_regop16(m_y); break; // Y
+ case 3: set_regop16(m_u); break; // U
+ case 4: set_regop16(m_s); break; // S
+ case 5: set_regop16(m_pc); break; // PC
+ case 6: set_regop16(m_w); break; // W
+ case 7: set_regop16(m_v); break; // V
+ case 8: if (promote) set_regop16(m_d); else set_regop8(m_d.b.h); break; // A
+ case 9: if (promote) set_regop16(m_d); else set_regop8(m_d.b.l); break; // B
+ case 10: if (promote) set_regop16(m_temp); else set_regop8(m_cc); break; // CC
+ case 11: if (promote) set_regop16(m_temp); else set_regop8(m_dp); break; // DP
+ case 12: if (promote) set_regop16(m_temp); else set_regop8(m_temp.b.l); break; // 0
+ case 13: if (promote) set_regop16(m_temp); else set_regop8(m_temp.b.l); break; // 0
+ case 14: if (promote) set_regop16(m_w); else set_regop8(m_w.b.h); break; // E
+ case 15: if (promote) set_regop16(m_w); else set_regop8(m_w.b.l); break; // F
default:
fatalerror("Should not reach here");
break;
@@ -525,22 +525,22 @@ void hd6309_device::register_register_op()
// set source
switch((operand >> 4) & 0x0F)
{
- case 0: m_addressing_mode = ADDRESSING_MODE_REGISTER_D; break; // D
- case 1: m_addressing_mode = ADDRESSING_MODE_REGISTER_X; break; // X
- case 2: m_addressing_mode = ADDRESSING_MODE_REGISTER_Y; break; // Y
- case 3: m_addressing_mode = ADDRESSING_MODE_REGISTER_U; break; // U
- case 4: m_addressing_mode = ADDRESSING_MODE_REGISTER_S; break; // S
- case 5: m_addressing_mode = ADDRESSING_MODE_REGISTER_PC; break; // PC
- case 6: m_addressing_mode = ADDRESSING_MODE_REGISTER_W; break; // W
- case 7: m_addressing_mode = ADDRESSING_MODE_REGISTER_V; break; // V
- case 8: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_D : ADDRESSING_MODE_REGISTER_A; break; // A
- case 9: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_D : ADDRESSING_MODE_REGISTER_B; break; // B
- case 10: m_addressing_mode = promote ? ADDRESSING_MODE_ZERO : ADDRESSING_MODE_REGISTER_CC; break; // CC
- case 11: m_addressing_mode = promote ? ADDRESSING_MODE_ZERO : ADDRESSING_MODE_REGISTER_DP; break; // DP
- case 12: m_addressing_mode = ADDRESSING_MODE_ZERO; break; // 0
- case 13: m_addressing_mode = ADDRESSING_MODE_ZERO; break; // 0
- case 14: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_W : ADDRESSING_MODE_REGISTER_E; break; // E
- case 15: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_W : ADDRESSING_MODE_REGISTER_F; break; // F
+ case 0: m_addressing_mode = ADDRESSING_MODE_REGISTER_D; break; // D
+ case 1: m_addressing_mode = ADDRESSING_MODE_REGISTER_X; break; // X
+ case 2: m_addressing_mode = ADDRESSING_MODE_REGISTER_Y; break; // Y
+ case 3: m_addressing_mode = ADDRESSING_MODE_REGISTER_U; break; // U
+ case 4: m_addressing_mode = ADDRESSING_MODE_REGISTER_S; break; // S
+ case 5: m_addressing_mode = ADDRESSING_MODE_REGISTER_PC; break; // PC
+ case 6: m_addressing_mode = ADDRESSING_MODE_REGISTER_W; break; // W
+ case 7: m_addressing_mode = ADDRESSING_MODE_REGISTER_V; break; // V
+ case 8: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_D : ADDRESSING_MODE_REGISTER_A; break; // A
+ case 9: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_D : ADDRESSING_MODE_REGISTER_B; break; // B
+ case 10: m_addressing_mode = promote ? ADDRESSING_MODE_ZERO : ADDRESSING_MODE_REGISTER_CC; break; // CC
+ case 11: m_addressing_mode = promote ? ADDRESSING_MODE_ZERO : ADDRESSING_MODE_REGISTER_DP; break; // DP
+ case 12: m_addressing_mode = ADDRESSING_MODE_ZERO; break; // 0
+ case 13: m_addressing_mode = ADDRESSING_MODE_ZERO; break; // 0
+ case 14: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_W : ADDRESSING_MODE_REGISTER_E; break; // E
+ case 15: m_addressing_mode = promote ? ADDRESSING_MODE_REGISTER_W : ADDRESSING_MODE_REGISTER_F; break; // F
default:
fatalerror("Should not reach here");
break;
@@ -623,7 +623,7 @@ bool hd6309_device::divq()
// soft overflow
m_cc |= CC_V;
- if ((result > 65536 ) || (result < -65535 ))
+ if ((result > 65536 ) || (result < -65535 ))
{
// hard overflow - division is aborted
if (old_q < 0)
diff --git a/src/emu/cpu/m6809/hd6309.h b/src/emu/cpu/m6809/hd6309.h
index f2deda9c24f..121f1209275 100644
--- a/src/emu/cpu/m6809/hd6309.h
+++ b/src/emu/cpu/m6809/hd6309.h
@@ -2,7 +2,7 @@
hd6309.h
- Portable Hitachi 6309 emulator
+ Portable Hitachi 6309 emulator
**********************************************************************/
@@ -67,14 +67,14 @@ private:
{
VECTOR_ILLEGAL = 0xFFF0
};
-
+
// CPU registers
- PAIR16 m_w;
- PAIR16 m_v;
- UINT8 m_md;
-
+ PAIR16 m_w;
+ PAIR16 m_v;
+ UINT8 m_md;
+
// other state
- UINT8 m_temp_im;
+ UINT8 m_temp_im;
// operand reading/writing
UINT8 read_operand();
@@ -83,8 +83,8 @@ private:
void write_operand(int ordinal, UINT8 data);
// interrupt registers
- bool firq_saves_entire_state() { return m_md & 0x02; }
- UINT16 entire_state_registers() { return hd6309_native_mode() ? 0x3FF : 0xFF; }
+ bool firq_saves_entire_state() { return m_md & 0x02; }
+ UINT16 entire_state_registers() { return hd6309_native_mode() ? 0x3FF : 0xFF; }
// bit tests
UINT8 &bittest_register();
@@ -102,16 +102,16 @@ private:
void put_q(UINT32 value);
// miscellaneous
- void set_e() { m_addressing_mode = ADDRESSING_MODE_REGISTER_E; }
- void set_f() { m_addressing_mode = ADDRESSING_MODE_REGISTER_F; }
- void set_w() { m_addressing_mode = ADDRESSING_MODE_REGISTER_W; }
+ void set_e() { m_addressing_mode = ADDRESSING_MODE_REGISTER_E; }
+ void set_f() { m_addressing_mode = ADDRESSING_MODE_REGISTER_F; }
+ void set_w() { m_addressing_mode = ADDRESSING_MODE_REGISTER_W; }
exgtfr_register read_exgtfr_register(UINT8 reg);
void write_exgtfr_register(UINT8 reg, exgtfr_register value);
bool tfr_read(UINT8 opcode, UINT8 arg, UINT8 &data);
bool tfr_write(UINT8 opcode, UINT8 arg, UINT8 data);
- bool add8_sets_h() { return (m_opcode & 0xFE) != 0x30; }
+ bool add8_sets_h() { return (m_opcode & 0xFE) != 0x30; }
void register_register_op();
- bool hd6309_native_mode() { return m_md & 0x01; }
+ bool hd6309_native_mode() { return m_md & 0x01; }
void execute_one();
};
@@ -140,4 +140,3 @@ enum
#define HD6309_FIRQ_LINE 1 /* FIRQ line number */
#endif // __HD6309_H__
-
diff --git a/src/emu/cpu/m6809/konami.c b/src/emu/cpu/m6809/konami.c
index 01abfa12cbf..25e00f8787f 100644
--- a/src/emu/cpu/m6809/konami.c
+++ b/src/emu/cpu/m6809/konami.c
@@ -2,7 +2,7 @@
konami.c
- Portable Konami cpu emulator
+ Portable Konami cpu emulator
Copyright Nicola Salmoria and the MAME Team
@@ -27,19 +27,19 @@
History:
March 2013 NPW:
- Rewrite of 6809/6309/Konami CPU; overall core is now unified and
- supports mid-instruction timings.
+ Rewrite of 6809/6309/Konami CPU; overall core is now unified and
+ supports mid-instruction timings.
- Some of the instruction timings have changed with the new core; the
- old core had some nonsensical timings. For example (from scontra):
-
- 819A 3A 07 1F 8C STA $1f8C
+ Some of the instruction timings have changed with the new core; the
+ old core had some nonsensical timings. For example (from scontra):
- Under the old core, this took four clock cycles, which is dubious
- because this instruction would have to do four opcode reads and one
- write. OGalibert says that the current timings are just a guess and
- nobody has done precise readings, so I'm replacing the old guesses
- with new guesses.
+ 819A 3A 07 1F 8C STA $1f8C
+
+ Under the old core, this took four clock cycles, which is dubious
+ because this instruction would have to do four opcode reads and one
+ write. OGalibert says that the current timings are just a guess and
+ nobody has done precise readings, so I'm replacing the old guesses
+ with new guesses.
991022 HJB:
Tried to improve speed: Using bit7 of cycles1 as flag for multi
@@ -133,10 +133,10 @@ inline ATTR_FORCE_INLINE UINT8 konami_cpu_device::read_operand(int ordinal)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
- case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
- case ADDRESSING_MODE_REGISTER_D: return (ordinal & 1) ? m_d.b.l : m_d.b.h;
- default: fatalerror("Unexpected"); return 0x00;
+ case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
+ case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
+ case ADDRESSING_MODE_REGISTER_D: return (ordinal & 1) ? m_d.b.l : m_d.b.h;
+ default: fatalerror("Unexpected"); return 0x00;
}
}
@@ -160,10 +160,10 @@ ATTR_FORCE_INLINE void konami_cpu_device::write_operand(int ordinal, UINT8 data)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
- case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
- case ADDRESSING_MODE_REGISTER_D: *((ordinal & 1) ? &m_d.b.l : &m_d.b.h) = data; break;
- default: fatalerror("Unexpected"); break;
+ case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
+ case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
+ case ADDRESSING_MODE_REGISTER_D: *((ordinal & 1) ? &m_d.b.l : &m_d.b.h) = data; break;
+ default: fatalerror("Unexpected"); break;
}
}
@@ -176,11 +176,11 @@ ATTR_FORCE_INLINE UINT16 &konami_cpu_device::ireg()
{
switch(m_opcode & 0x70)
{
- case 0x20: return m_x.w;
- case 0x30: return m_y.w;
- case 0x50: return m_u.w;
- case 0x60: return m_s.w;
- case 0x70: return m_pc.w;
+ case 0x20: return m_x.w;
+ case 0x30: return m_y.w;
+ case 0x50: return m_u.w;
+ case 0x60: return m_s.w;
+ case 0x70: return m_pc.w;
default:
fatalerror("Should not get here");
return m_x.w;
@@ -199,12 +199,12 @@ ATTR_FORCE_INLINE m6809_base_device::exgtfr_register konami_cpu_device::read_exg
switch(reg & 0x07)
{
- case 0: result.word_value = m_d.b.h; break; // A
- case 1: result.word_value = m_d.b.l; break; // B
- case 2: result.word_value = m_x.w; break; // X
- case 3: result.word_value = m_y.w; break; // Y
- case 4: result.word_value = m_s.w; break; // S
- case 5: result.word_value = m_u.w; break; // U
+ case 0: result.word_value = m_d.b.h; break; // A
+ case 1: result.word_value = m_d.b.l; break; // B
+ case 2: result.word_value = m_x.w; break; // X
+ case 3: result.word_value = m_y.w; break; // Y
+ case 4: result.word_value = m_s.w; break; // S
+ case 5: result.word_value = m_u.w; break; // U
}
result.byte_value = (UINT8) result.word_value;
return result;
@@ -219,12 +219,12 @@ ATTR_FORCE_INLINE void konami_cpu_device::write_exgtfr_register(UINT8 reg, m6809
{
switch(reg & 0x07)
{
- case 0: m_d.b.h = value.byte_value; break; // A
- case 1: m_d.b.l = value.byte_value; break; // B
- case 2: m_x.w = value.word_value; break; // X
- case 3: m_y.w = value.word_value; break; // Y
- case 4: m_s.w = value.word_value; break; // S
- case 5: m_u.w = value.word_value; break; // U
+ case 0: m_d.b.h = value.byte_value; break; // A
+ case 1: m_d.b.l = value.byte_value; break; // B
+ case 2: m_x.w = value.word_value; break; // X
+ case 3: m_y.w = value.word_value; break; // Y
+ case 4: m_s.w = value.word_value; break; // S
+ case 5: m_u.w = value.word_value; break; // U
}
}
diff --git a/src/emu/cpu/m6809/konami.h b/src/emu/cpu/m6809/konami.h
index 200762ab8e7..d8f6c006578 100644
--- a/src/emu/cpu/m6809/konami.h
+++ b/src/emu/cpu/m6809/konami.h
@@ -2,7 +2,7 @@
konami.h
- Portable Konami CPU emulator
+ Portable Konami CPU emulator
**********************************************************************/
diff --git a/src/emu/cpu/m6809/m6809.c b/src/emu/cpu/m6809/m6809.c
index 8f8d7c736c8..b7d1fa46142 100644
--- a/src/emu/cpu/m6809/m6809.c
+++ b/src/emu/cpu/m6809/m6809.c
@@ -21,7 +21,7 @@
History:
March 2013 NPW:
- Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
+ Rewrite of 6809/6309/Konami CPU; attempted to make cycle exact.
991026 HJB:
Fixed missing calls to cpu_changepc() for the TFR and EXG ocpodes.
@@ -84,7 +84,7 @@ March 2013 NPW:
// PARAMETERS
//**************************************************************************
-#define LOG_INTERRUPTS 0
+#define LOG_INTERRUPTS 0
// turn off 'unreferenced label' errors
#ifdef __GNUC__
@@ -150,18 +150,18 @@ void m6809_base_device::device_start()
// register our state for the debugger
astring tempstr;
state_add(STATE_GENPC, "GENPC", m_pc.w).noshow();
- state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc.w).noshow();
+ state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc.w).noshow();
state_add(STATE_GENFLAGS, "GENFLAGS", m_cc).callimport().callexport().formatstr("%8s").noshow();
- state_add(M6809_PC, "PC", m_pc.w).mask(0xffff);
- state_add(M6809_S, "S", m_s.w).mask(0xffff);
+ state_add(M6809_PC, "PC", m_pc.w).mask(0xffff);
+ state_add(M6809_S, "S", m_s.w).mask(0xffff);
state_add(M6809_CC, "CC", m_cc).mask(0xff);
- state_add(M6809_U, "U", m_u.w).mask(0xffff);
- state_add(M6809_A, "A", m_d.b.h).mask(0xff);
- state_add(M6809_B, "B", m_d.b.l).mask(0xff);
- state_add(M6809_X, "X", m_x.w).mask(0xffff);
- state_add(M6809_Y, "Y", m_y.w).mask(0xffff);
+ state_add(M6809_U, "U", m_u.w).mask(0xffff);
+ state_add(M6809_A, "A", m_d.b.h).mask(0xff);
+ state_add(M6809_B, "B", m_d.b.l).mask(0xff);
+ state_add(M6809_X, "X", m_x.w).mask(0xffff);
+ state_add(M6809_Y, "Y", m_y.w).mask(0xffff);
state_add(M6809_DP, "DP", m_dp).mask(0xff);
-
+
// initialize variables
m_cc = 0;
m_pc.w = 0;
@@ -215,10 +215,10 @@ void m6809_base_device::device_reset()
m_irq_line = false;
m_lds_encountered = false;
- m_dp = 0x00; // reset direct page register
+ m_dp = 0x00; // reset direct page register
- m_cc |= CC_I; // IRQ disabled
- m_cc |= CC_F; // FIRQ disabled
+ m_cc |= CC_I; // IRQ disabled
+ m_cc |= CC_F; // FIRQ disabled
m_pc.b.h = m_program->read_byte(VECTOR_RESET_FFFE + 0);
m_pc.b.l = m_program->read_byte(VECTOR_RESET_FFFE + 1);
@@ -462,10 +462,10 @@ const char *m6809_base_device::inputnum_string(int inputnum)
{
switch(inputnum)
{
- case INPUT_LINE_NMI: return "NMI";
- case M6809_FIRQ_LINE: return "FIRQ";
- case M6809_IRQ_LINE: return "IRQ";
- default: return "???";
+ case INPUT_LINE_NMI: return "NMI";
+ case M6809_FIRQ_LINE: return "FIRQ";
+ case M6809_IRQ_LINE: return "IRQ";
+ default: return "???";
}
}
@@ -482,16 +482,16 @@ ATTR_FORCE_INLINE m6809_base_device::exgtfr_register m6809_base_device::read_exg
switch(reg & 0x0F)
{
- case 0: result.word_value = m_d.w; break; // D
- case 1: result.word_value = m_x.w; break; // X
- case 2: result.word_value = m_y.w; break; // Y
- case 3: result.word_value = m_u.w; break; // U
- case 4: result.word_value = m_s.w; break; // S
- case 5: result.word_value = m_pc.w; break; // PC
- case 8: result.byte_value = m_d.b.h; break; // A
- case 9: result.byte_value = m_d.b.l; break; // B
- case 10: result.byte_value = m_cc; break; // CC
- case 11: result.byte_value = m_dp; break; // DP
+ case 0: result.word_value = m_d.w; break; // D
+ case 1: result.word_value = m_x.w; break; // X
+ case 2: result.word_value = m_y.w; break; // Y
+ case 3: result.word_value = m_u.w; break; // U
+ case 4: result.word_value = m_s.w; break; // S
+ case 5: result.word_value = m_pc.w; break; // PC
+ case 8: result.byte_value = m_d.b.h; break; // A
+ case 9: result.byte_value = m_d.b.l; break; // B
+ case 10: result.byte_value = m_cc; break; // CC
+ case 11: result.byte_value = m_dp; break; // DP
}
return result;
}
@@ -505,23 +505,23 @@ ATTR_FORCE_INLINE void m6809_base_device::write_exgtfr_register(UINT8 reg, m6809
{
switch(reg & 0x0F)
{
- case 0: m_d.w = value.word_value; break; // D
- case 1: m_x.w = value.word_value; break; // X
- case 2: m_y.w = value.word_value; break; // Y
- case 3: m_u.w = value.word_value; break; // U
- case 4: m_s.w = value.word_value; break; // S
- case 5: m_pc.w = value.word_value; break; // PC
- case 8: m_d.b.h = value.byte_value; break; // A
- case 9: m_d.b.l = value.byte_value; break; // B
- case 10: m_cc = value.byte_value; break; // CC
- case 11: m_dp = value.byte_value; break; // DP
+ case 0: m_d.w = value.word_value; break; // D
+ case 1: m_x.w = value.word_value; break; // X
+ case 2: m_y.w = value.word_value; break; // Y
+ case 3: m_u.w = value.word_value; break; // U
+ case 4: m_s.w = value.word_value; break; // S
+ case 5: m_pc.w = value.word_value; break; // PC
+ case 8: m_d.b.h = value.byte_value; break; // A
+ case 9: m_d.b.l = value.byte_value; break; // B
+ case 10: m_cc = value.byte_value; break; // CC
+ case 11: m_dp = value.byte_value; break; // DP
}
}
//-------------------------------------------------
// log_illegal - used to log hits to illegal
-// instructions (except for HD6309 which traps)
+// instructions (except for HD6309 which traps)
//-------------------------------------------------
void m6809_base_device::log_illegal()
diff --git a/src/emu/cpu/m6809/m6809.h b/src/emu/cpu/m6809/m6809.h
index d6e7f3c0953..6d806672360 100644
--- a/src/emu/cpu/m6809/m6809.h
+++ b/src/emu/cpu/m6809/m6809.h
@@ -2,7 +2,7 @@
m6809.h
- Portable Motorola 6809 emulator
+ Portable Motorola 6809 emulator
**********************************************************************/
@@ -77,116 +77,116 @@ protected:
// device_state_interface overrides
virtual void state_string_export(const device_state_entry &entry, astring &string);
-
+
// addressing modes
enum
{
- ADDRESSING_MODE_IMMEDIATE = 0,
- ADDRESSING_MODE_EA = 1,
- ADDRESSING_MODE_REGISTER_A = 2,
- ADDRESSING_MODE_REGISTER_B = 3,
+ ADDRESSING_MODE_IMMEDIATE = 0,
+ ADDRESSING_MODE_EA = 1,
+ ADDRESSING_MODE_REGISTER_A = 2,
+ ADDRESSING_MODE_REGISTER_B = 3,
ADDRESSING_MODE_REGISTER_D = 4
};
// register transfer
struct exgtfr_register
{
- UINT8 byte_value;
- UINT16 word_value;
+ UINT8 byte_value;
+ UINT16 word_value;
};
// flag bits in the cc register
enum
{
- CC_C = 0x01, // Carry
- CC_V = 0x02, // Overflow
- CC_Z = 0x04, // Zero
- CC_N = 0x08, // Negative
- CC_I = 0x10, // Inhibit IRQ
- CC_H = 0x20, // Half (auxiliary) carry
- CC_F = 0x40, // Inhibit FIRQ
- CC_E = 0x80 // Entire state pushed
+ CC_C = 0x01, // Carry
+ CC_V = 0x02, // Overflow
+ CC_Z = 0x04, // Zero
+ CC_N = 0x08, // Negative
+ CC_I = 0x10, // Inhibit IRQ
+ CC_H = 0x20, // Half (auxiliary) carry
+ CC_F = 0x40, // Inhibit FIRQ
+ CC_E = 0x80 // Entire state pushed
};
// flag combinations
enum
{
- CC_VC = CC_V | CC_C,
- CC_ZC = CC_Z | CC_C,
- CC_NZ = CC_N | CC_Z,
- CC_NZC = CC_N | CC_Z | CC_C,
- CC_NZV = CC_N | CC_Z | CC_V,
- CC_NZVC = CC_N | CC_Z | CC_V | CC_C,
+ CC_VC = CC_V | CC_C,
+ CC_ZC = CC_Z | CC_C,
+ CC_NZ = CC_N | CC_Z,
+ CC_NZC = CC_N | CC_Z | CC_C,
+ CC_NZV = CC_N | CC_Z | CC_V,
+ CC_NZVC = CC_N | CC_Z | CC_V | CC_C,
CC_HNZVC = CC_H | CC_N | CC_Z | CC_V | CC_C
};
// interrupt vectors
enum
{
- VECTOR_SWI3 = 0xFFF2,
- VECTOR_SWI2 = 0xFFF4,
- VECTOR_FIRQ = 0xFFF6,
- VECTOR_IRQ = 0xFFF8,
- VECTOR_SWI = 0xFFFA,
- VECTOR_NMI = 0xFFFC,
- VECTOR_RESET_FFFE = 0xFFFE
+ VECTOR_SWI3 = 0xFFF2,
+ VECTOR_SWI2 = 0xFFF4,
+ VECTOR_FIRQ = 0xFFF6,
+ VECTOR_IRQ = 0xFFF8,
+ VECTOR_SWI = 0xFFFA,
+ VECTOR_NMI = 0xFFFC,
+ VECTOR_RESET_FFFE = 0xFFFE
};
// CPU registers
- PAIR16 m_pc; // program counter
- PAIR16 m_ppc; // previous program counter
- PAIR16 m_d; // accumulator a and b
- PAIR16 m_x, m_y; // index registers
- PAIR16 m_u, m_s; // stack pointers
- UINT8 m_dp; // direct page register
- UINT8 m_cc;
- PAIR16 m_temp;
- UINT8 m_opcode;
+ PAIR16 m_pc; // program counter
+ PAIR16 m_ppc; // previous program counter
+ PAIR16 m_d; // accumulator a and b
+ PAIR16 m_x, m_y; // index registers
+ PAIR16 m_u, m_s; // stack pointers
+ UINT8 m_dp; // direct page register
+ UINT8 m_cc;
+ PAIR16 m_temp;
+ UINT8 m_opcode;
// other internal state
- bool m_nmi_line;
- bool m_nmi_asserted;
- bool m_firq_line;
- bool m_irq_line;
- bool m_lds_encountered;
- int m_icount;
- int m_addressing_mode;
- PAIR16 m_ea; // effective address
+ bool m_nmi_line;
+ bool m_nmi_asserted;
+ bool m_firq_line;
+ bool m_irq_line;
+ bool m_lds_encountered;
+ int m_icount;
+ int m_addressing_mode;
+ PAIR16 m_ea; // effective address
// eat cycles
- ATTR_FORCE_INLINE void eat(int cycles) { m_icount -= cycles; }
+ ATTR_FORCE_INLINE void eat(int cycles) { m_icount -= cycles; }
void eat_remaining();
// read a byte from given memory location
- ATTR_FORCE_INLINE UINT8 read_memory(UINT16 address) { eat(1); return m_program->read_byte(address); }
+ ATTR_FORCE_INLINE UINT8 read_memory(UINT16 address) { eat(1); return m_program->read_byte(address); }
// write a byte to given memory location
- ATTR_FORCE_INLINE void write_memory(UINT16 address, UINT8 data) { eat(1); m_program->write_byte(address, data); }
+ ATTR_FORCE_INLINE void write_memory(UINT16 address, UINT8 data) { eat(1); m_program->write_byte(address, data); }
// read_opcode() is like read_memory() except it is used for reading opcodes. In the case of a system
- // with memory mapped I/O, this function can be used to greatly speed up emulation.
- ATTR_FORCE_INLINE UINT8 read_opcode(UINT16 address) { eat(1); return m_direct->read_decrypted_byte(address); }
+ // with memory mapped I/O, this function can be used to greatly speed up emulation.
+ ATTR_FORCE_INLINE UINT8 read_opcode(UINT16 address) { eat(1); return m_direct->read_decrypted_byte(address); }
// read_opcode_arg() is identical to read_opcode() except it is used for reading opcode arguments. This
// difference can be used to support systems that use different encoding mechanisms for opcodes
// and opcode arguments.
- ATTR_FORCE_INLINE UINT8 read_opcode_arg(UINT16 address) { eat(1); return m_direct->read_raw_byte(address); }
+ ATTR_FORCE_INLINE UINT8 read_opcode_arg(UINT16 address) { eat(1); return m_direct->read_raw_byte(address); }
// read_opcode() and bump the program counter
- ATTR_FORCE_INLINE UINT8 read_opcode() { return read_opcode(m_pc.w++); }
- ATTR_FORCE_INLINE UINT8 read_opcode_arg() { return read_opcode_arg(m_pc.w++); }
+ ATTR_FORCE_INLINE UINT8 read_opcode() { return read_opcode(m_pc.w++); }
+ ATTR_FORCE_INLINE UINT8 read_opcode_arg() { return read_opcode_arg(m_pc.w++); }
// state stack - implemented as a UINT32
- void push_state(UINT8 state) { m_state = (m_state << 8) | state; }
- UINT8 pop_state() { UINT8 result = (UINT8) m_state; m_state >>= 8; return result; }
- void reset_state() { m_state = 0; }
+ void push_state(UINT8 state) { m_state = (m_state << 8) | state; }
+ UINT8 pop_state() { UINT8 result = (UINT8) m_state; m_state >>= 8; return result; }
+ void reset_state() { m_state = 0; }
// effective address reading/writing
- UINT8 read_ea() { return read_memory(m_ea.w); }
- void write_ea(UINT8 data) { write_memory(m_ea.w, data); }
- void set_ea(UINT16 ea) { m_ea.w = ea; m_addressing_mode = ADDRESSING_MODE_EA; }
- void set_ea_h(UINT8 ea_h) { m_ea.b.h = ea_h; }
- void set_ea_l(UINT8 ea_l) { m_ea.b.l = ea_l; m_addressing_mode = ADDRESSING_MODE_EA; }
+ UINT8 read_ea() { return read_memory(m_ea.w); }
+ void write_ea(UINT8 data) { write_memory(m_ea.w, data); }
+ void set_ea(UINT16 ea) { m_ea.w = ea; m_addressing_mode = ADDRESSING_MODE_EA; }
+ void set_ea_h(UINT8 ea_h) { m_ea.b.h = ea_h; }
+ void set_ea_l(UINT8 ea_l) { m_ea.b.l = ea_l; m_addressing_mode = ADDRESSING_MODE_EA; }
// operand reading/writing
UINT8 read_operand();
@@ -203,20 +203,20 @@ protected:
void mul();
// miscellaneous
- void nop() { }
+ void nop() { }
template<class T> T rotate_right(T value);
template<class T> UINT32 rotate_left(T value);
- void set_a() { m_addressing_mode = ADDRESSING_MODE_REGISTER_A; }
- void set_b() { m_addressing_mode = ADDRESSING_MODE_REGISTER_B; }
- void set_d() { m_addressing_mode = ADDRESSING_MODE_REGISTER_D; }
- void set_imm() { m_addressing_mode = ADDRESSING_MODE_IMMEDIATE; }
- void set_regop8(UINT8 &reg) { m_reg8 = &reg; m_reg16 = NULL; }
- void set_regop16(PAIR16 &reg) { m_reg16 = &reg; m_reg8 = NULL; }
- UINT8 &regop8() { assert(m_reg8 != NULL); return *m_reg8; }
- PAIR16 &regop16() { assert(m_reg16 != NULL); return *m_reg16; }
- bool is_register_register_op_16_bit() { return m_reg16 != NULL; }
- bool add8_sets_h() { return true; }
- bool hd6309_native_mode() { return false; }
+ void set_a() { m_addressing_mode = ADDRESSING_MODE_REGISTER_A; }
+ void set_b() { m_addressing_mode = ADDRESSING_MODE_REGISTER_B; }
+ void set_d() { m_addressing_mode = ADDRESSING_MODE_REGISTER_D; }
+ void set_imm() { m_addressing_mode = ADDRESSING_MODE_IMMEDIATE; }
+ void set_regop8(UINT8 &reg) { m_reg8 = &reg; m_reg16 = NULL; }
+ void set_regop16(PAIR16 &reg) { m_reg16 = &reg; m_reg8 = NULL; }
+ UINT8 &regop8() { assert(m_reg8 != NULL); return *m_reg8; }
+ PAIR16 &regop16() { assert(m_reg16 != NULL); return *m_reg16; }
+ bool is_register_register_op_16_bit() { return m_reg16 != NULL; }
+ bool add8_sets_h() { return true; }
+ bool hd6309_native_mode() { return false; }
// index reg
UINT16 &ireg();
@@ -226,20 +226,20 @@ protected:
template<class T> T set_flags(UINT8 mask, T r);
// branch conditions
- ATTR_FORCE_INLINE bool cond_hi() { return !(m_cc & CC_ZC); } // BHI/BLS
- ATTR_FORCE_INLINE bool cond_cc() { return !(m_cc & CC_C); } // BCC/BCS
- ATTR_FORCE_INLINE bool cond_ne() { return !(m_cc & CC_Z); } // BNE/BEQ
- ATTR_FORCE_INLINE bool cond_vc() { return !(m_cc & CC_V); } // BVC/BVS
- ATTR_FORCE_INLINE bool cond_pl() { return !(m_cc & CC_N); } // BPL/BMI
- ATTR_FORCE_INLINE bool cond_ge() { return (m_cc & CC_N ? true : false) == (m_cc & CC_V ? true : false); } // BGE/BLT
- ATTR_FORCE_INLINE bool cond_gt() { return cond_ge() && !(m_cc & CC_Z); } // BGT/BLE
- ATTR_FORCE_INLINE void set_cond(bool cond) { m_cond = cond; }
- ATTR_FORCE_INLINE bool branch_taken() { return m_cond; }
+ ATTR_FORCE_INLINE bool cond_hi() { return !(m_cc & CC_ZC); } // BHI/BLS
+ ATTR_FORCE_INLINE bool cond_cc() { return !(m_cc & CC_C); } // BCC/BCS
+ ATTR_FORCE_INLINE bool cond_ne() { return !(m_cc & CC_Z); } // BNE/BEQ
+ ATTR_FORCE_INLINE bool cond_vc() { return !(m_cc & CC_V); } // BVC/BVS
+ ATTR_FORCE_INLINE bool cond_pl() { return !(m_cc & CC_N); } // BPL/BMI
+ ATTR_FORCE_INLINE bool cond_ge() { return (m_cc & CC_N ? true : false) == (m_cc & CC_V ? true : false); } // BGE/BLT
+ ATTR_FORCE_INLINE bool cond_gt() { return cond_ge() && !(m_cc & CC_Z); } // BGT/BLE
+ ATTR_FORCE_INLINE void set_cond(bool cond) { m_cond = cond; }
+ ATTR_FORCE_INLINE bool branch_taken() { return m_cond; }
// interrupt registers
- bool firq_saves_entire_state() { return false; }
- UINT16 partial_state_registers() { return 0x81; }
- UINT16 entire_state_registers() { return 0xFF; }
+ bool firq_saves_entire_state() { return false; }
+ UINT16 partial_state_registers() { return 0x81; }
+ UINT16 entire_state_registers() { return 0xFF; }
// miscellaneous
exgtfr_register read_exgtfr_register(UINT8 reg);
@@ -252,19 +252,19 @@ protected:
private:
// address spaces
- const address_space_config m_program_config;
- address_space * m_program;
- direct_read_data * m_direct;
+ const address_space_config m_program_config;
+ address_space * m_program;
+ direct_read_data * m_direct;
// other state
- UINT32 m_state;
- int m_reg;
- UINT8 * m_reg8;
- PAIR16 * m_reg16;
- bool m_cond;
+ UINT32 m_state;
+ int m_reg;
+ UINT8 * m_reg8;
+ PAIR16 * m_reg16;
+ bool m_cond;
// incidentals
- int m_clock_divider;
+ int m_clock_divider;
// functions
void execute_one();
diff --git a/src/emu/cpu/m6809/m6809inl.h b/src/emu/cpu/m6809/m6809inl.h
index ac299d91818..09567f73c00 100644
--- a/src/emu/cpu/m6809/m6809inl.h
+++ b/src/emu/cpu/m6809/m6809inl.h
@@ -2,8 +2,8 @@
m6809inl.h
- Portable 6809 emulator - Inline functions for the purposes of
- optimization
+ Portable 6809 emulator - Inline functions for the purposes of
+ optimization
**********************************************************************/
@@ -67,11 +67,11 @@ inline ATTR_FORCE_INLINE UINT8 m6809_base_device::read_operand()
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: return read_memory(m_ea.w);
- case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
- case ADDRESSING_MODE_REGISTER_A: return m_d.b.h;
- case ADDRESSING_MODE_REGISTER_B: return m_d.b.l;
- default: fatalerror("Unexpected"); return 0x00;
+ case ADDRESSING_MODE_EA: return read_memory(m_ea.w);
+ case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
+ case ADDRESSING_MODE_REGISTER_A: return m_d.b.h;
+ case ADDRESSING_MODE_REGISTER_B: return m_d.b.l;
+ default: fatalerror("Unexpected"); return 0x00;
}
}
@@ -84,9 +84,9 @@ inline ATTR_FORCE_INLINE UINT8 m6809_base_device::read_operand(int ordinal)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
- case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
- default: fatalerror("Unexpected"); return 0x00;
+ case ADDRESSING_MODE_EA: return read_memory(m_ea.w + ordinal);
+ case ADDRESSING_MODE_IMMEDIATE: return read_opcode_arg();
+ default: fatalerror("Unexpected"); return 0x00;
}
}
@@ -99,11 +99,11 @@ inline ATTR_FORCE_INLINE void m6809_base_device::write_operand(UINT8 data)
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
- case ADDRESSING_MODE_EA: write_memory(m_ea.w, data); break;
- case ADDRESSING_MODE_REGISTER_A: m_d.b.h = data; break;
- case ADDRESSING_MODE_REGISTER_B: m_d.b.l = data; break;
- default: fatalerror("Unexpected"); break;
+ case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
+ case ADDRESSING_MODE_EA: write_memory(m_ea.w, data); break;
+ case ADDRESSING_MODE_REGISTER_A: m_d.b.h = data; break;
+ case ADDRESSING_MODE_REGISTER_B: m_d.b.l = data; break;
+ default: fatalerror("Unexpected"); break;
}
}
@@ -116,9 +116,9 @@ inline ATTR_FORCE_INLINE void m6809_base_device::write_operand(int ordinal, UINT
{
switch(m_addressing_mode)
{
- case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
- case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
- default: fatalerror("Unexpected"); break;
+ case ADDRESSING_MODE_IMMEDIATE: /* do nothing */ break;
+ case ADDRESSING_MODE_EA: write_memory(m_ea.w + ordinal, data); break;
+ default: fatalerror("Unexpected"); break;
}
}
@@ -129,10 +129,10 @@ inline ATTR_FORCE_INLINE void m6809_base_device::write_operand(int ordinal, UINT
inline ATTR_FORCE_INLINE bool m6809_base_device::match_target_bytes(UINT16 address, const UINT8 *bytes, int length)
{
- UINT8 *start_raw = (UINT8 *) m_direct->read_raw_ptr(address);
- UINT8 *start_decrypted = (UINT8 *) m_direct->read_decrypted_ptr(address);
- UINT8 *end_raw = (UINT8 *) m_direct->read_raw_ptr(address + length - 1);
- UINT8 *end_decrypted = (UINT8 *) m_direct->read_decrypted_ptr(address + length - 1);
+ UINT8 *start_raw = (UINT8 *) m_direct->read_raw_ptr(address);
+ UINT8 *start_decrypted = (UINT8 *) m_direct->read_decrypted_ptr(address);
+ UINT8 *end_raw = (UINT8 *) m_direct->read_raw_ptr(address + length - 1);
+ UINT8 *end_decrypted = (UINT8 *) m_direct->read_decrypted_ptr(address + length - 1);
return (start_raw != NULL)
&& (end_raw != NULL)
@@ -145,7 +145,7 @@ inline ATTR_FORCE_INLINE bool m6809_base_device::match_target_bytes(UINT16 addre
//-------------------------------------------------
// burn_any_delay_loops - optimization for delay
-// loops
+// loops
//-------------------------------------------------
inline ATTR_FORCE_INLINE void m6809_base_device::burn_any_delay_loops()
@@ -176,15 +176,15 @@ inline ATTR_FORCE_INLINE void m6809_base_device::daa()
UINT8 lsn = m_d.b.h & 0x0F;
// compute the carry
- if (lsn > 0x09 || m_cc & CC_H) cf |= 0x06;
- if (msn > 0x80 && lsn > 0x09 ) cf |= 0x60;
- if (msn > 0x90 || m_cc & CC_C) cf |= 0x60;
+ if (lsn > 0x09 || m_cc & CC_H) cf |= 0x06;
+ if (msn > 0x80 && lsn > 0x09 ) cf |= 0x60;
+ if (msn > 0x90 || m_cc & CC_C) cf |= 0x60;
// calculate the result
t = m_d.b.h + cf;
m_cc &= ~CC_V;
- if (t & 0x0100) // keep carry from previous operation
+ if (t & 0x0100) // keep carry from previous operation
m_cc |= CC_C;
// and put it back into A
@@ -220,10 +220,10 @@ inline ATTR_FORCE_INLINE UINT16 &m6809_base_device::ireg()
{
switch(m_opcode & 0x60)
{
- case 0x00: return m_x.w;
- case 0x20: return m_y.w;
- case 0x40: return m_u.w;
- case 0x60: return m_s.w;
+ case 0x00: return m_x.w;
+ case 0x20: return m_y.w;
+ case 0x40: return m_u.w;
+ case 0x60: return m_s.w;
default:
fatalerror("Unexpected");
return m_x.w;
@@ -276,7 +276,7 @@ inline void m6809_base_device::eat_remaining()
UINT16 real_pc = m_pc.w;
eat(m_icount);
-
+
m_pc.w = m_ppc.w;
debugger_instruction_hook(this, m_pc.w);
m_pc.w = real_pc;
@@ -333,10 +333,10 @@ inline UINT16 m6809_base_device::check_pending_interrupt()
switch(result)
{
case VECTOR_FIRQ:
- standard_irq_callback(M6809_FIRQ_LINE);
+ standard_irq_callback(M6809_FIRQ_LINE);
break;
case VECTOR_IRQ:
- standard_irq_callback(M6809_IRQ_LINE);
+ standard_irq_callback(M6809_IRQ_LINE);
break;
}
diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c
index e2963aa4033..6448ffa4257 100644
--- a/src/emu/cpu/sh2/sh2drc.c
+++ b/src/emu/cpu/sh2/sh2drc.c
@@ -1171,7 +1171,7 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit
UML_LABEL(block, label++); // label:
-#if 0 // DO NOT ENABLE - SEVERE AARON DAMAGE
+#if 0 // DO NOT ENABLE - SEVERE AARON DAMAGE
for (int ramnum = 0; ramnum < SH2_MAX_FASTRAM; ramnum++)
{
if (sh2->fastram[ramnum].base != NULL && (!iswrite || !sh2->fastram[ramnum].readonly))
@@ -2020,24 +2020,24 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
int skip = compiler->labelnum+1;
compiler->labelnum += 3;
- UML_MOV(block, I0, mem(&sh2->sleep_mode)); // mov i0, sleep_mode
- UML_CMP(block, I0, 0x2); // cmp i0, #2
- UML_JMPc(block, COND_E, skip+1); // beq skip + 1
+ UML_MOV(block, I0, mem(&sh2->sleep_mode)); // mov i0, sleep_mode
+ UML_CMP(block, I0, 0x2); // cmp i0, #2
+ UML_JMPc(block, COND_E, skip+1); // beq skip + 1
// sleep mode != 2
- UML_CMP(block, I0, 0x0); // cmp i0, #0
- UML_JMPc(block, COND_NE, skip); // bne skip
- UML_MOV(block, mem(&sh2->sleep_mode), 0x1); // mov sleep_mode, #1
+ UML_CMP(block, I0, 0x0); // cmp i0, #0
+ UML_JMPc(block, COND_NE, skip); // bne skip
+ UML_MOV(block, mem(&sh2->sleep_mode), 0x1); // mov sleep_mode, #1
- UML_LABEL(block, skip); // skip:
- generate_update_cycles(sh2, block, compiler, desc->pc, TRUE); // repeat this insn
- UML_JMP(block, skip+2); // jmp skip+2
+ UML_LABEL(block, skip); // skip:
+ generate_update_cycles(sh2, block, compiler, desc->pc, TRUE); // repeat this insn
+ UML_JMP(block, skip+2); // jmp skip+2
- UML_LABEL(block, skip+1); // skip + 1:
+ UML_LABEL(block, skip+1); // skip + 1:
// sleep_mode == 2
- UML_MOV(block, mem(&sh2->sleep_mode), 0x0); // sleep_mode = 0
- generate_update_cycles(sh2, block, compiler, desc->pc+2, TRUE); // go to next insn
+ UML_MOV(block, mem(&sh2->sleep_mode), 0x0); // sleep_mode = 0
+ generate_update_cycles(sh2, block, compiler, desc->pc+2, TRUE); // go to next insn
- UML_LABEL(block, skip+2); // skip + 2:
+ UML_LABEL(block, skip+2); // skip + 2:
}
return TRUE;