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-rw-r--r--src/emu/cpu/z8/z8.c98
-rw-r--r--src/emu/cpu/z8/z8.h2
-rw-r--r--src/emu/cpu/z8/z8dasm.c50
-rw-r--r--src/emu/cpu/z8/z8ops.c36
4 files changed, 93 insertions, 93 deletions
diff --git a/src/emu/cpu/z8/z8.c b/src/emu/cpu/z8/z8.c
index 052518be668..a899375fd68 100644
--- a/src/emu/cpu/z8/z8.c
+++ b/src/emu/cpu/z8/z8.c
@@ -9,15 +9,15 @@
/*
- TODO:
+ TODO:
- - strobed I/O
- - interrupts
- - expose register file to disassembler
- - decimal adjust instruction
- - timer Tin/Tout modes
- - serial
- - instruction pipeline
+ - strobed I/O
+ - interrupts
+ - expose register file to disassembler
+ - decimal adjust instruction
+ - timer Tin/Tout modes
+ - serial
+ - instruction pipeline
*/
@@ -241,7 +241,7 @@ INLINE z8_state *get_safe_token(const device_config *device)
assert(device != NULL);
assert(device->token != NULL);
assert(device->type == CPU);
- assert((cpu_get_type(device) == CPU_Z8601) ||
+ assert((cpu_get_type(device) == CPU_Z8601) ||
(cpu_get_type(device) == CPU_UB8830D) ||
(cpu_get_type(device) == CPU_Z8611));
return (z8_state *)device->token;
@@ -341,7 +341,7 @@ INLINE UINT8 register_read(z8_state *cpustate, UINT8 offset)
case Z8_REGISTER_IPR:
/* write only */
break;
-
+
default:
data = cpustate->r[offset];
break;
@@ -382,7 +382,7 @@ INLINE void register_write(z8_state *cpustate, UINT8 offset, UINT8 data)
case Z8_REGISTER_P3:
cpustate->output[offset] = data;
-
+
// TODO: special port 3 modes
if (!(P3M & 0x7c))
{
@@ -394,10 +394,10 @@ INLINE void register_write(z8_state *cpustate, UINT8 offset, UINT8 data)
case Z8_REGISTER_SIO:
break;
-
+
case Z8_REGISTER_TMR:
if (data & Z8_TMR_LOAD_T0)
- {
+ {
cpustate->t0 = T0;
timer_adjust_periodic(cpustate->t0_timer, attotime_zero, 0, ATTOTIME_IN_HZ(cpustate->clock / 2 / 4 / ((PRE0 >> 2) + 1)));
}
@@ -405,7 +405,7 @@ INLINE void register_write(z8_state *cpustate, UINT8 offset, UINT8 data)
timer_enable(cpustate->t0_timer, data & Z8_TMR_ENABLE_T0);
if (data & Z8_TMR_LOAD_T1)
- {
+ {
cpustate->t1 = T1;
timer_adjust_periodic(cpustate->t1_timer, attotime_zero, 0, ATTOTIME_IN_HZ(cpustate->clock / 2 / 4 / ((PRE1 >> 2) + 1)));
}
@@ -597,53 +597,53 @@ struct _z8_opcode_map
static const z8_opcode_map Z8601_OPCODE_MAP[] =
{
- { dec_R1, 6, 5 }, { dec_IR1, 6, 5 }, { add_r1_r2, 10, 5 }, { add_r1_Ir2, 10, 5 }, { add_R2_R1, 10, 5 }, { add_IR2_R1, 10, 5 }, { add_R1_IM, 10, 5 }, { add_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { dec_R1, 6, 5 }, { dec_IR1, 6, 5 }, { add_r1_r2, 10, 5 }, { add_r1_Ir2, 10, 5 }, { add_R2_R1, 10, 5 }, { add_IR2_R1, 10, 5 }, { add_R1_IM, 10, 5 }, { add_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { rlc_R1, 6, 5 }, { rlc_IR1, 6, 5 }, { adc_r1_r2, 6, 5 }, { adc_r1_Ir2, 6, 5 }, { adc_R2_R1, 10, 5 }, { adc_IR2_R1, 10, 5 }, { adc_R1_IM, 10, 5 }, { adc_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { rlc_R1, 6, 5 }, { rlc_IR1, 6, 5 }, { adc_r1_r2, 6, 5 }, { adc_r1_Ir2, 6, 5 }, { adc_R2_R1, 10, 5 }, { adc_IR2_R1, 10, 5 }, { adc_R1_IM, 10, 5 }, { adc_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { inc_R1, 6, 5 }, { inc_IR1, 6, 5 }, { sub_r1_r2, 6, 5 }, { sub_r1_Ir2, 6, 5 }, { sub_R2_R1, 10, 5 }, { sub_IR2_R1, 10, 5 }, { sub_R1_IM, 10, 5 }, { sub_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { inc_R1, 6, 5 }, { inc_IR1, 6, 5 }, { sub_r1_r2, 6, 5 }, { sub_r1_Ir2, 6, 5 }, { sub_R2_R1, 10, 5 }, { sub_IR2_R1, 10, 5 }, { sub_R1_IM, 10, 5 }, { sub_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { jp_IRR1, 8, 0 }, { srp_IM, 6, 1 }, { sbc_r1_r2, 6, 5 }, { sbc_r1_Ir2, 6, 5 }, { sbc_R2_R1, 10, 5 }, { sbc_IR2_R1, 10, 5 }, { sbc_R1_IM, 10, 5 }, { sbc_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { jp_IRR1, 8, 0 }, { srp_IM, 6, 1 }, { sbc_r1_r2, 6, 5 }, { sbc_r1_Ir2, 6, 5 }, { sbc_R2_R1, 10, 5 }, { sbc_IR2_R1, 10, 5 }, { sbc_R1_IM, 10, 5 }, { sbc_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { da_R1, 8, 5 }, { da_IR1, 8, 5 }, { or_r1_r2, 6, 5 }, { or_r1_Ir2, 6, 5 }, { or_R2_R1, 10, 5 }, { or_IR2_R1, 10, 5 }, { or_R1_IM, 10, 5 }, { or_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { da_R1, 8, 5 }, { da_IR1, 8, 5 }, { or_r1_r2, 6, 5 }, { or_r1_Ir2, 6, 5 }, { or_R2_R1, 10, 5 }, { or_IR2_R1, 10, 5 }, { or_R1_IM, 10, 5 }, { or_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { pop_R1, 10, 5 }, { pop_IR1, 10, 5 }, { and_r1_r2, 6, 5 }, { and_r1_Ir2, 6, 5 }, { and_R2_R1, 10, 5 }, { and_IR2_R1, 10, 5 }, { and_R1_IM, 10, 5 }, { and_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { pop_R1, 10, 5 }, { pop_IR1, 10, 5 }, { and_r1_r2, 6, 5 }, { and_r1_Ir2, 6, 5 }, { and_R2_R1, 10, 5 }, { and_IR2_R1, 10, 5 }, { and_R1_IM, 10, 5 }, { and_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { com_R1, 6, 5 }, { com_IR1, 6, 5 }, { tcm_r1_r2, 6, 5 }, { tcm_r1_Ir2, 6, 5 }, { tcm_R2_R1, 10, 5 }, { tcm_IR2_R1, 10, 5 }, { tcm_R1_IM, 10, 5 }, { tcm_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { com_R1, 6, 5 }, { com_IR1, 6, 5 }, { tcm_r1_r2, 6, 5 }, { tcm_r1_Ir2, 6, 5 }, { tcm_R2_R1, 10, 5 }, { tcm_IR2_R1, 10, 5 }, { tcm_R1_IM, 10, 5 }, { tcm_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { push_R2, 10, 1 }, { push_IR2, 12, 1 },{ tm_r1_r2, 6, 5 }, { tm_r1_Ir2, 6, 5 }, { tm_R2_R1, 10, 5 }, { tm_IR2_R1, 10, 5 }, { tm_R1_IM, 10, 5 }, { tm_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
+ { push_R2, 10, 1 }, { push_IR2, 12, 1 },{ tm_r1_r2, 6, 5 }, { tm_r1_Ir2, 6, 5 }, { tm_R2_R1, 10, 5 }, { tm_IR2_R1, 10, 5 }, { tm_R1_IM, 10, 5 }, { tm_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { illegal, 0, 0 },
- { decw_RR1, 10, 5 },{ decw_IR1, 10, 5 },{ lde_r1_Irr2, 12, 0 }, { ldei_Ir1_Irr2, 18, 0 },{ illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { di, 6, 1 },
+ { decw_RR1, 10, 5 },{ decw_IR1, 10, 5 },{ lde_r1_Irr2, 12, 0 }, { ldei_Ir1_Irr2, 18, 0 },{ illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { di, 6, 1 },
- { rl_R1, 6, 5 }, { rl_IR1, 6, 5 }, { lde_r2_Irr1, 12, 0 }, { ldei_Ir2_Irr1, 18, 0 },{ illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { ei, 6, 1 },
+ { rl_R1, 6, 5 }, { rl_IR1, 6, 5 }, { lde_r2_Irr1, 12, 0 }, { ldei_Ir2_Irr1, 18, 0 },{ illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { ei, 6, 1 },
- { incw_RR1, 10, 5 },{ incw_IR1, 10, 5 },{ cp_r1_r2, 6, 5 }, { cp_r1_Ir2, 6, 5 }, { cp_R2_R1, 10, 5 }, { cp_IR2_R1, 10, 5 }, { cp_R1_IM, 10, 5 }, { cp_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { ret, 14, 0 },
+ { incw_RR1, 10, 5 },{ incw_IR1, 10, 5 },{ cp_r1_r2, 6, 5 }, { cp_r1_Ir2, 6, 5 }, { cp_R2_R1, 10, 5 }, { cp_IR2_R1, 10, 5 }, { cp_R1_IM, 10, 5 }, { cp_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { ret, 14, 0 },
- { clr_R1, 6, 5 }, { clr_IR1, 6, 5 }, { xor_r1_r2, 6, 5 }, { xor_r1_Ir2, 6, 5 }, { xor_R2_R1, 10, 5 }, { xor_IR2_R1, 10, 5 }, { xor_R1_IM, 10, 5 }, { xor_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { iret, 16, 0 },
+ { clr_R1, 6, 5 }, { clr_IR1, 6, 5 }, { xor_r1_r2, 6, 5 }, { xor_r1_Ir2, 6, 5 }, { xor_R2_R1, 10, 5 }, { xor_IR2_R1, 10, 5 }, { xor_R1_IM, 10, 5 }, { xor_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { iret, 16, 0 },
- { rrc_R1, 6, 5 }, { rrc_IR1, 6, 5 }, { ldc_r1_Irr2, 12, 0 }, { ldci_Ir1_Irr2, 18, 0 },{ illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 }, { ld_r1_x_R2, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { rcf, 6, 5 },
+ { rrc_R1, 6, 5 }, { rrc_IR1, 6, 5 }, { ldc_r1_Irr2, 12, 0 }, { ldci_Ir1_Irr2, 18, 0 },{ illegal, 0, 0 }, { illegal, 0, 0 }, { illegal, 0, 0 }, { ld_r1_x_R2, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { rcf, 6, 5 },
- { sra_R1, 6, 5 }, { sra_IR1, 6, 5 }, { ldc_r2_Irr1, 12, 0 }, { ldci_Ir2_Irr1, 18, 0 },{ call_IRR1, 20, 0 }, { illegal, 0, 0 }, { call_DA, 20, 0 }, { ld_r2_x_R1, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { scf, 6, 5 },
+ { sra_R1, 6, 5 }, { sra_IR1, 6, 5 }, { ldc_r2_Irr1, 12, 0 }, { ldci_Ir2_Irr1, 18, 0 },{ call_IRR1, 20, 0 }, { illegal, 0, 0 }, { call_DA, 20, 0 }, { ld_r2_x_R1, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { scf, 6, 5 },
- { rr_R1, 6, 5 }, { rr_IR1, 6, 5 }, { illegal, 0, 0 }, { ld_r1_Ir2, 6, 5 }, { ld_R2_R1, 10, 5 }, { ld_IR2_R1, 10, 5 }, { ld_R1_IM, 10, 5 }, { ld_IR1_IM, 10, 5 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { ccf, 6, 5 },
+ { rr_R1, 6, 5 }, { rr_IR1, 6, 5 }, { illegal, 0, 0 }, { ld_r1_Ir2, 6, 5 }, { ld_R2_R1, 10, 5 }, { ld_IR2_R1, 10, 5 }, { ld_R1_IM, 10, 5 }, { ld_IR1_IM, 10, 5 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { ccf, 6, 5 },
{ swap_R1, 8, 5 }, { swap_IR1, 8, 5 }, { illegal, 0, 0 }, { ld_Ir1_r2, 6, 5 }, { illegal, 0, 0 }, { ld_R2_IR1, 10, 5 }, { illegal, 0, 0 }, { illegal, 0, 0 },
- { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { nop, 6, 0 },
+ { ld_r1_R2, 6, 5 }, { ld_r2_R1, 6, 5 }, { djnz_r1_RA, 10, 5 }, { jr_cc_RA, 10, 0 }, { ld_r1_IM, 6, 5 }, { jp_cc_DA, 10, 0 }, { inc_r1, 6, 5 }, { nop, 6, 0 },
};
/***************************************************************************
@@ -728,17 +728,17 @@ static CPU_EXECUTE( z8 )
int cycles;
debugger_instruction_hook(device, cpustate->pc);
-
+
/* TODO: sample interrupts */
cpustate->input[3] = memory_read_byte_8be(cpustate->io, 3);
-
+
/* fetch opcode */
opcode = fetch(cpustate);
cycles = Z8601_OPCODE_MAP[opcode].execution_cycles;
/* execute instruction */
(*(Z8601_OPCODE_MAP[opcode].function))(cpustate, opcode, &cycles);
-
+
cpustate->icount -= cycles;
}
while (cpustate->icount > 0);
@@ -793,7 +793,7 @@ static CPU_IMPORT_STATE( z8 )
cpustate->r[Z8_REGISTER_SPH] = cpustate->fake_sp >> 8;
cpustate->r[Z8_REGISTER_SPL] = cpustate->fake_sp & 0xff;
break;
-
+
case Z8_R0: case Z8_R1: case Z8_R2: case Z8_R3: case Z8_R4: case Z8_R5: case Z8_R6: case Z8_R7: case Z8_R8: case Z8_R9: case Z8_R10: case Z8_R11: case Z8_R12: case Z8_R13: case Z8_R14: case Z8_R15:
cpustate->r[cpustate->r[Z8_REGISTER_RP] + (entry->index - Z8_R0)] = cpustate->fake_r[entry->index - Z8_R0];
break;
diff --git a/src/emu/cpu/z8/z8.h b/src/emu/cpu/z8/z8.h
index 0f0bc364df6..5467a6f744e 100644
--- a/src/emu/cpu/z8/z8.h
+++ b/src/emu/cpu/z8/z8.h
@@ -18,7 +18,7 @@ enum
{
Z8_PC, Z8_SP, Z8_RP, Z8_T0, Z8_T1,
- Z8_R0, Z8_R1, Z8_R2, Z8_R3, Z8_R4, Z8_R5, Z8_R6, Z8_R7, Z8_R8, Z8_R9, Z8_R10, Z8_R11, Z8_R12, Z8_R13, Z8_R14, Z8_R15,
+ Z8_R0, Z8_R1, Z8_R2, Z8_R3, Z8_R4, Z8_R5, Z8_R6, Z8_R7, Z8_R8, Z8_R9, Z8_R10, Z8_R11, Z8_R12, Z8_R13, Z8_R14, Z8_R15,
Z8_GENPC = REG_GENPC,
Z8_GENSP = REG_GENSP
diff --git a/src/emu/cpu/z8/z8dasm.c b/src/emu/cpu/z8/z8dasm.c
index 07aef5bf9b2..5a3ca6ad099 100644
--- a/src/emu/cpu/z8/z8dasm.c
+++ b/src/emu/cpu/z8/z8dasm.c
@@ -9,27 +9,27 @@
static const char* REGISTER_NAME[256] =
{
"P0", "P1", "P2", "P3", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
"SIO", "TMR", "T1", "PRE1", "T0", "PRE0", "P2M", "P3M", "P01M", "IPR", "IRQ", "IMR", "FLAGS", "RP", "SPH", "SPL"
};
static const char* CONDITION_CODE[16] =
{
- "F", "LT", "LE", "ULE", "OV", "MI", "Z", "C",
- "", "GE", "GT", "UGT", "NOV", "PL", "NZ", "NC"
+ "F", "LT", "LE", "ULE", "OV", "MI", "Z", "C",
+ "", "GE", "GT", "UGT", "NOV", "PL", "NZ", "NC"
};
/***************************************************************************
@@ -90,7 +90,7 @@ CPU_DISASSEMBLE( z8 )
switch (pc)
{
- case 0x0000:
+ case 0x0000:
case 0x0002:
case 0x0004:
case 0x0006:
@@ -235,7 +235,7 @@ CPU_DISASSEMBLE( z8 )
case 0x7d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0x7e: mnemonic("INC"); arg_r(OPH); break;
case 0x7f: illegal; /* mnemonic("HALT"); */ break;
-
+
case 0x80: mnemonic("DECW"); arg_RR(*oprom++); break;
case 0x81: mnemonic("DECW"); arg_IR(B0); bytes(2); break;
case 0x82: mnemonic("LDE"); arg_r(B0H); arg_Irr(B0L); bytes(2); break;
@@ -252,7 +252,7 @@ CPU_DISASSEMBLE( z8 )
case 0x8d: mnemonic("JP"); arg_DA; bytes(3); break;
case 0x8e: mnemonic("INC"); arg_r(OPH); break;
case 0x8f: mnemonic("DI"); break;
-
+
case 0x90: mnemonic("RL"); arg_R(B0); bytes(2); break;
case 0x91: mnemonic("RL"); arg_IR(B0); bytes(2); break;
case 0x92: mnemonic("LDE"); arg_r(B0L); arg_Irr(B0H); bytes(2); break;
@@ -269,7 +269,7 @@ CPU_DISASSEMBLE( z8 )
case 0x9d: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0x9e: mnemonic("INC"); arg_r(OPH); break;
case 0x9f: mnemonic("EI"); break;
-
+
case 0xa0: mnemonic("INCW"); arg_RR(B0); bytes(2); break;
case 0xa1: mnemonic("INCW"); arg_IR(B0); bytes(2); break;
case 0xa2: mnemonic("CP"); arg_r(B0H); arg_r(B0L); bytes(2); break;
@@ -286,7 +286,7 @@ CPU_DISASSEMBLE( z8 )
case 0xad: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0xae: mnemonic("INC"); arg_r(OPH); break;
case 0xaf: mnemonic("RET"); step_out; break;
-
+
case 0xb0: mnemonic("CLR"); arg_R(B0); bytes(2); break;
case 0xb1: mnemonic("XOR"); arg_IR(B0); bytes(2); break;
case 0xb2: mnemonic("XOR"); arg_r(B0H); arg_r(B0L); bytes(2); break;
@@ -303,7 +303,7 @@ CPU_DISASSEMBLE( z8 )
case 0xbd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0xbe: mnemonic("INC"); arg_r(OPH); break;
case 0xbf: mnemonic("IRET"); step_out; break;
-
+
case 0xc0: mnemonic("RRC"); arg_R(B0); bytes(2); break;
case 0xc1: mnemonic("RRC"); arg_IR(B0); bytes(2); break;
case 0xc2: mnemonic("LDC"); arg_r(B0H); arg_Irr(B0L); bytes(2); break;
@@ -320,7 +320,7 @@ CPU_DISASSEMBLE( z8 )
case 0xcd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0xce: mnemonic("INC"); arg_r(OPH); break;
case 0xcf: mnemonic("RCF"); break;
-
+
case 0xd0: mnemonic("SRA"); arg_R(B0); bytes(2); break;
case 0xd1: mnemonic("SRA"); arg_IR(B0); bytes(2); break;
case 0xd2: mnemonic("LDC"); arg_Irr(B0L); arg_r(B0H); bytes(2); break;
@@ -337,7 +337,7 @@ CPU_DISASSEMBLE( z8 )
case 0xdd: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0xde: mnemonic("INC"); arg_r(OPH); break;
case 0xdf: mnemonic("SCF"); break;
-
+
case 0xe0: mnemonic("RR"); arg_R(B0); bytes(2); break;
case 0xe1: mnemonic("RR"); arg_IR(B0); bytes(2); break;
case 0xe2: illegal; break;
@@ -354,7 +354,7 @@ CPU_DISASSEMBLE( z8 )
case 0xed: mnemonic("JP"); arg_cc; arg_DA; bytes(3); break;
case 0xee: mnemonic("INC"); arg_r(OPH); break;
case 0xef: mnemonic("CCF"); break;
-
+
case 0xf0: mnemonic("SWAP"); arg_R(B0); bytes(2); break;
case 0xf1: mnemonic("SWAP"); arg_IR(B0); bytes(2); break;
case 0xf2: illegal; break;
diff --git a/src/emu/cpu/z8/z8ops.c b/src/emu/cpu/z8/z8ops.c
index fd9a7467674..9c014dd4cda 100644
--- a/src/emu/cpu/z8/z8ops.c
+++ b/src/emu/cpu/z8/z8ops.c
@@ -148,7 +148,7 @@ static void load_from_memory(z8_state *cpustate, const address_space *space)
UINT16 address = register_pair_read(cpustate, src);
UINT8 data = memory_decrypted_read_byte(cpustate->program, address);
-
+
register_write(cpustate, dst, data);
}
@@ -173,9 +173,9 @@ static void load_from_memory_autoinc(z8_state *cpustate, const address_space *sp
UINT16 address = register_pair_read(cpustate, src);
UINT8 data = memory_decrypted_read_byte(cpustate->program, address);
-
+
register_write(cpustate, real_dst, data);
-
+
register_write(cpustate, dst, real_dst + 1);
register_pair_write(cpustate, src, address + 1);
}
@@ -191,7 +191,7 @@ static void load_to_memory_autoinc(z8_state *cpustate, const address_space *spac
UINT8 data = register_read(cpustate, real_src);
memory_write_byte(cpustate->program, address, data);
-
+
register_pair_write(cpustate, dst, address + 1);
register_write(cpustate, src, real_src + 1);
}
@@ -208,7 +208,7 @@ INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->data);
static void pop(z8_state *cpustate, UINT8 dst)
{
/* dst <- @SP
- SP <- SP + 1 */
+ SP <- SP + 1 */
register_write(cpustate, dst, stack_pop_byte(cpustate));
}
@@ -218,7 +218,7 @@ INSTRUCTION( pop_IR1 ) { mode_IR1(pop) }
static void push(z8_state *cpustate, UINT8 src)
{
/* SP <- SP - 1
- @SP <- src */
+ @SP <- src */
stack_push_byte(cpustate, read(src));
}
@@ -495,7 +495,7 @@ INSTRUCTION( call_DA ) { UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate)
INSTRUCTION( djnz_r1_RA )
{
- INT8 ra = (INT8)fetch(cpustate);
+ INT8 ra = (INT8)fetch(cpustate);
/* r <- r - 1 */
int r = get_working_register(cpustate, opcode >> 4);
@@ -513,13 +513,13 @@ INSTRUCTION( djnz_r1_RA )
INSTRUCTION( iret )
{
/* FLAGS <- @SP
- SP <- SP + 1 */
+ SP <- SP + 1 */
register_write(cpustate, Z8_REGISTER_FLAGS, stack_pop_byte(cpustate));
/* PC <- @SP
- SP <- SP + 2 */
+ SP <- SP + 2 */
cpustate->pc = stack_pop_word(cpustate);
-
+
/* IMR (7) <- 1 */
cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE;
}
@@ -527,7 +527,7 @@ INSTRUCTION( iret )
INSTRUCTION( ret )
{
/* PC <- @SP
- SP <- SP + 2 */
+ SP <- SP + 2 */
cpustate->pc = stack_pop_word(cpustate);
}
@@ -562,14 +562,14 @@ static int check_condition_code(z8_state *cpustate, int cc)
case CC_NZ: truth = !flag(Z); break;
case CC_NC: truth = !flag(C); break;
}
-
+
return truth;
}
INSTRUCTION( jp_cc_DA )
{
- UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate);
-
+ UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate);
+
/* if cc is true, then PC <- dst */
if (check_condition_code(cpustate, opcode >> 4))
{
@@ -581,7 +581,7 @@ INSTRUCTION( jp_cc_DA )
INSTRUCTION( jr_cc_RA )
{
INT8 ra = (INT8)fetch(cpustate);
- UINT16 dst = cpustate->pc + ra;
+ UINT16 dst = cpustate->pc + ra;
/* if cc is true, then PC <- dst */
if (check_condition_code(cpustate, opcode >> 4))
@@ -599,7 +599,7 @@ static void test_complement_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src)
{
/* NOT(dst) AND src */
UINT8 data = (register_read(cpustate, dst) ^ 0xff) & src;
-
+
set_flag_z(data == 0);
set_flag_s(data & 0x80);
set_flag_v(0);
@@ -616,7 +616,7 @@ static void test_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src)
{
/* dst AND src */
UINT8 data = register_read(cpustate, dst) & src;
-
+
set_flag_z(data == 0);
set_flag_s(data & 0x80);
set_flag_v(0);
@@ -727,7 +727,7 @@ static void swap(z8_state *cpustate, UINT8 dst)
set_flag_z(data == 0);
set_flag_s(data & 0x80);
-// set_flag_v(0); undefined
+// set_flag_v(0); undefined
}
INSTRUCTION( swap_R1 ) { mode_R1(swap) }