diff options
Diffstat (limited to 'src/devices')
-rw-r--r-- | src/devices/cpu/unsp/unspdasm_extended.cpp | 2 | ||||
-rw-r--r-- | src/devices/machine/alpha_8921.h | 2 | ||||
-rw-r--r-- | src/devices/machine/bl_handhelds_menucontrol.h | 2 | ||||
-rw-r--r-- | src/devices/machine/cs8900a.cpp | 428 | ||||
-rw-r--r-- | src/devices/machine/cs8900a.h | 26 | ||||
-rw-r--r-- | src/devices/machine/generalplus_gpl16250soc.cpp | 4 | ||||
-rw-r--r-- | src/devices/sound/gaelco.cpp | 4 | ||||
-rw-r--r-- | src/devices/sound/hc55516.cpp | 8 | ||||
-rw-r--r-- | src/devices/sound/votrax.cpp | 2 | ||||
-rw-r--r-- | src/devices/video/ppu2c0x.cpp | 2 | ||||
-rw-r--r-- | src/devices/video/ppu2c0x_sh6578.cpp | 2 | ||||
-rw-r--r-- | src/devices/video/ppu2c0x_vt.cpp | 16 |
12 files changed, 249 insertions, 249 deletions
diff --git a/src/devices/cpu/unsp/unspdasm_extended.cpp b/src/devices/cpu/unsp/unspdasm_extended.cpp index 3caa182b237..1655936647b 100644 --- a/src/devices/cpu/unsp/unspdasm_extended.cpp +++ b/src/devices/cpu/unsp/unspdasm_extended.cpp @@ -147,7 +147,7 @@ offs_t unsp_20_disassembler::disassemble_extended_group(std::ostream& stream, of uint8_t rb = (ximm & 0x000f) >> 0; uint8_t size = (ximm & 0x7000) >> 12; uint8_t rx = (ximm & 0x0e00) >> 9; - + if (size == 0) size = 8; int start = (rx + 1)&7; diff --git a/src/devices/machine/alpha_8921.h b/src/devices/machine/alpha_8921.h index 88ecd850eb9..a6e8ccdb0ad 100644 --- a/src/devices/machine/alpha_8921.h +++ b/src/devices/machine/alpha_8921.h @@ -2,7 +2,7 @@ // copyright-holders:cam900 /*************************************************************************** - Alpha denshi ALPHA-8921 emulation + Alpha denshi ALPHA-8921 emulation ***************************************************************************/ diff --git a/src/devices/machine/bl_handhelds_menucontrol.h b/src/devices/machine/bl_handhelds_menucontrol.h index 419cea33550..747a60db76b 100644 --- a/src/devices/machine/bl_handhelds_menucontrol.h +++ b/src/devices/machine/bl_handhelds_menucontrol.h @@ -33,7 +33,7 @@ private: // internal state uint16_t m_menupos; - + // command handling uint8_t m_clockstate; uint8_t m_datashifterpos; diff --git a/src/devices/machine/cs8900a.cpp b/src/devices/machine/cs8900a.cpp index 8a33504a2d8..6f6535150f7 100644 --- a/src/devices/machine/cs8900a.cpp +++ b/src/devices/machine/cs8900a.cpp @@ -4,11 +4,11 @@ /************************************************************************* - CS8900A ethernet controller implementation + CS8900A ethernet controller implementation - by Rhett Aultman <roadriverrail@gmail.com> - ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/) - VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de> + by Rhett Aultman <roadriverrail@gmail.com> + ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/) + VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de> **************************************************************************/ @@ -20,17 +20,17 @@ DEFINE_DEVICE_TYPE(CS8900A, cs8900a_device, "cs8900a", "CS8900A Crystal LAN 10Base-T Ethernet MAC") /* warn illegal behaviour */ -#define CS8900_DEBUG_WARN_REG (1 << 1U) /* warn about invalid register accesses */ -#define CS8900_DEBUG_WARN_RXTX (1 << 2U) /* warn about invalid rx or tx conditions */ +#define CS8900_DEBUG_WARN_REG (1 << 1U) /* warn about invalid register accesses */ +#define CS8900_DEBUG_WARN_RXTX (1 << 2U) /* warn about invalid rx or tx conditions */ -#define CS8900_DEBUG (1 << 3U) /* enable to see port reads */ +#define CS8900_DEBUG (1 << 3U) /* enable to see port reads */ #define CS8900_DEBUG_INIT (1 << 4U) -#define CS8900_DEBUG_LOAD (1 << 5U) /* enable to see port reads */ -#define CS8900_DEBUG_STORE (1 << 6U) /* enable to see port writes */ -#define CS8900_DEBUG_REGISTERS (1 << 7U) /* enable to see CS8900a register I/O */ -#define CS8900_DEBUG_RXTX_STATE (1 << 8U) /* enable to see tranceiver state changes */ -#define CS8900_DEBUG_RXTX_DATA (1 << 9U) /* enable to see data in/out flow */ -#define CS8900_DEBUG_FRAMES (1 << 10U) /* enable to see arch frame send/recv */ +#define CS8900_DEBUG_LOAD (1 << 5U) /* enable to see port reads */ +#define CS8900_DEBUG_STORE (1 << 6U) /* enable to see port writes */ +#define CS8900_DEBUG_REGISTERS (1 << 7U) /* enable to see CS8900a register I/O */ +#define CS8900_DEBUG_RXTX_STATE (1 << 8U) /* enable to see tranceiver state changes */ +#define CS8900_DEBUG_RXTX_DATA (1 << 9U) /* enable to see data in/out flow */ +#define CS8900_DEBUG_FRAMES (1 << 10U) /* enable to see arch frame send/recv */ /** #define CS8900_DEBUG_IGNORE_RXEVENT 1 **/ /* enable to ignore RXEVENT in DEBUG_REGISTERS */ #define VERBOSE 0 @@ -41,57 +41,57 @@ DEFINE_DEVICE_TYPE(CS8900A, cs8900a_device, "cs8900a", "CS8900A Crystal LAN 10Ba /* CS8900 registers */ -/* these are the 8 16-bit-ports for "I/O space configuration" - (see 4.10 on page 75 of cs8900a-4.pdf, the cs8900a data sheet) +/* these are the 8 16-bit-ports for "I/O space configuration" + (see 4.10 on page 75 of cs8900a-4.pdf, the cs8900a data sheet) - REMARK: The code operatoes the cs8900a in IO space configuration, as - it generates I/OW and I/OR signals. + REMARK: The code operatoes the cs8900a in IO space configuration, as + it generates I/OW and I/OR signals. */ /* - RW: RXTXDATA = DE00/DE01 - RW: RXTXDATA2 = DE02/DE03 (for 32-bit-operation) - -W: TXCMD = DE04/DE05 (TxCMD, Transmit Command) mapped to PP + 0144 (Reg. 9, Sec. 4.4, page 46) - -W: TXLENGTH = DE06/DE07 (TxLenght, Transmit Length) mapped to PP + 0146 - R-: INTSTQUEUE = DE08/DE09 (Interrupt Status Queue) mapped to PP + 0120 (ISQ, Sec. 5.1, page 78) - RW: PP_PTR = DE0A/DE0B (PacketPage Pointer) (see. page 75p: Read -011.---- ----.----) - RW: PP_DATA0 = DE0C/DE0D (PacketPage Data (Port 0)) - RW: PP_DATA1 = DE0E/DE0F (PacketPage Data (Port 1)) (for 32 bit only) + RW: RXTXDATA = DE00/DE01 + RW: RXTXDATA2 = DE02/DE03 (for 32-bit-operation) + -W: TXCMD = DE04/DE05 (TxCMD, Transmit Command) mapped to PP + 0144 (Reg. 9, Sec. 4.4, page 46) + -W: TXLENGTH = DE06/DE07 (TxLenght, Transmit Length) mapped to PP + 0146 + R-: INTSTQUEUE = DE08/DE09 (Interrupt Status Queue) mapped to PP + 0120 (ISQ, Sec. 5.1, page 78) + RW: PP_PTR = DE0A/DE0B (PacketPage Pointer) (see. page 75p: Read -011.---- ----.----) + RW: PP_DATA0 = DE0C/DE0D (PacketPage Data (Port 0)) + RW: PP_DATA1 = DE0E/DE0F (PacketPage Data (Port 1)) (for 32 bit only) */ enum io_space_conf_regs_e : u8 { - CS8900_ADDR_RXTXDATA = 0x00, /* RW */ - CS8900_ADDR_RXTXDATA2 = 0x02, /* RW 32 bit only! */ - CS8900_ADDR_TXCMD = 0x04, /* -W Maps to PP+0144 */ - CS8900_ADDR_TXLENGTH = 0x06, /* -W Maps to PP+0146 */ - CS8900_ADDR_INTSTQUEUE = 0x08, /* R- Interrupt status queue, maps to PP + 0120 */ - CS8900_ADDR_PP_PTR = 0x0a, /* RW PacketPage Pointer */ - CS8900_ADDR_PP_DATA = 0x0c, /* RW PacketPage Data, Port 0 */ - CS8900_ADDR_PP_DATA2 = 0x0e /* RW PacketPage Data, Port 1 - 32 bit only */ + CS8900_ADDR_RXTXDATA = 0x00, /* RW */ + CS8900_ADDR_RXTXDATA2 = 0x02, /* RW 32 bit only! */ + CS8900_ADDR_TXCMD = 0x04, /* -W Maps to PP+0144 */ + CS8900_ADDR_TXLENGTH = 0x06, /* -W Maps to PP+0146 */ + CS8900_ADDR_INTSTQUEUE = 0x08, /* R- Interrupt status queue, maps to PP + 0120 */ + CS8900_ADDR_PP_PTR = 0x0a, /* RW PacketPage Pointer */ + CS8900_ADDR_PP_DATA = 0x0c, /* RW PacketPage Data, Port 0 */ + CS8900_ADDR_PP_DATA2 = 0x0e /* RW PacketPage Data, Port 1 - 32 bit only */ }; /* Makros for reading and writing the visible register: */ -#define GET_CS8900_8(_xxx_) \ - (assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \ - cs8900_ioregs[_xxx_] \ +#define GET_CS8900_8(_xxx_) \ + (assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \ + cs8900_ioregs[_xxx_] \ ) -#define SET_CS8900_8(_xxx_, _val_) \ - do { \ - assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \ - cs8900_ioregs[_xxx_] = (_val_) & 0xff; \ +#define SET_CS8900_8(_xxx_, _val_) \ + do { \ + assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \ + cs8900_ioregs[_xxx_] = (_val_) & 0xff; \ } while (0) -#define GET_CS8900_16(_xxx_) \ - (assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \ - cs8900_ioregs[_xxx_] | (cs8900_ioregs[_xxx_ + 1] << 8) \ +#define GET_CS8900_16(_xxx_) \ + (assert(_xxx_ < CS8900_COUNT_IO_REGISTER), \ + cs8900_ioregs[_xxx_] | (cs8900_ioregs[_xxx_ + 1] << 8) \ ) -#define SET_CS8900_16(_xxx_, _val_) \ - do { \ - assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \ - cs8900_ioregs[_xxx_] = (_val_) & 0xff; \ - cs8900_ioregs[_xxx_ + 1] = (_val_ >> 8) & 0xff; \ +#define SET_CS8900_16(_xxx_, _val_) \ + do { \ + assert(_xxx_ < CS8900_COUNT_IO_REGISTER); \ + cs8900_ioregs[_xxx_] = (_val_) & 0xff; \ + cs8900_ioregs[_xxx_ + 1] = (_val_ >> 8) & 0xff; \ } while (0) /* The PacketPage register */ @@ -99,106 +99,106 @@ enum io_space_conf_regs_e : u8 { /* Macros for reading and writing the PacketPage register: */ -#define GET_PP_8(_xxx_) \ - (assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \ - cs8900_packetpage[_xxx_] \ +#define GET_PP_8(_xxx_) \ + (assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \ + cs8900_packetpage[_xxx_] \ ) -#define GET_PP_16(_xxx_) \ - (assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \ - assert((_xxx_ & 1) == 0), \ - ((u16)cs8900_packetpage[_xxx_]) \ - |((u16)cs8900_packetpage[_xxx_ + 1] << 8) \ +#define GET_PP_16(_xxx_) \ + (assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \ + assert((_xxx_ & 1) == 0), \ + ((u16)cs8900_packetpage[_xxx_]) \ + |((u16)cs8900_packetpage[_xxx_ + 1] << 8) \ ) -#define GET_PP_32(_xxx_) \ - (assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \ - assert((_xxx_ & 3) == 0), \ - (((u32)cs8900_packetpage[_xxx_])) \ - |(((u32)cs8900_packetpage[_xxx_ + 1]) << 8) \ - |(((u32)cs8900_packetpage[_xxx_ + 2]) << 16) \ - |(((u32)cs8900_packetpage[_xxx_ + 3]) << 24) \ +#define GET_PP_32(_xxx_) \ + (assert(_xxx_ < MAX_PACKETPAGE_ARRAY), \ + assert((_xxx_ & 3) == 0), \ + (((u32)cs8900_packetpage[_xxx_])) \ + |(((u32)cs8900_packetpage[_xxx_ + 1]) << 8) \ + |(((u32)cs8900_packetpage[_xxx_ + 2]) << 16) \ + |(((u32)cs8900_packetpage[_xxx_ + 3]) << 24) \ ) -#define SET_PP_8(_xxx_, _val_) \ - do { \ - assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \ - cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \ +#define SET_PP_8(_xxx_, _val_) \ + do { \ + assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \ + cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \ } while (0) -#define SET_PP_16(_xxx_, _val_) \ - do { \ - assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \ - assert((_xxx_ & 1) == 0), \ - cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \ - cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \ +#define SET_PP_16(_xxx_, _val_) \ + do { \ + assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \ + assert((_xxx_ & 1) == 0), \ + cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \ + cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \ } while (0) -#define SET_PP_32(_xxx_, _val_) \ - do { \ - assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \ - assert((_xxx_ & 3) == 0), \ - cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \ - cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \ - cs8900_packetpage[_xxx_ + 2] = (_val_ >> 16) & 0xFF; \ - cs8900_packetpage[_xxx_ + 3] = (_val_ >> 24) & 0xFF; \ +#define SET_PP_32(_xxx_, _val_) \ + do { \ + assert(_xxx_ < MAX_PACKETPAGE_ARRAY); \ + assert((_xxx_ & 3) == 0), \ + cs8900_packetpage[_xxx_] = (_val_) & 0xFF; \ + cs8900_packetpage[_xxx_ + 1] = (_val_ >> 8) & 0xFF; \ + cs8900_packetpage[_xxx_ + 2] = (_val_ >> 16) & 0xFF; \ + cs8900_packetpage[_xxx_ + 3] = (_val_ >> 24) & 0xFF; \ } while (0) enum packetpage_regs_e : u16 { /* The packetpage register: see p. 39f */ - CS8900_PP_ADDR_PRODUCTID = 0x0000, /* R- - 4.3., p. 41 */ - CS8900_PP_ADDR_IOBASE = 0x0020, /* i RW - 4.3., p. 41 - 4.7., p. 72 */ - CS8900_PP_ADDR_INTNO = 0x0022, /* i RW - 3.2., p. 17 - 4.3., p. 41 */ - CS8900_PP_ADDR_DMA_CHAN = 0x0024, /* i RW - 3.2., p. 17 - 4.3., p. 41 */ - CS8900_PP_ADDR_DMA_SOF = 0x0026, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */ - CS8900_PP_ADDR_DMA_FC = 0x0028, /* ? R- - 4.3., p. 41, "Receive DMA" */ - CS8900_PP_ADDR_RXDMA_BC = 0x002a, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */ - CS8900_PP_ADDR_MEMBASE = 0x002c, /* i RW - 4.3., p. 41 - 4.9., p. 73 */ - CS8900_PP_ADDR_BPROM_BASE = 0x0030, /* i RW - 3.6., p. 24 - 4.3., p. 41 */ - CS8900_PP_ADDR_BPROM_MASK = 0x0034, /* i RW - 3.6., p. 24 - 4.3., p. 41 */ + CS8900_PP_ADDR_PRODUCTID = 0x0000, /* R- - 4.3., p. 41 */ + CS8900_PP_ADDR_IOBASE = 0x0020, /* i RW - 4.3., p. 41 - 4.7., p. 72 */ + CS8900_PP_ADDR_INTNO = 0x0022, /* i RW - 3.2., p. 17 - 4.3., p. 41 */ + CS8900_PP_ADDR_DMA_CHAN = 0x0024, /* i RW - 3.2., p. 17 - 4.3., p. 41 */ + CS8900_PP_ADDR_DMA_SOF = 0x0026, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */ + CS8900_PP_ADDR_DMA_FC = 0x0028, /* ? R- - 4.3., p. 41, "Receive DMA" */ + CS8900_PP_ADDR_RXDMA_BC = 0x002a, /* ? R- - 4.3., p. 41 - 5.4., p. 89 */ + CS8900_PP_ADDR_MEMBASE = 0x002c, /* i RW - 4.3., p. 41 - 4.9., p. 73 */ + CS8900_PP_ADDR_BPROM_BASE = 0x0030, /* i RW - 3.6., p. 24 - 4.3., p. 41 */ + CS8900_PP_ADDR_BPROM_MASK = 0x0034, /* i RW - 3.6., p. 24 - 4.3., p. 41 */ /* 0x0038 - 0x003F: reserved */ - CS8900_PP_ADDR_EEPROM_CMD = 0x0040, /* i RW - 3.5., p. 23 - 4.3., p. 41 */ - CS8900_PP_ADDR_EEPROM_DATA = 0x0042, /* i RW - 3.5., p. 23 - 4.3., p. 41 */ + CS8900_PP_ADDR_EEPROM_CMD = 0x0040, /* i RW - 3.5., p. 23 - 4.3., p. 41 */ + CS8900_PP_ADDR_EEPROM_DATA = 0x0042, /* i RW - 3.5., p. 23 - 4.3., p. 41 */ /* 0x0044 - 0x004F: reserved */ - CS8900_PP_ADDR_REC_FRAME_BC = 0x0050, /* RW - 4.3., p. 41 - 5.2.9., p. 86 */ + CS8900_PP_ADDR_REC_FRAME_BC = 0x0050, /* RW - 4.3., p. 41 - 5.2.9., p. 86 */ /* 0x0052 - 0x00FF: reserved */ - CS8900_PP_ADDR_CONF_CTRL = 0x0100, /* - RW - 4.4., p. 46; see below */ - CS8900_PP_ADDR_STATUS_EVENT = 0x0120, /* - R- - 4.4., p. 46; see below */ + CS8900_PP_ADDR_CONF_CTRL = 0x0100, /* - RW - 4.4., p. 46; see below */ + CS8900_PP_ADDR_STATUS_EVENT = 0x0120, /* - R- - 4.4., p. 46; see below */ /* 0x0140 - 0x0143: reserved */ - CS8900_PP_ADDR_TXCMD = 0x0144, /* # -W - 4.5., p. 70 - 5.7., p. 98 */ - CS8900_PP_ADDR_TXLENGTH = 0x0146, /* # -W - 4.5., p. 70 - 5.7., p. 98 */ + CS8900_PP_ADDR_TXCMD = 0x0144, /* # -W - 4.5., p. 70 - 5.7., p. 98 */ + CS8900_PP_ADDR_TXLENGTH = 0x0146, /* # -W - 4.5., p. 70 - 5.7., p. 98 */ /* 0x0148 - 0x014F: reserved */ - CS8900_PP_ADDR_LOG_ADDR_FILTER = 0x0150, /* RW - 4.6., p. 71 - 5.3., p. 86 */ - CS8900_PP_ADDR_MAC_ADDR = 0x0158, /* # RW - 4.6., p. 71 - 5.3., p. 86 */ + CS8900_PP_ADDR_LOG_ADDR_FILTER = 0x0150, /* RW - 4.6., p. 71 - 5.3., p. 86 */ + CS8900_PP_ADDR_MAC_ADDR = 0x0158, /* # RW - 4.6., p. 71 - 5.3., p. 86 */ /* 0x015E - 0x03FF: reserved */ - CS8900_PP_ADDR_RXSTATUS = 0x0400, /* R- - 4.7., p. 72 - 5.2., p. 78 */ - CS8900_PP_ADDR_RXLENGTH = 0x0402, /* R- - 4.7., p. 72 - 5.2., p. 78 */ - CS8900_PP_ADDR_RX_FRAMELOC = 0x0404, /* R- - 4.7., p. 72 - 5.2., p. 78 */ + CS8900_PP_ADDR_RXSTATUS = 0x0400, /* R- - 4.7., p. 72 - 5.2., p. 78 */ + CS8900_PP_ADDR_RXLENGTH = 0x0402, /* R- - 4.7., p. 72 - 5.2., p. 78 */ + CS8900_PP_ADDR_RX_FRAMELOC = 0x0404, /* R- - 4.7., p. 72 - 5.2., p. 78 */ /* here, the received frame is stored */ - CS8900_PP_ADDR_TX_FRAMELOC = 0x0A00, /* -W - 4.7., p. 72 - 5.7., p. 98 */ + CS8900_PP_ADDR_TX_FRAMELOC = 0x0A00, /* -W - 4.7., p. 72 - 5.7., p. 98 */ /* here, the frame to transmit is stored */ - CS8900_PP_ADDR_END = 0x1000, /* memory to CS8900_PP_ADDR_END-1 is used */ + CS8900_PP_ADDR_END = 0x1000, /* memory to CS8900_PP_ADDR_END-1 is used */ /* CS8900_PP_ADDR_CONF_CTRL is subdivided: */ - CS8900_PP_ADDR_CC_RXCFG = 0x0102, /* # RW - 4.4.6., p. 52 - 0003 */ - CS8900_PP_ADDR_CC_RXCTL = 0x0104, /* # RW - 4.4.8., p. 54 - 0005 */ - CS8900_PP_ADDR_CC_TXCFG = 0x0106, /* RW - 4.4.9., p. 55 - 0007 */ - CS8900_PP_ADDR_CC_TXCMD = 0x0108, /* R- - 4.4.11., p. 57 - 0009 */ - CS8900_PP_ADDR_CC_BUFCFG = 0x010A, /* RW - 4.4.12., p. 58 - 000B */ - CS8900_PP_ADDR_CC_LINECTL = 0x0112, /* # RW - 4.4.16., p. 62 - 0013 */ - CS8900_PP_ADDR_CC_SELFCTL = 0x0114, /* RW - 4.4.18., p. 64 - 0015 */ - CS8900_PP_ADDR_CC_BUSCTL = 0x0116, /* RW - 4.4.20., p. 66 - 0017 */ - CS8900_PP_ADDR_CC_TESTCTL = 0x0118, /* RW - 4.4.22., p. 68 - 0019 */ + CS8900_PP_ADDR_CC_RXCFG = 0x0102, /* # RW - 4.4.6., p. 52 - 0003 */ + CS8900_PP_ADDR_CC_RXCTL = 0x0104, /* # RW - 4.4.8., p. 54 - 0005 */ + CS8900_PP_ADDR_CC_TXCFG = 0x0106, /* RW - 4.4.9., p. 55 - 0007 */ + CS8900_PP_ADDR_CC_TXCMD = 0x0108, /* R- - 4.4.11., p. 57 - 0009 */ + CS8900_PP_ADDR_CC_BUFCFG = 0x010A, /* RW - 4.4.12., p. 58 - 000B */ + CS8900_PP_ADDR_CC_LINECTL = 0x0112, /* # RW - 4.4.16., p. 62 - 0013 */ + CS8900_PP_ADDR_CC_SELFCTL = 0x0114, /* RW - 4.4.18., p. 64 - 0015 */ + CS8900_PP_ADDR_CC_BUSCTL = 0x0116, /* RW - 4.4.20., p. 66 - 0017 */ + CS8900_PP_ADDR_CC_TESTCTL = 0x0118, /* RW - 4.4.22., p. 68 - 0019 */ /* CS8900_PP_ADDR_STATUS_EVENT is subdivided: */ - CS8900_PP_ADDR_SE_ISQ = 0x0120, /* R- - 4.4.5., p. 51 - 0000 */ - CS8900_PP_ADDR_SE_RXEVENT = 0x0124, /* # R- - 4.4.7., p. 53 - 0004 */ - CS8900_PP_ADDR_SE_TXEVENT = 0x0128, /* R- - 4.4.10., p. 56 - 0008 */ - CS8900_PP_ADDR_SE_BUFEVENT = 0x012C, /* R- - 4.4.13., p. 59 - 000C */ - CS8900_PP_ADDR_SE_RXMISS = 0x0130, /* R- - 4.4.14., p. 60 - 0010 */ - CS8900_PP_ADDR_SE_TXCOL = 0x0132, /* R- - 4.4.15., p. 61 - 0012 */ - CS8900_PP_ADDR_SE_LINEST = 0x0134, /* R- - 4.4.17., p. 63 - 0014 */ - CS8900_PP_ADDR_SE_SELFST = 0x0136, /* R- - 4.4.19., p. 65 - 0016 */ - CS8900_PP_ADDR_SE_BUSST = 0x0138, /* # R- - 4.4.21., p. 67 - 0018 */ - CS8900_PP_ADDR_SE_TDR = 0x013C /* R- - 4.4.23., p. 69 - 001C */ + CS8900_PP_ADDR_SE_ISQ = 0x0120, /* R- - 4.4.5., p. 51 - 0000 */ + CS8900_PP_ADDR_SE_RXEVENT = 0x0124, /* # R- - 4.4.7., p. 53 - 0004 */ + CS8900_PP_ADDR_SE_TXEVENT = 0x0128, /* R- - 4.4.10., p. 56 - 0008 */ + CS8900_PP_ADDR_SE_BUFEVENT = 0x012C, /* R- - 4.4.13., p. 59 - 000C */ + CS8900_PP_ADDR_SE_RXMISS = 0x0130, /* R- - 4.4.14., p. 60 - 0010 */ + CS8900_PP_ADDR_SE_TXCOL = 0x0132, /* R- - 4.4.15., p. 61 - 0012 */ + CS8900_PP_ADDR_SE_LINEST = 0x0134, /* R- - 4.4.17., p. 63 - 0014 */ + CS8900_PP_ADDR_SE_SELFST = 0x0136, /* R- - 4.4.19., p. 65 - 0016 */ + CS8900_PP_ADDR_SE_BUSST = 0x0138, /* # R- - 4.4.21., p. 67 - 0018 */ + CS8900_PP_ADDR_SE_TDR = 0x013C /* R- - 4.4.23., p. 69 - 001C */ }; enum tx_rx_min_max_e : u16 { @@ -209,21 +209,21 @@ enum tx_rx_min_max_e : u16 { }; enum cs8900_tx_state_e : u8 { - CS8900_TX_IDLE = 0, - CS8900_TX_GOT_CMD = 1, - CS8900_TX_GOT_LEN = 2, - CS8900_TX_READ_BUSST = 3 + CS8900_TX_IDLE = 0, + CS8900_TX_GOT_CMD = 1, + CS8900_TX_GOT_LEN = 2, + CS8900_TX_READ_BUSST = 3 }; enum cs8900_rx_state_e : u8 { - CS8900_RX_IDLE = 0, - CS8900_RX_GOT_FRAME = 1 + CS8900_RX_IDLE = 0, + CS8900_RX_GOT_FRAME = 1 }; enum pp_ptr_masks_e : u16 { - PP_PTR_AUTO_INCR_FLAG = 0x8000, /* auto increment flag in package pointer */ - PP_PTR_FLAG_MASK = 0xf000, /* is always : x y 1 1 (with x=auto incr) */ - PP_PTR_ADDR_MASK = 0x0fff /* address portion of packet page pointer */ + PP_PTR_AUTO_INCR_FLAG = 0x8000, /* auto increment flag in package pointer */ + PP_PTR_FLAG_MASK = 0xf000, /* is always : x y 1 1 (with x=auto incr) */ + PP_PTR_ADDR_MASK = 0x0fff /* address portion of packet page pointer */ }; #define LO_BYTE(x) (u8)((x)& 0xff) @@ -255,10 +255,10 @@ void cs8900a_device::cs8900_set_tx_status(int ready, int error) u16 new_status = old_status & ~0x180; if (ready) - new_status |= 0x100; /* set Rdy4TxNOW */ + new_status |= 0x100; /* set Rdy4TxNOW */ if (error) - new_status |= 0x080; /* set TxBidErr */ + new_status |= 0x080; /* set TxBidErr */ if (new_status != old_status) { @@ -301,39 +301,39 @@ void cs8900a_device::device_reset() SET_PP_16(CS8900_PP_ADDR_DMA_CHAN, 0x0003); /* xxxx xxxx xxxx xx11b */ /* according to descriptions of the registers, see definitions of - CS8900_PP_ADDR_CC_... and CS8900_PP_ADDR_SE_... above! */ - - SET_PP_16(CS8900_PP_ADDR_CC_RXCFG, 0x0003); - SET_PP_16(CS8900_PP_ADDR_CC_RXCTL, 0x0005); - SET_PP_16(CS8900_PP_ADDR_CC_TXCFG, 0x0007); - SET_PP_16(CS8900_PP_ADDR_CC_TXCMD, 0x0009); - SET_PP_16(CS8900_PP_ADDR_CC_BUFCFG, 0x000B); - SET_PP_16(CS8900_PP_ADDR_CC_LINECTL, 0x0013); - SET_PP_16(CS8900_PP_ADDR_CC_SELFCTL, 0x0015); - SET_PP_16(CS8900_PP_ADDR_CC_BUSCTL, 0x0017); - SET_PP_16(CS8900_PP_ADDR_CC_TESTCTL, 0x0019); - - SET_PP_16(CS8900_PP_ADDR_SE_ISQ, 0x0000); - SET_PP_16(CS8900_PP_ADDR_SE_RXEVENT, 0x0004); - SET_PP_16(CS8900_PP_ADDR_SE_TXEVENT, 0x0008); - SET_PP_16(CS8900_PP_ADDR_SE_BUFEVENT, 0x000C); - SET_PP_16(CS8900_PP_ADDR_SE_RXMISS, 0x0010); - SET_PP_16(CS8900_PP_ADDR_SE_TXCOL, 0x0012); - SET_PP_16(CS8900_PP_ADDR_SE_LINEST, 0x0014); - SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0016); - SET_PP_16(CS8900_PP_ADDR_SE_BUSST, 0x0018); - SET_PP_16(CS8900_PP_ADDR_SE_TDR, 0x001C); - - SET_PP_16(CS8900_PP_ADDR_TXCMD, 0x0009); + CS8900_PP_ADDR_CC_... and CS8900_PP_ADDR_SE_... above! */ + + SET_PP_16(CS8900_PP_ADDR_CC_RXCFG, 0x0003); + SET_PP_16(CS8900_PP_ADDR_CC_RXCTL, 0x0005); + SET_PP_16(CS8900_PP_ADDR_CC_TXCFG, 0x0007); + SET_PP_16(CS8900_PP_ADDR_CC_TXCMD, 0x0009); + SET_PP_16(CS8900_PP_ADDR_CC_BUFCFG, 0x000B); + SET_PP_16(CS8900_PP_ADDR_CC_LINECTL, 0x0013); + SET_PP_16(CS8900_PP_ADDR_CC_SELFCTL, 0x0015); + SET_PP_16(CS8900_PP_ADDR_CC_BUSCTL, 0x0017); + SET_PP_16(CS8900_PP_ADDR_CC_TESTCTL, 0x0019); + + SET_PP_16(CS8900_PP_ADDR_SE_ISQ, 0x0000); + SET_PP_16(CS8900_PP_ADDR_SE_RXEVENT, 0x0004); + SET_PP_16(CS8900_PP_ADDR_SE_TXEVENT, 0x0008); + SET_PP_16(CS8900_PP_ADDR_SE_BUFEVENT, 0x000C); + SET_PP_16(CS8900_PP_ADDR_SE_RXMISS, 0x0010); + SET_PP_16(CS8900_PP_ADDR_SE_TXCOL, 0x0012); + SET_PP_16(CS8900_PP_ADDR_SE_LINEST, 0x0014); + SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0016); + SET_PP_16(CS8900_PP_ADDR_SE_BUSST, 0x0018); + SET_PP_16(CS8900_PP_ADDR_SE_TDR, 0x001C); + + SET_PP_16(CS8900_PP_ADDR_TXCMD, 0x0009); /* 4.4.19 Self Status Register, p. 65 - Important: set INITD (Bit 7) to signal device is ready */ - SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0896); + Important: set INITD (Bit 7) to signal device is ready */ + SET_PP_16(CS8900_PP_ADDR_SE_SELFST, 0x0896); cs8900_recv_control = GET_PP_16(CS8900_PP_ADDR_CC_RXCTL); /* spec: mac address is undefined after reset. - real HW: keeps the last set address. */ + real HW: keeps the last set address. */ for (int i = 0; i < 6; i++) SET_PP_8(CS8900_PP_ADDR_MAC_ADDR + i, cs8900_ia_mac[i]); @@ -380,13 +380,13 @@ cs8900a_device::cs8900a_device(const machine_config& mconfig, device_type type, , device_network_interface(mconfig, *this, 10.0f) , cs8900_ia_mac{0, 0, 0, 0, 0, 0} , cs8900_packetpage_ptr(0) - , cs8900_recv_control(0) /* copy of CC_RXCTL (contains all bits below) */ - , cs8900_recv_broadcast(false) /* broadcast */ - , cs8900_recv_mac(false) /* individual address (IA) */ - , cs8900_recv_multicast(false) /* multicast if address passes the hash filter */ - , cs8900_recv_correct(false) /* accept correct frames */ - , cs8900_recv_promiscuous(false) /* promiscuous mode */ - , cs8900_recv_hashfilter(false) /* accept if IA passes the hash filter */ + , cs8900_recv_control(0) /* copy of CC_RXCTL (contains all bits below) */ + , cs8900_recv_broadcast(false) /* broadcast */ + , cs8900_recv_mac(false) /* individual address (IA) */ + , cs8900_recv_multicast(false) /* multicast if address passes the hash filter */ + , cs8900_recv_correct(false) /* accept correct frames */ + , cs8900_recv_promiscuous(false) /* promiscuous mode */ + , cs8900_recv_hashfilter(false) /* accept if IA passes the hash filter */ , tx_buffer(CS8900_PP_ADDR_TX_FRAMELOC) , rx_buffer(CS8900_PP_ADDR_RXSTATUS) , tx_count(0) @@ -405,8 +405,8 @@ cs8900a_device::cs8900a_device(machine_config const& mconfig, char const *tag, d {} /* - This is a helper for cs8900_receive() to determine if the received frame should be accepted - according to the settings. + This is a helper for cs8900_receive() to determine if the received frame should be accepted + according to the settings. */ bool cs8900a_device::cs8900_should_accept(unsigned char *buffer, int length, bool *phashed, int *phash_index, bool *pcorrect_mac, bool *pbroadcast, bool *pmulticast) @@ -419,8 +419,8 @@ bool cs8900a_device::cs8900_should_accept(unsigned char *buffer, int length, boo *phashed = false; *phash_index = 0; *pcorrect_mac = false; - *pbroadcast = false; - *pmulticast = false; + *pbroadcast = false; + *pmulticast = false; LOGMASKED(CS8900_DEBUG_FRAMES, "cs8900_should_accept called with %02X:%02X:%02X:%02X:%02X:%02X, length=%4u", cs8900_ia_mac[0], cs8900_ia_mac[1], cs8900_ia_mac[2], @@ -496,8 +496,8 @@ u16 cs8900a_device::cs8900_receive() u8 buffer[MAX_RXLENGTH]; int len; - bool hashed = false; - int hash_index = 0; + bool hashed = false; + int hash_index = 0; bool rx_ok = false; bool correct_mac = false; bool broadcast = false; @@ -536,7 +536,7 @@ u16 cs8900a_device::cs8900_receive() { /* we already know the type of frame: Trust it! */ LOGMASKED(CS8900_DEBUG_FRAMES, "+++ cs8900_receive(): *** hashed=%u, correct_mac=%u, " - "broadcast=%u", hashed, correct_mac, broadcast); + "broadcast=%u", hashed, correct_mac, broadcast); } else { @@ -619,21 +619,21 @@ u16 cs8900a_device::cs8900_receive() } /* ------------------------------------------------------------------------- */ -/* reading and writing IO register functions */ +/* reading and writing IO register functions */ /* - These registers are currently fully or partially supported: - - CS8900_PP_ADDR_CC_RXCFG 0x0102 * # RW - 4.4.6., p. 52 - 0003 * - CS8900_PP_ADDR_CC_RXCTL 0x0104 * # RW - 4.4.8., p. 54 - 0005 * - CS8900_PP_ADDR_CC_LINECTL 0x0112 * # RW - 4.4.16., p. 62 - 0013 * - CS8900_PP_ADDR_SE_RXEVENT 0x0124 * # R- - 4.4.7., p. 53 - 0004 * - CS8900_PP_ADDR_SE_BUSST 0x0138 * # R- - 4.4.21., p. 67 - 0018 * - CS8900_PP_ADDR_TXCMD 0x0144 * # -W - 4.5., p. 70 - 5.7., p. 98 * - CS8900_PP_ADDR_TXLENGTH 0x0146 * # -W - 4.5., p. 70 - 5.7., p. 98 * - CS8900_PP_ADDR_MAC_ADDR 0x0158 * # RW - 4.6., p. 71 - 5.3., p. 86 * - 0x015a - 0x015c + These registers are currently fully or partially supported: + + CS8900_PP_ADDR_CC_RXCFG 0x0102 * # RW - 4.4.6., p. 52 - 0003 * + CS8900_PP_ADDR_CC_RXCTL 0x0104 * # RW - 4.4.8., p. 54 - 0005 * + CS8900_PP_ADDR_CC_LINECTL 0x0112 * # RW - 4.4.16., p. 62 - 0013 * + CS8900_PP_ADDR_SE_RXEVENT 0x0124 * # R- - 4.4.7., p. 53 - 0004 * + CS8900_PP_ADDR_SE_BUSST 0x0138 * # R- - 4.4.21., p. 67 - 0018 * + CS8900_PP_ADDR_TXCMD 0x0144 * # -W - 4.5., p. 70 - 5.7., p. 98 * + CS8900_PP_ADDR_TXLENGTH 0x0146 * # -W - 4.5., p. 70 - 5.7., p. 98 * + CS8900_PP_ADDR_MAC_ADDR 0x0158 * # RW - 4.6., p. 71 - 5.3., p. 86 * + 0x015a + 0x015c */ /* ------------------------------------------------------------------------- */ @@ -674,7 +674,7 @@ void cs8900a_device::cs8900_write_tx_buffer(u8 value, int odd_address) /* full frame transmitted? */ if (tx_count == tx_length) { - LOGMASKED(CS8900_DEBUG_FRAMES, "cs8900_arch_transmit() called with: " + LOGMASKED(CS8900_DEBUG_FRAMES, "cs8900_arch_transmit() called with:\t\t\t\t\t\t\t\t\t" "length=%4u and buffer %s", tx_length, debug_outbuffer(tx_length, &cs8900_packetpage[CS8900_PP_ADDR_TX_FRAMELOC]) ); @@ -714,19 +714,19 @@ u8 cs8900a_device::cs8900_read_rx_buffer(int odd_address) else { /* - According to the CS8900 spec, the handling is the following: - first read H, then L (RX_STATUS), then H, then L (RX_LENGTH). - Inside the RX frame data, we always get L then H, until the end is reached. - - even odd - CS8900_PP_ADDR_RXSTATUS: - proceed - CS8900_PP_ADDR_RXLENGTH: - proceed - CS8900_PP_ADDR_RX_FRAMELOC: - - - CS8900_PP_ADDR_RX_FRAMELOC+2: proceed - - CS8900_PP_ADDR_RX_FRAMELOC+4: proceed - + According to the CS8900 spec, the handling is the following: + first read H, then L (RX_STATUS), then H, then L (RX_LENGTH). + Inside the RX frame data, we always get L then H, until the end is reached. + + even odd + CS8900_PP_ADDR_RXSTATUS: - proceed + CS8900_PP_ADDR_RXLENGTH: - proceed + CS8900_PP_ADDR_RX_FRAMELOC: - - + CS8900_PP_ADDR_RX_FRAMELOC+2: proceed - + CS8900_PP_ADDR_RX_FRAMELOC+4: proceed - */ u16 addr = odd_address ? 1 : 0; - u8 value; + u8 value; /* read RXSTATUS or RX_LENGTH */ if (rx_count < 4) @@ -769,7 +769,7 @@ u8 cs8900a_device::cs8900_read_rx_buffer(int odd_address) /* handle side-effects of read and write operations */ /* - This is called *after* the relevant octets are written + This is called *after* the relevant octets are written */ void cs8900a_device::cs8900_sideeffects_write_pp(u16 ppaddress, int odd_address) { @@ -934,7 +934,7 @@ void cs8900a_device::cs8900_sideeffects_write_pp(u16 ppaddress, int odd_address) } /* - This is called *before* the relevant octets are read + This is called *before* the relevant octets are read */ void cs8900a_device::cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address) { @@ -946,10 +946,10 @@ void cs8900a_device::cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address) { int access_mask = (odd_address) ? 1 : 2; - /* update the status register only if the full word of the last - status was read! unfortunately different access patterns are - possible: either the status is read LH, LH, LH... - or HL, HL, HL, or even L, L, L or H, H, H */ + /* update the status register only if the full word of the last + status was read! unfortunately different access patterns are + possible: either the status is read LH, LH, LH... + or HL, HL, HL, or even L, L, L or H, H, H */ if ((access_mask & rxevent_read_mask) != 0) { /* receiver is not enabled */ @@ -962,8 +962,8 @@ void cs8900a_device::cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address) /* perform frame reception */ u16 ret_val = cs8900_receive(); - /* RXSTATUS and RXEVENT are the same, except that RXSTATUS buffers - the old value while RXEVENT sets a new value whenever it is called + /* RXSTATUS and RXEVENT are the same, except that RXSTATUS buffers + the old value while RXEVENT sets a new value whenever it is called */ SET_PP_16(CS8900_PP_ADDR_RXSTATUS, ret_val); SET_PP_16(CS8900_PP_ADDR_SE_RXEVENT, ret_val); @@ -1399,11 +1399,11 @@ void cs8900a_device::cs8900_store(u16 io_address, u8 var) if (reg_base == CS8900_ADDR_PP_PTR) { - /* cv: we store the full package pointer in cs8900_packetpage_ptr variable. - this includes the mask area (0xf000) and the addr range (0x0fff). - we ensure that the bits 0x3000 are always set (as in real HW). - odd values of the pointer are valid and supported. - only register read and write have to be mapped to word boundary. */ + /* cv: we store the full package pointer in cs8900_packetpage_ptr variable. + this includes the mask area (0xf000) and the addr range (0x0fff). + we ensure that the bits 0x3000 are always set (as in real HW). + odd values of the pointer are valid and supported. + only register read and write have to be mapped to word boundary. */ word_value |= 0x3000; cs8900_packetpage_ptr = word_value; LOGMASKED(CS8900_DEBUG_STORE, "set PP Ptr to $%04X.\n", cs8900_packetpage_ptr); diff --git a/src/devices/machine/cs8900a.h b/src/devices/machine/cs8900a.h index 69931c583e5..74e4c8b20b3 100644 --- a/src/devices/machine/cs8900a.h +++ b/src/devices/machine/cs8900a.h @@ -3,11 +3,11 @@ /************************************************************************* - CS8900A ethernet controller implementation + CS8900A ethernet controller implementation - by Rhett Aultman <roadriverrail@gmail.com> - ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/) - VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de> + by Rhett Aultman <roadriverrail@gmail.com> + ported to MAME from VICE Project (https://sourceforge.net/p/vice-emu/) + VICE CS8900 code by Spiro Trikaliotis <Spiro.Trikaliotis@gmx.de> **************************************************************************/ @@ -19,7 +19,7 @@ #include <queue> /*************************************************************************** - TYPE DEFINITIONS + TYPE DEFINITIONS ***************************************************************************/ class cs8900a_device : public device_t, public device_network_interface { @@ -57,13 +57,13 @@ private: u16 cs8900_packetpage_ptr; /* reveiver setup */ - u16 cs8900_recv_control; /* copy of CC_RXCTL (contains all bits below) */ - bool cs8900_recv_broadcast; /* broadcast */ - bool cs8900_recv_mac; /* individual address (IA) */ - bool cs8900_recv_multicast; /* multicast if address passes the hash filter */ - bool cs8900_recv_correct; /* accept correct frames */ - bool cs8900_recv_promiscuous; /* promiscuous mode */ - bool cs8900_recv_hashfilter; /* accept if IA passes the hash filter */ + u16 cs8900_recv_control; /* copy of CC_RXCTL (contains all bits below) */ + bool cs8900_recv_broadcast; /* broadcast */ + bool cs8900_recv_mac; /* individual address (IA) */ + bool cs8900_recv_multicast; /* multicast if address passes the hash filter */ + bool cs8900_recv_correct; /* accept correct frames */ + bool cs8900_recv_promiscuous; /* promiscuous mode */ + bool cs8900_recv_hashfilter; /* accept if IA passes the hash filter */ u16 tx_buffer; u16 rx_buffer; @@ -90,7 +90,7 @@ private: void cs8900_set_transmitter(int enabled); bool cs8900_should_accept(unsigned char *buffer, int length, bool *phashed, int *phash_index, bool *pcorrect_mac, bool *pbroadcast, bool *pmulticast); u16 cs8900_receive(void); - void cs8900_write_tx_buffer(u8 value, int odd_address); + void cs8900_write_tx_buffer(u8 value, int odd_address); u8 cs8900_read_rx_buffer(int odd_address); void cs8900_sideeffects_write_pp(u16 ppaddress, int odd_address); void cs8900_sideeffects_read_pp(u16 ppaddress, int odd_address); diff --git a/src/devices/machine/generalplus_gpl16250soc.cpp b/src/devices/machine/generalplus_gpl16250soc.cpp index 2548929027c..d9bd2edc92c 100644 --- a/src/devices/machine/generalplus_gpl16250soc.cpp +++ b/src/devices/machine/generalplus_gpl16250soc.cpp @@ -219,12 +219,12 @@ void sunplus_gcm394_base_device::trigger_systemm_dma(int channel) // mem.write_word(0x4d8d4, 0x4841); // golden tee IRQ? wait hack //if (mem.read_word(0x3510f) == 0x4845) - // mem.write_word(0x3510f, 0x4840); // camp rock force service mode + // mem.write_word(0x3510f, 0x4840); // camp rock force service mode if (mem.read_word(0x4abe7) == 0x4840) mem.write_word(0x4abe7, 0x4841); // camp rock IRQ? wait hack - + // clear params after operation m_dma_params[0][channel] = m_dma_params[0][channel] & 0x00f7; diff --git a/src/devices/sound/gaelco.cpp b/src/devices/sound/gaelco.cpp index 52e71a606c6..2a213408095 100644 --- a/src/devices/sound/gaelco.cpp +++ b/src/devices/sound/gaelco.cpp @@ -181,8 +181,8 @@ void gaelco_gae1_device::sound_stream_update(sound_stream &stream, std::vector<r outputs[1].put_int(j, output_r, 32768); } -// if (wavraw) -// wav_add_data_buffer(wavraw, outputs[0], outputs[1]); +// if (wavraw) +// wav_add_data_buffer(wavraw, outputs[0], outputs[1]); } /*============================================================================ diff --git a/src/devices/sound/hc55516.cpp b/src/devices/sound/hc55516.cpp index 4ee6667ede4..5414f378802 100644 --- a/src/devices/sound/hc55516.cpp +++ b/src/devices/sound/hc55516.cpp @@ -188,10 +188,10 @@ void hc55516_device::process_digit() m_next_sample = temp; /* compress the sample range to fit better in a 16-bit word */ -/* if (temp < 0) - m_next_sample = (int)(temp / (-temp * (1.0 / 32768.0) + 1.0)); - else - m_next_sample = (int)(temp / (temp * (1.0 / 32768.0) + 1.0));*/ +/* if (temp < 0) + m_next_sample = (int)(temp / (-temp * (1.0 / 32768.0) + 1.0)); + else + m_next_sample = (int)(temp / (temp * (1.0 / 32768.0) + 1.0));*/ } void hc55516_device::clock_w(int state) diff --git a/src/devices/sound/votrax.cpp b/src/devices/sound/votrax.cpp index 000a568d2a3..f3a6e4d9234 100644 --- a/src/devices/sound/votrax.cpp +++ b/src/devices/sound/votrax.cpp @@ -489,7 +489,7 @@ void votrax_sc01_device::chip_update() m_noise = ((m_noise << 1) & 0x7ffe) | inp; m_cur_noise = !(((m_noise >> 14) ^ (m_noise >> 13)) & 1); - // logerror("%s tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", machine().time().to_string(), m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 3, m_pitch & 7, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure); + // logerror("%s tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", machine().time().to_string(), m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 3, m_pitch & 7, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure); } void votrax_sc01_device::filters_commit(bool force) diff --git a/src/devices/video/ppu2c0x.cpp b/src/devices/video/ppu2c0x.cpp index c92af287081..6dccd546a35 100644 --- a/src/devices/video/ppu2c0x.cpp +++ b/src/devices/video/ppu2c0x.cpp @@ -419,7 +419,7 @@ void ppu2c0x_device::init_palette_tables() m_nespens[entry] = (uint32_t)col; entry++; - + } } } diff --git a/src/devices/video/ppu2c0x_sh6578.cpp b/src/devices/video/ppu2c0x_sh6578.cpp index 8187856bc34..66ede857004 100644 --- a/src/devices/video/ppu2c0x_sh6578.cpp +++ b/src/devices/video/ppu2c0x_sh6578.cpp @@ -174,7 +174,7 @@ void ppu_sh6578_device::draw_background(uint8_t* line_priority) { color_mask = 0xff; } - + /* cache the background pen */ pen_t back_pen = m_nespens[m_back_color & color_mask]; diff --git a/src/devices/video/ppu2c0x_vt.cpp b/src/devices/video/ppu2c0x_vt.cpp index 5f160a98ff1..739b5490c8f 100644 --- a/src/devices/video/ppu2c0x_vt.cpp +++ b/src/devices/video/ppu2c0x_vt.cpp @@ -146,7 +146,7 @@ void ppu_vt03_device::init_vtxx_rgb555_palette_tables() { for (int palval = 0; palval < 0x8000; palval++) { - // uint16_t rgbval = (m_palette_ram[i & 0x7f] & 0xff) | ((m_palette_ram[(i & 0x7f) + 0x80] & 0xff) << 8); + // uint16_t rgbval = (m_palette_ram[i & 0x7f] & 0xff) | ((m_palette_ram[(i & 0x7f) + 0x80] & 0xff) << 8); uint8_t blue = (palval & 0x001f) << 3; uint8_t green = (palval & 0x3e0) >> 2; uint8_t red = (palval & 0x7C00) >> 7; @@ -364,7 +364,7 @@ void ppu_vt03_device::draw_sprite_pixel(int sprite_xpos, int color, int pixel, u if (!is16pix) { uint8_t pen = pixel_data + (4 * color); - draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel)); + draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel)); } else { @@ -374,13 +374,13 @@ void ppu_vt03_device::draw_sprite_pixel(int sprite_xpos, int color, int pixel, u if ((pixel_data & 0x03) != 0) { uint8_t pen = (pixel_data & 0x03) + (4 * color); - draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel)); + draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel)); } if (((pixel_data >> 5) & 0x03) != 0) { uint8_t pen = ((pixel_data >> 5) & 0x03) + (4 * color); - draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel + 8)); + draw_tile_pixel_inner(pen, &bitmap.pix32(m_scanline, sprite_xpos + pixel + 8)); } //ppu2c0x_device::draw_sprite_pixel(sprite_xpos, color, pixel, pixel_data & 0x03, bitmap); //ppu2c0x_device::draw_sprite_pixel(sprite_xpos, color, pixel + 8, (pixel_data >> 5) & 0x03, bitmap); @@ -450,7 +450,7 @@ void ppu_vt03_device::draw_tile_pixel_inner(uint8_t pen, uint32_t *dest) // does grayscale mode exist here? (we haven't calculated any colours for it) //if (m_regs[PPU_CONTROL1] & PPU_CONTROL1_DISPLAY_MONO) - // palval &= 0x30; + // palval &= 0x30; // apply colour emphasis (does it really exist here?) (we haven't calculated any colours for it, so ths has no effect) palval |= ((m_regs[PPU_CONTROL1] & PPU_CONTROL1_COLOR_EMPHASIS) << 10); @@ -466,7 +466,7 @@ void ppu_vt03_device::draw_tile_pixel_inner(uint8_t pen, uint32_t *dest) // does grayscale mode exist here? (we haven't calculated any colours for it) //if (m_regs[PPU_CONTROL1] & PPU_CONTROL1_DISPLAY_MONO) - // palval &= 0x30; + // palval &= 0x30; // apply colour emphasis (does it really exist here?) (we haven't calculated any colours for it, so ths has no effect) palval |= ((m_regs[PPU_CONTROL1] & PPU_CONTROL1_COLOR_EMPHASIS) << 7); @@ -482,7 +482,7 @@ void ppu_vt03_device::draw_tile_pixel_inner(uint8_t pen, uint32_t *dest) // does grayscale mode exist here? (we haven't calculated any colours for it) //if (m_regs[PPU_CONTROL1] & PPU_CONTROL1_DISPLAY_MONO) - // palval &= 0x30; + // palval &= 0x30; // apply colour emphasis (does it really exist here?) (we calculate values for it when building the palette lookup) palval |= ((m_regs[PPU_CONTROL1] & PPU_CONTROL1_COLOR_EMPHASIS) << 7); @@ -539,7 +539,7 @@ void ppu_vt03_device::draw_tile_pixel(uint8_t pix, int color, uint32_t back_pen, pen = 0; // back_pen; // fixme backpen logic probably differs on vt03 due to extra colours } - draw_tile_pixel_inner(pen, dest); + draw_tile_pixel_inner(pen, dest); } } |