diff options
Diffstat (limited to 'src/devices/machine')
| -rw-r--r-- | src/devices/machine/i8271.cpp | 1 | ||||
| -rw-r--r-- | src/devices/machine/k053252.cpp | 12 | ||||
| -rw-r--r-- | src/devices/machine/k053252.h | 10 | ||||
| -rw-r--r-- | src/devices/machine/laserdsc.cpp | 2 | ||||
| -rw-r--r-- | src/devices/machine/pdc.cpp | 194 | ||||
| -rw-r--r-- | src/devices/machine/pdc.h | 20 | ||||
| -rw-r--r-- | src/devices/machine/pla.cpp | 2 | ||||
| -rw-r--r-- | src/devices/machine/tms6100.cpp | 2 | ||||
| -rw-r--r-- | src/devices/machine/upd765.cpp | 1 | ||||
| -rw-r--r-- | src/devices/machine/z80ctc.cpp | 2 | ||||
| -rw-r--r-- | src/devices/machine/z80scc.h | 2 |
11 files changed, 121 insertions, 127 deletions
diff --git a/src/devices/machine/i8271.cpp b/src/devices/machine/i8271.cpp index 3d1d602dd74..cd8c0faf5bf 100644 --- a/src/devices/machine/i8271.cpp +++ b/src/devices/machine/i8271.cpp @@ -1541,7 +1541,6 @@ void i8271_device::device_timer(emu_timer &timer, device_timer_id id, int param, void i8271_device::index_callback(floppy_image_device *floppy, int state) { for(auto & fi : flopi) { - if(fi.dev != floppy) continue; diff --git a/src/devices/machine/k053252.cpp b/src/devices/machine/k053252.cpp index 6bd561233b4..45020926ace 100644 --- a/src/devices/machine/k053252.cpp +++ b/src/devices/machine/k053252.cpp @@ -123,7 +123,7 @@ void k053252_device::device_reset() m_regs[i] = 0; m_regs[0x08] = 1; // Xexex apparently does a wrong assignment for VC (sets up the INT enable register instead) - + reset_internal_state(); } @@ -173,14 +173,14 @@ void k053252_device::res_change() //(HC+1) - HFP - HBP - 8*(HSW+1) //VC - VFP - VBP - (VSW+1) attoseconds_t refresh = HZ_TO_ATTOSECONDS(clock()) * (m_hc) * m_vc; - + visarea.min_x = m_offsx; visarea.min_y = m_offsy; visarea.max_x = m_offsx + m_hc - m_hfp - m_hbp - 8*(m_hsw) - 1; visarea.max_y = m_offsy + m_vc - m_vfp - m_vbp - (m_vsw) - 1; - + m_screen->configure(m_hc, m_vc, visarea, refresh); - + if (m_slave_screen) m_slave_screen->configure(m_hc, m_vc, visarea, refresh); @@ -189,7 +189,7 @@ void k053252_device::res_change() printf("H %d HFP %d HSW %d HBP %d\n",m_hc,m_hfp,m_hsw*8,m_hbp); printf("V %d VFP %d VSW %d VBP %d\n",m_vc,m_vfp,m_vsw,m_vbp); // L stands for Legacy ... - printf("L %d %d\n",m_offsx,m_offsy); + printf("L %d %d\n",m_offsx,m_offsy); printf("Screen params: Clock: %u V-Sync %.2f H-Sync %.f\n",clock(),ATTOSECONDS_TO_HZ(refresh),ATTOSECONDS_TO_HZ(hsync)); printf("visible screen area: %d x %d\n\n",(visarea.max_x - visarea.min_x) + 1,(visarea.max_y - visarea.min_y) + 1); #endif @@ -251,7 +251,7 @@ WRITE8_MEMBER( k053252_device::write ) logerror("%02x VSW / %02x HSW set\n",m_vsw,m_hsw); res_change(); break; - + //case 0x0d: m_int_time(data); break; case 0x0e: m_int1_ack_cb(1); break; case 0x0f: m_int2_ack_cb(1); break; diff --git a/src/devices/machine/k053252.h b/src/devices/machine/k053252.h index a33b0f60698..a00743789ad 100644 --- a/src/devices/machine/k053252.h +++ b/src/devices/machine/k053252.h @@ -48,18 +48,18 @@ public: DECLARE_WRITE8_MEMBER( write ); void res_change(); - - + + static void static_set_slave_screen(device_t &device, const char *tag); protected: // device-level overrides virtual void device_start() override; - virtual void device_reset() override; + virtual void device_reset() override; virtual void device_clock_changed() override { reset_internal_state(); } void reset_internal_state(); - + private: // internal state UINT8 m_regs[16]; @@ -75,7 +75,7 @@ protected: int m_offsx; int m_offsy; - const char * m_slave_screen_tag; + const char * m_slave_screen_tag; screen_device * m_slave_screen; }; diff --git a/src/devices/machine/laserdsc.cpp b/src/devices/machine/laserdsc.cpp index b8ecf53611c..7dbae408ba7 100644 --- a/src/devices/machine/laserdsc.cpp +++ b/src/devices/machine/laserdsc.cpp @@ -805,7 +805,7 @@ void laserdisc_device::init_video() for (auto & frame : m_frame) { // first allocate a YUY16 bitmap at 2x the height - + frame.m_bitmap.allocate(m_width, m_height * 2); frame.m_bitmap.set_palette(m_videopalette); fillbitmap_yuy16(frame.m_bitmap, 40, 109, 240); diff --git a/src/devices/machine/pdc.cpp b/src/devices/machine/pdc.cpp index 0df1621f980..4a882d12a04 100644 --- a/src/devices/machine/pdc.cpp +++ b/src/devices/machine/pdc.cpp @@ -7,87 +7,87 @@ **********************************************************************/ /* - Device PDCN - Board Copyright - IBM Corp 1989 Made in USA - - Labels: - * 96D1975 - MN 90594C - - * EC# A6466SP - MFG 85575 - - Hardware: - * CPU - Zilog Z0840006PSC Z80 @ 5MHz - U19 - * FDC - NEC D765AC-2 9002P7004 - U35 - * HDC - HDC9224 SMC E8838 8/90 - U59 - * DMA - P8237A-5 L1041330 - U34 - * Channel 0 - FDC - * Channel 1 - Main system ram - * Memory - HM6264ALP-12 SRAM 8KB - U16 - * Memory - HM6116P-2 SRAM 2KB - U33 - Logic: - * U1 - PLS105AN Label: 59D9101 - * U11 - ?? Label: 59D10001 - * U27 - ?? Label: 96D1978 - * U28 - ?? Label: 97D8750 - * U31 - TIBPAL20L8-25CNT Label: 96D1987 - * U32 - ?? Label: 59D1001 - * U37 - PLS100N Label: 72D2701 - * U38 - PLS100N Label: 58D9201 - * U39 - ?? Label: 96D1981 - * U40 - ?? Label: 96D1984 - * U68 - ?? Label: 91D4301 - * U69 - ?? Label: 59D1001 - * U70 - ?? Label: 59D1001 - - Switches: - * S1 - Hard drive format configuration (Default all off) - * S2 - Floppy drive format configuration (Default 1-7 off, 8 on) - - Program Memory: - * 0x0000 - 0x3FFF : ROM 27128 Label: 97D9988 - * 0x8000 - 0x9FFF : SRAM HM6264ALP-12 8KB - * 0xC000 - 0xC7FF : SRAM HM6116P-2 2KB - - IO Memory: - * 0x00 - 0x01 : Old style command [0x5FF041B0] - * 0x02 - 0x03 : FDC command address [0x5FF0C0B0][0x5FF0C1B0] - * 0x04 - 0x05 : FDC command completion status [0x5FF030B0] - * 0x06 - 0x07 : FDC data address [0x5FF080B0] - * 0x10 - 0x18 : HDC registers (unknown) - * 0x21 - 0x21 : FDC unknown, resets bit 1 on 0x38 - * 0x22 - 0x22 : FDC unknown - * 0x23 - 0x24 : FDC Active DMA host address (auto increments) - * 0x25 - 0x25 : FDC unknown - * 0x26 - 0x26 : DREQ1 on - * 0x27 - 0x27 : FDC unknown - * 0x28 - 0x2A : Possibly LED lights - * 0x2C - 0x2C : DREQ1 off - * 0x2D - 0x2D : Unknown - * 0x2E - 0x2E : Transfer direction 0x80 = PDC -> Host (read data) - 0x00 = Host -> PDC (Commands, write data) - * 0x2F - 0x2F : Unknown - * 0x38 - 0x38 : FDC command request - Bit 1: Debug? - Bit 2: Command complete - Bit 3: Unknown - Bit 5: Unknown - Bit 6-7: Error conditions - * 0x39 - 0x39 : Interrupt status - Bit 0: HDC9224 interrupt - Bit 1: Incoming command - Bit 3: FDD related, maybe uPD interrupt pin? - * 0x3C - 0x3D : Dipswitch 2 and 1 - * 0x40 - 0x40 : HDC9224 DATA register - * 0x41 - 0x41 : HDC9224 COMMAND register - * 0x42 - 0x42 : uPD765 STATUS register - * 0x43 - 0x43 : uPD765 DATA register - * 0x50 - 0x51 : Unknown - reset latch maybe? - * 0x52 - 0x52 : FDD Master motor control - * 0x53 - 0x53 : Unknown - * 0x54 - 0x57 : FDD motor control (Units 1-4) - * 0x60 - 0x6F : P8237A DMA controller register set + Device PDCN + Board Copyright - IBM Corp 1989 Made in USA + + Labels: + * 96D1975 + MN 90594C + + * EC# A6466SP + MFG 85575 + + Hardware: + * CPU - Zilog Z0840006PSC Z80 @ 5MHz - U19 + * FDC - NEC D765AC-2 9002P7004 - U35 + * HDC - HDC9224 SMC E8838 8/90 - U59 + * DMA - P8237A-5 L1041330 - U34 + * Channel 0 - FDC + * Channel 1 - Main system ram + * Memory - HM6264ALP-12 SRAM 8KB - U16 + * Memory - HM6116P-2 SRAM 2KB - U33 + Logic: + * U1 - PLS105AN Label: 59D9101 + * U11 - ?? Label: 59D10001 + * U27 - ?? Label: 96D1978 + * U28 - ?? Label: 97D8750 + * U31 - TIBPAL20L8-25CNT Label: 96D1987 + * U32 - ?? Label: 59D1001 + * U37 - PLS100N Label: 72D2701 + * U38 - PLS100N Label: 58D9201 + * U39 - ?? Label: 96D1981 + * U40 - ?? Label: 96D1984 + * U68 - ?? Label: 91D4301 + * U69 - ?? Label: 59D1001 + * U70 - ?? Label: 59D1001 + + Switches: + * S1 - Hard drive format configuration (Default all off) + * S2 - Floppy drive format configuration (Default 1-7 off, 8 on) + + Program Memory: + * 0x0000 - 0x3FFF : ROM 27128 Label: 97D9988 + * 0x8000 - 0x9FFF : SRAM HM6264ALP-12 8KB + * 0xC000 - 0xC7FF : SRAM HM6116P-2 2KB + + IO Memory: + * 0x00 - 0x01 : Old style command [0x5FF041B0] + * 0x02 - 0x03 : FDC command address [0x5FF0C0B0][0x5FF0C1B0] + * 0x04 - 0x05 : FDC command completion status [0x5FF030B0] + * 0x06 - 0x07 : FDC data address [0x5FF080B0] + * 0x10 - 0x18 : HDC registers (unknown) + * 0x21 - 0x21 : FDC unknown, resets bit 1 on 0x38 + * 0x22 - 0x22 : FDC unknown + * 0x23 - 0x24 : FDC Active DMA host address (auto increments) + * 0x25 - 0x25 : FDC unknown + * 0x26 - 0x26 : DREQ1 on + * 0x27 - 0x27 : FDC unknown + * 0x28 - 0x2A : Possibly LED lights + * 0x2C - 0x2C : DREQ1 off + * 0x2D - 0x2D : Unknown + * 0x2E - 0x2E : Transfer direction 0x80 = PDC -> Host (read data) + 0x00 = Host -> PDC (Commands, write data) + * 0x2F - 0x2F : Unknown + * 0x38 - 0x38 : FDC command request + Bit 1: Debug? + Bit 2: Command complete + Bit 3: Unknown + Bit 5: Unknown + Bit 6-7: Error conditions + * 0x39 - 0x39 : Interrupt status + Bit 0: HDC9224 interrupt + Bit 1: Incoming command + Bit 3: FDD related, maybe uPD interrupt pin? + * 0x3C - 0x3D : Dipswitch 2 and 1 + * 0x40 - 0x40 : HDC9224 DATA register + * 0x41 - 0x41 : HDC9224 COMMAND register + * 0x42 - 0x42 : uPD765 STATUS register + * 0x43 - 0x43 : uPD765 DATA register + * 0x50 - 0x51 : Unknown - reset latch maybe? + * 0x52 - 0x52 : FDD Master motor control + * 0x53 - 0x53 : Unknown + * 0x54 - 0x57 : FDD motor control (Units 1-4) + * 0x60 - 0x6F : P8237A DMA controller register set */ @@ -98,10 +98,10 @@ // MACROS / CONSTANTS //************************************************************************** -#define Z80_TAG "pdc_z80" // U19 +#define Z80_TAG "pdc_z80" // U19 #define FDC_TAG "fdc" -#define HDC_TAG "hdc" -#define FDCDMA_TAG "i8237dma" +#define HDC_TAG "hdc" +#define FDCDMA_TAG "i8237dma" #define TRACE_PDC_FDC 0 #define TRACE_PDC_HDC 0 @@ -119,8 +119,8 @@ const device_type PDC = &device_creator<pdc_device>; //------------------------------------------------- ROM_START( pdc ) - ROM_REGION( 0x4000, "rom", 0 ) - ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17 + ROM_REGION( 0x4000, "rom", 0 ) + ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17 ROM_END //------------------------------------------------- @@ -129,7 +129,7 @@ ROM_END const rom_entry *pdc_device::device_rom_region() const { - return ROM_NAME( pdc ); + return ROM_NAME( pdc ); } //------------------------------------------------- @@ -232,10 +232,10 @@ SLOT_INTERFACE_END //------------------------------------------------- static SLOT_INTERFACE_START( pdc_harddisks ) - SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image) - SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB) - SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB) - SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB) + SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image) + SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB) + SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB) + SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB) SLOT_INTERFACE_END //------------------------------------------------- @@ -243,7 +243,7 @@ SLOT_INTERFACE_END //------------------------------------------------- FLOPPY_FORMATS_MEMBER( pdc_device::floppy_formats ) - FLOPPY_PC_FORMAT + FLOPPY_PC_FORMAT FLOPPY_FORMATS_END //------------------------------------------------- @@ -252,8 +252,8 @@ FLOPPY_FORMATS_END static MACHINE_CONFIG_FRAGMENT( pdc ) /* CPU - Zilog Z0840006PSC */ - MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2) - MCFG_CPU_PROGRAM_MAP(pdc_mem) + MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2) + MCFG_CPU_PROGRAM_MAP(pdc_mem) MCFG_CPU_IO_MAP(pdc_io) //MCFG_QUANTUM_PERFECT_CPU(M6502_TAG) @@ -290,7 +290,7 @@ MACHINE_CONFIG_END machine_config_constructor pdc_device::device_mconfig_additions() const { - return MACHINE_CONFIG_NAME( pdc ); + return MACHINE_CONFIG_NAME( pdc ); } ioport_constructor pdc_device::device_input_ports() const @@ -308,7 +308,7 @@ ioport_constructor pdc_device::device_input_ports() const pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, PDC, "ROLM PDC", tag, owner, clock, "pdc", __FILE__), - m_pdccpu(*this, Z80_TAG), + m_pdccpu(*this, Z80_TAG), m_dma8237(*this, FDCDMA_TAG), m_fdc(*this, FDC_TAG), m_hdc9224(*this, HDC_TAG), @@ -338,7 +338,7 @@ void pdc_device::device_reset() //reg_p38 |= 0x20; // no idea at all - bit 5 (32) /* Reset CPU */ - m_pdccpu->reset(); + m_pdccpu->reset(); /* Resolve callbacks */ m_m68k_r_cb.resolve_safe(0); diff --git a/src/devices/machine/pdc.h b/src/devices/machine/pdc.h index ac085ea02cd..c1f3a3cbf51 100644 --- a/src/devices/machine/pdc.h +++ b/src/devices/machine/pdc.h @@ -34,11 +34,11 @@ class pdc_device : public device_t { public: - /* Constructor and Destructor */ + /* Constructor and Destructor */ pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - /* Optional information overrides */ - virtual machine_config_constructor device_mconfig_additions() const override; + /* Optional information overrides */ + virtual machine_config_constructor device_mconfig_additions() const override; virtual ioport_constructor device_input_ports() const override; virtual const rom_entry *device_rom_region() const override; @@ -69,7 +69,7 @@ public: DECLARE_WRITE8_MEMBER(m68k_dma_w); DECLARE_WRITE_LINE_MEMBER(fdc_irq); - DECLARE_FLOPPY_FORMATS( floppy_formats ); + DECLARE_FLOPPY_FORMATS( floppy_formats ); /* Main CPU accessible registers */ UINT8 reg_p0; @@ -84,16 +84,16 @@ public: UINT8 reg_p38; UINT32 fdd_68k_dma_address; /* FDD <-> m68k DMA read/write address */ protected: - /* Device-level overrides */ - virtual void device_start() override; - virtual void device_reset() override; + /* Device-level overrides */ + virtual void device_start() override; + virtual void device_reset() override; /* Protected variables */ //UINT32 fdd_68k_dma_address; bool b_fdc_irq; /* Attached devices */ - required_device<cpu_device> m_pdccpu; + required_device<cpu_device> m_pdccpu; required_device<am9517a_device> m_dma8237; required_device<upd765a_device> m_fdc; //required_device<floppy_connector> m_floppy; @@ -103,8 +103,8 @@ protected: required_shared_ptr<UINT8> m_pdc_ram; /* Callbacks */ - devcb_read8 m_m68k_r_cb; - devcb_write8 m_m68k_w_cb; + devcb_read8 m_m68k_r_cb; + devcb_write8 m_m68k_w_cb; }; /* Device type */ diff --git a/src/devices/machine/pla.cpp b/src/devices/machine/pla.cpp index 417fb4e6c3f..f96a2bd8f60 100644 --- a/src/devices/machine/pla.cpp +++ b/src/devices/machine/pla.cpp @@ -148,8 +148,6 @@ UINT32 pla_device::read(UINT32 input) for (auto cache2_entry : m_cache2) { - - if ((UINT32)cache2_entry == input) { // cache2 hit diff --git a/src/devices/machine/tms6100.cpp b/src/devices/machine/tms6100.cpp index fc340de9247..402ba1ad7ca 100644 --- a/src/devices/machine/tms6100.cpp +++ b/src/devices/machine/tms6100.cpp @@ -206,7 +206,7 @@ WRITE_LINE_MEMBER(tms6100_device::romclock_w) UINT8 word = m_rom[m_address >> 3]; if (m_reverse_bits) word = BITSWAP8(word,0,1,2,3,4,5,6,7); - + if (m_4bit_read) { m_data = word >> (m_address & 4) & 0xf; diff --git a/src/devices/machine/upd765.cpp b/src/devices/machine/upd765.cpp index 6587c44d360..48901ef2314 100644 --- a/src/devices/machine/upd765.cpp +++ b/src/devices/machine/upd765.cpp @@ -2247,7 +2247,6 @@ void upd765_family_device::run_drive_ready_polling() void upd765_family_device::index_callback(floppy_image_device *floppy, int state) { for(auto & fi : flopi) { - if(fi.dev != floppy) continue; diff --git a/src/devices/machine/z80ctc.cpp b/src/devices/machine/z80ctc.cpp index 13c4844c9e3..276254d96f1 100644 --- a/src/devices/machine/z80ctc.cpp +++ b/src/devices/machine/z80ctc.cpp @@ -185,8 +185,6 @@ int z80ctc_device::z80daisy_irq_state() int state = 0; for (auto & channel : m_channel) { - - // if we're servicing a request, don't indicate more interrupts if (channel.m_int_state & Z80_DAISY_IEO) { diff --git a/src/devices/machine/z80scc.h b/src/devices/machine/z80scc.h index edd0d9b6992..7f956ec9b74 100644 --- a/src/devices/machine/z80scc.h +++ b/src/devices/machine/z80scc.h @@ -137,7 +137,7 @@ public: UINT8 do_sccreg_rr5(); UINT8 do_sccreg_rr6(); UINT8 do_sccreg_rr7(); -// UINT8 do_sccreg_rr8(); +// UINT8 do_sccreg_rr8(); UINT8 do_sccreg_rr9(); UINT8 do_sccreg_rr10(); UINT8 do_sccreg_rr11(); |
