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Diffstat (limited to 'src/devices/machine/pci.h')
-rw-r--r--src/devices/machine/pci.h225
1 files changed, 131 insertions, 94 deletions
diff --git a/src/devices/machine/pci.h b/src/devices/machine/pci.h
index a9a2a84744f..3d2173de545 100644
--- a/src/devices/machine/pci.h
+++ b/src/devices/machine/pci.h
@@ -5,7 +5,6 @@
#pragma once
-
class pci_device : public device_t {
public:
typedef delegate<void ()> mapper_cb;
@@ -30,46 +29,46 @@ public:
void map_config(uint8_t device, address_space *config_space);
- virtual void config_map(address_map &map);
+ virtual void config_map(address_map &map) ATTR_COLD;
uint32_t unmapped_r(offs_t offset, uint32_t mem_mask, int bank);
void unmapped_w(offs_t offset, uint32_t data, uint32_t mem_mask, int bank);
- READ32_MEMBER (unmapped0_r);
- WRITE32_MEMBER(unmapped0_w);
- READ32_MEMBER (unmapped1_r);
- WRITE32_MEMBER(unmapped1_w);
- READ32_MEMBER (unmapped2_r);
- WRITE32_MEMBER(unmapped2_w);
- READ32_MEMBER (unmapped3_r);
- WRITE32_MEMBER(unmapped3_w);
- READ32_MEMBER (unmapped4_r);
- WRITE32_MEMBER(unmapped4_w);
- READ32_MEMBER (unmapped5_r);
- WRITE32_MEMBER(unmapped5_w);
-
-
- DECLARE_READ16_MEMBER(vendor_r);
- DECLARE_READ16_MEMBER(device_r);
- DECLARE_READ16_MEMBER(command_r);
- DECLARE_WRITE16_MEMBER(command_w);
- DECLARE_READ16_MEMBER(status_r);
- DECLARE_READ32_MEMBER(class_rev_r);
- virtual DECLARE_READ8_MEMBER(cache_line_size_r);
- virtual DECLARE_READ8_MEMBER(latency_timer_r);
- virtual DECLARE_READ8_MEMBER(header_type_r);
- virtual DECLARE_READ8_MEMBER(bist_r);
- DECLARE_READ32_MEMBER(address_base_r);
- DECLARE_WRITE32_MEMBER(address_base_w);
- DECLARE_READ16_MEMBER(subvendor_r);
- DECLARE_READ16_MEMBER(subsystem_r);
- DECLARE_READ32_MEMBER (expansion_base_r);
- DECLARE_WRITE32_MEMBER(expansion_base_w);
- virtual DECLARE_READ8_MEMBER(capptr_r);
- DECLARE_READ8_MEMBER(interrupt_line_r);
- DECLARE_WRITE8_MEMBER(interrupt_line_w);
- DECLARE_READ8_MEMBER(interrupt_pin_r);
- DECLARE_WRITE8_MEMBER(interrupt_pin_w);
+ uint32_t unmapped0_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped1_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped2_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped3_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped3_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped4_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped4_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t unmapped5_r(offs_t offset, uint32_t mem_mask = ~0);
+ void unmapped5_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+
+
+ uint16_t vendor_r();
+ uint16_t device_r();
+ uint16_t command_r();
+ void command_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t status_r();
+ uint32_t class_rev_r();
+ virtual uint8_t cache_line_size_r();
+ virtual uint8_t latency_timer_r();
+ virtual uint8_t header_type_r();
+ virtual uint8_t bist_r();
+ uint32_t address_base_r(offs_t offset);
+ void address_base_w(offs_t offset, uint32_t data);
+ uint16_t subvendor_r();
+ uint16_t subsystem_r();
+ uint32_t expansion_base_r();
+ void expansion_base_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ virtual uint8_t capptr_r();
+ uint8_t interrupt_line_r();
+ void interrupt_line_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
+ uint8_t interrupt_pin_r();
+ void interrupt_pin_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0);
protected:
pci_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@@ -102,6 +101,8 @@ protected:
int bank_count, bank_reg_count;
bank_reg_info bank_reg_infos[6];
+ class pci_root_device *m_pci_root;
+
uint32_t main_id, subsystem_id;
uint32_t pclass;
uint8_t revision;
@@ -112,8 +113,8 @@ protected:
bool is_multifunction_device;
uint8_t intr_line, intr_pin;
- virtual void device_start() override;
- virtual void device_reset() override;
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
void skip_map_regs(int count);
void add_map(uint64_t size, int flags, const address_map_constructor &map, device_t *relative_to = nullptr);
@@ -121,6 +122,10 @@ protected:
address_map_constructor delegate(map, name, static_cast<T *>(this));
add_map(size, flags, delegate);
}
+ template <typename T> void add_map(uint64_t size, int flags, T &device, void (T::*map)(address_map &map), const char *name) {
+ address_map_constructor delegate(map, name, &device);
+ add_map(size, flags, delegate, &device);
+ }
void add_rom(const uint8_t *data, uint32_t size);
void add_rom_from_region();
@@ -128,14 +133,16 @@ protected:
void set_map_address(int id, uint64_t adr);
void set_map_size(int id, uint64_t size);
void set_map_flags(int id, int flags);
+
+ inline address_space *get_pci_busmaster_space() const;
};
class agp_device : public pci_device {
protected:
agp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
- virtual void device_start() override;
- virtual void device_reset() override;
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
};
class pci_bridge_device : public pci_device, public device_memory_interface {
@@ -152,44 +159,44 @@ public:
uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
virtual void reset_all_mappings() override;
- virtual DECLARE_READ8_MEMBER(header_type_r) override;
-
- virtual void config_map(address_map &map) override;
-
- DECLARE_READ32_MEMBER (b_address_base_r);
- DECLARE_WRITE32_MEMBER(b_address_base_w);
- DECLARE_READ8_MEMBER (primary_bus_r);
- DECLARE_WRITE8_MEMBER (primary_bus_w);
- DECLARE_READ8_MEMBER (secondary_bus_r);
- DECLARE_WRITE8_MEMBER (secondary_bus_w);
- DECLARE_READ8_MEMBER (subordinate_bus_r);
- DECLARE_WRITE8_MEMBER (subordinate_bus_w);
- DECLARE_READ8_MEMBER (secondary_latency_r);
- DECLARE_WRITE8_MEMBER (secondary_latency_w);
- DECLARE_READ8_MEMBER (iobase_r);
- DECLARE_WRITE8_MEMBER (iobase_w);
- DECLARE_READ8_MEMBER (iolimit_r);
- DECLARE_WRITE8_MEMBER (iolimit_w);
- DECLARE_READ16_MEMBER (secondary_status_r);
- DECLARE_WRITE16_MEMBER(secondary_status_w);
- DECLARE_READ16_MEMBER (memory_base_r);
- DECLARE_WRITE16_MEMBER(memory_base_w);
- DECLARE_READ16_MEMBER (memory_limit_r);
- DECLARE_WRITE16_MEMBER(memory_limit_w);
- DECLARE_READ16_MEMBER (prefetch_base_r);
- DECLARE_WRITE16_MEMBER(prefetch_base_w);
- DECLARE_READ16_MEMBER (prefetch_limit_r);
- DECLARE_WRITE16_MEMBER(prefetch_limit_w);
- DECLARE_READ32_MEMBER (prefetch_baseu_r);
- DECLARE_WRITE32_MEMBER(prefetch_baseu_w);
- DECLARE_READ32_MEMBER (prefetch_limitu_r);
- DECLARE_WRITE32_MEMBER(prefetch_limitu_w);
- DECLARE_READ16_MEMBER (iobaseu_r);
- DECLARE_WRITE16_MEMBER(iobaseu_w);
- DECLARE_READ16_MEMBER (iolimitu_r);
- DECLARE_WRITE16_MEMBER(iolimitu_w);
- DECLARE_READ16_MEMBER (bridge_control_r);
- DECLARE_WRITE16_MEMBER(bridge_control_w);
+ virtual uint8_t header_type_r() override;
+
+ virtual void config_map(address_map &map) override ATTR_COLD;
+
+ uint32_t b_address_base_r(offs_t offset);
+ void b_address_base_w(offs_t offset, uint32_t data);
+ uint8_t primary_bus_r();
+ void primary_bus_w(uint8_t data);
+ uint8_t secondary_bus_r();
+ void secondary_bus_w(uint8_t data);
+ uint8_t subordinate_bus_r();
+ void subordinate_bus_w(uint8_t data);
+ uint8_t secondary_latency_r();
+ void secondary_latency_w(uint8_t data);
+ uint8_t iobase_r();
+ void iobase_w(uint8_t data);
+ uint8_t iolimit_r();
+ void iolimit_w(uint8_t data);
+ uint16_t secondary_status_r();
+ void secondary_status_w(uint16_t data);
+ uint16_t memory_base_r();
+ void memory_base_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t memory_limit_r();
+ void memory_limit_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t prefetch_base_r();
+ void prefetch_base_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t prefetch_limit_r();
+ void prefetch_limit_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint32_t prefetch_baseu_r();
+ void prefetch_baseu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t prefetch_limitu_r();
+ void prefetch_limitu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint16_t iobaseu_r();
+ void iobaseu_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t iolimitu_r();
+ void iolimitu_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bridge_control_r();
+ virtual void bridge_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
protected:
enum
@@ -199,8 +206,9 @@ protected:
pci_bridge_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
- virtual void device_start() override;
- virtual void device_reset() override;
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
+ virtual void interface_post_reset() override;
virtual space_config_vector memory_space_config() const override;
virtual device_t *bus_root();
@@ -229,24 +237,29 @@ class agp_bridge_device : public pci_bridge_device {
protected:
agp_bridge_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
- virtual void device_start() override;
- virtual void device_reset() override;
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
};
class pci_host_device : public pci_bridge_device {
public:
- void io_configuration_access_map(address_map &map);
+ void io_configuration_access_map(address_map &map) ATTR_COLD;
+
+ void set_spaces(address_space *memory, address_space *io = nullptr, address_space *busmaster = nullptr);
protected:
pci_host_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
- DECLARE_READ32_MEMBER(config_address_r);
- DECLARE_WRITE32_MEMBER(config_address_w);
- DECLARE_READ32_MEMBER(config_data_r);
- DECLARE_WRITE32_MEMBER(config_data_w);
+ uint32_t config_address_r();
+ void config_address_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t config_data_r(offs_t offset, uint32_t mem_mask = ~0);
+ void config_data_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ uint32_t config_data_ex_r(offs_t offset, uint32_t mem_mask = ~0);
+ void config_data_ex_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- virtual void device_start() override;
- virtual void device_reset() override;
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
+ virtual void interface_post_reset() override;
virtual device_t *bus_root() override;
@@ -255,23 +268,47 @@ protected:
void regenerate_mapping();
- address_space *memory_space, *io_space;
-
uint64_t memory_window_start, memory_window_end, memory_offset;
uint64_t io_window_start, io_window_end, io_offset;
uint32_t config_address;
+
+private:
+ address_space *memory_space, *io_space;
};
+using pci_pin_mapper = device_delegate<int (int)>;
+using pci_irq_handler = device_delegate<void (int, int)>;
+
class pci_root_device : public device_t {
public:
pci_root_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ void irq_pin_w(int pin, int state);
+ void irq_w(int line, int state);
+
+ void set_pin_mapper(pci_pin_mapper &&mapper) { m_pin_mapper = std::move(mapper); }
+ void set_irq_handler(pci_irq_handler &&handler) { m_irq_handler = std::move(handler); }
+
+ address_space *get_pci_busmaster_space() const { return m_pci_busmaster_space; }
+
+ void set_pci_busmaster_space(address_space *space) { m_pci_busmaster_space = space; }
+
protected:
- virtual void device_start() override;
- virtual void device_reset() override;
+ virtual void device_start() override ATTR_COLD;
+ virtual void device_reset() override ATTR_COLD;
+
+private:
+ pci_pin_mapper m_pin_mapper;
+ pci_irq_handler m_irq_handler;
+ address_space *m_pci_busmaster_space;
};
+address_space *pci_device::get_pci_busmaster_space() const
+{
+ return m_pci_root->get_pci_busmaster_space();
+}
+
DECLARE_DEVICE_TYPE(PCI_ROOT, pci_root_device)
DECLARE_DEVICE_TYPE(PCI_BRIDGE, pci_bridge_device)