diff options
Diffstat (limited to 'src/devices/machine/dmac.h')
-rw-r--r-- | src/devices/machine/dmac.h | 213 |
1 files changed, 133 insertions, 80 deletions
diff --git a/src/devices/machine/dmac.h b/src/devices/machine/dmac.h index 203317dd742..0bd2d1f7caa 100644 --- a/src/devices/machine/dmac.h +++ b/src/devices/machine/dmac.h @@ -1,5 +1,5 @@ -// license:GPL-2.0+ -// copyright-holders:Dirk Best +// license: GPL-2.0+ +// copyright-holders: Dirk Best /*************************************************************************** DMAC @@ -16,110 +16,163 @@ #include "autoconfig.h" -//************************************************************************** -// TYPE DEFINITIONS -//************************************************************************** - class amiga_dmac_device : public device_t, public amiga_autoconfig { public: - // construction/destruction - amiga_dmac_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - // callbacks - auto cfgout_handler() { return m_cfgout_handler.bind(); } - auto int_handler() { return m_int_handler.bind(); } - auto xdack_handler() { return m_xdack_handler.bind(); } - auto scsi_read_handler() { return m_scsi_read_handler.bind(); } - auto scsi_write_handler() { return m_scsi_write_handler.bind(); } - auto io_read_handler() { return m_io_read_handler.bind(); } - auto io_write_handler() { return m_io_write_handler.bind(); } + auto cfgout_cb() { return m_cfgout_cb.bind(); } + auto int_cb() { return m_int_cb.bind(); } + auto css_read_cb() { return m_css_read_cb.bind(); } + auto css_write_cb() { return m_css_write_cb.bind(); } + auto csx0_read_cb() { return m_csx0_read_cb.bind(); } + auto csx0_write_cb() { return m_csx0_write_cb.bind(); } + auto csx0_a4_read_cb() { return m_csx0_a4_read_cb.bind(); } + auto csx0_a4_write_cb() { return m_csx0_a4_write_cb.bind(); } + auto csx1_read_cb() { return m_csx1_read_cb.bind(); } + auto csx1_write_cb() { return m_csx1_write_cb.bind(); } + auto sdack_read_cb() { return m_sdack_read_cb.bind(); } + auto sdack_write_cb() { return m_sdack_write_cb.bind(); } + auto xdack_read_cb() { return m_xdack_read_cb.bind(); } + auto xdack_write_cb() { return m_xdack_write_cb.bind(); } void set_address_space(address_space *space) { m_space = space; } - void set_rom(uint8_t *rom) { m_rom = rom; } - void set_ram(uint8_t *ram) { m_ram = ram; } + void set_rom(const char *region) { m_rom.set_tag(region); } + void set_ram(uint16_t *ram) { m_ram = ram; } // input lines - DECLARE_WRITE_LINE_MEMBER( configin_w ); - DECLARE_WRITE_LINE_MEMBER( ramsz_w ); - DECLARE_WRITE_LINE_MEMBER( rst_w ); - DECLARE_WRITE_LINE_MEMBER( intx_w ); - DECLARE_WRITE_LINE_MEMBER( xdreq_w ); - - // dmac register access - DECLARE_READ16_MEMBER( register_read ); - DECLARE_WRITE16_MEMBER( register_write ); + void configin_w(int state); + void ramsz_w(int state); + void rst_w(int state); + void intx_w(int state); + void sdreq_w(int state); + void xdreq_w(int state); protected: - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; + amiga_dmac_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool rev1); + + virtual void device_start() override ATTR_COLD; // amiga_autoconfig overrides virtual void autoconfig_base_address(offs_t address) override; private: - // control register flags - enum - { - CNTR_TCEN = 0x80, // terminal count enable - CNTR_PREST = 0x40, // peripheral reset - CNTR_PDMD = 0x20, // peripheral device mode select (1=scsi, 0=xt) - CNTR_INTEN = 0x10, // interrupt enable - CNTR_DDIR = 0x08 // device direction (1=rd host, wr to peripheral) - }; - - // interrupt status register - enum - { - ISTR_INTX = 0x100, // xt interrupt pending - ISTR_INT_F = 0x080, // interrupt follow - ISTR_INTS = 0x040, // scsi peripheral interrupt - ISTR_E_INT = 0x020, // end-of-process interrupt - ISTR_INT_P = 0x010, // interrupt pending - ISTR_UE_INT = 0x008, // under-run fifo error interrupt - ISTR_OE_INT = 0x004, // over-run fifo error interrupt - ISTR_FF_FLG = 0x002, // fifo-full flag - ISTR_FE_FLG = 0x001 // fifo-empty flag - }; - - static constexpr int ISTR_INT_MASK = 0x1ec; + void map(address_map &map) ATTR_COLD; - // callbacks - devcb_write_line m_cfgout_handler; - devcb_write_line m_int_handler; - devcb_write_line m_xdack_handler; - devcb_read8 m_scsi_read_handler; - devcb_write8 m_scsi_write_handler; - devcb_read8 m_io_read_handler; - devcb_write8 m_io_write_handler; + TIMER_CALLBACK_MEMBER(update_dma); + void update_interrupts(); + void start_dma(); + void stop_dma(); + + uint16_t autoconfig_r(offs_t offset, uint16_t mem_mask); + void autoconfig_w(offs_t offset, uint16_t data, uint16_t mem_mask); + + uint16_t istr_r(offs_t offset, uint16_t mem_mask); + uint16_t cntr_r(offs_t offset, uint16_t mem_mask); + void cntr_w(offs_t offset, uint16_t data,uint16_t mem_mask); + void wtc_hi_w(offs_t offset, uint16_t data,uint16_t mem_mask); + void wtc_lo_w(offs_t offset, uint16_t data,uint16_t mem_mask); + void acr_hi_w(offs_t offset, uint16_t data,uint16_t mem_mask); + void acr_lo_w(offs_t offset, uint16_t data,uint16_t mem_mask); + void dawr_w(offs_t offset, uint16_t data,uint16_t mem_mask); + + uint8_t css_r(offs_t offset); + void css_w(offs_t offset, uint8_t data); + uint8_t csx0_r(offs_t offset); + void csx0_w(offs_t offset, uint8_t data); + uint8_t csx0_a4_r(offs_t offset); + void csx0_a4_w(offs_t offset, uint8_t data); + uint8_t csx1_r(offs_t offset); + void csx1_w(offs_t offset, uint8_t data); + + // strobe register + void st_dma(); + uint16_t st_dma_r(offs_t offset, uint16_t mem_mask) { st_dma(); return 0; }; + void st_dma_w(offs_t offset, uint16_t data, uint16_t mem_mask) { st_dma(); }; + void sp_dma(); + uint16_t sp_dma_r(offs_t offset, uint16_t mem_mask) { sp_dma(); return 0; }; + void sp_dma_w(offs_t offset, uint16_t data, uint16_t mem_mask) { sp_dma(); }; + void cint(); + uint16_t cint_r(offs_t offset, uint16_t mem_mask) { cint(); return 0; }; + void cint_w(offs_t offset, uint16_t data, uint16_t mem_mask) { cint(); }; + void flush(); + uint16_t flush_r(offs_t offset, uint16_t mem_mask) { flush(); return 0; }; + void flush_w(offs_t offset, uint16_t data, uint16_t mem_mask) { flush(); }; + + // control register definitions + static constexpr uint16_t CNTR_TCEN = 0x80; // terminal count enable + static constexpr uint16_t CNTR_PREST = 0x40; // peripheral reset + static constexpr uint16_t CNTR_PDMD = 0x20; // peripheral device mode select (1=scsi/0=xt) + static constexpr uint16_t CNTR_INTEN = 0x10; // interrupt enable + static constexpr uint16_t CNTR_DDIR = 0x08; // device direction (1=from host to peripheral) + + // interrupt status register definitions + static constexpr uint16_t ISTR_INT_F = 0x80; // interrupt follow + static constexpr uint16_t ISTR_INTS = 0x40; // scsi peripheral interrupt + static constexpr uint16_t ISTR_E_INT = 0x20; // end-of-process interrupt + static constexpr uint16_t ISTR_INT_P = 0x10; // interrupt pending + static constexpr uint16_t ISTR_UE_INT = 0x08; // fifo underrun interrupt + static constexpr uint16_t ISTR_OE_INT = 0x04; // fifo overflow interrupt + static constexpr uint16_t ISTR_FF_FLG = 0x02; // fifo full flag + static constexpr uint16_t ISTR_FE_FLG = 0x01; // fifo empty flag + + static constexpr uint16_t ISTR_INT_MASK = 0x6c; + // callbacks + devcb_write_line m_cfgout_cb; + devcb_write_line m_int_cb; + devcb_read8 m_css_read_cb; + devcb_write8 m_css_write_cb; + devcb_read8 m_csx0_read_cb; + devcb_write8 m_csx0_write_cb; + devcb_read8 m_csx0_a4_read_cb; + devcb_write8 m_csx0_a4_write_cb; + devcb_read8 m_csx1_read_cb; + devcb_write8 m_csx1_write_cb; + devcb_read8 m_sdack_read_cb; + devcb_write8 m_sdack_write_cb; + devcb_read8 m_xdack_read_cb; + devcb_write8 m_xdack_write_cb; + + optional_memory_region m_rom; address_space *m_space; - uint8_t *m_rom; - uint8_t *m_ram; + uint16_t *m_ram; int m_ram_size; + bool m_rev1; - // autoconfig state - bool m_configured; + // internal registers + uint16_t m_cntr; // control register + uint16_t m_istr; // interrupt status register + uint32_t m_wtc; // word transfer count + uint32_t m_acr; // address control register - // state of lines - int m_rst; + // state of input lines + bool m_intx; + bool m_sdreq; + bool m_xdreq; - // register - uint16_t m_cntr; // control register - uint16_t m_istr; // interrupt status register - uint32_t m_wtc; // word transfer count - uint32_t m_acr; // address control register + emu_timer *m_dma_timer; - bool m_dma_active; + // autoconfig state + bool m_autoconfig_dmac_done; + bool m_autoconfig_ram_done; + offs_t m_dmac_address; + offs_t m_ram_address; +}; - void check_interrupts(); - void start_dma(); - void stop_dma(); +class amiga_dmac_rev1_device : public amiga_dmac_device +{ +public: + amiga_dmac_rev1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); }; +class amiga_dmac_rev2_device : public amiga_dmac_device +{ +public: + amiga_dmac_rev2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); +}; -// device type definition -DECLARE_DEVICE_TYPE(AMIGA_DMAC, amiga_dmac_device) +// device type declaration +DECLARE_DEVICE_TYPE(AMIGA_DMAC_REV1, amiga_dmac_rev1_device) +DECLARE_DEVICE_TYPE(AMIGA_DMAC_REV2, amiga_dmac_rev2_device) #endif // MAME_MACHINE_DMAC_H |