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-rw-r--r--src/devices/cpu/drcbex64.cpp27
-rw-r--r--src/devices/cpu/drcbex86.cpp40
-rw-r--r--src/devices/cpu/hphybrid/hphybrid.cpp80
-rw-r--r--src/devices/cpu/hphybrid/hphybrid.h4
-rw-r--r--src/devices/cpu/hphybrid/hphybrid_dasm.cpp6
-rw-r--r--src/devices/cpu/mips/mips3drc.cpp698
-rw-r--r--src/devices/cpu/powerpc/ppccom.cpp2
-rw-r--r--src/devices/cpu/sm510/sm500.h4
-rw-r--r--src/devices/cpu/sm510/sm500op.cpp1
-rw-r--r--src/devices/cpu/sm510/sm510.cpp4
-rw-r--r--src/devices/cpu/sm510/sm510d.cpp6
-rw-r--r--src/devices/cpu/sm510/sm511core.cpp2
12 files changed, 436 insertions, 438 deletions
diff --git a/src/devices/cpu/drcbex64.cpp b/src/devices/cpu/drcbex64.cpp
index a8fea0ed27e..8d7e852b66c 100644
--- a/src/devices/cpu/drcbex64.cpp
+++ b/src/devices/cpu/drcbex64.cpp
@@ -6756,21 +6756,20 @@ void drcbe_x64::op_fcopyi(x86code *&dst, const instruction &inst)
{
if (dstp.is_memory())
{
- emit_mov_p32_r32(dst, dstp, srcp.ireg()); // mov dstp,srcp
+ emit_mov_p32_r32(dst, dstp, srcp.ireg()); // mov dstp,srcp
}
else
{
- emit_movd_r128_r32(dst, dstreg, srcp.ireg()); // movd dstreg,srcp
- emit_movss_p32_r128(dst, dstp, dstreg); // movss dstp,dstreg
+ emit_movd_r128_r32(dst, dstreg, srcp.ireg()); // movd dstreg,srcp
+ emit_movss_p32_r128(dst, dstp, dstreg); // movss dstp,dstreg
}
}
-
+
}
// 64-bit form
else if (inst.size() == 8)
{
-
if (srcp.is_memory())
{
emit_movq_r128_m64(dst, dstreg, MABS(srcp.memory())); // movq dstreg,[srcp]
@@ -6780,12 +6779,12 @@ void drcbe_x64::op_fcopyi(x86code *&dst, const instruction &inst)
{
if (dstp.is_memory())
{
- emit_mov_p64_r64(dst, dstp, srcp.ireg()); // mov dstp,srcp
+ emit_mov_p64_r64(dst, dstp, srcp.ireg()); // mov dstp,srcp
}
else
{
- emit_movq_r128_r64(dst, dstreg, srcp.ireg()); // movq dstreg,srcp
- emit_movsd_p64_r128(dst, dstp, dstreg); // movsd dstp,dstreg
+ emit_movq_r128_r64(dst, dstreg, srcp.ireg()); // movq dstreg,srcp
+ emit_movsd_p64_r128(dst, dstp, dstreg); // movsd dstp,dstreg
}
}
@@ -6821,13 +6820,13 @@ void drcbe_x64::op_icopyf(x86code *&dst, const instruction &inst)
{
if (dstp.is_memory())
{
- emit_movd_m32_r128(dst, MABS(dstp.memory()), srcp.freg()); // movd dstp,srcp
+ emit_movd_m32_r128(dst, MABS(dstp.memory()), srcp.freg()); // movd dstp,srcp
}
else
{
- emit_movd_r32_r128(dst, dstp.ireg(), srcp.freg()); // movd dstp,srcp
+ emit_movd_r32_r128(dst, dstp.ireg(), srcp.freg()); // movd dstp,srcp
}
- }
+ }
}
// 64-bit form
@@ -6843,12 +6842,12 @@ void drcbe_x64::op_icopyf(x86code *&dst, const instruction &inst)
{
if (dstp.is_memory())
{
- emit_movq_m64_r128(dst, MABS(dstp.memory()), srcp.freg()); // movq dstp,srcp
+ emit_movq_m64_r128(dst, MABS(dstp.memory()), srcp.freg()); // movq dstp,srcp
}
else
{
- emit_movq_r64_r128(dst, dstp.ireg(), srcp.freg()); // movq dstp,srcp
+ emit_movq_r64_r128(dst, dstp.ireg(), srcp.freg()); // movq dstp,srcp
}
}
}
-} \ No newline at end of file
+}
diff --git a/src/devices/cpu/drcbex86.cpp b/src/devices/cpu/drcbex86.cpp
index 4ff6a90774b..478e9f08bc0 100644
--- a/src/devices/cpu/drcbex86.cpp
+++ b/src/devices/cpu/drcbex86.cpp
@@ -272,8 +272,8 @@ const drcbe_x86::opcode_table_entry drcbe_x86::s_opcode_table_source[] =
{ uml::OP_FSQRT, &drcbe_x86::op_fsqrt }, // FSQRT dst,src1
{ uml::OP_FRECIP, &drcbe_x86::op_frecip }, // FRECIP dst,src1
{ uml::OP_FRSQRT, &drcbe_x86::op_frsqrt }, // FRSQRT dst,src1
- { uml::OP_FCOPYI, &drcbe_x86::op_fcopyi }, // FCOPYI dst,src
- { uml::OP_ICOPYF, &drcbe_x86::op_icopyf }, // ICOPYF dst,src
+ { uml::OP_FCOPYI, &drcbe_x86::op_fcopyi }, // FCOPYI dst,src
+ { uml::OP_ICOPYF, &drcbe_x86::op_icopyf }, // ICOPYF dst,src
};
@@ -6471,12 +6471,12 @@ void drcbe_x86::op_fcopyi(x86code *&dst, const instruction &inst)
{
if (srcp.is_memory())
{
- emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
- emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
+ emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
+ emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
}
else if (srcp.is_int_register())
{
- emit_mov_m32_r32(dst, MABS(dstp.memory()), srcp.ireg()); // mov [dstp],srcp
+ emit_mov_m32_r32(dst, MABS(dstp.memory()), srcp.ireg()); // mov [dstp],srcp
}
}
@@ -6485,17 +6485,17 @@ void drcbe_x86::op_fcopyi(x86code *&dst, const instruction &inst)
{
if (srcp.is_memory())
{
- emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
- emit_mov_r32_m32(dst, REG_EDX, MABS(srcp.memory(4))); // mov edx,[srcp+4]
+ emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
+ emit_mov_r32_m32(dst, REG_EDX, MABS(srcp.memory(4))); // mov edx,[srcp+4]
}
else if (srcp.is_int_register())
{
- emit_mov_r32_m32(dst, REG_EDX, MABS(m_reghi[srcp.ireg()])); // mov edx,[reghi[srcp]]
- emit_mov_r32_r32(dst, REG_EAX, srcp.ireg()); // mov eax,srcp
+ emit_mov_r32_m32(dst, REG_EDX, MABS(m_reghi[srcp.ireg()])); // mov edx,[reghi[srcp]]
+ emit_mov_r32_r32(dst, REG_EAX, srcp.ireg()); // mov eax,srcp
}
- emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
- emit_mov_m32_r32(dst, MABS(dstp.memory(4)), REG_EDX); // mov [dstp+4],edx
+ emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
+ emit_mov_m32_r32(dst, MABS(dstp.memory(4)), REG_EDX); // mov [dstp+4],edx
}
}
@@ -6518,33 +6518,33 @@ void drcbe_x86::op_icopyf(x86code *&dst, const instruction &inst)
// 32-bit case
if (inst.size() == 4)
{
- emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
+ emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
if (dstp.is_memory())
{
- emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
+ emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
}
else if (dstp.is_int_register())
{
- emit_mov_r32_r32(dst, dstp.ireg(), REG_EAX); // mov dstp,eax
+ emit_mov_r32_r32(dst, dstp.ireg(), REG_EAX); // mov dstp,eax
}
}
// 64-bit case
else if (inst.size() == 8)
{
- emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
- emit_mov_r32_m32(dst, REG_EDX, MABS(srcp.memory(4))); // mov edx,[srcp+4]
+ emit_mov_r32_m32(dst, REG_EAX, MABS(srcp.memory())); // mov eax,[srcp]
+ emit_mov_r32_m32(dst, REG_EDX, MABS(srcp.memory(4))); // mov edx,[srcp+4]
if (dstp.is_memory())
{
- emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
- emit_mov_m32_r32(dst, MABS(dstp.memory(4)), REG_EDX); // mov [dstp+4],edx
+ emit_mov_m32_r32(dst, MABS(dstp.memory()), REG_EAX); // mov [dstp],eax
+ emit_mov_m32_r32(dst, MABS(dstp.memory(4)), REG_EDX); // mov [dstp+4],edx
}
else
{
- emit_mov_m32_r32(dst, MABS(m_reghi[dstp.ireg()]), REG_EDX); // mov [reghi[dstp]],edx
- emit_mov_r32_r32(dst, dstp.ireg(), REG_EAX); // mov dstp,eax
+ emit_mov_m32_r32(dst, MABS(m_reghi[dstp.ireg()]), REG_EDX); // mov [reghi[dstp]],edx
+ emit_mov_r32_r32(dst, dstp.ireg(), REG_EAX); // mov dstp,eax
}
}
}
diff --git a/src/devices/cpu/hphybrid/hphybrid.cpp b/src/devices/cpu/hphybrid/hphybrid.cpp
index da9470a91ae..62b406c1d28 100644
--- a/src/devices/cpu/hphybrid/hphybrid.cpp
+++ b/src/devices/cpu/hphybrid/hphybrid.cpp
@@ -534,7 +534,7 @@ UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode)
memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS);
m_pa_changed_func((UINT8)CURRENT_PA);
}
- BIT_CLR(m_flags, HPHYBRID_IM_BIT);
+ BIT_CLR(m_flags, HPHYBRID_IM_BIT);
}
tmp = RM(AEC_CASE_C , m_reg_R--) + (opcode & 0x1f);
return BIT(opcode , 5) ? tmp - 0x20 : tmp;
@@ -903,17 +903,17 @@ UINT16 hp_hybrid_cpu_device::get_skip_addr_sc(UINT16 opcode , UINT16& v , unsign
UINT16 hp_hybrid_cpu_device::get_skip_addr_sc(UINT16 opcode , UINT32& v , unsigned n)
{
- bool val = BIT(v , n);
+ bool val = BIT(v , n);
- if (BIT(opcode , 7)) {
- if (BIT(opcode , 6)) {
- BIT_SET(v , n);
- } else {
- BIT_CLR(v , n);
- }
- }
+ if (BIT(opcode , 7)) {
+ if (BIT(opcode , 6)) {
+ BIT_SET(v , n);
+ } else {
+ BIT_CLR(v , n);
+ }
+ }
- return get_skip_addr(opcode , val);
+ return get_skip_addr(opcode , val);
}
void hp_hybrid_cpu_device::do_pw(UINT16 opcode)
@@ -1007,7 +1007,7 @@ void hp_hybrid_cpu_device::do_pw(UINT16 opcode)
void hp_hybrid_cpu_device::check_for_interrupts(void)
{
- if (!BIT(m_flags , HPHYBRID_INTEN_BIT) || BIT(m_flags , HPHYBRID_IRH_SVC_BIT) || BIT(m_flags , HPHYBRID_IM_BIT)) {
+ if (!BIT(m_flags , HPHYBRID_INTEN_BIT) || BIT(m_flags , HPHYBRID_IRH_SVC_BIT) || BIT(m_flags , HPHYBRID_IM_BIT)) {
return;
}
@@ -1017,9 +1017,9 @@ void hp_hybrid_cpu_device::check_for_interrupts(void)
// Service high-level interrupt
BIT_SET(m_flags , HPHYBRID_IRH_SVC_BIT);
irqline = HPHYBRID_IRH;
- if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
- logerror("H pre-empted L @ %06x\n" , m_genpc);
- }
+ if (BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
+ logerror("H pre-empted L @ %06x\n" , m_genpc);
+ }
} else if (BIT(m_flags , HPHYBRID_IRL_BIT) && !BIT(m_flags , HPHYBRID_IRL_SVC_BIT)) {
// Service low-level interrupt
BIT_SET(m_flags , HPHYBRID_IRL_SVC_BIT);
@@ -1055,8 +1055,8 @@ void hp_hybrid_cpu_device::check_for_interrupts(void)
// lasts for 32 cycles
m_icount -= 32;
- // Allow special processing in 5061-3001
- enter_isr();
+ // Allow special processing in 5061-3001
+ enter_isr();
// Do a double-indirect JSM IV,I instruction
WM(AEC_CASE_C , ++m_reg_R , m_reg_P);
@@ -1066,7 +1066,7 @@ void hp_hybrid_cpu_device::check_for_interrupts(void)
void hp_hybrid_cpu_device::enter_isr(void)
{
- // Do nothing special
+ // Do nothing special
}
void hp_hybrid_cpu_device::handle_dma(void)
@@ -1477,33 +1477,33 @@ UINT16 hp_5061_3001_cpu_device::execute_no_bpc_ioc(UINT16 opcode)
do_mpy();
break;
- case 0x7026:
- // CIM
- // Undocumented instruction, see beginning of this file
- // Probably "Clear Interrupt Mask"
- // No idea at all about exec. time: make it 9 cycles
- m_icount -= 9;
+ case 0x7026:
+ // CIM
+ // Undocumented instruction, see beginning of this file
+ // Probably "Clear Interrupt Mask"
+ // No idea at all about exec. time: make it 9 cycles
+ m_icount -= 9;
#ifndef NO_ISR_WITH_IM_CLEARED
- BIT_CLR(m_flags, HPHYBRID_IM_BIT);
+ BIT_CLR(m_flags, HPHYBRID_IM_BIT);
#else
- BIT_SET(m_flags, HPHYBRID_IM_BIT);
+ BIT_SET(m_flags, HPHYBRID_IM_BIT);
#endif
- logerror("hp-5061-3001: CIM, P = %06x flags = %05x\n" , m_genpc , m_flags);
- break;
-
- case 0x7027:
- // SIM
- // Undocumented instruction, see beginning of this file
- // Probably "Set Interrupt Mask"
- // No idea at all about exec. time: make it 9 cycles
- m_icount -= 9;
+ logerror("hp-5061-3001: CIM, P = %06x flags = %05x\n" , m_genpc , m_flags);
+ break;
+
+ case 0x7027:
+ // SIM
+ // Undocumented instruction, see beginning of this file
+ // Probably "Set Interrupt Mask"
+ // No idea at all about exec. time: make it 9 cycles
+ m_icount -= 9;
#ifndef NO_ISR_WITH_IM_CLEARED
- BIT_SET(m_flags, HPHYBRID_IM_BIT);
+ BIT_SET(m_flags, HPHYBRID_IM_BIT);
#else
- BIT_CLR(m_flags, HPHYBRID_IM_BIT);
+ BIT_CLR(m_flags, HPHYBRID_IM_BIT);
#endif
- logerror("hp-5061-3001: SIM, P = %06x flags = %05x\n" , m_genpc , m_flags);
- break;
+ logerror("hp-5061-3001: SIM, P = %06x flags = %05x\n" , m_genpc , m_flags);
+ break;
default:
if ((opcode & 0xfec0) == 0x74c0) {
@@ -1655,9 +1655,9 @@ void hp_5061_3001_cpu_device::write_non_common_reg(UINT16 addr , UINT16 v)
void hp_5061_3001_cpu_device::enter_isr(void)
{
- // Set interrupt mask when entering an ISR
+ // Set interrupt mask when entering an ISR
#ifndef NO_ISR_WITH_IM_CLEARED
- BIT_SET(m_flags, HPHYBRID_IM_BIT);
+ BIT_SET(m_flags, HPHYBRID_IM_BIT);
#endif
}
diff --git a/src/devices/cpu/hphybrid/hphybrid.h b/src/devices/cpu/hphybrid/hphybrid.h
index d61785cb146..e0cfbc893d4 100644
--- a/src/devices/cpu/hphybrid/hphybrid.h
+++ b/src/devices/cpu/hphybrid/hphybrid.h
@@ -182,7 +182,7 @@ private:
UINT16 get_skip_addr_sc(UINT16 opcode , UINT32& v , unsigned n);
void do_pw(UINT16 opcode);
void check_for_interrupts(void);
- virtual void enter_isr(void);
+ virtual void enter_isr(void);
void handle_dma(void);
UINT16 RIO(UINT8 pa , UINT8 ic);
@@ -228,7 +228,7 @@ private:
UINT16 m_reg_r27; // R27 register
UINT16 m_reg_aec[ HP_REG_R37_ADDR - HP_REG_R32_ADDR + 1 ]; // AEC registers R32-R37
- virtual void enter_isr(void) override;
+ virtual void enter_isr(void) override;
};
class hp_5061_3011_cpu_device : public hp_hybrid_cpu_device
diff --git a/src/devices/cpu/hphybrid/hphybrid_dasm.cpp b/src/devices/cpu/hphybrid/hphybrid_dasm.cpp
index 78b586f2310..869cbb0f32b 100644
--- a/src/devices/cpu/hphybrid/hphybrid_dasm.cpp
+++ b/src/devices/cpu/hphybrid/hphybrid_dasm.cpp
@@ -355,9 +355,9 @@ static const dis_entry_t dis_table_emc[] = {
{0xffff , 0x7b40 , "MRY" , param_none , 0 },
{0xffff , 0x7b61 , "MLY" , param_none , 0 },
{0xffff , 0x7b8f , "MPY" , param_none , 0 },
- // *** Undocumented instructions of 5061-3001 ***
- {0xffff , 0x7026 , "CIM" , param_none , 0 },
- {0xffff , 0x7027 , "SIM" , param_none , 0 },
+ // *** Undocumented instructions of 5061-3001 ***
+ {0xffff , 0x7026 , "CIM" , param_none , 0 },
+ {0xffff , 0x7027 , "SIM" , param_none , 0 },
// *** END ***
{0 , 0 , nullptr , nullptr , 0 }
};
diff --git a/src/devices/cpu/mips/mips3drc.cpp b/src/devices/cpu/mips/mips3drc.cpp
index efcda7dbfa5..c7b2499b9e5 100644
--- a/src/devices/cpu/mips/mips3drc.cpp
+++ b/src/devices/cpu/mips/mips3drc.cpp
@@ -48,7 +48,7 @@ using namespace uml;
#define HI32 R32(REG_HI)
#define CPR032(reg) mem(LOPTR(&m_core->cpr[0][reg]))
#define CCR032(reg) mem(LOPTR(&m_core->ccr[0][reg]))
-#define FPR32_FR0(reg) mem(&((float *)&m_core->cpr[1][reg])[BYTE_XOR_LE(0)])
+#define FPR32_FR0(reg) mem(&((float *)&m_core->cpr[1][reg])[BYTE_XOR_LE(0)])
#define CCR132(reg) mem(LOPTR(&m_core->ccr[1][reg]))
#define CPR232(reg) mem(LOPTR(&m_core->cpr[2][reg]))
#define CCR232(reg) mem(LOPTR(&m_core->ccr[2][reg]))
@@ -58,7 +58,7 @@ using namespace uml;
#define HI64 R64(REG_HI)
#define CPR064(reg) mem(&m_core->cpr[0][reg])
#define CCR064(reg) mem(&m_core->ccr[0][reg])
-#define FPR64_FR1(reg) mem((double *)&m_core->cpr[1][reg])
+#define FPR64_FR1(reg) mem((double *)&m_core->cpr[1][reg])
#define CCR164(reg) mem(&m_core->ccr[1][reg])
#define CPR264(reg) mem(&m_core->cpr[2][reg])
#define CCR264(reg) mem(&m_core->ccr[2][reg])
@@ -1635,18 +1635,18 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
return TRUE;
case 0x1b: /* LDR - MIPS III */
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_SHL(block, I1, I0, 3); // shl i1,i0,3
- UML_AND(block, I0, I0, ~7); // and i0,i0,~7
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_SHL(block, I1, I0, 3); // shl i1,i0,3
+ UML_AND(block, I0, I0, ~7); // and i0,i0,~7
if (m_bigendian)
- UML_XOR(block, I1, I1, 0x38); // xor i1,i1,0x38
- UML_DSHL(block, I2, (UINT64)~0, I1); // dshl i2,~0,i1
- UML_CALLH(block, *m_read64mask[m_core->mode >> 1]); // callh read64mask
+ UML_XOR(block, I1, I1, 0x38); // xor i1,i1,0x38
+ UML_DSHL(block, I2, (UINT64)~0, I1); // dshl i2,~0,i1
+ UML_CALLH(block, *m_read64mask[m_core->mode >> 1]); // callh read64mask
if (RTREG != 0)
{
- UML_DSHR(block, I2, (UINT64)~0, I1); // dshr i2,~0,i1
- UML_SUB(block, I1, 64, I1); // sub i1,64,i1
- UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2
+ UML_DSHR(block, I2, (UINT64)~0, I1); // dshr i2,~0,i1
+ UML_SUB(block, I1, 64, I1); // sub i1,64,i1
+ UML_DROLINS(block, R64(RTREG), I0, I1, I2); // drolins <rtreg>,i0,i1,i2
}
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
@@ -1654,17 +1654,17 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x31: /* LWC1 - MIPS I */
check_cop1_access(block);
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
- UML_MOV(block, FPR32_FR0(RTREG), I0); // mov <cpr1_rt>,i0
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
+ UML_MOV(block, FPR32_FR0(RTREG), I0); // mov <cpr1_rt>,i0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
case 0x35: /* LDC1 - MIPS III */
check_cop1_access(block);
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
generate_set_cop1_reg64_i2d(block, compiler, desc, RTREG, I0);
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
@@ -1727,7 +1727,7 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x3f: /* SD - MIPS III */
UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
+ UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
@@ -1776,14 +1776,14 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
return TRUE;
case 0x2c: /* SDL - MIPS III */
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_SHL(block, I3, I0, 3); // shl i3,i0,3
- UML_AND(block, I0, I0, ~7); // and i0,i0,~7
- UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_SHL(block, I3, I0, 3); // shl i3,i0,3
+ UML_AND(block, I0, I0, ~7); // and i0,i0,~7
+ UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
if (!m_bigendian)
- UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38
- UML_DSHR(block, I2, (UINT64)~0, I3); // dshr i2,~0,i3
- UML_DSHR(block, I1, I1, I3); // dshr i1,i1,i3
+ UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38
+ UML_DSHR(block, I2, (UINT64)~0, I3); // dshr i2,~0,i3
+ UML_DSHR(block, I1, I1, I3); // dshr i1,i1,i3
UML_CALLH(block, *m_write64mask[m_core->mode >> 1]);// callh write64mask
if (!in_delay_slot)
@@ -1791,14 +1791,14 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
return TRUE;
case 0x2d: /* SDR - MIPS III */
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_SHL(block, I3, I0, 3); // shl i3,i0,3
- UML_AND(block, I0, I0, ~7); // and i0,i0,~7
- UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_SHL(block, I3, I0, 3); // shl i3,i0,3
+ UML_AND(block, I0, I0, ~7); // and i0,i0,~7
+ UML_DMOV(block, I1, R64(RTREG)); // dmov i1,<rtreg>
if (m_bigendian)
- UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38
- UML_DSHL(block, I2, (UINT64)~0, I3); // dshl i2,~0,i3
- UML_DSHL(block, I1, I1, I3); // dshl i1,i1,i3
+ UML_XOR(block, I3, I3, 0x38); // xor i3,i3,0x38
+ UML_DSHL(block, I2, (UINT64)~0, I3); // dshl i2,~0,i3
+ UML_DSHL(block, I1, I1, I3); // dshl i1,i1,i3
UML_CALLH(block, *m_write64mask[m_core->mode >> 1]);// callh write64mask
if (!in_delay_slot)
@@ -1807,8 +1807,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x39: /* SWC1 - MIPS I */
check_cop1_access(block);
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_MOV(block, I1, FPR32_FR0(RTREG)); // mov i1,<cpr1_rt>
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_MOV(block, I1, FPR32_FR0(RTREG)); // mov i1,<cpr1_rt>
UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
@@ -1817,8 +1817,8 @@ int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler,
case 0x3d: /* SDC1 - MIPS III */
check_cop1_access(block);
generate_get_cop1_reg64_d2i(block, compiler, desc, RTREG, I1);
- UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
- UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
+ UML_ADD(block, I0, R32(RSREG), SIMMVAL); // add i0,<rsreg>,SIMMVAL
+ UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
@@ -2317,12 +2317,12 @@ int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler,
{
UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0
UML_JMPc(block, COND_L, skip = compiler->labelnum++); // jmp skip,L
- generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
+ generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
}
else
{
- generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
+ generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
}
return TRUE;
@@ -2711,12 +2711,12 @@ void mips3_device::generate_get_cop1_reg64(drcuml_block *block, compiler_state *
{
UML_ICOPYFS(block, I0, FPR32_FR0((reg & 0x1E) + 1));
UML_DSHL(block, I0, I0, 32);
- UML_ICOPYFS(block, I1, FPR32_FR0(reg & 0x1E));
- UML_DROLINS(block, I0, I1, 0, 0x00000000ffffffffL);
- UML_FDCOPYI(block, param, I0);
+ UML_ICOPYFS(block, I1, FPR32_FR0(reg & 0x1E));
+ UML_DROLINS(block, I0, I1, 0, 0x00000000ffffffffL);
+ UML_FDCOPYI(block, param, I0);
}
- else
- {
+ else
+ {
UML_FDMOV(block, param, FPR64_FR1(reg));
}
}
@@ -2772,7 +2772,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
case 0x00: /* MFC1 - MIPS I */
if (RTREG != 0)
{
- UML_DSEXT(block, R64(RTREG), FPR32_FR0(RDREG), SIZE_DWORD); // dsext <rtreg>,fpr[rdreg],dword
+ UML_DSEXT(block, R64(RTREG), FPR32_FR0(RDREG), SIZE_DWORD); // dsext <rtreg>,fpr[rdreg],dword
}
return TRUE;
@@ -2786,11 +2786,11 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
case 0x02: /* CFC1 - MIPS I */
if (RTREG != 0)
- UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr132[rdreg],dword
+ UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr132[rdreg],dword
return TRUE;
case 0x04: /* MTC1 - MIPS I */
- UML_MOV(block, FPR32_FR0(RDREG), R32(RTREG)); // mov fpr[rdreg],<rtreg>
+ UML_MOV(block, FPR32_FR0(RDREG), R32(RTREG)); // mov fpr[rdreg],<rtreg>
return TRUE;
case 0x05: /* DMTC1 - MIPS III */
@@ -2801,18 +2801,18 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
case 0x06: /* CTC1 - MIPS I */
if (RDREG != 31)
{
- UML_DSEXT(block, CCR164(RDREG), R32(RTREG), SIZE_DWORD); // dsext ccr1[rdreg],<rtreg>,dword
+ UML_DSEXT(block, CCR164(RDREG), R32(RTREG), SIZE_DWORD); // dsext ccr1[rdreg],<rtreg>,dword
}
else
{
- UML_XOR(block, I0, CCR132(31), R32(RTREG)); // xor i0,ccr1[31],<rtreg>
- UML_DSEXT(block, CCR164(31), R32(RTREG), SIZE_DWORD); // dsext ccr1[31],<rtreg>,dword
- UML_TEST(block, I0, 3); // test i0,3
- UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
- UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3
- UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte
- UML_SETFMOD(block, I0); // setfmod i0
- UML_LABEL(block, skip); // skip:
+ UML_XOR(block, I0, CCR132(31), R32(RTREG)); // xor i0,ccr1[31],<rtreg>
+ UML_DSEXT(block, CCR164(31), R32(RTREG), SIZE_DWORD); // dsext ccr1[31],<rtreg>,dword
+ UML_TEST(block, I0, 3); // test i0,3
+ UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
+ UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3
+ UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte
+ UML_SETFMOD(block, I0); // setfmod i0
+ UML_LABEL(block, skip); // skip:
}
return TRUE;
@@ -2821,18 +2821,18 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
{
case 0x00: /* BCzF - MIPS I */
case 0x02: /* BCzFL - MIPS II */
- UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
- UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ
- generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- UML_LABEL(block, skip); // skip:
+ UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
+ UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ
+ generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
+ UML_LABEL(block, skip); // skip:
return TRUE;
case 0x01: /* BCzT - MIPS I */
case 0x03: /* BCzTL - MIPS II */
- UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
- UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
- generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- UML_LABEL(block, skip); // skip:
+ UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
+ UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
+ generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
+ UML_LABEL(block, skip); // skip:
return TRUE;
}
break;
@@ -2843,126 +2843,126 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
case 0x00:
if (IS_SINGLE(op)) /* ADD.S - MIPS I */
{
- UML_FSADD(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fsadd <fdreg>,<fsreg>,<ftreg>
+ UML_FSADD(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fsadd <fdreg>,<fsreg>,<ftreg>
}
else /* ADD.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
- UML_FDADD(block, F2, F0, F1); // fdadd F2,F0,F1
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
+ UML_FDADD(block, F2, F0, F1); // fdadd F2,F0,F1
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
return TRUE;
case 0x01:
if (IS_SINGLE(op)) /* SUB.S - MIPS I */
{
- UML_FSSUB(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fssub <fdreg>,<fsreg>,<ftreg>
+ UML_FSSUB(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fssub <fdreg>,<fsreg>,<ftreg>
}
else /* SUB.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
- UML_FDSUB(block, F2, F0, F1); // fdsub F2,F0,F1
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
+ UML_FDSUB(block, F2, F0, F1); // fdsub F2,F0,F1
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
return TRUE;
case 0x02:
if (IS_SINGLE(op)) /* MUL.S - MIPS I */
{
- UML_FSMUL(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fsmul <fdreg>,<fsreg>,<ftreg>
+ UML_FSMUL(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fsmul <fdreg>,<fsreg>,<ftreg>
}
else /* MUL.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
- UML_FDMUL(block, F2, F0, F1); // fdmul F2,F0,F1
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
+ UML_FDMUL(block, F2, F0, F1); // fdmul F2,F0,F1
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
return TRUE;
case 0x03:
if (IS_SINGLE(op)) /* DIV.S - MIPS I */
{
- UML_FSDIV(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fsdiv <fdreg>,<fsreg>,<ftreg>
+ UML_FSDIV(block, FDVALS_FR0, FSVALS_FR0, FTVALS_FR0); // fsdiv <fdreg>,<fsreg>,<ftreg>
}
else /* DIV.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
- UML_FDDIV(block, F2, F0, F1); // fddiv F2,F0,F1
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov F1,<ftreg>
+ UML_FDDIV(block, F2, F0, F1); // fddiv F2,F0,F1
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,F2
}
return TRUE;
case 0x04:
if (IS_SINGLE(op)) /* SQRT.S - MIPS II */
{
- UML_FSSQRT(block, FDVALS_FR0, FSVALS_FR0); // fssqrt <fdreg>,<fsreg>
+ UML_FSSQRT(block, FDVALS_FR0, FSVALS_FR0); // fssqrt <fdreg>,<fsreg>
}
else /* SQRT.D - MIPS II */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDSQRT(block, F0, F0); // fdsqrt F0,F0
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDSQRT(block, F0, F0); // fdsqrt F0,F0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
return TRUE;
case 0x05:
if (IS_SINGLE(op)) /* ABS.S - MIPS I */
{
- UML_FSABS(block, FDVALS_FR0, FSVALS_FR0); // fsabs <fdreg>,<fsreg>
+ UML_FSABS(block, FDVALS_FR0, FSVALS_FR0); // fsabs <fdreg>,<fsreg>
}
else /* ABS.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDABS(block, F0, F0); // fdabs F0,F0
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDABS(block, F0, F0); // fdabs F0,F0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
return TRUE;
case 0x06:
if (IS_SINGLE(op)) /* MOV.S - MIPS I */
{
- UML_FSMOV(block, FDVALS_FR0, FSVALS_FR0); // fsmov <fdreg>,<fsreg>
+ UML_FSMOV(block, FDVALS_FR0, FSVALS_FR0); // fsmov <fdreg>,<fsreg>
}
else /* MOV.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
return TRUE;
case 0x07:
if (IS_SINGLE(op)) /* NEG.S - MIPS I */
{
- UML_FSNEG(block, FDVALS_FR0, FSVALS_FR0); // fsneg <fdreg>,<fsreg>
- UML_CMP(block, FSVALS_FR0, 0); // cmp <fsreg>,0.0
- UML_MOVc(block, COND_E, FDVALS_FR0, 0x80000000); // mov <fdreg>,-0.0,e
+ UML_FSNEG(block, FDVALS_FR0, FSVALS_FR0); // fsneg <fdreg>,<fsreg>
+ UML_CMP(block, FSVALS_FR0, 0); // cmp <fsreg>,0.0
+ UML_MOVc(block, COND_E, FDVALS_FR0, 0x80000000); // mov <fdreg>,-0.0,e
}
else /* NEG.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDNEG(block, F1, F0); // fdneg F1,F0
- UML_DCMP(block, F0, 0); // cmp F0,0.0
- UML_DMOVc(block, COND_E, F1, U64(0x8000000000000000)); // dmov F1,-0.0,e
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov <fdreg>,F1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDNEG(block, F1, F0); // fdneg F1,F0
+ UML_DCMP(block, F0, 0); // cmp F0,0.0
+ UML_DMOVc(block, COND_E, F1, U64(0x8000000000000000)); // dmov F1,-0.0,e
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov <fdreg>,F1
}
return TRUE;
case 0x08:
if (IS_SINGLE(op)) /* ROUND.L.S - MIPS III */
{
- UML_FSTOINT(block, F0, FSVALS_FR0, SIZE_QWORD, ROUND_ROUND);// fstoint f0,<fsreg>,qword,round
+ UML_FSTOINT(block, F0, FSVALS_FR0, SIZE_QWORD, ROUND_ROUND);// fstoint f0,<fsreg>,qword,round
}
else /* ROUND.L.D - MIPS III */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_ROUND); // fdtoint f0,f0,qword,round
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_ROUND); // fdtoint f0,f0,qword,round
}
- UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
- generate_set_cop1_reg64_i2d(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
+ UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
+ generate_set_cop1_reg64_i2d(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
return TRUE;
case 0x09:
@@ -2972,11 +2972,11 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* TRUNC.L.D - MIPS III */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_TRUNC); // fdtoint f0,f0,qword,trunc
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_TRUNC); // fdtoint f0,f0,qword,trunc
}
- UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
- generate_set_cop1_reg64_i2d(block, compiler, desc, FDREG, I0); // dmov <fdreg>,i0
+ UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
+ generate_set_cop1_reg64_i2d(block, compiler, desc, FDREG, I0); // dmov <fdreg>,i0
return TRUE;
case 0x0a:
@@ -2986,11 +2986,11 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* CEIL.L.D - MIPS III */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_CEIL); // fdtoint f0,<fsreg>,qword,ceil
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_CEIL); // fdtoint f0,<fsreg>,qword,ceil
}
- UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
- generate_set_cop1_reg64(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
+ UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
return TRUE;
case 0x0b:
@@ -3000,11 +3000,11 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* FLOOR.L.D - MIPS III */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_FLOOR); // fdtoint f0,<fsreg>,qword,floor
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_FLOOR); // fdtoint f0,<fsreg>,qword,floor
}
- UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
- generate_set_cop1_reg64(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
+ UML_ICOPYFD(block, I0, F0); // icopyfd i0,f0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, I0); // dmov <fdreg>,f0
return TRUE;
case 0x0c:
@@ -3014,8 +3014,8 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* ROUND.W.D - MIPS II */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_ROUND); // fdtoint <fdreg>,F0,dword,round
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_ROUND); // fdtoint <fdreg>,F0,dword,round
}
return TRUE;
@@ -3026,8 +3026,8 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* TRUNC.W.D - MIPS II */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_TRUNC); // fdtoint <fdreg>,F0,dword,trunc
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_TRUNC); // fdtoint <fdreg>,F0,dword,trunc
}
return TRUE;
@@ -3038,8 +3038,8 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* CEIL.W.D - MIPS II */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_CEIL); // fdtoint <fdreg>,F0,dword,ceil
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_CEIL); // fdtoint <fdreg>,F0,dword,ceil
}
return TRUE;
@@ -3050,8 +3050,8 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* FLOOR.W.D - MIPS II */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
- UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_FLOOR); // fdtoint <fdreg>,F0,dword,floor
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_FLOOR); // fdtoint <fdreg>,F0,dword,floor
}
return TRUE;
@@ -3066,71 +3066,71 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
else /* MOVT/F.D - MIPS IV */
{
condition = ((op >> 16) & 1) ? COND_Z : COND_NZ;
- generate_get_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov F0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov F0,<fsreg>
UML_JMPc(block, condition, skip = compiler->labelnum++);
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov F0,<fsreg>
UML_LABEL(block, skip);
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,F0
}
return TRUE;
case 0x12:
- UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
+ UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
if (IS_SINGLE(op)) /* MOVZ.S - MIPS IV */
{
- UML_FSMOVc(block, COND_Z, FDVALS_FR0, FSVALS_FR0); // fsmov <fdreg>,<fsreg>,Z
+ UML_FSMOVc(block, COND_Z, FDVALS_FR0, FSVALS_FR0); // fsmov <fdreg>,<fsreg>,Z
}
else /* MOVZ.D - MIPS IV */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov f1,<fdreg>
- UML_FDMOVc(block, COND_Z, F2, F0); // fdmov f2,<fsreg>,Z
- UML_FDMOVc(block, COND_NZ, F2, F1); // fdmov f2,<fdreg>,NZ
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,f0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov f1,<fdreg>
+ UML_FDMOVc(block, COND_Z, F2, F0); // fdmov f2,<fsreg>,Z
+ UML_FDMOVc(block, COND_NZ, F2, F1); // fdmov f2,<fdreg>,NZ
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,f0
}
return TRUE;
case 0x13:
- UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
+ UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
if (IS_SINGLE(op)) /* MOVN.S - MIPS IV */
{
- UML_FSMOVc(block, COND_NZ, FDVALS_FR0, FSVALS_FR0); // fsmov <fdreg>,<fsreg>,NZ
+ UML_FSMOVc(block, COND_NZ, FDVALS_FR0, FSVALS_FR0); // fsmov <fdreg>,<fsreg>,NZ
}
else /* MOVN.D - MIPS IV */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov f1,<fdreg>
- UML_FDMOVc(block, COND_NZ, F2, F0); // fdmov f2,<fsreg>,NZ
- UML_FDMOVc(block, COND_Z, F2, F1); // fdmov f2,<fdreg>,Z
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,f2
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FDREG, F1); // dmov f1,<fdreg>
+ UML_FDMOVc(block, COND_NZ, F2, F0); // fdmov f2,<fsreg>,NZ
+ UML_FDMOVc(block, COND_Z, F2, F1); // fdmov f2,<fdreg>,Z
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F2); // dmov <fdreg>,f2
}
return TRUE;
case 0x15:
if (IS_SINGLE(op)) /* RECIP.S - MIPS IV */
{
- UML_FSRECIP(block, FDVALS_FR0, FSVALS_FR0); // fsrecip <fdreg>,<fsreg>
+ UML_FSRECIP(block, FDVALS_FR0, FSVALS_FR0); // fsrecip <fdreg>,<fsreg>
}
else /* RECIP.D - MIPS IV */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDRECIP(block, F0, F0); // fdrecip f0,<fsreg>
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDRECIP(block, F0, F0); // fdrecip f0,<fsreg>
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
return TRUE;
case 0x16:
if (IS_SINGLE(op)) /* RSQRT.S - MIPS IV */
{
- UML_FSRSQRT(block, FDVALS_FR0, FSVALS_FR0); // fsrsqrt <fdreg>,<fsreg>
+ UML_FSRSQRT(block, FDVALS_FR0, FSVALS_FR0); // fsrsqrt <fdreg>,<fsreg>
}
else /* RSQRT.D - MIPS IV */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDRSQRT(block, F0, F0); // fdrsqrt f0,<fsreg>
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDRSQRT(block, F0, F0); // fdrsqrt f0,<fsreg>
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
return TRUE;
@@ -3143,14 +3143,14 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* CVT.S.L - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FSFRINT(block, FDVALS_FR0, F0, SIZE_QWORD); // fsfrint <fdreg>,f0,qword
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FSFRINT(block, FDVALS_FR0, F0, SIZE_QWORD); // fsfrint <fdreg>,f0,qword
}
}
else /* CVT.S.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FSFRFLT(block, FDVALS_FR0, F0, SIZE_QWORD); // fsfrflt <fdreg>,f0,qword
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FSFRFLT(block, FDVALS_FR0, F0, SIZE_QWORD); // fsfrflt <fdreg>,f0,qword
}
return TRUE;
@@ -3159,19 +3159,19 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
{
if (IS_SINGLE(op)) /* CVT.D.W - MIPS I */
{
- UML_FDFRINT(block, F0, FSVALS_FR0, SIZE_DWORD); // fdfrint f0,<fsreg>,dword
+ UML_FDFRINT(block, F0, FSVALS_FR0, SIZE_DWORD); // fdfrint f0,<fsreg>,dword
}
else /* CVT.D.L - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDFRINT(block, F0, F0, SIZE_QWORD); // fdfrint f0,f0,qword
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDFRINT(block, F0, F0, SIZE_QWORD); // fdfrint f0,f0,qword
}
}
else /* CVT.D.S - MIPS I */
{
- UML_FDFRFLT(block, F0, FSVALS_FR0, SIZE_DWORD); // fdfrflt f0,<fsreg>,dword
+ UML_FDFRFLT(block, F0, FSVALS_FR0, SIZE_DWORD); // fdfrflt f0,<fsreg>,dword
}
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
return TRUE;
case 0x24:
@@ -3181,7 +3181,7 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* CVT.W.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
UML_FDTOINT(block, FDVALS_FR0, F0, SIZE_DWORD, ROUND_DEFAULT);// fdtoint <fdreg>,f0,dword,default
}
return TRUE;
@@ -3190,13 +3190,13 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
if (IS_SINGLE(op)) /* CVT.L.S - MIPS I */
{
UML_FSTOINT(block, F0, FSVALS_FR0, SIZE_QWORD, ROUND_DEFAULT);// fstoint f0,<fsreg>,qword,default
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
else /* CVT.L.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,qword,default
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ UML_FDTOINT(block, F0, F0, SIZE_QWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,qword,default
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F0); // dmov <fdreg>,f0
}
return TRUE;
@@ -3213,9 +3213,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.UN.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_U, I0); // set i0,u
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8));
@@ -3230,9 +3230,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.EQ.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_E, I0); // set i0,e
UML_SETc(block, COND_NU, I1); // set i1,nu
@@ -3249,9 +3249,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.UEQ.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_U, I0); // set i0,u
UML_SETc(block, COND_E, I1); // set i1,e
@@ -3268,9 +3268,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.OLT.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_B, I0); // set i0,b
UML_SETc(block, COND_NU, I1); // set i1,nu
@@ -3287,9 +3287,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.ULT.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_U, I0); // set i0,u
UML_SETc(block, COND_B, I1); // set i1,b
@@ -3306,9 +3306,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.OLE.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_BE, I0); // set i0,be
UML_SETc(block, COND_NU, I1); // set i1,nu
@@ -3325,9 +3325,9 @@ int mips3_device::generate_cop1_fr0(drcuml_block *block, compiler_state *compile
}
else /* C.ULE.D - MIPS I */
{
- generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
- generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
- UML_FDCMP(block, F0, F1); // fdcmp f0,f1
+ generate_get_cop1_reg64(block, compiler, desc, FSREG, F0); // dmov f0,<fsreg>
+ generate_get_cop1_reg64(block, compiler, desc, FTREG, F1); // dmov f1,<ftreg>
+ UML_FDCMP(block, F0, F1); // fdcmp f0,f1
}
UML_SETc(block, COND_U, I0); // set i0,u
UML_SETc(block, COND_BE, I1); // set i1,be
@@ -3358,7 +3358,7 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
case 0x00: /* MFC1 - MIPS I */
if (RTREG != 0)
{
- UML_DSEXT(block, R64(RTREG), FPR32_FR0(RDREG), SIZE_DWORD); // dsext <rtreg>,fpr[rdreg],dword
+ UML_DSEXT(block, R64(RTREG), FPR32_FR0(RDREG), SIZE_DWORD); // dsext <rtreg>,fpr[rdreg],dword
}
return TRUE;
@@ -3372,11 +3372,11 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
case 0x02: /* CFC1 - MIPS I */
if (RTREG != 0)
- UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr132[rdreg],dword
+ UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD); // dsext <rtreg>,ccr132[rdreg],dword
return TRUE;
case 0x04: /* MTC1 - MIPS I */
- UML_MOV(block, FPR32_FR0(RDREG), R32(RTREG)); // mov fpr[rdreg],<rtreg>
+ UML_MOV(block, FPR32_FR0(RDREG), R32(RTREG)); // mov fpr[rdreg],<rtreg>
return TRUE;
case 0x05: /* DMTC1 - MIPS III */
@@ -3387,18 +3387,18 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
case 0x06: /* CTC1 - MIPS I */
if (RDREG != 31)
{
- UML_DSEXT(block, CCR164(RDREG), R32(RTREG), SIZE_DWORD); // dsext ccr1[rdreg],<rtreg>,dword
+ UML_DSEXT(block, CCR164(RDREG), R32(RTREG), SIZE_DWORD); // dsext ccr1[rdreg],<rtreg>,dword
}
else
{
- UML_XOR(block, I0, CCR132(31), R32(RTREG)); // xor i0,ccr1[31],<rtreg>
- UML_DSEXT(block, CCR164(31), R32(RTREG), SIZE_DWORD); // dsext ccr1[31],<rtreg>,dword
- UML_TEST(block, I0, 3); // test i0,3
- UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
- UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3
- UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte
- UML_SETFMOD(block, I0); // setfmod i0
- UML_LABEL(block, skip); // skip:
+ UML_XOR(block, I0, CCR132(31), R32(RTREG)); // xor i0,ccr1[31],<rtreg>
+ UML_DSEXT(block, CCR164(31), R32(RTREG), SIZE_DWORD); // dsext ccr1[31],<rtreg>,dword
+ UML_TEST(block, I0, 3); // test i0,3
+ UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
+ UML_AND(block, I0, CCR132(31), 3); // and i0,ccr1[31],3
+ UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1); // load i0,fpmode,i0,byte
+ UML_SETFMOD(block, I0); // setfmod i0
+ UML_LABEL(block, skip); // skip:
}
return TRUE;
@@ -3407,18 +3407,18 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
{
case 0x00: /* BCzF - MIPS I */
case 0x02: /* BCzFL - MIPS II */
- UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
- UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ
- generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- UML_LABEL(block, skip); // skip:
+ UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
+ UML_JMPc(block, COND_NZ, skip = compiler->labelnum++); // jmp skip,NZ
+ generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
+ UML_LABEL(block, skip); // skip:
return TRUE;
case 0x01: /* BCzT - MIPS I */
case 0x03: /* BCzTL - MIPS II */
- UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
- UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
- generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
- UML_LABEL(block, skip); // skip:
+ UML_TEST(block, CCR132(31), FCCMASK(op >> 18)); // test ccr1[31],fccmask[which]
+ UML_JMPc(block, COND_Z, skip = compiler->labelnum++); // jmp skip,Z
+ generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
+ UML_LABEL(block, skip); // skip:
return TRUE;
}
break;
@@ -3428,122 +3428,122 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
{
case 0x00:
if (IS_SINGLE(op)) /* ADD.S - MIPS I */
- UML_FSADD(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsadd <fdreg>,<fsreg>,<ftreg>
+ UML_FSADD(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsadd <fdreg>,<fsreg>,<ftreg>
else /* ADD.D - MIPS I */
- UML_FDADD(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdadd <fdreg>,<fsreg>,<ftreg>
+ UML_FDADD(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdadd <fdreg>,<fsreg>,<ftreg>
return TRUE;
case 0x01:
if (IS_SINGLE(op)) /* SUB.S - MIPS I */
- UML_FSSUB(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fssub <fdreg>,<fsreg>,<ftreg>
+ UML_FSSUB(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fssub <fdreg>,<fsreg>,<ftreg>
else /* SUB.D - MIPS I */
- UML_FDSUB(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdsub <fdreg>,<fsreg>,<ftreg>
+ UML_FDSUB(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdsub <fdreg>,<fsreg>,<ftreg>
return TRUE;
case 0x02:
if (IS_SINGLE(op)) /* MUL.S - MIPS I */
- UML_FSMUL(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsmul <fdreg>,<fsreg>,<ftreg>
+ UML_FSMUL(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsmul <fdreg>,<fsreg>,<ftreg>
else /* MUL.D - MIPS I */
- UML_FDMUL(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdmul <fdreg>,<fsreg>,<ftreg>
+ UML_FDMUL(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fdmul <fdreg>,<fsreg>,<ftreg>
return TRUE;
case 0x03:
if (IS_SINGLE(op)) /* DIV.S - MIPS I */
- UML_FSDIV(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsdiv <fdreg>,<fsreg>,<ftreg>
+ UML_FSDIV(block, FDVALS_FR1, FSVALS_FR1, FTVALS_FR1); // fsdiv <fdreg>,<fsreg>,<ftreg>
else /* DIV.D - MIPS I */
- UML_FDDIV(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fddiv <fdreg>,<fsreg>,<ftreg>
+ UML_FDDIV(block, FDVALD_FR1, FSVALD_FR1, FTVALD_FR1); // fddiv <fdreg>,<fsreg>,<ftreg>
return TRUE;
case 0x04:
if (IS_SINGLE(op)) /* SQRT.S - MIPS II */
- UML_FSSQRT(block, FDVALS_FR1, FSVALS_FR1); // fssqrt <fdreg>,<fsreg>
+ UML_FSSQRT(block, FDVALS_FR1, FSVALS_FR1); // fssqrt <fdreg>,<fsreg>
else /* SQRT.D - MIPS II */
- UML_FDSQRT(block, FDVALD_FR1, FSVALD_FR1); // fdsqrt <fdreg>,<fsreg>
+ UML_FDSQRT(block, FDVALD_FR1, FSVALD_FR1); // fdsqrt <fdreg>,<fsreg>
return TRUE;
case 0x05:
if (IS_SINGLE(op)) /* ABS.S - MIPS I */
- UML_FSABS(block, FDVALS_FR1, FSVALS_FR1); // fsabs <fdreg>,<fsreg>
+ UML_FSABS(block, FDVALS_FR1, FSVALS_FR1); // fsabs <fdreg>,<fsreg>
else /* ABS.D - MIPS I */
- UML_FDABS(block, FDVALD_FR1, FSVALD_FR1); // fdabs <fdreg>,<fsreg>
+ UML_FDABS(block, FDVALD_FR1, FSVALD_FR1); // fdabs <fdreg>,<fsreg>
return TRUE;
case 0x06:
if (IS_SINGLE(op)) /* MOV.S - MIPS I */
- UML_FSMOV(block, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>
+ UML_FSMOV(block, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>
else /* MOV.D - MIPS I */
- UML_FDMOV(block, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>
+ UML_FDMOV(block, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>
return TRUE;
case 0x07:
if (IS_SINGLE(op)) /* NEG.S - MIPS I */
{
- UML_FSNEG(block, FDVALS_FR1, FSVALS_FR1); // fsneg <fdreg>,<fsreg>
- UML_CMP(block, FSVALS_FR1, 0); // cmp <fsreg>,0.0
- UML_MOVc(block, COND_E, FDVALS_FR1, 0x80000000); // mov <fdreg>,-0.0,e
+ UML_FSNEG(block, FDVALS_FR1, FSVALS_FR1); // fsneg <fdreg>,<fsreg>
+ UML_CMP(block, FSVALS_FR1, 0); // cmp <fsreg>,0.0
+ UML_MOVc(block, COND_E, FDVALS_FR1, 0x80000000); // mov <fdreg>,-0.0,e
}
else /* NEG.D - MIPS I */
{
- UML_FDNEG(block, FDVALD_FR1, FSVALD_FR1); // fdneg <fdreg>,<fsreg>
- UML_DCMP(block, FSVALD_FR1, 0); // dcmp <fsreg>,0.0
- UML_DMOVc(block, COND_E, FDVALD_FR1, 0x8000000000000000L);// mov <fdreg>,-0.0,e
+ UML_FDNEG(block, FDVALD_FR1, FSVALD_FR1); // fdneg <fdreg>,<fsreg>
+ UML_DCMP(block, FSVALD_FR1, 0); // dcmp <fsreg>,0.0
+ UML_DMOVc(block, COND_E, FDVALD_FR1, 0x8000000000000000L);// mov <fdreg>,-0.0,e
}
return TRUE;
case 0x08:
if (IS_SINGLE(op)) /* ROUND.L.S - MIPS III */
- UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_ROUND); // fstoint f0,<fsreg>,qword,round
+ UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_ROUND); // fstoint f0,<fsreg>,qword,round
else /* ROUND.L.D - MIPS III */
- UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_ROUND); // fdtoint f0,f0,qword,round
+ UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_ROUND); // fdtoint f0,f0,qword,round
return TRUE;
case 0x09:
if (IS_SINGLE(op)) /* TRUNC.L.S - MIPS III */
- UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_TRUNC); // fstoint f0,<fsreg>,qword,trunc
+ UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_TRUNC); // fstoint f0,<fsreg>,qword,trunc
else /* TRUNC.L.D - MIPS III */
- UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_TRUNC); // fdtoint f0,f0,qword,trunc
+ UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_TRUNC); // fdtoint f0,f0,qword,trunc
return TRUE;
case 0x0a:
if (IS_SINGLE(op)) /* CEIL.L.S - MIPS III */
- UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_CEIL); // fstoint f0,<fsreg>,qword,ceil
+ UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_CEIL); // fstoint f0,<fsreg>,qword,ceil
else /* CEIL.L.D - MIPS III */
- UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_CEIL); // fdtoint f0,<fsreg>,qword,ceil
+ UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_CEIL); // fdtoint f0,<fsreg>,qword,ceil
return TRUE;
case 0x0b:
if (IS_SINGLE(op)) /* FLOOR.L.S - MIPS III */
- UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_FLOOR); // fstoint f0,<fsreg>,qword,floor
+ UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_FLOOR); // fstoint f0,<fsreg>,qword,floor
else /* FLOOR.L.D - MIPS III */
- UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_FLOOR); // fdtoint f0,<fsreg>,qword,floor
+ UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_FLOOR); // fdtoint f0,<fsreg>,qword,floor
return TRUE;
case 0x0c:
if (IS_SINGLE(op)) /* ROUND.W.S - MIPS II */
- UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_ROUND); // fstoint <fdreg>,<fsreg>,dword,round
+ UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_ROUND); // fstoint <fdreg>,<fsreg>,dword,round
else /* ROUND.W.D - MIPS II */
- UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_ROUND); // fdtoint <fdreg>,F0,dword,round
+ UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_ROUND); // fdtoint <fdreg>,F0,dword,round
return TRUE;
case 0x0d:
if (IS_SINGLE(op)) /* TRUNC.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_TRUNC);// fstoint <fdreg>,<fsreg>,dword,trunc
else /* TRUNC.W.D - MIPS II */
- UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_TRUNC); // fdtoint <fdreg>,F0,dword,trunc
+ UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_TRUNC); // fdtoint <fdreg>,F0,dword,trunc
return TRUE;
case 0x0e:
if (IS_SINGLE(op)) /* CEIL.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_CEIL);// fstoint <fdreg>,<fsreg>,dword,ceil
else /* CEIL.W.D - MIPS II */
- UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_CEIL); // fdtoint <fdreg>,F0,dword,ceil
+ UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_CEIL); // fdtoint <fdreg>,F0,dword,ceil
return TRUE;
case 0x0f:
if (IS_SINGLE(op)) /* FLOOR.W.S - MIPS II */
UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_FLOOR);// fstoint <fdreg>,<fsreg>,dword,floor
else /* FLOOR.W.D - MIPS II */
- UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_FLOOR); // fdtoint <fdreg>,F0,dword,floor
+ UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_FLOOR); // fdtoint <fdreg>,F0,dword,floor
return TRUE;
case 0x11:
@@ -3556,46 +3556,46 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
return TRUE;
case 0x12:
- UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
+ UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
if (IS_SINGLE(op)) /* MOVZ.S - MIPS IV */
- UML_FSMOVc(block, COND_Z, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,Z
+ UML_FSMOVc(block, COND_Z, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,Z
else /* MOVZ.D - MIPS IV */
- UML_FDMOVc(block, COND_Z, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,Z
+ UML_FDMOVc(block, COND_Z, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,Z
return TRUE;
case 0x13:
- UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
+ UML_DCMP(block, R64(RTREG), 0); // dcmp <rtreg>,0
if (IS_SINGLE(op)) /* MOVN.S - MIPS IV */
- UML_FSMOVc(block, COND_NZ, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,NZ
+ UML_FSMOVc(block, COND_NZ, FDVALS_FR1, FSVALS_FR1); // fsmov <fdreg>,<fsreg>,NZ
else /* MOVN.D - MIPS IV */
- UML_FDMOVc(block, COND_NZ, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,NZ
+ UML_FDMOVc(block, COND_NZ, FDVALD_FR1, FSVALD_FR1); // fdmov <fdreg>,<fsreg>,NZ
return TRUE;
case 0x15:
if (IS_SINGLE(op)) /* RECIP.S - MIPS IV */
- UML_FSRECIP(block, FDVALS_FR1, FSVALS_FR1); // fsrecip <fdreg>,<fsreg>
+ UML_FSRECIP(block, FDVALS_FR1, FSVALS_FR1); // fsrecip <fdreg>,<fsreg>
else /* RECIP.D - MIPS IV */
- UML_FDRECIP(block, FDVALD_FR1, FSVALD_FR1); // fdrecip <fdreg>,<fsreg>
+ UML_FDRECIP(block, FDVALD_FR1, FSVALD_FR1); // fdrecip <fdreg>,<fsreg>
return TRUE;
case 0x16:
if (IS_SINGLE(op)) /* RSQRT.S - MIPS IV */
- UML_FSRSQRT(block, FDVALS_FR1, FSVALS_FR1); // fsrsqrt <fdreg>,<fsreg>
+ UML_FSRSQRT(block, FDVALS_FR1, FSVALS_FR1); // fsrsqrt <fdreg>,<fsreg>
else /* RSQRT.D - MIPS IV */
- UML_FDRSQRT(block, FDVALD_FR1, FSVALD_FR1); // fdrsqrt <fdreg>,<fsreg>
+ UML_FDRSQRT(block, FDVALD_FR1, FSVALD_FR1); // fdrsqrt <fdreg>,<fsreg>
return TRUE;
case 0x20:
if (IS_INTEGRAL(op))
{
if (IS_SINGLE(op)) /* CVT.S.W - MIPS I */
- UML_FSFRINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD); // fsfrint <fdreg>,<fsreg>,dword
+ UML_FSFRINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD); // fsfrint <fdreg>,<fsreg>,dword
else /* CVT.S.L - MIPS I */
- UML_FSFRINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_QWORD); // fsfrint <fdreg>,<fsreg>,qword
+ UML_FSFRINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_QWORD); // fsfrint <fdreg>,<fsreg>,qword
}
else /* CVT.S.D - MIPS I */
{
- UML_FSFRFLT(block, FDVALS_FR1, FSVALD_FR1, SIZE_QWORD); // fsfrflt <fdreg>,f0,qword
+ UML_FSFRFLT(block, FDVALS_FR1, FSVALD_FR1, SIZE_QWORD); // fsfrflt <fdreg>,f0,qword
}
return TRUE;
@@ -3603,28 +3603,28 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
if (IS_INTEGRAL(op))
{
if (IS_SINGLE(op)) /* CVT.D.W - MIPS I */
- UML_FDFRINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_DWORD); // fdfrint <fdreg>,<fsreg>,dword
+ UML_FDFRINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_DWORD); // fdfrint <fdreg>,<fsreg>,dword
else /* CVT.D.L - MIPS I */
- UML_FDFRINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD); // fdfrint <fdreg>,<fsreg>,qword
+ UML_FDFRINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD); // fdfrint <fdreg>,<fsreg>,qword
}
else /* CVT.D.S - MIPS I */
{
- UML_FDFRFLT(block, FDVALD_FR1, FDVALS_FR1, SIZE_DWORD); // fdfrflt <fdreg>,<fsreg>,dword
+ UML_FDFRFLT(block, FDVALD_FR1, FDVALS_FR1, SIZE_DWORD); // fdfrflt <fdreg>,<fsreg>,dword
}
return TRUE;
case 0x24:
if (IS_SINGLE(op)) /* CVT.W.S - MIPS I */
- UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_DEFAULT); // fstoint <fdreg>,<fsreg>,dword,default
+ UML_FSTOINT(block, FDVALS_FR1, FSVALS_FR1, SIZE_DWORD, ROUND_DEFAULT); // fstoint <fdreg>,<fsreg>,dword,default
else /* CVT.W.D - MIPS I */
- UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,dword,default
+ UML_FDTOINT(block, FDVALS_FR1, FSVALD_FR1, SIZE_DWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,dword,default
return TRUE;
case 0x25:
if (IS_SINGLE(op)) /* CVT.L.S - MIPS I */
- UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_DEFAULT); // fstoint <fdreg>,<fsreg>,qword,default
+ UML_FSTOINT(block, FDVALD_FR1, FSVALS_FR1, SIZE_QWORD, ROUND_DEFAULT); // fstoint <fdreg>,<fsreg>,qword,default
else /* CVT.L.D - MIPS I */
- UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,qword,default
+ UML_FDTOINT(block, FDVALD_FR1, FSVALD_FR1, SIZE_QWORD, ROUND_DEFAULT); // fdtoint <fdreg>,<fsreg>,qword,default
return TRUE;
case 0x30:
@@ -3635,82 +3635,82 @@ int mips3_device::generate_cop1_fr1(drcuml_block *block, compiler_state *compile
case 0x31:
case 0x39:
if (IS_SINGLE(op)) /* C.UN.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.UN.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp <fsreg>,<ftreg>
- UML_SETc(block, COND_U, I0); // set i0,u
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp <fsreg>,<ftreg>
+ UML_SETc(block, COND_U, I0); // set i0,u
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
case 0x32:
case 0x3a:
if (IS_SINGLE(op)) /* C.EQ.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.EQ.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp <fsreg>,<ftreg>
- UML_SETc(block, COND_E, I0); // set i0,e
- UML_SETc(block, COND_NU, I1); // set i1,nu
- UML_AND(block, I0, I0, I1); // and i0,i0,i1
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp <fsreg>,<ftreg>
+ UML_SETc(block, COND_E, I0); // set i0,e
+ UML_SETc(block, COND_NU, I1); // set i1,nu
+ UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
case 0x33:
case 0x3b:
if (IS_SINGLE(op)) /* C.UEQ.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.UEQ.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
- UML_SETc(block, COND_U, I0); // set i0,u
- UML_SETc(block, COND_E, I1); // set i1,e
- UML_OR(block, I0, I0, I1); // or i0,i0,i1
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
+ UML_SETc(block, COND_U, I0); // set i0,u
+ UML_SETc(block, COND_E, I1); // set i1,e
+ UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
case 0x34:
case 0x3c:
if (IS_SINGLE(op)) /* C.OLT.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.OLT.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
- UML_SETc(block, COND_B, I0); // set i0,b
- UML_SETc(block, COND_NU, I1); // set i1,nu
- UML_AND(block, I0, I0, I1); // and i0,i0,i1
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
+ UML_SETc(block, COND_B, I0); // set i0,b
+ UML_SETc(block, COND_NU, I1); // set i1,nu
+ UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
case 0x35:
case 0x3d:
if (IS_SINGLE(op)) /* C.ULT.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.ULT.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
- UML_SETc(block, COND_U, I0); // set i0,u
- UML_SETc(block, COND_B, I1); // set i1,b
- UML_OR(block, I0, I0, I1); // or i0,i0,i1
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
+ UML_SETc(block, COND_U, I0); // set i0,u
+ UML_SETc(block, COND_B, I1); // set i1,b
+ UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
case 0x36:
case 0x3e:
if (IS_SINGLE(op)) /* C.OLE.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.OLE.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
- UML_SETc(block, COND_BE, I0); // set i0,be
- UML_SETc(block, COND_NU, I1); // set i1,nu
- UML_AND(block, I0, I0, I1); // and i0,i0,i1
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
+ UML_SETc(block, COND_BE, I0); // set i0,be
+ UML_SETc(block, COND_NU, I1); // set i1,nu
+ UML_AND(block, I0, I0, I1); // and i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
case 0x37:
case 0x3f:
if (IS_SINGLE(op)) /* C.ULE.S - MIPS I */
- UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
+ UML_FSCMP(block, FSVALS_FR1, FTVALS_FR1); // fscmp <fsreg>,<ftreg>
else /* C.ULE.D - MIPS I */
- UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
- UML_SETc(block, COND_U, I0); // set i0,u
- UML_SETc(block, COND_BE, I1); // set i1,be
- UML_OR(block, I0, I0, I1); // or i0,i0,i1
+ UML_FDCMP(block, FSVALD_FR1, FTVALD_FR1); // fdcmp f0,f1
+ UML_SETc(block, COND_U, I0); // set i0,u
+ UML_SETc(block, COND_BE, I1); // set i1,be
+ UML_OR(block, I0, I0, I1); // or i0,i0,i1
UML_ROLINS(block, CCR132(31), I0, FCCSHIFT(op >> 8), FCCMASK(op >> 8)); // rolins ccr31,i0,fccshift,fcc
return TRUE;
}
@@ -3737,33 +3737,33 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
switch (op & 0x3f)
{
case 0x00: /* LWXC1 - MIPS IV */
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
- UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
- UML_MOV(block, FDVALS_FR0, I0); // mov <cpr1_fd>,i0
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
+ UML_MOV(block, FDVALS_FR0, I0); // mov <cpr1_fd>,i0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
case 0x01: /* LDXC1 - MIPS IV */
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
- UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
generate_set_cop1_reg64_i2d(block, compiler, desc, RTREG, I0);
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
case 0x08: /* SWXC1 - MIPS IV */
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
- UML_MOV(block, I1, FSVALS_FR0); // mov i1,<cpr1_fs>
- UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_MOV(block, I1, FSVALS_FR0); // mov i1,<cpr1_fs>
+ UML_CALLH(block, *m_write32[m_core->mode >> 1]); // callh write32
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
case 0x09: /* SDXC1 - MIPS IV */
generate_get_cop1_reg64_d2i(block, compiler, desc, FSREG, I1);
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
- UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_CALLH(block, *m_write64[m_core->mode >> 1]); // callh write64
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
@@ -3772,61 +3772,61 @@ int mips3_device::generate_cop1x_fr0(drcuml_block *block, compiler_state *compil
return TRUE;
case 0x20: /* MADD.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
- UML_FSADD(block, FDVALS_FR0, F0, FRVALS_FR0); // fsadd <fdreg>,f0,<frreg>
+ UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSADD(block, FDVALS_FR0, F0, FRVALS_FR0); // fsadd <fdreg>,f0,<frreg>
return TRUE;
case 0x21: /* MADD.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
generate_get_cop1_reg64(block, compiler, desc, FTREG, F1);
generate_get_cop1_reg64(block, compiler, desc, FRREG, F2);
- UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
- UML_FDADD(block, F3, F3, F2); // fdadd f3,f3,f2
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
+ UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
+ UML_FDADD(block, F3, F3, F2); // fdadd f3,f3,f2
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
return TRUE;
case 0x28: /* MSUB.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
- UML_FSSUB(block, FDVALS_FR0, F0, FRVALS_FR0); // fssub <fdreg>,f0,<frreg>
+ UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSSUB(block, FDVALS_FR0, F0, FRVALS_FR0); // fssub <fdreg>,f0,<frreg>
return TRUE;
case 0x29: /* MSUB.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
generate_get_cop1_reg64(block, compiler, desc, FTREG, F1);
generate_get_cop1_reg64(block, compiler, desc, FRREG, F2);
- UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
- UML_FDSUB(block, F3, F3, F2); // fdadd f3,f3,f2
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
+ UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
+ UML_FDSUB(block, F3, F3, F2); // fdadd f3,f3,f2
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
return TRUE;
case 0x30: /* NMADD.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
- UML_FSADD(block, F0, F0, FRVALS_FR0); // fsadd f0,f0,<frreg>
- UML_FSNEG(block, FDVALS_FR0, F0); // fsneg <fdreg>,f0
+ UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSADD(block, F0, F0, FRVALS_FR0); // fsadd f0,f0,<frreg>
+ UML_FSNEG(block, FDVALS_FR0, F0); // fsneg <fdreg>,f0
return TRUE;
case 0x31: /* NMADD.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
generate_get_cop1_reg64(block, compiler, desc, FTREG, F1);
generate_get_cop1_reg64(block, compiler, desc, FRREG, F2);
- UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
- UML_FDADD(block, F3, F3, F2); // fdadd f3,f3,f2
- UML_FDNEG(block, F3, F3); // fdneg f3,f3
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
+ UML_FDMUL(block, F3, F0, F1); // fdmul f3,f0,f1
+ UML_FDADD(block, F3, F3, F2); // fdadd f3,f3,f2
+ UML_FDNEG(block, F3, F3); // fdneg f3,f3
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
return TRUE;
case 0x38: /* NMSUB.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
- UML_FSSUB(block, FDVALS_FR0, FRVALS_FR0, F0); // fssub <fdreg>,<frreg>,f0
+ UML_FSMUL(block, F0, FSVALS_FR0, FTVALS_FR0); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSSUB(block, FDVALS_FR0, FRVALS_FR0, F0); // fssub <fdreg>,<frreg>,f0
return TRUE;
case 0x39: /* NMSUB.D - MIPS IV */
generate_get_cop1_reg64(block, compiler, desc, FSREG, F0);
generate_get_cop1_reg64(block, compiler, desc, FTREG, F1);
generate_get_cop1_reg64(block, compiler, desc, FRREG, F2);
- UML_FDMUL(block, F3, F0, F1); // fdmul f4,f0,f1
- UML_FDSUB(block, F3, F2, F0); // fdsub f3,f2,f0
- generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
+ UML_FDMUL(block, F3, F0, F1); // fdmul f4,f0,f1
+ UML_FDSUB(block, F3, F2, F0); // fdsub f3,f2,f0
+ generate_set_cop1_reg64(block, compiler, desc, FDREG, F3); // dmov <fdreg>,f3
return TRUE;
default:
@@ -3850,24 +3850,24 @@ int mips3_device::generate_cop1x_fr1(drcuml_block *block, compiler_state *compil
switch (op & 0x3f)
{
case 0x00: /* LWXC1 - MIPS IV */
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
- UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
- UML_MOV(block, FDVALS_FR1, I0); // mov <cpr1_fd>,i0
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh read32
+ UML_MOV(block, FDVALS_FR1, I0); // mov <cpr1_fd>,i0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
case 0x01: /* LDXC1 - MIPS IV */
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh read64
- UML_DMOV(block, FDVALD_FR1, I0); // dmov <cpr1_fd>,i0
+ UML_DMOV(block, FDVALD_FR1, I0); // dmov <cpr1_fd>,i0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
return TRUE;
case 0x08: /* SWXC1 - MIPS IV */
- UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
- UML_MOV(block, I1, FSVALS_FR1); // mov i1,<cpr1_fs>
+ UML_ADD(block, I0, R32(RSREG), R32(RTREG)); // add i0,<rsreg>,<rtreg>
+ UML_MOV(block, I1, FSVALS_FR1); // mov i1,<cpr1_fs>
UML_CALLH(block, *m_write32[m_core->mode >> 1]);// callh write32
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
@@ -3885,45 +3885,45 @@ int mips3_device::generate_cop1x_fr1(drcuml_block *block, compiler_state *compil
return TRUE;
case 0x20: /* MADD.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
- UML_FSADD(block, FDVALS_FR1, F0, FRVALS_FR1); // fsadd <fdreg>,f0,<frreg>
+ UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSADD(block, FDVALS_FR1, F0, FRVALS_FR1); // fsadd <fdreg>,f0,<frreg>
return TRUE;
case 0x21: /* MADD.D - MIPS IV */
- UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
- UML_FDADD(block, FDVALD_FR1, F0, FRVALD_FR1); // fdadd <fdreg>,f0,<frreg>
+ UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
+ UML_FDADD(block, FDVALD_FR1, F0, FRVALD_FR1); // fdadd <fdreg>,f0,<frreg>
return TRUE;
case 0x28: /* MSUB.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
- UML_FSSUB(block, FDVALS_FR1, F0, FRVALS_FR1); // fssub <fdreg>,f0,<frreg>
+ UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSSUB(block, FDVALS_FR1, F0, FRVALS_FR1); // fssub <fdreg>,f0,<frreg>
return TRUE;
case 0x29: /* MSUB.D - MIPS IV */
- UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
- UML_FDSUB(block, FDVALD_FR1, F0, FRVALD_FR1); // fdsub <fdreg>,f0,<frreg>
+ UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
+ UML_FDSUB(block, FDVALD_FR1, F0, FRVALD_FR1); // fdsub <fdreg>,f0,<frreg>
return TRUE;
case 0x30: /* NMADD.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
- UML_FSADD(block, F0, F0, FRVALS_FR1); // fsadd f0,f0,<frreg>
- UML_FSNEG(block, FDVALS_FR1, F0); // fsneg <fdreg>,f0
+ UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSADD(block, F0, F0, FRVALS_FR1); // fsadd f0,f0,<frreg>
+ UML_FSNEG(block, FDVALS_FR1, F0); // fsneg <fdreg>,f0
return TRUE;
case 0x31: /* NMADD.D - MIPS IV */
- UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
- UML_FDADD(block, F0, F0, FRVALD_FR1); // fdadd f0,f0,<frreg>
- UML_FDNEG(block, FDVALD_FR1, F0); // fdneg <fdreg>,f0
+ UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
+ UML_FDADD(block, F0, F0, FRVALD_FR1); // fdadd f0,f0,<frreg>
+ UML_FDNEG(block, FDVALD_FR1, F0); // fdneg <fdreg>,f0
return TRUE;
case 0x38: /* NMSUB.S - MIPS IV */
- UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
- UML_FSSUB(block, FDVALS_FR1, FRVALS_FR1, F0); // fssub <fdreg>,<frreg>,f0
+ UML_FSMUL(block, F0, FSVALS_FR1, FTVALS_FR1); // fsmul f0,<fsreg>,<ftreg>
+ UML_FSSUB(block, FDVALS_FR1, FRVALS_FR1, F0); // fssub <fdreg>,<frreg>,f0
return TRUE;
case 0x39: /* NMSUB.D - MIPS IV */
- UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
- UML_FDSUB(block, FDVALD_FR1, FRVALD_FR1, F1); // fdsub <fdreg>,<frreg>,f0
+ UML_FDMUL(block, F0, FSVALD_FR1, FTVALD_FR1); // fdmul f0,<fsreg>,<ftreg>
+ UML_FDSUB(block, FDVALD_FR1, FRVALD_FR1, F1); // fdsub <fdreg>,<frreg>,f0
return TRUE;
default:
diff --git a/src/devices/cpu/powerpc/ppccom.cpp b/src/devices/cpu/powerpc/ppccom.cpp
index f83e28e5750..ce7249a6414 100644
--- a/src/devices/cpu/powerpc/ppccom.cpp
+++ b/src/devices/cpu/powerpc/ppccom.cpp
@@ -951,7 +951,7 @@ void ppc_device::device_start()
if (beinfo.direct_iregs > 7)
m_regmap[2] = uml::I7;
-
+
if (beinfo.direct_fregs > 3)
m_fdregmap[0] = uml::F3;
if (beinfo.direct_fregs > 4)
diff --git a/src/devices/cpu/sm510/sm500.h b/src/devices/cpu/sm510/sm500.h
index aaf083c293a..0743632609d 100644
--- a/src/devices/cpu/sm510/sm500.h
+++ b/src/devices/cpu/sm510/sm500.h
@@ -39,7 +39,7 @@ O46 47 | | 14 K3
O36 48 | * | 13 K2
|________________________________________________/
- 1 2 3 4 5 6 7 8 9 10 11 12
+ 1 2 3 4 5 6 7 8 9 10 11 12
O26 O16 R4 R3 R2 R1 GND _T bt al ACL K1 note: bt = beta symbol, al = alpha symbol
*/
@@ -57,7 +57,7 @@ protected:
// opcode handlers
virtual void op_lb() override;
virtual void op_incb() override;
-
+
virtual void op_comcb();
virtual void op_ssr();
virtual void op_trs();
diff --git a/src/devices/cpu/sm510/sm500op.cpp b/src/devices/cpu/sm510/sm500op.cpp
index bb0bc6f043b..ee4571b4e76 100644
--- a/src/devices/cpu/sm510/sm500op.cpp
+++ b/src/devices/cpu/sm510/sm500op.cpp
@@ -92,4 +92,3 @@ void sm500_device::op_comcn()
}
// Test instructions
-
diff --git a/src/devices/cpu/sm510/sm510.cpp b/src/devices/cpu/sm510/sm510.cpp
index a602e611d99..b5eb56ab24f 100644
--- a/src/devices/cpu/sm510/sm510.cpp
+++ b/src/devices/cpu/sm510/sm510.cpp
@@ -3,7 +3,7 @@
/*
Known chips: (* means not emulated yet)
-
+
Sharp SM510 MCU family:
- SM510: 2.7Kx8 ROM, 128x4 RAM(32x4 for LCD)
- SM511: 4Kx8 ROM, 128x4 RAM(32x4 for LCD), melody controller
@@ -16,7 +16,7 @@
- *SM530: x
- *SM531: x
- *KB1013VK1-2: Soviet-era clone of SM500, minor differences
-
+
References:
- 1990 Sharp Microcomputers Data Book
- 1996 Sharp Microcomputer Databook
diff --git a/src/devices/cpu/sm510/sm510d.cpp b/src/devices/cpu/sm510/sm510d.cpp
index 7c78c33b318..ba765a716e2 100644
--- a/src/devices/cpu/sm510/sm510d.cpp
+++ b/src/devices/cpu/sm510/sm510d.cpp
@@ -26,14 +26,14 @@ enum e_mnemonics
mRM, mSM,
mPRE, mSME, mRME, mTMEL,
mSKIP, mCEND, mIDIV, mDR, mDTA,
-
+
// SM500-specific
mCOMCB, mRTN, mRTNS, mSSR, mTR, mTRS,
mADDC, mPDTW, mTW, mDTW,
mATS, mEXKSA, mEXKFA,
mRMF, mSMF, mCOMCN,
mTA, mTM2, mTG,
-
+
// KB1013VK1-2 aliases
mLC, mLM, mLE, mLAF, mLAS, mLDF, mBS0, mBS1, mXL, mXM, mXI, mXEI, mXD, mXED, mXE, mBM0, mBM1, mSM1,
mAM, mAC, mA10, mAS, mCLL, mCOM, mCLC, mSTC, mSCO, mSAO, mINC, mDEC, mSAM, mSAL, mNOP,
@@ -81,7 +81,7 @@ static const UINT8 s_bits[] =
2, 2,
8, 0, 0, 0,
0, 0, 0, 0, 0,
-
+
//
0, 0, 0, 4, 6, 6,
0, 0, 0, 0,
diff --git a/src/devices/cpu/sm510/sm511core.cpp b/src/devices/cpu/sm510/sm511core.cpp
index e98374f5905..c4c59d2d06a 100644
--- a/src/devices/cpu/sm510/sm511core.cpp
+++ b/src/devices/cpu/sm510/sm511core.cpp
@@ -159,7 +159,7 @@ void sm511_device::execute_one()
break; // 0xfc
} // big switch
-
+
// BM high bit is only valid for 1 step
m_sbm = (m_op == 0x02);
}