diff options
Diffstat (limited to 'src/devices/cpu')
| -rw-r--r-- | src/devices/cpu/hphybrid/hphybrid.cpp | 28 | ||||
| -rw-r--r-- | src/devices/cpu/hphybrid/hphybrid.h | 154 | ||||
| -rw-r--r-- | src/devices/cpu/i86/i86.cpp | 6 | ||||
| -rw-r--r-- | src/devices/cpu/m68000/m68kops.cpp | 2 | ||||
| -rw-r--r-- | src/devices/cpu/tlcs900/tlcs900.cpp | 36 | ||||
| -rw-r--r-- | src/devices/cpu/tlcs900/tlcs900.h | 16 | ||||
| -rw-r--r-- | src/devices/cpu/tms32051/32051ops.inc | 58 |
7 files changed, 149 insertions, 151 deletions
diff --git a/src/devices/cpu/hphybrid/hphybrid.cpp b/src/devices/cpu/hphybrid/hphybrid.cpp index 3d9c9631c5d..052c7058604 100644 --- a/src/devices/cpu/hphybrid/hphybrid.cpp +++ b/src/devices/cpu/hphybrid/hphybrid.cpp @@ -1485,20 +1485,20 @@ UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr) bsc_reg = HP_REG_R37_ADDR; break; - case AEC_CASE_I: - // Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware. - // Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does: - // top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35 - // (see pg 334 of patent). - bsc_reg = top_half ? 0 : HP_REG_R35_ADDR; - break; - - default: - logerror("hphybrid: aec_case=%d\n" , aec_case); - return 0; - } - - UINT16 aec_reg = (bsc_reg != 0) ? (m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK) : 0; + case AEC_CASE_I: + // Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware. + // Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does: + // top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35 + // (see pg 334 of patent). + bsc_reg = top_half ? 0 : HP_REG_R35_ADDR; + break; + + default: + logerror("hphybrid: aec_case=%d\n" , aec_case); + return 0; + } + + UINT16 aec_reg = (bsc_reg != 0) ? (m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK) : 0; if (m_forced_bsc_25) { aec_reg = (aec_reg & 0xf) | 0x20; diff --git a/src/devices/cpu/hphybrid/hphybrid.h b/src/devices/cpu/hphybrid/hphybrid.h index 8baeeb66c1d..97aea0febce 100644 --- a/src/devices/cpu/hphybrid/hphybrid.h +++ b/src/devices/cpu/hphybrid/hphybrid.h @@ -90,83 +90,83 @@ public: template<class _Object> static devcb_base &set_pa_changed_func(device_t &device, _Object object) { return downcast<hp_hybrid_cpu_device &>(device).m_pa_changed_func.set_callback(object); } protected: - hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth); - - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; - - // device_execute_interface overrides - virtual UINT32 execute_min_cycles() const override { return 6; } - virtual UINT32 execute_input_lines() const override { return 2; } - virtual UINT32 execute_default_irq_vector() const override { return 0xffff; } - virtual void execute_run() override; - virtual void execute_set_input(int inputnum, int state) override; - - UINT16 execute_one(UINT16 opcode); - UINT16 execute_one_sub(UINT16 opcode); - // Execute an instruction that doesn't belong to either BPC or IOC - virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0; - - // device_memory_interface overrides - virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } - - // device_state_interface overrides - void state_string_export(const device_state_entry &entry, std::string &str) const override; - - // device_disasm_interface overrides - virtual UINT32 disasm_min_opcode_bytes() const override { return 2; } - virtual UINT32 disasm_max_opcode_bytes() const override { return 2; } - virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; - - // Different cases of memory access - // See patent @ pg 361 - typedef enum { - AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses - AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses - AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses - AEC_CASE_D, // DMA accesses - AEC_CASE_I // Interrupt vector fetches - } aec_cases_t; - - // do memory address extension - virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0; - - UINT16 remove_mae(UINT32 addr); - - UINT16 RM(aec_cases_t aec_case , UINT16 addr); - UINT16 RM(UINT32 addr); - virtual UINT16 read_non_common_reg(UINT16 addr) = 0; - - void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v); - void WM(UINT32 addr , UINT16 v); - virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0; - - UINT16 fetch(void); - - UINT16 get_skip_addr(UINT16 opcode , bool condition) const; - - devcb_write8 m_pa_changed_func; - - int m_icount; - bool m_forced_bsc_25; - - // State of processor - UINT16 m_reg_A; // Register A - UINT16 m_reg_B; // Register B - UINT16 m_reg_P; // Register P - UINT16 m_reg_R; // Register R - UINT16 m_reg_C; // Register C - UINT16 m_reg_D; // Register D - UINT16 m_reg_IV; // Register IV - UINT16 m_reg_W; // Register W - UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long) - UINT16 m_flags; // Flags - UINT8 m_dmapa; // DMA peripheral address (4 bits) - UINT16 m_dmama; // DMA address - UINT16 m_dmac; // DMA counter - UINT16 m_reg_I; // Instruction register - UINT32 m_genpc; // Full PC + hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth); + + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const override { return 6; } + virtual UINT32 execute_input_lines() const override { return 2; } + virtual UINT32 execute_default_irq_vector() const override { return 0xffff; } + virtual void execute_run() override; + virtual void execute_set_input(int inputnum, int state) override; + + UINT16 execute_one(UINT16 opcode); + UINT16 execute_one_sub(UINT16 opcode); + // Execute an instruction that doesn't belong to either BPC or IOC + virtual UINT16 execute_no_bpc_ioc(UINT16 opcode) = 0; + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, std::string &str) const override; + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const override { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const override { return 2; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) override; + + // Different cases of memory access + // See patent @ pg 361 + typedef enum { + AEC_CASE_A, // Instr. fetches, non-base page fetches of link pointers, BPC direct non-base page accesses + AEC_CASE_B, // Base page fetches of link pointers, BPC direct base page accesses + AEC_CASE_C, // IOC, EMC & BPC indirect final destination accesses + AEC_CASE_D, // DMA accesses + AEC_CASE_I // Interrupt vector fetches + } aec_cases_t; + + // do memory address extension + virtual UINT32 add_mae(aec_cases_t aec_case , UINT16 addr) = 0; + + UINT16 remove_mae(UINT32 addr); + + UINT16 RM(aec_cases_t aec_case , UINT16 addr); + UINT16 RM(UINT32 addr); + virtual UINT16 read_non_common_reg(UINT16 addr) = 0; + + void WM(aec_cases_t aec_case , UINT16 addr , UINT16 v); + void WM(UINT32 addr , UINT16 v); + virtual void write_non_common_reg(UINT16 addr , UINT16 v) = 0; + + UINT16 fetch(void); + + UINT16 get_skip_addr(UINT16 opcode , bool condition) const; + + devcb_write8 m_pa_changed_func; + + int m_icount; + bool m_forced_bsc_25; + + // State of processor + UINT16 m_reg_A; // Register A + UINT16 m_reg_B; // Register B + UINT16 m_reg_P; // Register P + UINT16 m_reg_R; // Register R + UINT16 m_reg_C; // Register C + UINT16 m_reg_D; // Register D + UINT16 m_reg_IV; // Register IV + UINT16 m_reg_W; // Register W + UINT8 m_reg_PA[ HPHYBRID_INT_LVLS + 1 ]; // Stack of register PA (4 bit-long) + UINT16 m_flags; // Flags + UINT8 m_dmapa; // DMA peripheral address (4 bits) + UINT16 m_dmama; // DMA address + UINT16 m_dmac; // DMA counter + UINT16 m_reg_I; // Instruction register + UINT32 m_genpc; // Full PC private: address_space_config m_program_config; diff --git a/src/devices/cpu/i86/i86.cpp b/src/devices/cpu/i86/i86.cpp index 398d93ee987..28669d16563 100644 --- a/src/devices/cpu/i86/i86.cpp +++ b/src/devices/cpu/i86/i86.cpp @@ -159,7 +159,7 @@ void i8086_cpu_device::execute_run() } } - /* Trap should allow one instruction to be executed. + /* Trap should allow one instruction to be executed. CPUID.ASM (by Bob Smith, 1985) suggests that in situations where m_no_interrupt is 1, (directly after POP SS / MOV_SREG), single step IRQs don't fire. */ @@ -167,7 +167,7 @@ void i8086_cpu_device::execute_run() { if ( (m_fire_trap >= 2) && (m_no_interrupt == 0) ) { - m_fire_trap = 0; // reset trap flag upon entry + m_fire_trap = 0; // reset trap flag upon entry interrupt(1); } else @@ -1408,7 +1408,7 @@ bool i8086_common_cpu_device::common_op(UINT8 op) m_src = GetRMWord(); m_sregs[(m_modrm & 0x18) >> 3] = m_src; // confirmed on hw: modrm bit 5 ignored CLKM(MOV_SR,MOV_SM); - m_no_interrupt = 1; // Disable IRQ after load segment register. + m_no_interrupt = 1; // Disable IRQ after load segment register. break; case 0x8f: // i_popw diff --git a/src/devices/cpu/m68000/m68kops.cpp b/src/devices/cpu/m68000/m68kops.cpp index 4cbeb42d78c..0505f863c73 100644 --- a/src/devices/cpu/m68000/m68kops.cpp +++ b/src/devices/cpu/m68000/m68kops.cpp @@ -34872,5 +34872,3 @@ void m68ki_build_opcode_table(void) /* ======================================================================== */ /* ============================== END OF FILE ============================= */ /* ======================================================================== */ - - diff --git a/src/devices/cpu/tlcs900/tlcs900.cpp b/src/devices/cpu/tlcs900/tlcs900.cpp index 4ac6f8b07a3..2b5d45d7757 100644 --- a/src/devices/cpu/tlcs900/tlcs900.cpp +++ b/src/devices/cpu/tlcs900/tlcs900.cpp @@ -1748,62 +1748,62 @@ void tmp95c063_device::tlcs900_handle_ad() int ad_value; /* Store A/D converted value */ - if ((m_reg[TMP95C063_ADMOD1] & 0x10) == 0) // conversion channel fixed + if ((m_reg[TMP95C063_ADMOD1] & 0x10) == 0) // conversion channel fixed { switch( m_reg[TMP95C063_ADMOD2] & 0x07 ) { - case 0x00: // AN0 + case 0x00: // AN0 ad_value = m_an0_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; break; - case 0x01: // AN1 + case 0x01: // AN1 ad_value = m_an1_read(0) & 0x3ff; m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; break; - case 0x02: // AN2 + case 0x02: // AN2 ad_value = m_an2_read(0) & 0x3ff; m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; break; - case 0x03: // AN3 + case 0x03: // AN3 ad_value = m_an3_read(0) & 0x3ff; m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; break; - case 0x04: // AN4 + case 0x04: // AN4 ad_value = m_an4_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; break; - case 0x05: // AN5 + case 0x05: // AN5 ad_value = m_an5_read(0) & 0x3ff; m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; break; - case 0x06: // AN6 + case 0x06: // AN6 ad_value = m_an6_read(0) & 0x3ff; m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; break; - case 0x07: // AN7 + case 0x07: // AN7 ad_value = m_an7_read(0) & 0x3ff; m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; break; } } - else // conversion channel sweep + else // conversion channel sweep { switch( m_reg[TMP95C063_ADMOD2] & 0x07 ) { - case 0x00: // AN0 + case 0x00: // AN0 ad_value = m_an0_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; break; - case 0x01: // AN0 -> AN1 + case 0x01: // AN0 -> AN1 ad_value = m_an0_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; @@ -1811,7 +1811,7 @@ void tmp95c063_device::tlcs900_handle_ad() m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; break; - case 0x02: // AN0 -> AN1 -> AN2 + case 0x02: // AN0 -> AN1 -> AN2 ad_value = m_an0_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; @@ -1822,7 +1822,7 @@ void tmp95c063_device::tlcs900_handle_ad() m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; break; - case 0x03: // AN0 -> AN1 -> AN2 -> AN3 + case 0x03: // AN0 -> AN1 -> AN2 -> AN3 ad_value = m_an0_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; @@ -1836,12 +1836,12 @@ void tmp95c063_device::tlcs900_handle_ad() m_reg[TMP95C063_ADREG37L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG37H] = (ad_value >> 2) & 0xff; break; - case 0x04: // AN4 + case 0x04: // AN4 ad_value = m_an4_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; break; - case 0x05: // AN4 -> AN5 + case 0x05: // AN4 -> AN5 ad_value = m_an4_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; @@ -1849,7 +1849,7 @@ void tmp95c063_device::tlcs900_handle_ad() m_reg[TMP95C063_ADREG15L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG15H] = (ad_value >> 2) & 0xff; break; - case 0x06: // AN4 -> AN5 -> AN6 + case 0x06: // AN4 -> AN5 -> AN6 ad_value = m_an4_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; @@ -1860,7 +1860,7 @@ void tmp95c063_device::tlcs900_handle_ad() m_reg[TMP95C063_ADREG26L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG26H] = (ad_value >> 2) & 0xff; break; - case 0x07: // AN4 -> AN5 -> AN6 -> AN7 + case 0x07: // AN4 -> AN5 -> AN6 -> AN7 ad_value = m_an4_read(0) & 0x3ff; m_reg[TMP95C063_ADREG04L] = (ad_value & 0x3) << 6; m_reg[TMP95C063_ADREG04H] = (ad_value >> 2) & 0xff; diff --git a/src/devices/cpu/tlcs900/tlcs900.h b/src/devices/cpu/tlcs900/tlcs900.h index 0dcf3d84994..54b68a090d5 100644 --- a/src/devices/cpu/tlcs900/tlcs900.h +++ b/src/devices/cpu/tlcs900/tlcs900.h @@ -852,14 +852,14 @@ private: devcb_write8 m_porte_write; // analogue inputs, sampled at 10 bits - devcb_read16 m_an0_read; - devcb_read16 m_an1_read; - devcb_read16 m_an2_read; - devcb_read16 m_an3_read; - devcb_read16 m_an4_read; - devcb_read16 m_an5_read; - devcb_read16 m_an6_read; - devcb_read16 m_an7_read; + devcb_read16 m_an0_read; + devcb_read16 m_an1_read; + devcb_read16 m_an2_read; + devcb_read16 m_an3_read; + devcb_read16 m_an4_read; + devcb_read16 m_an5_read; + devcb_read16 m_an6_read; + devcb_read16 m_an7_read; }; #endif diff --git a/src/devices/cpu/tms32051/32051ops.inc b/src/devices/cpu/tms32051/32051ops.inc index 52519c7f692..83e769416a1 100644 --- a/src/devices/cpu/tms32051/32051ops.inc +++ b/src/devices/cpu/tms32051/32051ops.inc @@ -198,39 +198,39 @@ UINT16 tms32051_device::GET_ADDRESS() bool tms32051_device::GET_ZLVC_CONDITION(int zlvc, int zlvc_mask) { - if (zlvc_mask & 0x2) // OV-bit + if (zlvc_mask & 0x2) // OV-bit { - if ((zlvc & 0x2) && m_st0.ov == 0) // OV + if ((zlvc & 0x2) && m_st0.ov == 0) // OV return false; - if (((zlvc & 0x2) == 0) && m_st0.ov != 0) // NOV + if (((zlvc & 0x2) == 0) && m_st0.ov != 0) // NOV return false; } - if (zlvc_mask & 0x1) // C-bit + if (zlvc_mask & 0x1) // C-bit { - if ((zlvc & 0x1) && m_st1.c == 0) // C + if ((zlvc & 0x1) && m_st1.c == 0) // C return false; - if (((zlvc & 0x1) == 0) && m_st1.c != 0) // NC + if (((zlvc & 0x1) == 0) && m_st1.c != 0) // NC return false; } switch ((zlvc_mask & 0xc) | ((zlvc >> 2) & 0x3)) { - case 0x00: break; // MZ=0, ML=0, Z=0, L=0 - case 0x01: break; // MZ=0, ML=0, Z=0, L=1 - case 0x02: break; // MZ=0, ML=0, Z=1, L=0 - case 0x03: break; // MZ=0, ML=0, Z=1, L=1 - case 0x04: if ((INT32)(m_acc) <= 0) return false; break; // MZ=0, ML=1, Z=0, L=0 (GT) - case 0x05: if ((INT32)(m_acc) >= 0) return false; break; // MZ=0, ML=1, Z=0, L=1 (LT) - case 0x06: if ((INT32)(m_acc) <= 0) return false; break; // MZ=0, ML=1, Z=1, L=0 (GT) - case 0x07: if ((INT32)(m_acc) >= 0) return false; break; // MZ=0, ML=1, Z=1, L=1 (LT) - case 0x08: if ((INT32)(m_acc) == 0) return false; break; // MZ=1, ML=0, Z=0, L=0 (NEQ) - case 0x09: if ((INT32)(m_acc) == 0) return false; break; // MZ=1, ML=0, Z=0, L=1 (NEQ) - case 0x0a: if ((INT32)(m_acc) != 0) return false; break; // MZ=1, ML=0, Z=1, L=0 (EQ) - case 0x0b: if ((INT32)(m_acc) != 0) return false; break; // MZ=1, ML=0, Z=1, L=1 (EQ) - case 0x0c: if ((INT32)(m_acc) <= 0) return false; break; // MZ=1, ML=1, Z=0, L=0 (GT) - case 0x0d: if ((INT32)(m_acc) >= 0) return false; break; // MZ=1, ML=1, Z=0, L=1 (LT) - case 0x0e: if ((INT32)(m_acc) < 0) return false; break; // MZ=1, ML=1, Z=1, L=0 (GEQ) - case 0x0f: if ((INT32)(m_acc) > 0) return false; break; // MZ=1, ML=1, Z=1, L=1 (LEQ) + case 0x00: break; // MZ=0, ML=0, Z=0, L=0 + case 0x01: break; // MZ=0, ML=0, Z=0, L=1 + case 0x02: break; // MZ=0, ML=0, Z=1, L=0 + case 0x03: break; // MZ=0, ML=0, Z=1, L=1 + case 0x04: if ((INT32)(m_acc) <= 0) return false; break; // MZ=0, ML=1, Z=0, L=0 (GT) + case 0x05: if ((INT32)(m_acc) >= 0) return false; break; // MZ=0, ML=1, Z=0, L=1 (LT) + case 0x06: if ((INT32)(m_acc) <= 0) return false; break; // MZ=0, ML=1, Z=1, L=0 (GT) + case 0x07: if ((INT32)(m_acc) >= 0) return false; break; // MZ=0, ML=1, Z=1, L=1 (LT) + case 0x08: if ((INT32)(m_acc) == 0) return false; break; // MZ=1, ML=0, Z=0, L=0 (NEQ) + case 0x09: if ((INT32)(m_acc) == 0) return false; break; // MZ=1, ML=0, Z=0, L=1 (NEQ) + case 0x0a: if ((INT32)(m_acc) != 0) return false; break; // MZ=1, ML=0, Z=1, L=0 (EQ) + case 0x0b: if ((INT32)(m_acc) != 0) return false; break; // MZ=1, ML=0, Z=1, L=1 (EQ) + case 0x0c: if ((INT32)(m_acc) <= 0) return false; break; // MZ=1, ML=1, Z=0, L=0 (GT) + case 0x0d: if ((INT32)(m_acc) >= 0) return false; break; // MZ=1, ML=1, Z=0, L=1 (LT) + case 0x0e: if ((INT32)(m_acc) < 0) return false; break; // MZ=1, ML=1, Z=1, L=0 (GEQ) + case 0x0f: if ((INT32)(m_acc) > 0) return false; break; // MZ=1, ML=1, Z=1, L=1 (LEQ) } return true; } @@ -239,14 +239,14 @@ bool tms32051_device::GET_TP_CONDITION(int tp) { switch (tp) { - case 0: // BIO pin low + case 0: // BIO pin low // TODO return false; - - case 1: // TC == 1 + + case 1: // TC == 1 return m_st1.tc != 0; - case 2: // TC == 0 + case 2: // TC == 0 return m_st1.tc == 0; case 3: @@ -1376,7 +1376,7 @@ void tms32051_device::op_out() { UINT16 port = ROPCODE(); UINT16 ea = GET_ADDRESS(); - + UINT16 data = DM_READ16(ea); m_io->write_word(port << 1, data); @@ -1438,7 +1438,7 @@ void tms32051_device::op_apl_dbmr() { UINT16 ea = GET_ADDRESS(); UINT16 data = DM_READ16(ea); - + data &= m_dbmr; m_st1.tc = (data == 0) ? 1 : 0; @@ -1452,7 +1452,7 @@ void tms32051_device::op_apl_imm() UINT16 ea = GET_ADDRESS(); UINT16 imm = ROPCODE(); UINT16 data = DM_READ16(ea); - + data &= imm; m_st1.tc = (data == 0) ? 1 : 0; |
