diff options
Diffstat (limited to 'src/devices/cpu/z80')
45 files changed, 14713 insertions, 3703 deletions
diff --git a/src/devices/cpu/z80/ez80.cpp b/src/devices/cpu/z80/ez80.cpp new file mode 100644 index 00000000000..525dc1c3b11 --- /dev/null +++ b/src/devices/cpu/z80/ez80.cpp @@ -0,0 +1,39 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Zilog eZ80 CPU + + TODO: all differences from Z80 + +***************************************************************************/ + +#include "emu.h" +#include "ez80.h" + + +//************************************************************************** +// GLOBAL VARIABLES +//************************************************************************** + +// device type definition +DEFINE_DEVICE_TYPE(EZ80, ez80_device, "ez80", "Zilog eZ80") + + +//************************************************************************** +// DEVICE IMPLEMENTATION +//************************************************************************** + +//------------------------------------------------- +// ez80_device - constructor +//------------------------------------------------- + +ez80_device::ez80_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) + : z80_device(mconfig, type, tag, owner, clock) +{ +} + +ez80_device::ez80_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : ez80_device(mconfig, EZ80, tag, owner, clock) +{ +} diff --git a/src/devices/cpu/z80/ez80.h b/src/devices/cpu/z80/ez80.h new file mode 100644 index 00000000000..2ae563d5b80 --- /dev/null +++ b/src/devices/cpu/z80/ez80.h @@ -0,0 +1,35 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Zilog eZ80 CPU + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_EZ80_H +#define MAME_CPU_Z80_EZ80_H + +#pragma once + +#include "z80.h" + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class ez80_device : public z80_device +{ +public: + // device type constructor + ez80_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + +protected: + // construction/destruction + ez80_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock); +}; + +// device type declaration +DECLARE_DEVICE_TYPE(EZ80, ez80_device) + +#endif // MAME_CPU_Z80_EZ80_H diff --git a/src/devices/cpu/z80/kc82.cpp b/src/devices/cpu/z80/kc82.cpp new file mode 100644 index 00000000000..fd09910429c --- /dev/null +++ b/src/devices/cpu/z80/kc82.cpp @@ -0,0 +1,245 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KC82 CPU core with MMU + +***************************************************************************/ + +#include "emu.h" +#include "kc82.h" + +#define VERBOSE 0 +#include "logmacro.h" + + +//------------------------------------------------- +// kc82_device - constructor +//------------------------------------------------- + +kc82_device::kc82_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor mem_map, address_map_constructor io_map) + : z80_device(mconfig, type, tag, owner, clock) + , m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0, 16, 10, mem_map) + , m_opcodes_config("opcodes", ENDIANNESS_LITTLE, 8, 20, 0, 16, 10, mem_map) + , m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0, io_map) +{ + std::fill_n(&m_mmu_a[0], 4, 0); + std::fill_n(&m_mmu_b[0], 5, 0); + std::fill_n(&m_mmu_base[0], 0x40, 0); +} + + +//------------------------------------------------- +// memory_space_config - return a vector of +// address space configurations for this device +//------------------------------------------------- + +device_memory_interface::space_config_vector kc82_device::memory_space_config() const +{ + if (has_space(AS_OPCODES)) + { + return space_config_vector { + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_IO, &m_io_config), + std::make_pair(AS_OPCODES, &m_opcodes_config) + }; + } + else + { + return space_config_vector { + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_IO, &m_io_config) + }; + } +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void kc82_device::device_start() +{ + z80_device::device_start(); + + for (int n = 1; n <= 4; n++) + { + state_add(KC82_B1 + n - 1, string_format("B%d", n).c_str(), m_mmu_b[n], + [this, n](u8 data) { m_mmu_b[n] = data; mmu_remap_pages(); } + ).mask(0x3f); + if (n != 4) + state_add(KC82_A1 + n - 1, string_format("A%d", n).c_str(), m_mmu_a[n], + [this, n](u16 data) { m_mmu_a[n] = data; mmu_remap_pages(); } + ).mask(0x3ff); + } + + save_item(NAME(m_mmu_a)); + save_item(NAME(m_mmu_b)); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void kc82_device::device_reset() +{ + z80_device::device_reset(); + + std::fill_n(&m_mmu_a[1], 3, 0); + std::fill_n(&m_mmu_b[1], 4, 0x3f); + std::fill_n(&m_mmu_base[0], 0x40, 0); +} + + +//------------------------------------------------- +// device_post_load - called after loading a +// saved state +//------------------------------------------------- + +void kc82_device::device_post_load() +{ + z80_device::device_post_load(); + + mmu_remap_pages(); +} + + +//************************************************************************** +// KC82 MMU +//************************************************************************** + +//------------------------------------------------- +// mmu_remap_pages - recalculate base addresses +// for memory pages +//------------------------------------------------- + +void kc82_device::mmu_remap_pages() +{ + int n = 4; + u32 base = 0xf0000; // A4 is fixed + for (u8 i = 0x3f; i != 0; --i) + { + while (n != 0 && m_mmu_b[n] >= i) + { + --n; + base = u32(m_mmu_a[n]) << 10; + } + if (m_mmu_base[i] != base) + { + u32 old_mapping = ((i << 10) + base) & 0xffc00; + u32 new_mapping = ((i << 10) + m_mmu_base[i]) & 0xffc00; + LOG("%s: MMU: %04X-%04XH => %05X-%05XH (was %05X-%05XH)\n", + machine().describe_context(), + i << 10, (i << 10) | 0x3ff, + old_mapping, old_mapping | 0x3ff, + new_mapping, new_mapping | 0x3ff); + } + m_mmu_base[i] = base; + } +} + + +//------------------------------------------------- +// mmu_r - read MMU register +//------------------------------------------------- + +u8 kc82_device::mmu_r(offs_t offset) +{ + int n = (offset >> 1) + 1; + if (BIT(offset, 0)) + { + // read base register BRn + return n == 4 ? 0xf0 : (m_mmu_a[n] & 0x3fc) >> 2; + } + else + { + // read boundary/base register BBRn + return (n == 4 ? 0 : (m_mmu_a[n] & 0x003) << 6) | m_mmu_b[n]; + } +} + + +//------------------------------------------------- +// mmu_w - write to MMU register +//------------------------------------------------- + +void kc82_device::mmu_w(offs_t offset, u8 data) +{ + int n = (offset >> 1) + 1; + if (BIT(offset, 0)) + { + // write to base register BRn + if (n != 4) + m_mmu_a[n] = u16(data) << 2 | (m_mmu_a[n] & 0x003); + else if (data != 0xf0) + logerror("%s: Attempt to write %02X to upper 8 bits of A4\n", machine().describe_context(), data); + } + else + { + // write to boundary/base register BBRn + m_mmu_b[n] = data & 0x3f; + if (n != 4) + m_mmu_a[n] = (m_mmu_a[n] & 0x3fc) | (data & 0xc0) >> 6; + else if ((data & 0xc0) != 0) + logerror("%s: Attempt to write %d to lower 2 bits of A4\n", machine().describe_context(), (data & 0xc0) >> 6); + } + mmu_remap_pages(); +} + + +//------------------------------------------------- +// memory_translate - translate from logical to +// physical addresses +//------------------------------------------------- + +bool kc82_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) +{ + if (spacenum == AS_PROGRAM || spacenum == AS_OPCODES) + address = (address + m_mmu_base[(address & 0xfc00) >> 10]) & 0xfffff; + target_space = &space(spacenum); + return true; +} + + +//------------------------------------------------- +// rm - read one byte from memory +//------------------------------------------------- + +u8 kc82_device::data_read(u16 addr) +{ + return m_data.read_byte(addr + m_mmu_base[addr >> 10]); +} + + +//------------------------------------------------- +// wm - write one byte to memory +//------------------------------------------------- + +void kc82_device::data_write(u16 addr, u8 value) +{ + m_data.write_byte(addr + m_mmu_base[addr >> 10], value); +} + + +//------------------------------------------------- +// rop - read opcode +//------------------------------------------------- + +u8 kc82_device::opcode_read() +{ + u32 pc = m_pc.w + m_mmu_base[m_pc.b.h >> 2]; + // no refresh + return m_opcodes.read_byte(pc); +} + + +//------------------------------------------------- +// arg - read 8-bit argument +//------------------------------------------------- + +u8 kc82_device::arg_read() +{ + u32 pc = m_pc.w + m_mmu_base[m_pc.b.h >> 2]; + return m_args.read_byte(pc); +} diff --git a/src/devices/cpu/z80/kc82.h b/src/devices/cpu/z80/kc82.h new file mode 100644 index 00000000000..a1a30b07ac6 --- /dev/null +++ b/src/devices/cpu/z80/kc82.h @@ -0,0 +1,69 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KC82 CPU core with MMU + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_KC82_H +#define MAME_CPU_Z80_KC82_H + +#pragma once + +#include "z80.h" + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class kc82_device : public z80_device +{ +public: + enum + { + KC82_B1 = Z80_WZ + 1, KC82_B2, KC82_B3, KC82_B4, + KC82_A1, KC82_A2, KC82_A3 + }; + +protected: + // construction/destruction + kc82_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor mem_map, address_map_constructor io_map); + + // device-level overrides + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + virtual void device_post_load() override; + + // device_memory_interface overrides + virtual space_config_vector memory_space_config() const override; + virtual bool memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) override; + + // z80_device overrides + virtual u8 data_read(u16 addr) override; + virtual void data_write(u16 addr, u8 value) override; + virtual u8 opcode_read() override; + virtual u8 arg_read() override; + + // MMU access + u8 mmu_r(offs_t offset); + void mmu_w(offs_t offset, u8 data); + +private: + // internal helpers + void mmu_remap_pages(); + + // address spaces + address_space_config m_program_config; + address_space_config m_opcodes_config; + address_space_config m_io_config; + + // MMU registers + u16 m_mmu_a[4]; + u8 m_mmu_b[5]; + u32 m_mmu_base[0x40]; +}; + + +#endif // MAME_CPU_Z80_KC82_H diff --git a/src/devices/cpu/z80/kl5c80a12.cpp b/src/devices/cpu/z80/kl5c80a12.cpp index a061f3e7cf3..702facf2ad2 100644 --- a/src/devices/cpu/z80/kl5c80a12.cpp +++ b/src/devices/cpu/z80/kl5c80a12.cpp @@ -1,27 +1,88 @@ // license:BSD-3-Clause -// copyright-holders:David Haywood +// copyright-holders:AJR /*************************************************************************** - Kawasaki LSI - KL5C80A12 CPU (KL5C80A12CFP on hng64.c) + Kawasaki Steel (Kawatetsu) KL5C80A12 CPU - Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz - Timers / Counters, Parallel / Serial ports/ MMU, Interrupt Controller + This is based on KC82, an MMU-enhanced version of KC80 (KL5C8400), + Kawasaki's Z80-compatible core with an internal 16-bit architecture + and significantly faster opcode timings, operating at up to 10 MHz + (CLK = XIN/2). - (is this different enough to need it's own core?) - (todo: everything, some code currently lives in machine/hng64_net.c but not much) + Important functional blocks: + — MMU + — USART (KP51) (unemulated) + — 16-bit timer/counters (KP64, KP63) + — 16-level interrupt controller (KP69) + — Parallel ports (KP65, KP66) + — 512-byte high-speed RAM + — External bus interface unit (unemulated) ***************************************************************************/ #include "emu.h" #include "kl5c80a12.h" +#include "kp63.h" +#include "kp64.h" -DEFINE_DEVICE_TYPE(KL5C80A12, kl5c80a12_device, "kl5c80a12", "Kawasaki LSI KL5C80A12") +// device type definition +DEFINE_DEVICE_TYPE(KL5C80A12, kl5c80a12_device, "kl5c80a12", "Kawasaki Steel KL5C80A12") +static const z80_daisy_config pseudo_daisy_config[] = { { "kp69" }, { nullptr } }; -kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : z80_device(mconfig, KL5C80A12, tag, owner, clock) + +//------------------------------------------------- +// kl5c80a12_device - constructor +//------------------------------------------------- + +kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : kc82_device(mconfig, KL5C80A12, tag, owner, clock, + address_map_constructor(FUNC(kl5c80a12_device::internal_ram), this), + address_map_constructor(FUNC(kl5c80a12_device::internal_io), this)) + , m_kp69(*this, "kp69") + , m_porta_in_callback(*this, 0) + , m_porta_out_callback(*this) + , m_portb_in_callback(*this, 0) + , m_portb_out_callback(*this) + , m_porta_data{0, 0} + , m_porta_direction{0, 0} + , m_porta_3state{0, 0} + , m_portb_data{0, 0, 0} + , m_portb_direction(0) + , m_portb_3state{0, 0, 0} +{ +} + + +//------------------------------------------------- +// internal_ram - map for high-speed internal RAM +//------------------------------------------------- + +void kl5c80a12_device::internal_ram(address_map &map) { + map(0xffe00, 0xfffff).ram().share("ram"); +} + + +//------------------------------------------------- +// internal_io - map for internal I/O registers +//------------------------------------------------- + +void kl5c80a12_device::internal_io(address_map &map) +{ + map(0x00, 0x07).mirror(0xff00).rw(FUNC(kl5c80a12_device::mmu_r), FUNC(kl5c80a12_device::mmu_w)); + map(0x20, 0x25).mirror(0xff00).rw("timerb", FUNC(kp63_3channel_device::read), FUNC(kp63_3channel_device::write)); + map(0x28, 0x28).mirror(0xff00).rw("timera0", FUNC(kp64_device::counter_r), FUNC(kp64_device::counter_w)); + map(0x29, 0x29).mirror(0xff00).rw("timera0", FUNC(kp64_device::status_r), FUNC(kp64_device::control_w)); + map(0x2a, 0x2a).mirror(0xff00).rw("timera1", FUNC(kp64_device::counter_r), FUNC(kp64_device::counter_w)); + map(0x2b, 0x2b).mirror(0xff00).rw("timera1", FUNC(kp64_device::status_r), FUNC(kp64_device::control_w)); + map(0x2c, 0x2f).mirror(0xff00).rw(FUNC(kl5c80a12_device::porta_r), FUNC(kl5c80a12_device::porta_w)); + map(0x30, 0x32).mirror(0xff00).rw(FUNC(kl5c80a12_device::portb_r), FUNC(kl5c80a12_device::portb_w)); + map(0x33, 0x33).mirror(0xff00).rw(FUNC(kl5c80a12_device::portb_control_r), FUNC(kl5c80a12_device::portb_control_w)); + map(0x34, 0x34).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::isrl_r), FUNC(kp69_device::lerl_pgrl_w)); + map(0x35, 0x35).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::isrh_r), FUNC(kp69_device::lerh_pgrh_w)); + map(0x36, 0x36).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::imrl_r), FUNC(kp69_device::imrl_w)); + map(0x37, 0x37).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::imrh_r), FUNC(kp69_device::ivr_imrh_w)); } @@ -31,7 +92,15 @@ kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *ta void kl5c80a12_device::device_start() { - z80_device::device_start(); + kc82_device::device_start(); + + m_kp69->add_to_state(*this, KP69_IRR); + + // Register save state + save_item(NAME(m_porta_data)); + save_item(NAME(m_porta_direction)); + save_item(NAME(m_portb_data)); + save_item(NAME(m_portb_direction)); } @@ -41,11 +110,222 @@ void kl5c80a12_device::device_start() void kl5c80a12_device::device_reset() { - z80_device::device_reset(); + kc82_device::device_reset(); + + // Reset parallel port registers + std::fill(std::begin(m_porta_data), std::end(m_porta_data), 0x00); + std::fill(std::begin(m_porta_direction), std::end(m_porta_direction), 0x00); + std::fill(std::begin(m_portb_data), std::end(m_portb_data), 0x00); + m_portb_direction = 0x00; + + // Reset parallel port outputs + for (int i = 0; i < 2; i++) + m_porta_out_callback[i](0, m_porta_3state[i], 0x00); + for (int i = 0; i < 3; i++) + m_portb_out_callback[i](0, m_portb_3state[i], 0x00); } -/* CPU interface */ +//------------------------------------------------- +// device_add_mconfig - add device-specific +// machine configuration +//------------------------------------------------- + void kl5c80a12_device::device_add_mconfig(machine_config &config) { + KP69(config, m_kp69); + m_kp69->int_callback().set_inputline(*this, INPUT_LINE_IRQ0); + + kp64_device &timera0(KP64(config, "timera0", DERIVED_CLOCK(1, 2))); + timera0.out_callback().set(m_kp69, FUNC(kp69_device::ir_w<11>)); + + kp64_device &timera1(KP64(config, "timera1", DERIVED_CLOCK(1, 2))); + timera1.out_callback().set(m_kp69, FUNC(kp69_device::ir_w<12>)); + + kp63_3channel_device &timerb(KP63_3CHANNEL(config, "timerb", DERIVED_CLOCK(1, 2))); + timerb.outs_callback<0>().set(m_kp69, FUNC(kp69_device::ir_w<13>)); + timerb.outs_callback<1>().set(m_kp69, FUNC(kp69_device::ir_w<14>)); + timerb.outs_callback<2>().set(m_kp69, FUNC(kp69_device::ir_w<15>)); +} + + +//------------------------------------------------- +// device_config_complete - perform any +// operations now that the configuration is +// complete +//------------------------------------------------- + +void kl5c80a12_device::device_config_complete() +{ + kc82_device::device_config_complete(); + + set_daisy_config(pseudo_daisy_config); + + for (int i = 0; i < 2; i++) + { + if (m_porta_in_callback[i].isunset()) + m_porta_in_callback[i].bind().set_constant(m_porta_3state[i]); + } + for (int i = 0; i < 3; i++) + { + if (m_portb_in_callback[i].isunset()) + m_portb_in_callback[i].bind().set_constant(m_portb_3state[i]); + } +} + + +//************************************************************************** +// KP65 PARALLEL PORT +//************************************************************************** + +//------------------------------------------------- +// porta_r - read from parallel port A data or +// direction register +//------------------------------------------------- + +u8 kl5c80a12_device::porta_r(offs_t offset) +{ + const unsigned n = offset >> 1; + if (BIT(offset, 0)) + return m_porta_direction[n]; + else + { + u8 data = m_porta_data[n]; + const u8 dir = m_porta_direction[n]; + if (dir != 0xff) + data = (data & dir) | (m_porta_in_callback[n](0, u8(~dir)) & ~dir); + return data; + } +} + + +//------------------------------------------------- +// porta_w - write to parallel port A data or +// direction register +//------------------------------------------------- + +void kl5c80a12_device::porta_w(offs_t offset, u8 data) +{ + const unsigned n = offset >> 1; + u8 dir = m_porta_direction[n]; + if (BIT(offset, 0)) + { + if (dir == data) + return; + m_porta_direction[n] = dir = data; + data = m_porta_data[n]; + } + else + { + u8 old_data = std::exchange(m_porta_data[n], data); + if (((old_data ^ data) & dir) == 0) + return; + } + + // Update port output + m_porta_out_callback[n](0, (data & dir) | (m_porta_3state[n] & ~dir), dir); +} + + +//************************************************************************** +// KP66 PARALLEL PORT +//************************************************************************** + +//------------------------------------------------- +// portb_r - read from parallel port B data +// register +//------------------------------------------------- + +u8 kl5c80a12_device::portb_r(offs_t offset) +{ + u8 data = m_portb_data[offset]; + const u8 dir = std::array<u8, 4>{{0x00, 0x0f, 0xf0, 0xff}}[BIT(m_portb_direction, offset * 2, 2)]; + if (dir != 0xff) + data = (data & dir) | (m_portb_in_callback[offset](0, u8(~dir)) & ~dir); + return data; +} + + +//------------------------------------------------- +// portb_update_output - update output for one +// port in parallel port B +//------------------------------------------------- + +void kl5c80a12_device::portb_update_output(unsigned n) +{ + const u8 dir = std::array<u8, 4>{{0x00, 0x0f, 0xf0, 0xff}}[BIT(m_portb_direction, n * 2, 2)]; + m_portb_out_callback[n](0, (m_portb_data[n] & dir) | (m_portb_3state[n] & ~dir), dir); +} + + +//------------------------------------------------- +// portb_w - write to parallel port B data +// register +//------------------------------------------------- + +void kl5c80a12_device::portb_w(offs_t offset, u8 data) +{ + const u8 old_data = std::exchange(m_portb_data[offset], data); + const u8 dir = std::array<u8, 4>{{0x00, 0x0f, 0xf0, 0xff}}[BIT(m_portb_direction, offset * 2, 2)]; + if (((old_data ^ data) & dir) != 0) + portb_update_output(offset); +} + + +//------------------------------------------------- +// portb_control_r - read from parallel port B +// direction register +//------------------------------------------------- + +u8 kl5c80a12_device::portb_control_r() +{ + return m_portb_direction; +} + + +//------------------------------------------------- +// portb_control_w - write to parallel port B +// direction register or bit command +//------------------------------------------------- + +void kl5c80a12_device::portb_control_w(u8 data) +{ + if ((data & 0xc0) == 0xc0) + { + // Bit set/reset command + const unsigned b = BIT(data, 1, 3); + const unsigned n = BIT(data, 4, 2); + if (n < 3) + { + if (BIT(m_portb_data[n], b) != BIT(data, 0)) + { + m_portb_data[n] ^= 1 << b; + if (BIT(m_portb_direction, n * 2 + (b < 4 ? 0 : 1))) + portb_update_output(n); + } + } + else + { + if ((data & 0x0d) == 0x0d) + logerror("%s: Attempt to set bit %d in port B direction register\n", machine().describe_context(), BIT(data, 1, 3)); + else if (BIT(m_portb_direction, b) != BIT(data, 0)) + { + m_portb_direction ^= 1 << b; + portb_update_output(b >> 1); + } + } + } + else if ((data & 0xc0) == 0) + { + // Write direction register + const u8 old_dir = std::exchange(m_portb_direction, data); + if (((data ^ old_dir) & 0x03) != 0) + portb_update_output(0); + if (((data ^ old_dir) & 0x0c) != 0) + portb_update_output(1); + if (((data ^ old_dir) & 0x30) != 0) + portb_update_output(2); + } + else + logerror("%s: Writing %02X to port B command register\n", machine().describe_context(), data); } diff --git a/src/devices/cpu/z80/kl5c80a12.h b/src/devices/cpu/z80/kl5c80a12.h index d77dce279c5..1a6340c6045 100644 --- a/src/devices/cpu/z80/kl5c80a12.h +++ b/src/devices/cpu/z80/kl5c80a12.h @@ -1,15 +1,8 @@ // license:BSD-3-Clause -// copyright-holders:David Haywood +// copyright-holders:AJR /*************************************************************************** - Kawasaki LSI - KL5C80A12 CPU (KL5C80A12CFP on hng64.c) - - Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz - Timers / Counters, Parallel / Serial ports/ MMU, Interrupt Controller - - (is this different enough to need it's own core?) - (todo: everything, some code currently lives in machine/hng64_net.c but not much) + Kawasaki Steel (Kawatetsu) KL5C80A12 CPU ***************************************************************************/ @@ -18,33 +11,93 @@ #pragma once -#include "z80.h" -#include "machine/z80ctc.h" - - -/*************************************************************************** - DEVICE CONFIGURATION MACROS -***************************************************************************/ +#include "kc82.h" +#include "kp69.h" -/*************************************************************************** - TYPE DEFINITIONS -***************************************************************************/ +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** -class kl5c80a12_device : public z80_device +class kl5c80a12_device : public kc82_device { public: - kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t); + enum + { + KP69_IRR = KC82_A3 + 1, KP69_ISR, KP69_IVR, KP69_LER, KP69_PGR, KP69_IMR + }; + + // device type constructor + kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + // callback configuration + auto in_p0_callback() { return m_porta_in_callback[0].bind(); } + auto out_p0_callback() { return m_porta_out_callback[0].bind(); } + auto in_p1_callback() { return m_porta_in_callback[1].bind(); } + auto out_p1_callback() { return m_porta_out_callback[1].bind(); } + auto in_p2_callback() { return m_portb_in_callback[0].bind(); } + auto out_p2_callback() { return m_portb_out_callback[0].bind(); } + auto in_p3_callback() { return m_portb_in_callback[1].bind(); } + auto out_p3_callback() { return m_portb_out_callback[1].bind(); } + auto in_p4_callback() { return m_portb_in_callback[2].bind(); } + auto out_p4_callback() { return m_portb_out_callback[2].bind(); } + + // misc. configuration + void set_p0_3state(u8 value) { m_porta_3state[0] = value; } + void set_p1_3state(u8 value) { m_porta_3state[1] = value; } + void set_p2_3state(u8 value) { m_portb_3state[0] = value; } + void set_p3_3state(u8 value) { m_portb_3state[1] = value; } + void set_p4_3state(u8 value) { m_portb_3state[2] = value; } protected: - // device-level overrides - virtual void device_add_mconfig(machine_config &config) override; - virtual void device_start() override; - virtual void device_reset() override; + // device_t implementation + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + virtual void device_config_complete() override; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + + // device_execute_interface implementation + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 2 - 1) / 2; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 2); } + +private: + // internal I/O handlers + u8 porta_r(offs_t offset); + void porta_w(offs_t offset, u8 data); + u8 portb_r(offs_t offset); + void portb_w(offs_t offset, u8 data); + u8 portb_control_r(); + void portb_control_w(u8 data); + + // internal helpers + void portb_update_output(unsigned n); + + // internal address maps + void internal_ram(address_map &map) ATTR_COLD; + void internal_io(address_map &map) ATTR_COLD; + + // subdevice finders + required_device<kp69_device> m_kp69; + + // callback objects + devcb_read8::array<2> m_porta_in_callback; + devcb_write8::array<2> m_porta_out_callback; + devcb_read8::array<3> m_portb_in_callback; + devcb_write8::array<3> m_portb_out_callback; + + // parallel port A state + u8 m_porta_data[2]; + u8 m_porta_direction[2]; + u8 m_porta_3state[2]; + + // parallel port B state + u8 m_portb_data[3]; + u8 m_portb_direction; + u8 m_portb_3state[3]; }; -// device type definition +// device type declaration DECLARE_DEVICE_TYPE(KL5C80A12, kl5c80a12_device) #endif // MAME_CPU_Z80_KL5C80A12_H diff --git a/src/devices/cpu/z80/kl5c80a16.cpp b/src/devices/cpu/z80/kl5c80a16.cpp new file mode 100644 index 00000000000..5efe26a0d9b --- /dev/null +++ b/src/devices/cpu/z80/kl5c80a16.cpp @@ -0,0 +1,196 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KL5C80A16 CPU + + Important functional blocks: + — MMU + — DMA controller (KP27) (unemulated) + — UART (KP61) (unemulated) + — Synchronous serial port (KP62) (unemulated) + — 16-bit timer/counters (KP63A) + — 16-level interrupt controller (KP69) + — Parallel ports (KP67) + — External bus/DRAM interface unit (unemulated) + +***************************************************************************/ + +#include "emu.h" +#include "kl5c80a16.h" +#include "kp63.h" + +// device type definition +DEFINE_DEVICE_TYPE(KL5C80A16, kl5c80a16_device, "kl5c80a16", "Kawasaki Steel KL5C80A16") + +static const z80_daisy_config pseudo_daisy_config[] = { { "kp69" }, { nullptr } }; + + +//------------------------------------------------- +// kl5c80a16_device - constructor +//------------------------------------------------- + +kl5c80a16_device::kl5c80a16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : kc82_device(mconfig, KL5C80A16, tag, owner, clock, + address_map_constructor(), + address_map_constructor(FUNC(kl5c80a16_device::internal_io), this)) + , m_kp69(*this, "kp69") + , m_port_in_callback(*this, 0) + , m_port_out_callback(*this) + , m_port_data{0, 0, 0, 0} + , m_port_direction{0x0f, 0, 0, 0} + , m_port_3state{0, 0, 0, 0} +{ +} + + +//------------------------------------------------- +// internal_io - map for internal I/O registers +//------------------------------------------------- + +void kl5c80a16_device::internal_io(address_map &map) +{ + map(0x00, 0x07).mirror(0xff00).rw(FUNC(kl5c80a16_device::mmu_r), FUNC(kl5c80a16_device::mmu_w)); + map(0x20, 0x27).mirror(0xff00).rw("timer", FUNC(kp63a_device::read), FUNC(kp63a_device::write)); + map(0x34, 0x34).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::isrl_r), FUNC(kp69_device::lerl_pgrl_w)); + map(0x35, 0x35).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::isrh_r), FUNC(kp69_device::lerh_pgrh_w)); + map(0x36, 0x36).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::imrl_r), FUNC(kp69_device::imrl_w)); + map(0x37, 0x37).mirror(0xff00).rw(m_kp69, FUNC(kp69_device::imrh_r), FUNC(kp69_device::ivr_imrh_w)); + map(0x38, 0x3f).mirror(0xff00).rw(FUNC(kl5c80a16_device::port_r), FUNC(kl5c80a16_device::port_w)); +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void kl5c80a16_device::device_start() +{ + kc82_device::device_start(); + + m_kp69->add_to_state(*this, KP69_IRR); + + // Register save state + save_item(NAME(m_port_data)); + save_item(NAME(m_port_direction)); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void kl5c80a16_device::device_reset() +{ + kc82_device::device_reset(); + + // Reset parallel port registers (Port 0 direction is fixed to upper 4 bits input & lower 4 bits output) + std::fill(std::begin(m_port_data), std::end(m_port_data), 0x00); + std::fill(std::begin(m_port_direction) + 1, std::end(m_port_direction), 0x00); + + // Reset parallel port outputs + for (int i = 1; i < 4; i++) + m_port_out_callback[i](0, m_port_3state[i] & ~m_port_direction[i], m_port_direction[i]); +} + + +//------------------------------------------------- +// device_add_mconfig - add device-specific +// machine configuration +//------------------------------------------------- + +void kl5c80a16_device::device_add_mconfig(machine_config &config) +{ + KP69(config, m_kp69); + m_kp69->int_callback().set_inputline(*this, INPUT_LINE_IRQ0); + + kp63a_device &timer(KP63A(config, "timer", DERIVED_CLOCK(1, 2))); + timer.outs_callback<0>().set(m_kp69, FUNC(kp69_device::ir_w<12>)); + timer.outs_callback<1>().set(m_kp69, FUNC(kp69_device::ir_w<13>)); + //timer.outs_callback<2>().set(m_kp69, FUNC(kp69_device::ir_w<0>)); // TODO: multiplexed with P20 input by SCR1 bit 4 + //timer.outs_callback<3>().set(m_kp69, FUNC(kp69_device::ir_w<1>)); // TODO: multiplexed with P21 input by SCR1 bit 5 (may also be NMI) +} + + +//------------------------------------------------- +// device_config_complete - perform any +// operations now that the configuration is +// complete +//------------------------------------------------- + +void kl5c80a16_device::device_config_complete() +{ + kc82_device::device_config_complete(); + + set_daisy_config(pseudo_daisy_config); + + for (int i = 0; i < 4; i++) + { + if (m_port_in_callback[i].isunset()) + m_port_in_callback[i].bind().set_constant(m_port_3state[i]); + } +} + + +//************************************************************************** +// KP67 PARALLEL PORT +//************************************************************************** + +//------------------------------------------------- +// port_r - read from parallel port data or +// direction register +//------------------------------------------------- + +u8 kl5c80a16_device::port_r(offs_t offset) +{ + if (BIT(offset, 0)) + return m_port_direction[offset >> 1]; + else + { + u8 data = m_port_data[offset >> 1]; + const u8 dir = m_port_direction[offset >> 1]; + if (dir != 0xff) + data = (data & dir) | (m_port_in_callback[offset >> 1](0, u8(~dir)) & ~dir); + return data; + } +} + + +//------------------------------------------------- +// port_w - write to parallel port data or +// direction register or bit control +//------------------------------------------------- + +void kl5c80a16_device::port_w(offs_t offset, u8 data) +{ + unsigned p = offset >> 1; + u8 dir = m_port_direction[p]; + if (offset == 1) + { + // Bit set/reset command + const unsigned b = BIT(data, 1, 3); + p = BIT(data, 4, 2); + if (BIT(m_port_data[p], b) == BIT(data, 0)) + return; + data = (m_port_data[p] ^= 1 << b); + dir = m_port_direction[p]; + if (!BIT(dir, b)) + return; + } + else if (BIT(offset, 0)) + { + if (dir == data) + return; + m_port_direction[p] = dir = data; + data = m_port_data[p]; + } + else + { + u8 old_data = std::exchange(m_port_data[p], data); + if (((old_data ^ data) & dir) == 0) + return; + } + + // Update port output + m_port_out_callback[offset >> 1](0, (data & dir) | (m_port_3state[offset >> 1] & ~dir), dir); +} diff --git a/src/devices/cpu/z80/kl5c80a16.h b/src/devices/cpu/z80/kl5c80a16.h new file mode 100644 index 00000000000..10ba3df08f4 --- /dev/null +++ b/src/devices/cpu/z80/kl5c80a16.h @@ -0,0 +1,85 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KL5C80A16 CPU + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_KL5C80A16_H +#define MAME_CPU_Z80_KL5C80A16_H + +#pragma once + +#include "kc82.h" +#include "kp69.h" + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class kl5c80a16_device : public kc82_device +{ +public: + enum + { + KP69_IRR = KC82_A3 + 1, KP69_ISR, KP69_IVR, KP69_LER, KP69_PGR, KP69_IMR + }; + + // device type constructor + kl5c80a16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + // callback configuration + auto in_p0_callback() { return m_port_in_callback[0].bind(); } + auto out_p0_callback() { return m_port_out_callback[0].bind(); } + auto in_p1_callback() { return m_port_in_callback[1].bind(); } + auto out_p1_callback() { return m_port_out_callback[1].bind(); } + auto in_p2_callback() { return m_port_in_callback[2].bind(); } + auto out_p2_callback() { return m_port_out_callback[2].bind(); } + auto in_p3_callback() { return m_port_in_callback[3].bind(); } + auto out_p3_callback() { return m_port_out_callback[3].bind(); } + + // misc. configuration + void set_p0_3state(u8 value) { m_port_3state[0] = value; } + void set_p1_3state(u8 value) { m_port_3state[1] = value; } + void set_p2_3state(u8 value) { m_port_3state[2] = value; } + void set_p3_3state(u8 value) { m_port_3state[3] = value; } + +protected: + // device_t implementation + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + virtual void device_config_complete() override; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + + // device_execute_interface implementation + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 2 - 1) / 2; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 2); } + +private: + // internal I/O handlers + u8 port_r(offs_t offset); + void port_w(offs_t offset, u8 data); + + // internal address map + void internal_io(address_map &map) ATTR_COLD; + + // subdevice finders + required_device<kp69_device> m_kp69; + + // callback objects + devcb_read8::array<4> m_port_in_callback; + devcb_write8::array<4> m_port_out_callback; + + // parallel port state + u8 m_port_data[4]; + u8 m_port_direction[4]; + u8 m_port_3state[4]; +}; + + +// device type declaration +DECLARE_DEVICE_TYPE(KL5C80A16, kl5c80a16_device) + +#endif // MAME_CPU_Z80_KL5C80A16_H diff --git a/src/devices/cpu/z80/kp63.cpp b/src/devices/cpu/z80/kp63.cpp new file mode 100644 index 00000000000..2d8d693d11f --- /dev/null +++ b/src/devices/cpu/z80/kp63.cpp @@ -0,0 +1,463 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KP63(A) Timer/Counter + + These macro cells provide 4 independent 16-bit down counters (reduced + to 3 in some versions) driven by an 8-bit prescaler attached to the + system clock. This prescaler is not fully emulated here, since its + operations are mostly transparent, though a divide-by-4 clock output + (SYNC) may be selected to appear on a port pin. + + Each counter has a single and optional external input (GATEn), which + on the KP63 can only be used to gate a divide-by-4 count but can also + be configured as an input clock on the KP63A. + + Two outputs are generated for each counter. The pulse or toggle output + (OUTPn) has configurable polarity and can be used for 8-bit PWM. The + strobe output (OUTSn) goes active high for 4 clock cycles when the + counter underflows and is connected to the interrupt controller. + + Writing the initial count register (CR) and reading the current count + are two-step processes, effective at the second write or first read. + These must not be overlapped with each other since they share a + temporary register. + +***************************************************************************/ + +#include "emu.h" +#include "kp63.h" + +#define VERBOSE 0 +#include "logmacro.h" + + +//************************************************************************** +// GLOBAL VARIABLES +//************************************************************************** + +// device type definitions +DEFINE_DEVICE_TYPE(KP63_3CHANNEL, kp63_3channel_device, "kp63_3channel", "Kawasaki Steel KP63 Timer/Counter (3 channels)") +DEFINE_DEVICE_TYPE(KP63A, kp63a_device, "kp63a", "Kawasaki Steel KP63A Timer/Counter") + +const char *const kp63_device::s_count_modes[4] = +{ + "one-shot", + "continuous count", + "WDT", + "PWM" +}; + + +//************************************************************************** +// KP63 DEVICE +//************************************************************************** + +//------------------------------------------------- +// kp63_device - constructor +//------------------------------------------------- + +kp63_device::kp63_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 num_counters, u8 mode_mask) + : device_t(mconfig, type, tag, owner, clock) + , m_out_pulse_callback(*this) + , m_out_strobe_callback(*this) + , c_num_counters(num_counters) + , c_mode_mask(mode_mask) + , m_timer{0} + , m_strobe_timer{0} + , m_pwm_timer{0} + , m_cr{0} + , m_last_count{0} + , m_count_tmp{0} + , m_status{0} + , m_rw_seq(0) + , m_timer_started(0) + , m_gate_input(0xf) +{ +} + + +//------------------------------------------------- +// kp63_3channel_device - constructor +//------------------------------------------------- + +kp63_3channel_device::kp63_3channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : kp63_device(mconfig, KP63_3CHANNEL, tag, owner, clock, 3, 0x1f) +{ +} + + +//------------------------------------------------- +// kp63a_device - constructor +//------------------------------------------------- + +kp63a_device::kp63a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : kp63_device(mconfig, KP63A, tag, owner, clock, 4, 0x3f) +{ +} + + +//------------------------------------------------- +// timer_expired - handle timed count underflow +//------------------------------------------------- + +template <int N> +TIMER_CALLBACK_MEMBER(kp63_device::timer_expired) +{ + timer_pulse(N); +} + + +//------------------------------------------------- +// strobe_off - handle end of strobe output +//------------------------------------------------- + +template <int N> +TIMER_CALLBACK_MEMBER(kp63_device::strobe_off) +{ + m_out_strobe_callback[N](0); +} + + +//------------------------------------------------- +// pwm_off - handle PWM phase change +//------------------------------------------------- + +template <int N> +TIMER_CALLBACK_MEMBER(kp63_device::pwm_off) +{ + m_status[N] &= 0x7f; + m_out_pulse_callback[N](BIT(m_status[N], 4) ? 1 : 0); +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void kp63_device::device_start() +{ + // Setup timers + m_timer[0] = timer_alloc(FUNC(kp63_device::timer_expired<0>), this); + m_strobe_timer[0] = timer_alloc(FUNC(kp63_device::strobe_off<0>), this); + m_pwm_timer[0] = timer_alloc(FUNC(kp63_device::pwm_off<0>), this); + m_timer[1] = timer_alloc(FUNC(kp63_device::timer_expired<1>), this); + m_strobe_timer[1] = timer_alloc(FUNC(kp63_device::strobe_off<1>), this); + m_pwm_timer[1] = timer_alloc(FUNC(kp63_device::pwm_off<1>), this); + m_timer[2] = timer_alloc(FUNC(kp63_device::timer_expired<2>), this); + m_strobe_timer[2] = timer_alloc(FUNC(kp63_device::strobe_off<2>), this); + m_pwm_timer[2] = timer_alloc(FUNC(kp63_device::pwm_off<2>), this); + if (c_num_counters > 3) + { + m_timer[3] = timer_alloc(FUNC(kp63_device::timer_expired<3>), this); + m_strobe_timer[3] = timer_alloc(FUNC(kp63_device::strobe_off<3>), this); + m_pwm_timer[3] = timer_alloc(FUNC(kp63_device::pwm_off<3>), this); + } + + // Save state + save_item(NAME(m_cr)); + save_item(NAME(m_last_count)); + save_item(NAME(m_count_tmp)); + save_item(NAME(m_status)); + save_item(NAME(m_rw_seq)); + save_item(NAME(m_timer_started)); + save_item(NAME(m_gate_input)); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void kp63_device::device_reset() +{ + for (unsigned n = 0; n < c_num_counters; n++) + { + // Turn off timers + m_timer[n]->adjust(attotime::never); + m_strobe_timer[n]->adjust(attotime::never); + m_pwm_timer[n]->adjust(attotime::never); + + // Reset status and count + m_status[n] = 0; + m_cr[n] = 0xffff; + m_last_count[n] = 0xffff; + + // Clear outputs + m_out_pulse_callback[n](0); + m_out_strobe_callback[n](0); + } + + // Clear read/write sequence for all counters + m_rw_seq = 0; + m_timer_started = 0; +} + + +//------------------------------------------------- +// timer_pulse - change outputs and stop or +// reload timer as count underflows +//------------------------------------------------- + +void kp63_device::timer_pulse(unsigned n) +{ + // Toggle pulse output + m_status[n] ^= 0x80; + m_out_pulse_callback[n](BIT(m_status[n], 7) != BIT(m_status[n], 4) ? 1 : 0); + + // Begin strobe output + m_out_strobe_callback[n](1); + m_strobe_timer[n]->adjust(clocks_to_attotime(4)); + + // Reload timer in continuous count and PWM modes + if (BIT(m_status[n], 2)) + timer_reload(n); + else + { + // Stop count at FFFF in one-shot and WDT modes + m_last_count[n] = 0xffff; + m_timer_started &= ~(1 << n); + } +} + + +//------------------------------------------------- +// timer_reload - reload timer from CR +//------------------------------------------------- + +void kp63_device::timer_reload(unsigned n) +{ + m_timer_started |= 1 << n; + + if (BIT(m_status[n], 5) || ((m_status[n] & 0x03) == 0x03 && !BIT(m_gate_input, n))) + m_last_count[n] = m_cr[n]; + else + { + unsigned prescale = BIT(m_status[n], 1) ? 4 : BIT(m_status[n], 0) ? 16 : 256; + if ((m_status[n] & 0x0c) == 0x0c) + { + // PWM + m_timer[n]->adjust(clocks_to_attotime(prescale * ((m_cr[n] & 0x00ff) + 1))); + m_pwm_timer[n]->adjust(clocks_to_attotime(prescale * ((m_cr[n] >> 8) + 1))); + } + else + m_timer[n]->adjust(clocks_to_attotime(prescale * (u32(m_cr[n]) + 1))); + } +} + + +//------------------------------------------------- +// timer_resume_count - start counting again +//------------------------------------------------- + +void kp63_device::timer_resume_count(unsigned n) +{ + if (!BIT(m_status[n], 5) || ((m_status[n] & 0x03) != 0x03 || BIT(m_gate_input, n))) + { + unsigned prescale = BIT(m_status[n], 1) ? 4 : BIT(m_status[n], 0) ? 16 : 256; + if ((m_status[n] & 0x0c) == 0x0c) + { + // PWM + m_timer[n]->adjust(clocks_to_attotime(prescale * ((m_last_count[n] & 0x00ff) + 1))); + m_pwm_timer[n]->adjust(clocks_to_attotime(prescale * ((m_last_count[n] >> 8) + 1))); + } + else + m_timer[n]->adjust(clocks_to_attotime(prescale * (u32(m_last_count[n]) + 1))); + } +} + + +//------------------------------------------------- +// timer_get_count - obtain the instant count in +// case of a readout or pause +//------------------------------------------------- + +u16 kp63_device::timer_get_count(unsigned n) const +{ + if (!BIT(m_timer_started, n) || BIT(m_status[n], 5) || ((m_status[n] & 0x03) == 0x03 && !BIT(m_gate_input, n))) + return m_last_count[n]; + else + { + unsigned prescale = BIT(m_status[n], 1) ? 4 : BIT(m_status[n], 0) ? 16 : 256; + if ((m_status[n] & 0x0c) == 0x0c) + { + // PWM + u8 ticks = attotime_to_clocks(m_timer[n]->remaining()) / prescale; + return ticks | ((m_cr[n] - (u16(ticks) << 8)) & 0xff00); + } + else + return attotime_to_clocks(m_timer[n]->remaining()) / prescale; + } +} + + +//------------------------------------------------- +// read - read count or status register +//------------------------------------------------- + +u8 kp63_device::read(offs_t offset) +{ + const unsigned n = offset >> 1; + assert(n < c_num_counters); + + if (BIT(offset, 0)) + { + // Status read clears read/write sequence + if (!machine().side_effects_disabled()) + m_rw_seq &= ~(1 << n); + return m_status[n]; + } + else if (BIT(m_rw_seq, n)) + { + // Second step of counter readout + if (!machine().side_effects_disabled()) + m_rw_seq &= ~(1 << n); + return m_count_tmp[n]; + } + else + { + // First step of counter readout + u16 count = timer_get_count(n); + if (!machine().side_effects_disabled()) + { + // Latch high byte into TMP register + m_rw_seq |= 1 << n; + m_count_tmp[n] = count >> 8; + } + return count & 0x00ff; + } +} + +//------------------------------------------------- +// write - set CR or mode register +//------------------------------------------------- + +void kp63_device::write(offs_t offset, u8 data) +{ + const unsigned n = offset >> 1; + assert(n < c_num_counters); + + if (BIT(offset, 0)) + { + bool old_outp = BIT(m_status[n], 7) != BIT(m_status[n], 4); + + // Stop count before setting mode + if (BIT(m_timer_started, n)) + { + if (!BIT(m_status[n], 5) || ((m_status[n] & 0x03) != 0x03 || BIT(m_gate_input, n))) + { + m_last_count[n] = timer_get_count(n); + m_timer[n]->adjust(attotime::never); + m_pwm_timer[n]->adjust(attotime::never); + } + m_timer_started &= ~(1 << n); + } + + if (BIT(data & c_mode_mask, 5)) + LOG("%s: Timer #%d configured for %s mode, %s edges of GATE, initial output %c\n", + machine().describe_context(), + n, + s_count_modes[BIT(data, 2, 2)], + BIT(data, 1) ? "???" : BIT(data, 0) ? "falling" : "rising", + BIT(data, 4) ? 'H' : 'L'); + else + LOG("%s: Timer #%d configured for %s mode, 1/%d system clock (GATE %s), initial output %c\n", + machine().describe_context(), + n, + s_count_modes[BIT(data, 2, 2)], + BIT(data, 1) ? 4 : BIT(data, 0) ? 16 : 256, + (data & 0x03) == 0x03 ? "effective" : "ignored", + BIT(data, 4) ? 'H' : 'L'); + m_status[n] = data & c_mode_mask; + + // Update OUTP + if (old_outp != BIT(data, 4)) + m_out_pulse_callback[n](BIT(data, 4) ? 1 : 0); + } + else if ((m_status[n] & 0x0c) == 0x08) + { + // WDT retrigger (data ignored; initial count must be written using a different mode) + timer_reload(n); + } + else if (BIT(m_rw_seq, n)) + { + // Second step of initial count write + m_rw_seq &= ~(1 << n); + m_cr[n] = u16(data) << 8 | m_count_tmp[n]; + + LOG("%s: Timer #%d initial count = %d\n", machine().describe_context(), n, (m_status[n] == 0x0c) ? m_cr[n] & 0x00ff : m_cr[n]); + + // Automatic retrigger in one-shot and continuous modes + if (!BIT(m_status[n], 3) || !BIT(m_timer_started, n)) + { + if (!BIT(m_status[n], 7)) + { + // Toggle OUTP + m_status[n] |= 0x80; + m_out_pulse_callback[n](BIT(m_status[n], 4) ? 0 : 1); + } + timer_reload(n); + } + } + else + { + // First step of initial count write (held in TMP register) + m_rw_seq |= 1 << n; + m_count_tmp[n] = data; + } +} + +//------------------------------------------------- +// write_gate - handle gate inputs +//------------------------------------------------- + +void kp63_device::write_gate(unsigned n, bool state) +{ + assert(n < c_num_counters); + + if (BIT(m_gate_input, n) != state) + return; + + if (state) + m_gate_input |= 1 << n; + else + m_gate_input &= ~(1 << n); + + if (BIT(m_timer_started, n)) + { + if ((m_status[n] & 0x23) == 0x03) + { + // Timer gated on or off + if (state) + timer_resume_count(n); + else + { + m_last_count[n] = timer_get_count(n); + m_timer[n]->adjust(attotime::never); + } + } + else if ((m_status[n] & 0x23) == (state ? 0x21 : 0x20)) + { + // Count edges of gate input + if ((m_status[n] & 0x0c) == 0x0c) + { + // PWM: count is in lower 8 bits + if ((m_last_count[n] & 0x00ff) == 0) + timer_pulse(n); + else + { + // Decrement both halves and check for underflow in upper half + m_last_count[n] -= 0x0101; + if (m_last_count[n] >= 0xff00) + { + m_status[n] &= 0x7f; + m_out_pulse_callback[n](BIT(m_status[n], 4) ? 1 : 0); + } + } + } + else if (m_last_count[n]-- == 0) + timer_pulse(n); + } + } +} diff --git a/src/devices/cpu/z80/kp63.h b/src/devices/cpu/z80/kp63.h new file mode 100644 index 00000000000..7d58017b6fa --- /dev/null +++ b/src/devices/cpu/z80/kp63.h @@ -0,0 +1,97 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KP63(A) Timer/Counter + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_KP63_H +#define MAME_CPU_Z80_KP63_H + +#pragma once + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class kp63_device : public device_t +{ +public: + // callback configuration + template <int N> auto outp_callback() { return m_out_pulse_callback[N].bind(); } + template <int N> auto outs_callback() { return m_out_strobe_callback[N].bind(); } + + // register interface + u8 read(offs_t offset); + void write(offs_t offset, u8 data); + + // input line interface + template <int N> void gate_w(int state) { write_gate(N, state); } + +protected: + // construction/destruction + kp63_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u8 num_counters, u8 mode_mask); + + // device_t implementation + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + +private: + static const char *const s_count_modes[4]; + + // timer callbacks + template <int N> TIMER_CALLBACK_MEMBER(timer_expired); + template <int N> TIMER_CALLBACK_MEMBER(strobe_off); + template <int N> TIMER_CALLBACK_MEMBER(pwm_off); + + // internal helpers + void timer_pulse(unsigned n); + void timer_reload(unsigned n); + void timer_resume_count(unsigned n); + u16 timer_get_count(unsigned n) const; + void write_gate(unsigned n, bool state); + + // callback objects + devcb_write_line::array<4> m_out_pulse_callback; + devcb_write_line::array<4> m_out_strobe_callback; + + // constant parameters + const u8 c_num_counters; + const u8 c_mode_mask; + + // internal timers + emu_timer *m_timer[4]; + emu_timer *m_strobe_timer[4]; + emu_timer *m_pwm_timer[4]; + + // internal state + u16 m_cr[4]; + u16 m_last_count[4]; + u8 m_count_tmp[4]; + u8 m_status[4]; + u8 m_rw_seq; + u8 m_timer_started; + u8 m_gate_input; +}; + +class kp63_3channel_device : public kp63_device +{ +public: + // device type constructor + kp63_3channel_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); +}; + +class kp63a_device : public kp63_device +{ +public: + // device type constructor + kp63a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); +}; + +// device type declarations +DECLARE_DEVICE_TYPE(KP63_3CHANNEL, kp63_3channel_device) +DECLARE_DEVICE_TYPE(KP63A, kp63a_device) + +#endif // MAME_CPU_Z80_KP63_H diff --git a/src/devices/cpu/z80/kp64.cpp b/src/devices/cpu/z80/kp64.cpp new file mode 100644 index 00000000000..ec0b8fdfa87 --- /dev/null +++ b/src/devices/cpu/z80/kp64.cpp @@ -0,0 +1,554 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KP64 Timer/Counter Unit + + This is a macro cell providing one 16-bit counter/timer with four + operating modes. KL5C80A12 allows two of these to be cascaded as one + 32-bit counter, but this option is scarcely documented and has not been + emulated here. + + Either the system clock (CLK) or the falling edge of an external clock + (XCLK) can be selected as the count source for any mode of operation. + The output (OUT) is initialized to L after reset and for most mode + settings, after which it may either toggle or pulse high depending on + the mode setting. In pulse mode, the OUT polarity is selectable. OUT + is also connected to the KL5C80A12 interrupt controller. + + Each time a mode control word is written, a new 16-bit value must be + provided for the CR register except in pulse width/frequency + measurement mode, which instead uses CR to hold the measured count. + Since the CPU can only write to registers 8 bits at a time, a separate + 8-bit holding register (TMP) is used to prevent CR from being updated + until both lower and higher bytes have been written. Likewise, the + counter value can only be read 8 bits at a time, and a stable readout + is guaranteed by requiring the count to be first latched into the + OR register by a command. Another command is used to reset the read/ + write sequence to the lower byte state. + + In the frequency divide and PWM modes, the counter is loaded when the + first count value is written and automatically reloaded on each + subsequent underflow. In the pulse mode, counting stops after + underflow, and the counter is loaded and started or restarted whenever + a new count value is written in the soft trigger submode, or following + the rising edge of the GATE input in the hard trigger submode. In the + pulse width/frequency measurement mode, the counter is loaded with + FFFFH after either the rising or falling edge of the GATE input, and + another selectable GATE edge completes the measurement and loads the + complement of the count value into CR. Counting continues after + measurement is complete if continuous measurement is selected. + + For all modes which do not use GATE as a trigger to start or restart + counting, counting is enabled when the GATE input is at a high level. + The H and L periods of GATE must be at least two system clock cycles + wide. + +***************************************************************************/ + +#include "emu.h" +#include "kp64.h" + +#define VERBOSE 0 +#include "logmacro.h" + +//************************************************************************** +// GLOBAL VARIABLES +//************************************************************************** + +// device type definition +DEFINE_DEVICE_TYPE(KP64, kp64_device, "kp64", "Kawasaki Steel KP64 Timer/Counter") + + +//************************************************************************** +// KP64 DEVICE +//************************************************************************** + +//------------------------------------------------- +// kp64_device - constructor +//------------------------------------------------- + +kp64_device::kp64_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : device_t(mconfig, KP64, tag, owner, clock) + , m_out_callback(*this) + , m_count_timer(nullptr) + , m_pulse_timer(nullptr) + , m_xclk(true) + , m_gate(true) + , m_count(0) + , m_cr(0) + , m_or(0) + , m_tmp(0) + , m_status(0x40) + , m_read_msb(false) + , m_write_msb(false) + , m_reload(false) + , m_started(false) +{ +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void kp64_device::device_start() +{ + // Setup timers + m_count_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(kp64_device::count_underflow), this)); + m_pulse_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(kp64_device::pulse_off), this)); + + // Save state + save_item(NAME(m_xclk)); + save_item(NAME(m_gate)); + save_item(NAME(m_count)); + save_item(NAME(m_cr)); + save_item(NAME(m_or)); + save_item(NAME(m_tmp)); + save_item(NAME(m_status)); + save_item(NAME(m_read_msb)); + save_item(NAME(m_write_msb)); + save_item(NAME(m_reload)); + save_item(NAME(m_started)); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void kp64_device::device_reset() +{ + // Stop timers + m_count_timer->enable(false); + m_pulse_timer->enable(false); + + // Clear all registers + m_count = 0xffff; + m_cr = 0xffff; + m_or = 0xffff; + m_status = 0x01; // system clock synchronous + m_read_msb = false; + m_write_msb = false; + m_reload = false; + m_started = false; + + // Set output low + set_out(false); +} + + +//------------------------------------------------- +// set_out - update OUT and status register +//------------------------------------------------- + +void kp64_device::set_out(bool state) +{ + if (BIT(m_status, 6) != state) + { + LOG("%s: OUT = %c\n", machine().time().to_string(), state ? 'H' : 'L'); + if (state) + m_status |= 0x40; + else + m_status &= 0xbf; + m_out_callback(state); + } +} + + +//------------------------------------------------- +// count_value - get current counter value +//------------------------------------------------- + +u16 kp64_device::count_value() const noexcept +{ + if (m_count_timer->enabled()) + return std::min<u32>(attotime_to_clocks(m_count_timer->remaining()), 0xffff); + else + return m_count; +} + + +//------------------------------------------------- +// reload_count - reload and begin counting +//------------------------------------------------- + +void kp64_device::reload_count() +{ + m_count = BIT(m_status, 5) ? 0xffff : m_cr; + if (BIT(m_status, 0)) + { + // hng64 network MCU configures this supposedly invalid value and thrashes the scheduler if the timer is enabled + if (m_count == 0) + logerror("%s: Zero reload value specified for timer\n", machine().describe_context()); + else + m_count_timer->adjust(clocks_to_attotime(u32(m_count) + 1)); + } + + // Count is now started whether or not it was before + m_reload = false; + m_started = true; + + switch (BIT(m_status, 3, 3)) + { + case 0b000: + // Set OUT low before pulse + if (BIT(m_status, 2)) + set_out(false); + break; + + case 0b001: + // Initiate H phase of PWM mode + set_out(true); + break; + + case 0b010: + // One-shot pulse mode + set_out(BIT(m_status, 1)); + break; + + case 0b011: + // Strobe pulse mode + set_out(!BIT(m_status, 1)); + break; + } +} + + +//------------------------------------------------- +// finish_count - handle counter decrement from 0 +//------------------------------------------------- + +void kp64_device::finish_count() +{ + if (BIT(m_status, 5)) + { + // Count merely wraps around in pulse width/frequency measurement mode + m_count = 0xffff; + if (BIT(m_status, 0)) + m_count_timer->adjust(clocks_to_attotime(u32(m_count) + 1)); + } + else if (BIT(m_status, 4)) + { + // Toggle output + set_out(!BIT(m_status, 6)); + if (BIT(m_status, 0) && BIT(m_status, 3)) + m_pulse_timer->adjust(clocks_to_attotime(1)); + + // Wait for retrigger + m_started = false; + } + else if (BIT(m_status, 3)) + { + // Alternating reload for PWM mode + m_count = (BIT(m_status, 6) ? ~m_cr : m_cr) & ((0x40 << (m_status & 0x06)) - 1); + if (BIT(m_status, 0)) + m_count_timer->adjust(clocks_to_attotime(u32(m_count) + 1)); + + // Toggle output + set_out(!BIT(m_status, 6)); + } + else + { + // Automatic reload + m_count = m_cr; + if (BIT(m_status, 0)) + { + m_count_timer->adjust(clocks_to_attotime(u32(m_count) + 1)); + if (BIT(m_status, 2)) + m_pulse_timer->adjust(clocks_to_attotime(1)); + } + + // Pulse or toggle output + set_out(BIT(m_status, 2) || !BIT(m_status, 6)); + } +} + + +//------------------------------------------------- +// count_underflow - handle timer expiry +//------------------------------------------------- + +TIMER_CALLBACK_MEMBER(kp64_device::count_underflow) +{ + finish_count(); +} + + +//------------------------------------------------- +// pulse_off - end strobe +//------------------------------------------------- + +TIMER_CALLBACK_MEMBER(kp64_device::pulse_off) +{ + set_out(BIT(m_status, 4) && !BIT(m_status, 1)); +} + + +//************************************************************************** +// I/O REGISTER INTERFACE +//************************************************************************** + +//------------------------------------------------- +// counter_r - read OR or CR byte in sequence +//------------------------------------------------- + +u8 kp64_device::counter_r() +{ + u8 data = (BIT(m_status, 5) ? m_cr : m_or) >> (m_read_msb ? 8 : 0); + + // Advance read sequence + if (!machine().side_effects_disabled()) + m_read_msb = !m_read_msb; + + return data; +} + + +//------------------------------------------------- +// counter_w - write count byte in sequence +//------------------------------------------------- + +void kp64_device::counter_w(u8 data) +{ + if (m_write_msb) + { + m_cr = u16(data) << 8 | m_tmp; + LOG("%s: %04XH entered into CR while %s\n", machine().describe_context(), m_cr, m_started ? "started" : "stopped"); + + // Load count into CR for frequency divide modes and PWM modes if this was the initial count + if (!m_started && BIT(m_status, 4, 2) == 0) + { + if (BIT(m_status, 0) && m_gate) + reload_count(); + else + m_reload = true; + } + + m_write_msb = false; + } + else + { + m_tmp = data; + m_write_msb = true; + } +} + + +//------------------------------------------------- +// status_r - read status word +//------------------------------------------------- + +u8 kp64_device::status_r() +{ + // Bit 6 is always 0 in pulse width/frequency measurement mode + return m_status & (BIT(m_status, 5) ? 0xbf : 0xff); +} + + +//------------------------------------------------- +// control_w - write control word +//------------------------------------------------- + +void kp64_device::control_w(u8 data) +{ + switch (BIT(data, 3, 3)) + { + case 0b000: + LOG("%s: Frequency divide mode selected (%s source, %s output)\n", + machine().describe_context(), + BIT(data, 0) ? "CLK" : "XCLK", + BIT(data, 2) ? "pulse" : "toggle"); + + m_status = data & 0x3d; + m_cr = 0xffff; + m_count = 0xffff; + m_started = false; + m_reload = false; + set_out(false); + m_count_timer->enable(false); + m_pulse_timer->enable(false); + break; + + case 0b001: + LOG("%s: PWM mode selected (period = %s/%d)\n", + machine().describe_context(), + BIT(data, 0) ? "CLK" : "XCLK", + (0x40 << (data & 0x06)) + 1); + m_status = data & 0x3f; + m_cr = 0xffff; + m_count = (0x40 << (m_status & 0x06)) - 1; + m_started = false; + m_reload = false; + set_out(false); + m_count_timer->enable(false); + m_pulse_timer->enable(false); + break; + + case 0b010: case 0b011: + LOG("%s: Pulse mode selected (%s source, %s trigger, %s%s output)\n", + machine().describe_context(), + BIT(data, 0) ? "CLK" : "XCLK", + BIT(data, 2) ? "hard" : "soft", + BIT(data, 1) ? "reverse " : "", + BIT(data, 3) ? "strobe" : "one shot"); + m_status = data & 0x3f; + m_cr = 0xffff; + m_count = 0xffff; + m_started = false; + m_reload = false; + set_out(!BIT(data, 1)); + m_count_timer->enable(false); + m_pulse_timer->enable(false); + break; + + case 0b100: case 0b101: + LOG("%s: Pulse width/frequency measurement mode selected (%s source, %s edge to %s edge, %s)\n", + machine().describe_context(), + BIT(data, 0) ? "CLK" : "XCLK", + BIT(data, 2) ? "rising" : "falling", + BIT(data, 1) ? "rising" : "falling", + BIT(data, 3) ? "continuous" : "once"); + m_status = data & 0x3f; + m_cr = 0xffff; + m_count = 0xffff; + m_started = false; + m_reload = false; + set_out(false); + m_count_timer->enable(false); + m_pulse_timer->enable(false); + break; + + case 0b111: + if (BIT(data, 0, 2) == 0) + { + // Counter latch command + m_or = count_value(); + LOG("%s: %04XH latched into OR\n", machine().describe_context(), m_or); + } + else + { + // Flag clear command + if (BIT(data, 0)) + { + if (BIT(m_status, 7)) + LOG("%s: Flag cleared\n", machine().describe_context()); + m_status &= 0x7f; + } + + // R/W sequence clear command + if (BIT(data, 1)) + { + m_read_msb = false; + m_write_msb = false; + } + } + break; + + default: + logerror("%s: Unrecognized control word %02XH written\n", machine().describe_context(), data); + break; + } +} + + +//************************************************************************** +// INPUT LINES +//************************************************************************** + +//------------------------------------------------- +// xclk_w - set external count input +//------------------------------------------------- + +void kp64_device::xclk_w(int state) +{ + // Only falling edges count + if (std::exchange(m_xclk, state) && !state) + { + // Ignore if system clock selected + if (BIT(m_status, 0)) + return; + + // Ignore if gated off + if (!m_gate && !BIT(m_status, 5) && (!BIT(m_status, 4) || !BIT(m_status, 2))) + return; + + if (m_reload) + reload_count(); + else if (m_started && m_count-- == 0) + finish_count(); + else + { + // Terminate pulse + if (BIT(m_status, 2, 4) == 0b0001) + set_out(0); + else if (BIT(m_status, 3, 3) == 0b011) + set_out(!BIT(m_status, 1)); + } + } +} + + +//------------------------------------------------- +// gate_w - set gate input +//------------------------------------------------- + +void kp64_device::gate_w(int state) +{ + if (m_gate == bool(state)) + return; + + m_gate = state; + if (BIT(m_status, 5)) + { + if (BIT(m_status, 2) == state && (BIT(m_status, 3) || !BIT(m_status, 7))) + m_reload = true; + + if (BIT(m_status, 1) == state && m_started) + { + m_cr = ~count_value(); + LOG("%s: Measurement completed (count = %04X)\n", machine().time().to_string(), m_cr); + m_status |= 0x80; + if (!BIT(m_status, 3)) + { + m_started = false; + m_reload = false; + } + + // Pulse H for one system clock cycle + set_out(true); + m_pulse_timer->adjust(clocks_to_attotime(1)); + } + + if (m_reload && BIT(m_status, 0)) + reload_count(); + } + else if (BIT(m_status, 4) && BIT(m_status, 2)) + { + if (state) + { + LOG("%s: Hard trigger received\n", machine().time().to_string()); + m_status |= 0x80; + if (BIT(m_status, 0)) + reload_count(); + else + m_reload = true; + } + } + else if (BIT(m_status, 0)) + { + LOG("%s: Timer gated %s\n", machine().time().to_string(), state ? "on" : "off"); + if (state) + { + if (m_reload) + reload_count(); + else if (m_started) + m_count_timer->adjust(clocks_to_attotime(u32(m_count) + 1)); + } + else if (m_started) + { + m_count = count_value(); + m_count_timer->enable(false); + } + } +} diff --git a/src/devices/cpu/z80/kp64.h b/src/devices/cpu/z80/kp64.h new file mode 100644 index 00000000000..53391c6dbc0 --- /dev/null +++ b/src/devices/cpu/z80/kp64.h @@ -0,0 +1,80 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KP64 Timer/Counter Unit + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_KP64_H +#define MAME_CPU_Z80_KP64_H + +#pragma once + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class kp64_device : public device_t +{ +public: + // device type constructor + kp64_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + // callback configuration + auto out_callback() { return m_out_callback.bind(); } + + // I/O register interface + u8 counter_r(); + void counter_w(u8 data); + u8 status_r(); + void control_w(u8 data); + + // input line interface + void xclk_w(int state); + void gate_w(int state); + +protected: + // device_t implementation + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + +private: + // timer callbacks + TIMER_CALLBACK_MEMBER(count_underflow); + TIMER_CALLBACK_MEMBER(pulse_off); + + // internal helpers + void set_out(bool state); + u16 count_value() const noexcept; + void reload_count(); + void finish_count(); + + // callback objects + devcb_write_line m_out_callback; + + // internal timer + emu_timer *m_count_timer; + emu_timer *m_pulse_timer; + + // input state + bool m_xclk; + bool m_gate; + + // internal state + u16 m_count; + u16 m_cr; + u16 m_or; + u8 m_tmp; + u8 m_status; + bool m_read_msb; + bool m_write_msb; + bool m_reload; + bool m_started; +}; + +// device type declaration +DECLARE_DEVICE_TYPE(KP64, kp64_device) + +#endif // MAME_CPU_Z80_KP64_H diff --git a/src/devices/cpu/z80/kp69.cpp b/src/devices/cpu/z80/kp69.cpp new file mode 100644 index 00000000000..3b1b59dcb20 --- /dev/null +++ b/src/devices/cpu/z80/kp69.cpp @@ -0,0 +1,464 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KP69 Interrupt Controller + + This macro cell is the sole provider of maskable interrupts for + KC80/KC82-based microcontrollers. It responds to the CPU's internal + IACK and EOI outputs (the latter associated with the RETI instruction) + with prioritized Mode 2 vectors and nested in-service lockouts. It + offers no support for polled operation or daisy-chaining other + interrupt controllers, but it does allow code to recognize spurious + interrupts. + + Each of the 16 interrupt sources may be programmed either as level- + triggered or edge-triggered, though the latter is required for + interrupts that are internal timer/counter outputs. These and the + interrupt vector register must be written first after a reset before + the mask and priority group registers can be defined, with no way of + returning to the initial mode once the vector has been set. + +***************************************************************************/ + +#include "emu.h" +#include "kp69.h" + +#define VERBOSE 0 +#include "logmacro.h" + +// device type definition +DEFINE_DEVICE_TYPE(KP69, kp69_device, "kp69", "Kawasaki Steel KP69 Interrupt Controller") + + +//------------------------------------------------- +// kp69_base_device - constructor +//------------------------------------------------- + +kp69_base_device::kp69_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) + : device_t(mconfig, type, tag, owner, clock) + , device_z80daisy_interface(mconfig, *this) + , m_int_callback(*this) + , m_input_levels(0) + , m_irr(0) + , m_isr(0) + , m_illegal_state(false) + , m_ivr(0) + , m_imr(0xffff) + , m_ler(0) + , m_pgr(0) + , m_int_active(false) +{ +} + + +//------------------------------------------------- +// kp69_device - constructor +//------------------------------------------------- + +kp69_device::kp69_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : kp69_base_device(mconfig, KP69, tag, owner, clock) + , m_ivr_written(false) +{ +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void kp69_base_device::device_start() +{ + // Register state for saving + save_item(NAME(m_input_levels)); + save_item(NAME(m_irr)); + save_item(NAME(m_isr)); + save_item(NAME(m_illegal_state)); + save_item(NAME(m_ivr)); + save_item(NAME(m_imr)); + save_item(NAME(m_ler)); + save_item(NAME(m_pgr)); + save_item(NAME(m_int_active)); +} + +void kp69_device::device_start() +{ + kp69_base_device::device_start(); + save_item(NAME(m_ivr_written)); +} + + +//------------------------------------------------- +// add_to_state - debug state interface for MCU +//------------------------------------------------- + +void kp69_base_device::add_to_state(device_state_interface &state, int index) +{ + state.state_add(index, "IRR", m_irr, [this](u16 data) { set_irr(data); }); + state.state_add(index + 1, "ISR", m_isr, [this](u16 data) { set_isr(data); }); + state.state_add(index + 2, "IVR", m_ivr).mask(0xe0); + state.state_add(index + 3, "LER", m_ler, [this](u16 data) { set_ler(data); }); + state.state_add(index + 4, "PGR", m_pgr, [this](u16 data) { set_pgr(data); }); + state.state_add(index + 5, "IMR", m_imr, [this](u16 data) { set_imr(data); }); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void kp69_base_device::device_reset() +{ + // Reset inputs to level mode + m_ler = 0; + + // Mask all interrupts, cancel requests and end service + m_imr = 0xffff; + m_irr = 0; + m_isr = 0; + m_illegal_state = false; + + // Reset priority groups + m_pgr = 0; + + // Deassert interrupt output + set_int(false); +} + +void kp69_device::device_reset() +{ + kp69_base_device::device_reset(); + + // Allow LER and IVR to be written first + m_ivr_written = false; +} + + +//------------------------------------------------- +// isrl_r - read lower 8 bits of ISR +//------------------------------------------------- + +u8 kp69_base_device::isrl_r() +{ + return m_isr & 0x00ff; +} + + +//------------------------------------------------- +// isrh_r - read upper 8 bits of ISR +//------------------------------------------------- + +u8 kp69_base_device::isrh_r() +{ + return (m_isr & 0xff00) >> 8; +} + + +//------------------------------------------------- +// imrl_r - read lower 8 bits of IMR +//------------------------------------------------- + +u8 kp69_base_device::imrl_r() +{ + return m_imr & 0x00ff; +} + + +//------------------------------------------------- +// imrh_r - read upper 8 bits of IMR +//------------------------------------------------- + +u8 kp69_base_device::imrh_r() +{ + return (m_imr & 0xff00) >> 8; +} + + +//------------------------------------------------- +// lerl_pgrl_w - write lower 8 bits of LER or PGR +//------------------------------------------------- + +void kp69_device::lerl_pgrl_w(u8 data) +{ + if (m_ivr_written) + set_pgr((m_pgr & 0xff00) | data); + else + set_ler((m_ler & 0xff00) | data); +} + + +//------------------------------------------------- +// lerh_pgrh_w - write upper 8 bits of LER or PGR +//------------------------------------------------- + +void kp69_device::lerh_pgrh_w(u8 data) +{ + if (m_ivr_written) + set_pgr(u16(data) << 8 | (m_pgr & 0x00ff)); + else + set_ler(u16(data) << 8 | (m_ler & 0x00ff)); +} + + +//------------------------------------------------- +// imrl_w - write lower 8 bits of IMR +//------------------------------------------------- + +void kp69_device::imrl_w(u8 data) +{ + if (!m_ivr_written) + logerror("%s: IMRL written before IVR\n", machine().describe_context()); + + set_imr((m_imr & 0xff00) | data); +} + + +//------------------------------------------------- +// ivr_imrh_w - write IVR or upper 8 bits of IMR +//------------------------------------------------- + +void kp69_device::ivr_imrh_w(u8 data) +{ + if (m_ivr_written) + set_imr(u16(data) << 8 | (m_imr & 0x00ff)); + else + { + m_ivr = data & 0xe0; + m_ivr_written = true; + } +} + + +//------------------------------------------------- +// int_active - determine whether or not the INT +// output is currently active +//------------------------------------------------- + +bool kp69_base_device::int_active() const +{ + if (m_illegal_state) + return false; + + // Compare priority of pending interrupt request with any being serviced + if ((m_irr & m_pgr) != 0 || (m_isr & m_pgr) != 0) + return (m_irr & ~m_isr & m_pgr) > (m_isr & m_pgr); + else + return (m_irr & ~m_isr) > m_isr; +} + + +//------------------------------------------------- +// set_int - update the INT output state +//------------------------------------------------- + +void kp69_base_device::set_int(bool active) +{ + if (m_int_active != active) + { + m_int_active = active; + m_int_callback(m_int_active ? ASSERT_LINE : CLEAR_LINE); + } +} + + +//------------------------------------------------- +// set_input_level - set the level state of one +// out of 16 interrupt inputs +//------------------------------------------------- + +void kp69_base_device::set_input_level(int level, bool state) +{ + if (!BIT(m_input_levels, level) && state) + { + m_input_levels |= 1 << level; + + // Masked-out interrupts cannot be requested + if (!BIT(m_irr, level) && !BIT(m_imr, level)) + { + u16 old_ints = m_irr | m_isr; + m_irr |= 1 << level; + LOG("IRR[%d] asserted\n", level); + if (!m_illegal_state && (1 << level) > (BIT(m_pgr, level) ? old_ints & m_pgr : old_ints)) + set_int(true); + } + } + else if (BIT(m_input_levels, level) && !state) + { + m_input_levels &= ~(1 << level); + + // Level-triggered interrupts may be deasserted + if (!BIT(m_ler, level) && BIT(m_irr, level)) + { + m_irr &= ~(1 << level); + LOG("IRR[%d] cleared\n", level); + if (!m_illegal_state) + set_int(int_active()); + } + } +} + + +//------------------------------------------------- +// set_irr - write a new value to the Interrupt +// Request Register (not accessible by software) +//------------------------------------------------- + +void kp69_base_device::set_irr(u16 data) +{ + m_irr = (data & ~m_imr & m_ler) | (m_irr & ~m_ler); + set_int(int_active()); +} + + +//------------------------------------------------- +// set_isr - write a new value to the In Service +// Register (not writable by software) +//------------------------------------------------- + +void kp69_base_device::set_isr(u16 data) +{ + m_isr = data; + set_int(int_active()); +} + + +//------------------------------------------------- +// set_imr - write a new value to the Interrupt +// Mask Register +//------------------------------------------------- + +void kp69_base_device::set_imr(u16 data) +{ + u16 old_irr = m_irr; + m_imr = data; + m_irr = (m_irr & ~data & m_ler) | (m_input_levels & ~data & ~m_ler); + if (m_irr != old_irr) + { + bool active = int_active(); + if (active != m_int_active) + LOG("%s: INT %s (IRR = %04X, was %04X)\n", machine().describe_context(), active ? "unmasked" : "masked out", m_irr, old_irr); + set_int(active); + } +} + + +//------------------------------------------------- +// set_ler - write a new value to the Level/Edge +// Register +//------------------------------------------------- + +void kp69_base_device::set_ler(u16 data) +{ + u16 old_irr = m_irr; + m_irr = (m_input_levels & ~data) | (m_irr & m_ler & data); + m_ler = data; + if (m_irr != old_irr) + set_int(int_active()); +} + + +//------------------------------------------------- +// set_pgr - write a new value to the Priority +// Group Register +//------------------------------------------------- + +void kp69_base_device::set_pgr(u16 data) +{ + if (m_pgr != data) + { + m_pgr = data; + if (!m_illegal_state && m_isr != 0) + set_int(int_active()); + } +} + + +//------------------------------------------------- +// z80daisy_irq_state - return the overall IRQ +// state for this device +//------------------------------------------------- + +int kp69_base_device::z80daisy_irq_state() +{ + return m_int_active ? (Z80_DAISY_INT | Z80_DAISY_IEO) : Z80_DAISY_IEO; +} + + +//------------------------------------------------- +// z80daisy_irq_ack - acknowledge an IRQ and +// return the appropriate vector +//------------------------------------------------- + +int kp69_base_device::z80daisy_irq_ack() +{ + int level = -1; + + // Restrict to high-priority interrupts if any of those are pending + if ((m_irr & m_pgr) != 0) + { + level = 31 - count_leading_zeros_32(u32(m_irr & m_pgr)); + assert(level >= 0 && level < 16); + if ((1 << level) < (m_isr & m_pgr)) + level = -1; + } + else if (m_irr != 0 && (m_isr & m_pgr) == 0) + { + level = 31 - count_leading_zeros_32(u32(m_irr)); + assert(level >= 0 && level < 16); + if ((1 << level) < m_isr) + level = -1; + } + + if (level != -1) + { + u8 vector = m_ivr | (level << 1); + if (BIT(m_ler, level)) + { + LOG("%s: IRR[%d] acknowledged and cleared (vector = %02X)\n", machine().describe_context(), level, vector); + m_irr &= ~(1 << level); + } + else + LOG("%s: IR[%d] acknowledged (vector = %02X)\n", machine().describe_context(), level, vector); + + m_isr |= 1 << level; + set_int(false); + + return vector; + } + + // Illegal interrupt operation: same vector as IR[0] but ISR[0] not set + LOG("%s: Illegal interrupt at IACK (vector = %02X)\n", machine().describe_context(), m_ivr); + m_illegal_state = true; + set_int(false); + return m_ivr; +} + + +//------------------------------------------------- +// z80daisy_irq_reti - clear the interrupt +// pending state to allow other interrupts through +//------------------------------------------------- + +void kp69_base_device::z80daisy_irq_reti() +{ + if (m_illegal_state) + { + LOG("%s: End of illegal interrupt\n", machine().describe_context()); + m_illegal_state = false; + } + else if (m_isr != 0) + { + int level = 31 - count_leading_zeros_32(u32((m_isr & m_pgr) != 0 ? (m_isr & m_pgr) : m_isr)); + assert(level >= 0 && level < 16); + + m_isr &= ~(1 << level); + LOG("%s: EOI for ISR[%d]\n", machine().describe_context(), level); + } + else + { + logerror("%s: RETI before interrupt acknowledged\n", machine().describe_context()); + return; + } + + set_int(int_active()); +} diff --git a/src/devices/cpu/z80/kp69.h b/src/devices/cpu/z80/kp69.h new file mode 100644 index 00000000000..ad93c6a86af --- /dev/null +++ b/src/devices/cpu/z80/kp69.h @@ -0,0 +1,104 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Kawasaki Steel (Kawatetsu) KP69 Interrupt Controller + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_KP69_H +#define MAME_CPU_Z80_KP69_H + +#pragma once + +#include "machine/z80daisy.h" + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class kp69_base_device : public device_t, public device_z80daisy_interface +{ +public: + // callback to CPU + auto int_callback() { return m_int_callback.bind(); } + + // read handlers + u8 isrl_r(); + u8 isrh_r(); + u8 imrl_r(); + u8 imrh_r(); + + // interrupt inputs + template <int N> void ir_w(int state) + { + static_assert(N >= 0 && N < 16, "Invalid level"); + set_input_level(N, state); + } + + void add_to_state(device_state_interface &state, int index); + +protected: + // construction/destruction + kp69_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock); + + // device_t implementation + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + + // device_z80daisy_interface implementation + virtual int z80daisy_irq_state() override; + virtual int z80daisy_irq_ack() override; + virtual void z80daisy_irq_reti() override; + + // internal helpers + bool int_active() const; + void set_int(bool active); + void set_input_level(int level, bool state); + void set_irr(u16 data); + void set_isr(u16 data); + void set_imr(u16 data); + void set_ler(u16 data); + void set_pgr(u16 data); + + // callback object + devcb_write_line m_int_callback; + + // internal state + u16 m_input_levels; + u16 m_irr; + u16 m_isr; + bool m_illegal_state; + u8 m_ivr; + u16 m_imr; + u16 m_ler; + u16 m_pgr; + bool m_int_active; +}; + +class kp69_device : public kp69_base_device +{ +public: + // device type constructor + kp69_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); + + // write handlers + void lerl_pgrl_w(u8 data); + void lerh_pgrh_w(u8 data); + void imrl_w(u8 data); + void ivr_imrh_w(u8 data); + +protected: + // device-level overrides + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + +private: + bool m_ivr_written; +}; + +// device type declaration +DECLARE_DEVICE_TYPE(KP69, kp69_device) + +#endif // MAME_CPU_Z80_KP69_H diff --git a/src/devices/cpu/z80/ky80.cpp b/src/devices/cpu/z80/ky80.cpp new file mode 100644 index 00000000000..b55237efa95 --- /dev/null +++ b/src/devices/cpu/z80/ky80.cpp @@ -0,0 +1,56 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Taxan KY-80 + + This 100-pin QFP device seems to be a custom derivative of the + Kawasaki KC82 CPU core (fast Z80-like with built-in MMU). It seems + possible that it was built entirely out of Kawasaki LSI macrocells, + but the on-chip peripherals are at least mapped differently than in + either KL5C80A12 or KL5C80A16 (in the top 3/8ths of the I/O space + rather the bottom quarter). + + On-chip features appear to include 1024 bytes of RAM, an interrupt + controller (not quite the same as KP69), a KP63-like timer/counter + block, 5 parallel ports and 2 8251-like serial ports. + +***************************************************************************/ + +#include "emu.h" +#include "ky80.h" + +// device type definition +DEFINE_DEVICE_TYPE(KY80, ky80_device, "ky80", "Taxan KY-80") + + +//------------------------------------------------- +// ky80_device - constructor +//------------------------------------------------- + +ky80_device::ky80_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : kc82_device(mconfig, KY80, tag, owner, clock, + address_map_constructor(FUNC(ky80_device::internal_ram), this), + address_map_constructor(FUNC(ky80_device::internal_io), this)) +{ +} + + +//------------------------------------------------- +// internal_ram - map for high-speed internal RAM +//------------------------------------------------- + +void ky80_device::internal_ram(address_map &map) +{ + map(0xffc00, 0xfffff).ram().share("ram"); +} + + +//------------------------------------------------- +// internal_io - map for internal I/O registers +//------------------------------------------------- + +void ky80_device::internal_io(address_map &map) +{ + map(0xa0, 0xa7).mirror(0xff00).rw(FUNC(ky80_device::mmu_r), FUNC(ky80_device::mmu_w)); +} diff --git a/src/devices/cpu/z80/ky80.h b/src/devices/cpu/z80/ky80.h new file mode 100644 index 00000000000..2f5cef749f2 --- /dev/null +++ b/src/devices/cpu/z80/ky80.h @@ -0,0 +1,42 @@ +// license:BSD-3-Clause +// copyright-holders:AJR +/*************************************************************************** + + Taxan KY-80 + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_KY80_H +#define MAME_CPU_Z80_KY80_H + +#pragma once + +#include "kc82.h" + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class ky80_device : public kc82_device +{ +public: + // device type constructor + ky80_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + +protected: + // device_execute_interface overrides + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 2 - 1) / 2; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 2); } + +private: + // internal address maps + void internal_ram(address_map &map) ATTR_COLD; + void internal_io(address_map &map) ATTR_COLD; +}; + + +// device type declaration +DECLARE_DEVICE_TYPE(KY80, ky80_device) + +#endif // MAME_CPU_Z80_KY80_H diff --git a/src/devices/cpu/z80/lz8420m.cpp b/src/devices/cpu/z80/lz8420m.cpp new file mode 100644 index 00000000000..26e41a6b248 --- /dev/null +++ b/src/devices/cpu/z80/lz8420m.cpp @@ -0,0 +1,47 @@ +// license:BSD-3-Clause +// copyright-holders:cam900 +/*************************************************************************** + + Sharp LZ8420M Z80 with Built-in RAM + + (TODO: everything; + 8 Bit IO, 4 Bit Input, 4 Bit Output, 512 Byte RAM) + +***************************************************************************/ + +#include "emu.h" +#include "lz8420m.h" + +DEFINE_DEVICE_TYPE(LZ8420M, lz8420m_device, "lz8420m", "Sharp LZ8420M") + + +lz8420m_device::lz8420m_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : z80_device(mconfig, LZ8420M, tag, owner, clock) +{ +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void lz8420m_device::device_start() +{ + z80_device::device_start(); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void lz8420m_device::device_reset() +{ + z80_device::device_reset(); +} + + +/* CPU interface */ +void lz8420m_device::device_add_mconfig(machine_config &config) +{ +} diff --git a/src/devices/cpu/z80/lz8420m.h b/src/devices/cpu/z80/lz8420m.h new file mode 100644 index 00000000000..50941b8a2b2 --- /dev/null +++ b/src/devices/cpu/z80/lz8420m.h @@ -0,0 +1,45 @@ +// license:BSD-3-Clause +// copyright-holders:cam900 +/*************************************************************************** + + Sharp LZ8420M Z80 with Built-in RAM + + (TODO: everything; + 8 Bit IO, 4 Bit Input, 4 Bit Output, 512 Byte RAM) + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_LZ8420M_H +#define MAME_CPU_Z80_LZ8420M_H + +#pragma once + +#include "z80.h" + + +/*************************************************************************** + DEVICE CONFIGURATION MACROS +***************************************************************************/ + + +/*************************************************************************** + TYPE DEFINITIONS +***************************************************************************/ + +class lz8420m_device : public z80_device +{ +public: + lz8420m_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t); + +protected: + // device-level overrides + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; +}; + + +// device type definition +DECLARE_DEVICE_TYPE(LZ8420M, lz8420m_device) + +#endif // MAME_CPU_Z80_LZ8420M_H diff --git a/src/devices/cpu/z80/mc8123.cpp b/src/devices/cpu/z80/mc8123.cpp new file mode 100644 index 00000000000..33acc77b096 --- /dev/null +++ b/src/devices/cpu/z80/mc8123.cpp @@ -0,0 +1,416 @@ +// license:BSD-3-Clause +// copyright-holders:Nicola Salmoria, David Widel +/*************************************************************************** + +NEC MC-8123 encryption emulation + +Decryption tables provided by David Widel +Decryption algorithm by Nicola Salmoria + +The NEC MC-8123 is a Z80 with built-in encryption. +It contains 0x2000 bytes of battery-backed RAM, when the battery dies the +game stops working. It's possible that the CPU would work as a normal Z80 +in that case, this hasn't been verified. + +When the CPU reads a byte from memory, it uses 12 bits of the address and +the information of whether the byte is an opcode or not to select a byte in +the internal RAM. The byte controls how the decryption works. + +A special value in the internal RAM instructs the CPU to not apply the decryption +algorithm at all. This is necessary for the CPU to be able to use RAM areas +normally. + +In theory, the size of the key would make the encryption quite secure. + +In practice, the contents of the internal RAM were generated using a linear +congruential generator, so the whole key can be generated starting from a single +24-bit seed. + +The LCG is the same that was used to generate the FD1094 keys. +Note that the algorithm skips the special value that would instruct the CPU to +not decrypt at that address. + +void generate_key(uint8_t (&key)[0x2000], uint32_t seed, unsigned upper_bound) +{ + unsigned i; + + for (i = 0; i < upper_bound; ++i) + { + uint8_t byteval; + + do + { + seed *= 0x29; + seed += seed << 16; + + byteval = (~seed >> 16) & 0xff; + } + while (byteval == 0xff); + + key[i] = byteval; + } + + for ( ; i < 0x2000; ++i) + key[i] = 0xff; +} + + +The known games that use this CPU are: + +CPU # Game Notes Seed Upper Limit +-------- ------------------------- ------------------ ------ ----- +317-0029 Block Gal NEC MC-8123B 651 091755 1800? +317-0030 Perfect Billiard 9451EC 1C00 +317-0040 Toki no Senshi - Chrono Soldier 068713 1c00 +317-0042 Opa Opa B31FD0 1C00 +317-0043 Wonder Boy Monster Land 640708 1C00 +317-0054 Shinobi (sound CPU) NEC MC-8123B 652 088992 1800 +317-0057 Fantasy Zone 2 ADFACE 1800 +317-0064 Ufo Senshi Yohko Chan 880603 1C00 +317-0066 Altered Beast (sound CPU) NEC MC-8123B 704 ED8600 1800 +317-5002 Gigas 1 & 2 NEC MC-8123 638 234567 1C00 +317-5004 Eagle Writer Not Dumped +317-5005 Astro Flash Not Dumped +317-5008 Perfect Billiard 9451EC 1C00 +317-5012 Ganbare Chinsan Ooshoubu NEC MC-8123A 804B54 1C00 +317-5014 DakkoChan Jansoh NEC MC-8123B 206850 1C00 +317-5??? Ninja Kid II (sound CPU) NEC MC-8123A 646 27998D 1800 +317-???? Center Court (sound CPU) NEC MC-8123B 703 640506 1800 +317-???? Omega 861226 1C00? + +***************************************************************************/ + +#include "emu.h" +#include "mc8123.h" + + +DEFINE_DEVICE_TYPE(MC8123, mc8123_device, "mc8123", "MC-8123") + +//------------------------------------------------- +// mc8123_device - constructor +//------------------------------------------------- + +mc8123_device::mc8123_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : z80_device(mconfig, MC8123, tag, owner, clock) + , m_key(*this, "key") +{ +} + + +namespace { + +template <typename T> constexpr u8 BITS(T b) { return u8(1) << b; } +template <typename T, typename... U> constexpr u8 BITS(T b, U... c) { return (u8(1) << b) | BITS(c...); } + +} // anonymous namespace + +u8 mc8123_device::decrypt_type0(u8 val, u8 param, unsigned swap) +{ + if (swap == 0) val = bitswap<8>(val,7,5,3,1,2,0,6,4); + if (swap == 1) val = bitswap<8>(val,5,3,7,2,1,0,4,6); + if (swap == 2) val = bitswap<8>(val,0,3,4,6,7,1,5,2); + if (swap == 3) val = bitswap<8>(val,0,7,3,2,6,4,1,5); + + if (BIT(param,3) && BIT(val,7)) + val ^= BITS(5,3,0); + + if (BIT(param,2) && BIT(val,6)) + val ^= BITS(7,2,1); + + if (BIT(val,6)) val ^= BITS(7); + + if (BIT(param,1) && BIT(val,7)) + val ^= BITS(6); + + if (BIT(val,2)) val ^= BITS(5,0); + + val ^= BITS(4,3,1); + + if (BIT(param,2)) val ^= BITS(5,2,0); + if (BIT(param,1)) val ^= BITS(7,6); + if (BIT(param,0)) val ^= BITS(5,0); + + if (BIT(param,0)) val = bitswap<8>(val,7,6,5,1,4,3,2,0); + + return val; +} + + +u8 mc8123_device::decrypt_type1a(u8 val, u8 param, unsigned swap) +{ + if (swap == 0) val = bitswap<8>(val,4,2,6,5,3,7,1,0); + if (swap == 1) val = bitswap<8>(val,6,0,5,4,3,2,1,7); + if (swap == 2) val = bitswap<8>(val,2,3,6,1,4,0,7,5); + if (swap == 3) val = bitswap<8>(val,6,5,1,3,2,7,0,4); + + if (BIT(param,2)) val = bitswap<8>(val,7,6,1,5,3,2,4,0); + + if (BIT(val,1)) val ^= BITS(0); + if (BIT(val,6)) val ^= BITS(3); + if (BIT(val,7)) val ^= BITS(6,3); + if (BIT(val,2)) val ^= BITS(6,3,1); + if (BIT(val,4)) val ^= BITS(7,6,2); + + if (BIT(val,7) ^ BIT(val,2)) + val ^= BITS(4); + + val ^= BITS(6,3,1,0); + + if (BIT(param,3)) val ^= BITS(7,2); + if (BIT(param,1)) val ^= BITS(6,3); + + if (BIT(param,0)) val = bitswap<8>(val,7,6,1,4,3,2,5,0); + + return val; +} + +u8 mc8123_device::decrypt_type1b(u8 val, u8 param, unsigned swap) +{ + if (swap == 0) val = bitswap<8>(val,1,0,3,2,5,6,4,7); + if (swap == 1) val = bitswap<8>(val,2,0,5,1,7,4,6,3); + if (swap == 2) val = bitswap<8>(val,6,4,7,2,0,5,1,3); + if (swap == 3) val = bitswap<8>(val,7,1,3,6,0,2,5,4); + + if (BIT(val,2) && BIT(val,0)) + val ^= BITS(7,4); + + if (BIT(val,7)) val ^= BITS(2); + if (BIT(val,5)) val ^= BITS(7,2); + if (BIT(val,1)) val ^= BITS(5); + if (BIT(val,6)) val ^= BITS(1); + if (BIT(val,4)) val ^= BITS(6,5); + if (BIT(val,0)) val ^= BITS(6,2,1); + if (BIT(val,3)) val ^= BITS(7,6,2,1,0); + + val ^= BITS(6,4,0); + + if (BIT(param,3)) val ^= BITS(4,1); + if (BIT(param,2)) val ^= BITS(7,6,3,0); + if (BIT(param,1)) val ^= BITS(4,3); + if (BIT(param,0)) val ^= BITS(6,2,1,0); + + return val; +} + +u8 mc8123_device::decrypt_type2a(u8 val, u8 param, unsigned swap) +{ + if (swap == 0) val = bitswap<8>(val,0,1,4,3,5,6,2,7); + if (swap == 1) val = bitswap<8>(val,6,3,0,5,7,4,1,2); + if (swap == 2) val = bitswap<8>(val,1,6,4,5,0,3,7,2); + if (swap == 3) val = bitswap<8>(val,4,6,7,5,2,3,1,0); + + if (BIT(val,3) || (BIT(param,1) && BIT(val,2))) + val = bitswap<8>(val,6,0,7,4,3,2,1,5); + + if (BIT(val,5)) val ^= BITS(7); + if (BIT(val,6)) val ^= BITS(5); + if (BIT(val,0)) val ^= BITS(6); + if (BIT(val,4)) val ^= BITS(3,0); + if (BIT(val,1)) val ^= BITS(2); + + val ^= BITS(7,6,5,4,1); + + if (BIT(param,2)) val ^= BITS(4,3,2,1,0); + + if (BIT(param,3)) + { + if (BIT(param,0)) + val = bitswap<8>(val,7,6,5,3,4,1,2,0); + else + val = bitswap<8>(val,7,6,5,1,2,4,3,0); + } + else if (BIT(param,0)) + { + val = bitswap<8>(val,7,6,5,2,1,3,4,0); + } + + return val; +} + +u8 mc8123_device::decrypt_type2b(u8 val, u8 param, unsigned swap) +{ + // only 0x20 possible encryptions for this method - all others have 0x40 + // this happens because BIT(param,2) cancels the other three + + if (swap == 0) val = bitswap<8>(val,1,3,4,6,5,7,0,2); + if (swap == 1) val = bitswap<8>(val,0,1,5,4,7,3,2,6); + if (swap == 2) val = bitswap<8>(val,3,5,4,1,6,2,0,7); + if (swap == 3) val = bitswap<8>(val,5,2,3,0,4,7,6,1); + + if (BIT(val,7) && BIT(val,3)) + val ^= BITS(6,4,0); + + if (BIT(val,7)) val ^= BITS(2); + if (BIT(val,5)) val ^= BITS(7,3); + if (BIT(val,1)) val ^= BITS(5); + if (BIT(val,4)) val ^= BITS(7,5,3,1); + + if (BIT(val,7) && BIT(val,5)) + val ^= BITS(4,0); + + if (BIT(val,5) && BIT(val,1)) + val ^= BITS(4,0); + + if (BIT(val,6)) val ^= BITS(7,5); + if (BIT(val,3)) val ^= BITS(7,6,5,1); + if (BIT(val,2)) val ^= BITS(3,1); + + val ^= BITS(7,3,2,1); + + if (BIT(param,3)) val ^= BITS(6,3,1); + if (BIT(param,2)) val ^= BITS(7,6,5,3,2,1); // same as the other three combined + if (BIT(param,1)) val ^= BITS(7); + if (BIT(param,0)) val ^= BITS(5,2); + + return val; +} + +u8 mc8123_device::decrypt_type3a(u8 val, u8 param, unsigned swap) +{ + if (swap == 0) val = bitswap<8>(val,5,3,1,7,0,2,6,4); + if (swap == 1) val = bitswap<8>(val,3,1,2,5,4,7,0,6); + if (swap == 2) val = bitswap<8>(val,5,6,1,2,7,0,4,3); + if (swap == 3) val = bitswap<8>(val,5,6,7,0,4,2,1,3); + + if (BIT(val,2)) val ^= BITS(7,5,4); + if (BIT(val,3)) val ^= BITS(0); + + if (BIT(param,0)) val = bitswap<8>(val,7,2,5,4,3,1,0,6); + + if (BIT(val,1)) val ^= BITS(6,0); + if (BIT(val,3)) val ^= BITS(4,2,1); + + if (BIT(param,3)) val ^= BITS(4,3); + + if (BIT(val,3)) val = bitswap<8>(val,5,6,7,4,3,2,1,0); + + if (BIT(val,5)) val ^= BITS(2,1); + + val ^= BITS(6,5,4,3); + + if (BIT(param,2)) val ^= BITS(7); + if (BIT(param,1)) val ^= BITS(4); + if (BIT(param,0)) val ^= BITS(0); + + return val; +} + +u8 mc8123_device::decrypt_type3b(u8 val, u8 param, unsigned swap) +{ + if (swap == 0) val = bitswap<8>(val,3,7,5,4,0,6,2,1); + if (swap == 1) val = bitswap<8>(val,7,5,4,6,1,2,0,3); + if (swap == 2) val = bitswap<8>(val,7,4,3,0,5,1,6,2); + if (swap == 3) val = bitswap<8>(val,2,6,4,1,3,7,0,5); + + if (BIT(val,2)) val ^= BITS(7); + + if (BIT(val,7)) val = bitswap<8>(val,7,6,3,4,5,2,1,0); + + if (BIT(param,3)) val ^= BITS(7); + + if (BIT(val,4)) val ^= BITS(6); + if (BIT(val,1)) val ^= BITS(6,4,2); + + if (BIT(val,7) && BIT(val,6)) + val ^= BITS(1); + + if (BIT(val,7)) val ^= BITS(1); + + if (BIT(param,3)) val ^= BITS(7); + if (BIT(param,2)) val ^= BITS(0); + + if (BIT(param,3)) val = bitswap<8>(val,4,6,3,2,5,0,1,7); + + if (BIT(val,4)) val ^= BITS(1); + if (BIT(val,5)) val ^= BITS(4); + if (BIT(val,7)) val ^= BITS(2); + + val ^= BITS(5,3,2); + + if (BIT(param,1)) val ^= BITS(7); + if (BIT(param,0)) val ^= BITS(3); + + return val; +} + +u8 mc8123_device::decrypt_internal(u8 val, u8 key, bool opcode) +{ + unsigned type = 0; + unsigned swap = 0; + u8 param = 0; + + key ^= 0xff; + + // no encryption + if (key == 0x00) + return val; + + type ^= BIT(key,0) << 0; + type ^= BIT(key,2) << 0; + type ^= BIT(key,0) << 1; + type ^= BIT(key,1) << 1; + type ^= BIT(key,2) << 1; + type ^= BIT(key,4) << 1; + type ^= BIT(key,4) << 2; + type ^= BIT(key,5) << 2; + + swap ^= BIT(key,0) << 0; + swap ^= BIT(key,1) << 0; + swap ^= BIT(key,2) << 1; + swap ^= BIT(key,3) << 1; + + param ^= BIT(key,0) << 0; + param ^= BIT(key,0) << 1; + param ^= BIT(key,2) << 1; + param ^= BIT(key,3) << 1; + param ^= BIT(key,0) << 2; + param ^= BIT(key,1) << 2; + param ^= BIT(key,6) << 2; + param ^= BIT(key,1) << 3; + param ^= BIT(key,6) << 3; + param ^= BIT(key,7) << 3; + + if (!opcode) + { + param ^= BITS(0); + type ^= BITS(0); + } + + switch (type) + { + default: + case 0: return decrypt_type0(val, param, swap); + case 1: return decrypt_type0(val, param, swap); + case 2: return decrypt_type1a(val, param, swap); + case 3: return decrypt_type1b(val, param, swap); + case 4: return decrypt_type2a(val, param, swap); + case 5: return decrypt_type2b(val, param, swap); + case 6: return decrypt_type3a(val, param, swap); + case 7: return decrypt_type3b(val, param, swap); + } +} + + +u8 mc8123_device::decrypt(offs_t addr, u8 val, bool opcode) +{ + // pick the translation table from bits fd57 of the address + offs_t const tbl_num = bitswap<12>(addr,15,14,13,12,11,10,8,6,4,2,1,0); + + return decrypt_internal(val, m_key[tbl_num | (opcode ? 0x0000 : 0x1000)], opcode); +} + + +void mc8123_device::decode(u8 *rom, u8 *opcodes, unsigned length) +{ + for (unsigned i = 0; i < length; i++) + { + unsigned const adr = (i >= 0xc000) ? ((i & 0x3fff) | 0x8000) : i; + u8 const src = rom[i]; + + // decode the opcodes + opcodes[i] = decrypt(adr, src, true); + + // decode the data + rom[i] = decrypt(adr, src, false); + } +} diff --git a/src/devices/cpu/z80/mc8123.h b/src/devices/cpu/z80/mc8123.h new file mode 100644 index 00000000000..8fad72dbee7 --- /dev/null +++ b/src/devices/cpu/z80/mc8123.h @@ -0,0 +1,43 @@ +// license:BSD-3-Clause +// copyright-holders:Nicola Salmoria, David Widel +/*************************************************************************** + + NEC MC-8123 encryption emulation + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_MC8123_H +#define MAME_CPU_Z80_MC8123_H + +#pragma once + +#include "z80.h" + +class mc8123_device : public z80_device +{ +public: + // construction/destruction + mc8123_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + // this function assumes a fixed portion of ROM at 0000-7FFF, and + // an arbitrary amount of banks at 8000-BFFF. + void decode(u8 *rom, u8 *opcodes, unsigned length); + +private: + static u8 decrypt_type0(u8 val, u8 param, unsigned swap); + static u8 decrypt_type1a(u8 val, u8 param, unsigned swap); + static u8 decrypt_type1b(u8 val, u8 param, unsigned swap); + static u8 decrypt_type2a(u8 val, u8 param, unsigned swap); + static u8 decrypt_type2b(u8 val, u8 param, unsigned swap); + static u8 decrypt_type3a(u8 val, u8 param, unsigned swap); + static u8 decrypt_type3b(u8 val, u8 param, unsigned swap); + static u8 decrypt_internal(u8 val, u8 key, bool opcode); + + u8 decrypt(offs_t addr, u8 val, bool opcode); + + required_region_ptr<u8> m_key; +}; + +DECLARE_DEVICE_TYPE(MC8123, mc8123_device) + +#endif // MAME_CPU_Z80_MC8123_H diff --git a/src/devices/cpu/z80/nsc800.cpp b/src/devices/cpu/z80/nsc800.cpp new file mode 100644 index 00000000000..e2c0bfd0087 --- /dev/null +++ b/src/devices/cpu/z80/nsc800.cpp @@ -0,0 +1,87 @@ +// license:BSD-3-Clause +// copyright-holders:Juergen Buchmueller +/* + + National Semiconductor NSC800 + +*/ + +#include "emu.h" +#include "nsc800.h" + +#include "z80.inc" + +#define LOG_INT (1U << 1) // z80.lst + +//#define VERBOSE (LOG_INT) +#include "logmacro.h" + + +// device type definition +DEFINE_DEVICE_TYPE(NSC800, nsc800_device, "nsc800", "National Semiconductor NSC800") + +nsc800_device::nsc800_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : z80_device(mconfig, NSC800, tag, owner, clock) +{ +} + + +//------------------------------------------------- +// initialization +//------------------------------------------------- + +void nsc800_device::device_start() +{ + z80_device::device_start(); + + save_item(NAME(m_nsc800_irq_state)); +} + +void nsc800_device::device_reset() +{ + z80_device::device_reset(); + memset(m_nsc800_irq_state, 0, sizeof(m_nsc800_irq_state)); +} + + +//------------------------------------------------- +// execute +//------------------------------------------------- +void nsc800_device::execute_run() +{ + #include "cpu/z80/nsc800.hxx" +} + +void nsc800_device::execute_set_input(int inputnum, int state) +{ + bool update_irq_attention = false; + switch (inputnum) + { + case NSC800_RSTA: + update_irq_attention = true; + m_nsc800_irq_state[0] = state; + break; + + case NSC800_RSTB: + update_irq_attention = true; + m_nsc800_irq_state[1] = state; + break; + + case NSC800_RSTC: + update_irq_attention = true; + m_nsc800_irq_state[2] = state; + break; + + default: + z80_device::execute_set_input(inputnum, state); + break; + } + + if (update_irq_attention) + { + if (m_nsc800_irq_state[0] != CLEAR_LINE || m_nsc800_irq_state[1] != CLEAR_LINE || m_nsc800_irq_state[2] != CLEAR_LINE) + set_service_attention<SA_NSC800_IRQ_ON, 1>(); + else + set_service_attention<SA_NSC800_IRQ_ON, 0>(); + } +} diff --git a/src/devices/cpu/z80/nsc800.h b/src/devices/cpu/z80/nsc800.h new file mode 100644 index 00000000000..aa05d2adf51 --- /dev/null +++ b/src/devices/cpu/z80/nsc800.h @@ -0,0 +1,38 @@ +// license:BSD-3-Clause +// copyright-holders:Juergen Buchmueller +#ifndef MAME_CPU_Z80_NSC800_H +#define MAME_CPU_Z80_NSC800_H + +#pragma once + +#include "z80.h" + +enum +{ + NSC800_RSTA = Z80_INPUT_LINE_MAX, + NSC800_RSTB, + NSC800_RSTC +}; + + +class nsc800_device : public z80_device +{ +public: + nsc800_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + +protected: + // device_t implementation + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + + // device_execute_interface implementation + virtual void execute_run() override; + virtual void execute_set_input(int inputnum, int state) override; + + u8 m_nsc800_irq_state[3]; // state of NSC800 restart interrupts A, B, C +}; + +DECLARE_DEVICE_TYPE(NSC800, nsc800_device) + + +#endif // MAME_CPU_Z80_NSC800_H diff --git a/src/devices/cpu/z80/r800.cpp b/src/devices/cpu/z80/r800.cpp new file mode 100644 index 00000000000..648735462e6 --- /dev/null +++ b/src/devices/cpu/z80/r800.cpp @@ -0,0 +1,103 @@ +// license:BSD-3-Clause +// copyright-holders:AJR,Wilbert Pol +/*************************************************************************** + + ASCII R800 CPU + +TODO: +- Internal configuration registers. +- External 24 bits address bus accessible through 9 memory mappers. +- DMA channels. +- Interrupt levels. +- Bits 3 and 5 of the flag register behave differently from the z80. +- Page break penalties. +- Refresh delays. + +***************************************************************************/ + +#include "emu.h" +#include "r800.h" +#include "r800dasm.h" + +#include "z80.inc" + +#define LOG_INT (1U << 1) // z80.lst + +//#define VERBOSE (LOG_INT) +#include "logmacro.h" + + +//************************************************************************** +// GLOBAL VARIABLES +//************************************************************************** + +// device type definition +DEFINE_DEVICE_TYPE(R800, r800_device, "r800", "ASCII R800") + + +//************************************************************************** +// DEVICE IMPLEMENTATION +//************************************************************************** + +//------------------------------------------------- +// r800_device - constructor +//------------------------------------------------- + +r800_device::r800_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : z80_device(mconfig, R800, tag, owner, clock) +{ + z80_set_m1_cycles(1); + z80_set_memrq_cycles(1); + z80_set_iorq_cycles(1); +} + +std::unique_ptr<util::disasm_interface> r800_device::create_disassembler() +{ + return std::make_unique<r800_disassembler>(); +} + +void r800_device::device_validity_check(validity_checker &valid) const +{ + cpu_device::device_validity_check(valid); +} + + +/*************************************************************** + * adjust cycle count by n T-states + ***************************************************************/ +#define T(icount) { m_icount -= icount; } + +/*************************************************************** + * SLL r8 + ***************************************************************/ +u8 r800_device::r800_sll(u8 value) +{ + const u8 c = (value & 0x80) ? CF : 0; + const u8 res = u8(value << 1); + set_f(SZP[res] | c); + return res; +} + +void r800_device::mulub(u8 value) +{ + const u16 res = A * value; + HL = res; + const u8 c = (H) ? CF : 0; + const u8 z = (res) ? 0 : ZF; + set_f((F & (HF|NF)) | z | c); +} + +void r800_device::muluw(u16 value) +{ + const u32 res = HL * value; + DE = res >> 16; + HL = res & 0xffff; + const u8 c = (DE) ? CF : 0; + const u8 z = (res) ? 0 : ZF; + set_f((F & (HF|NF)) | z | c); +} + +void r800_device::execute_run() +{ + #include "cpu/z80/r800.hxx" +} diff --git a/src/devices/cpu/z80/r800.h b/src/devices/cpu/z80/r800.h new file mode 100644 index 00000000000..967ed29417d --- /dev/null +++ b/src/devices/cpu/z80/r800.h @@ -0,0 +1,49 @@ +// license:BSD-3-Clause +// copyright-holders:AJR,Wilbert Pol +/*************************************************************************** + + ASCII R800 CPU + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_R800_H +#define MAME_CPU_Z80_R800_H + +#pragma once + +#include "z80.h" + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +class r800_device : public z80_device +{ +public: + // device type constructor + r800_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + static constexpr feature_type imperfect_features() { return feature::TIMING; } + +protected: + // device_t implementation + virtual void device_validity_check(validity_checker &valid) const override; + + // device_execute_interface overrides + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 4 - 1) / 4; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 4); } + virtual void execute_run() override; + + // device_disasm_interface implementation + virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; + + u8 r800_sll(u8 value); + void mulub(u8 value); + void muluw(u16 value); +}; + +// device type declaration +DECLARE_DEVICE_TYPE(R800, r800_device) + +#endif // MAME_CPU_Z80_R800_H diff --git a/src/devices/cpu/z80/r800dasm.cpp b/src/devices/cpu/z80/r800dasm.cpp new file mode 100644 index 00000000000..462feb07dad --- /dev/null +++ b/src/devices/cpu/z80/r800dasm.cpp @@ -0,0 +1,607 @@ +// license:BSD-3-Clause +// copyright-holders:Wilbert Pol +/***************************************************************************** + * + * r800dasm.cpp + * Disassembler for ASCII R800 based on portable Z80 disassembler. + * + *****************************************************************************/ + +#include "emu.h" +#include "r800dasm.h" + +enum r800_disassembler::e_mnemonics : unsigned +{ + zADD ,zADDC ,zADJ ,zAND ,zBC ,zBIT ,zBM ,zBNC , + zBNZ ,zBP ,zBPE ,zBPO ,zBR ,zBRK ,zBZ ,zCALL , + zCLR ,zCMP ,zCMPM ,zDB ,zDBNZ ,zDEC ,zDI ,zEI , + zHALT ,zIM ,zIN ,zINC ,zINM ,zLD ,zMOVE ,zMOVEM, + zMULUB,zMULUW,zNEG ,zNOP ,zNOT ,zNOTC ,zOR ,zOUT , + zOUTM ,zPOP ,zPUSH ,zRET ,zRETI ,zRETN ,zROL ,zROL4 , + zROLA ,zROLC ,zROLCA,zROR ,zROR4 ,zRORA ,zRORC ,zRORCA, + zSET ,zSETC ,zSHL ,zSHORT,zSHR ,zSHRA ,zSLA ,zSUB , + zSUBC ,zXCH ,zXCHX ,zXOR +}; + +struct r800_disassembler::r800dasm +{ + e_mnemonics mnemonic; + const char *arguments; +}; + +static const char *const s_mnemonic[] = +{ + "add" ,"addc" ,"adj" ,"and" ,"bc" ,"bit" ,"bm" ,"bnc" , + "bnz" ,"bp" ,"bpe" ,"bpo" ,"br" ,"brk" ,"bz" ,"call" , + "clr" ,"cmp" ,"cmpm" ,"db" ,"dbnz" ,"dec" ,"di" ,"ei" , + "halt" ,"im" ,"in" ,"inc" ,"inm" ,"ld" ,"move" ,"movem", + "mulub","muluw","neg" ,"nop" ,"not" ,"notc" ,"or" ,"out" , + "outm" ,"pop" ,"push" ,"ret" ,"reti" ,"retn" ,"rol" ,"rol4" , + "rola" ,"rolc" ,"rolca","ror" ,"ror4" ,"rora" ,"rorc" ,"rorca", + "set" ,"setc" ,"shl" ,"short","shr" ,"shra" ,"sla" ,"sub" , + "subc" ,"xch" ,"xchx" ,"xor" +}; + +const u32 r800_disassembler::s_flags[] = +{ + 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,STEP_OVER,0 ,STEP_OVER, + 0 ,0 ,STEP_COND,0 ,STEP_COND,0 ,0 ,0 , + STEP_OVER,0 ,0 ,0 ,STEP_COND,0 ,0 ,STEP_COND, + 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + STEP_COND,0 ,0 ,STEP_OUT ,STEP_OUT ,STEP_OUT ,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + 0 ,0 ,0 ,0 +}; + +const r800_disassembler::r800dasm r800_disassembler::mnemonic_xx_cb[256] = +{ + // 00 - 0F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zROLC,"Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zRORC,"Y"}, {zDB,"?"}, + // 10 - 1F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zROL,"Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zROR,"Y"}, {zDB,"?"}, + // 20 - 2F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSLA,"Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSHRA,"Y"}, {zDB,"?"}, + // 30 - 3F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSHL,"Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSHR,"Y"}, {zDB,"?"}, + // 40 - 4F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"0,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"1,Y"}, {zDB,"?"}, + // 50 - 5F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"2,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"3,Y"}, {zDB,"?"}, + // 60 - 6F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"4,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"5,Y"}, {zDB,"?"}, + // 70 - 6F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"6,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zBIT,"7,Y"}, {zDB,"?"}, + // 80 - 8F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"0,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"1,Y"}, {zDB,"?"}, + // 90 - 9F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"2,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"3,Y"}, {zDB,"?"}, + // A0 - AF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"4,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"5,Y"}, {zDB,"?"}, + // B0 - BF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"6,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zCLR,"7,Y"}, {zDB,"?"}, + // C0 - CF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"0,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"1,Y"}, {zDB,"?"}, + // D0 - DF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"2,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"3,Y"}, {zDB,"?"}, + // E0 - EF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"4,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"5,Y"}, {zDB,"?"}, + // F0 - FF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"6,Y"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zSET,"7,Y"}, {zDB,"?"} +}; + +const r800_disassembler::r800dasm r800_disassembler::mnemonic_cb[256] = +{ + // 00 - 1F + {zROLC,".b"}, {zROLC,".c"}, {zROLC,".d"}, {zROLC,".e"}, + {zROLC,".h"}, {zROLC,".l"}, {zROLC,"[.hl]"}, {zROLC,".a"}, + {zRORC,".b"}, {zRORC,".c"}, {zRORC,".d"}, {zRORC,".e"}, + {zRORC,".h"}, {zRORC,".l"}, {zRORC,"[.hl]"}, {zRORC,".a"}, + // 10 - 1F + {zROL,".b"}, {zROL,".c"}, {zROL,".d"}, {zROL,".e"}, + {zROL,".h"}, {zROL,".l"}, {zROL,"[.hl]"}, {zROL,".a"}, + {zROR,".b"}, {zROR,".c"}, {zROR,".d"}, {zROR,".e"}, + {zROR,".h"}, {zROR,".l"}, {zROR,"[.hl]"}, {zROR,".a"}, + // 20 - 2F + {zSHL,".b"}, {zSHL,".c"}, {zSHL,".d"}, {zSHL,".e"}, + {zSHL,".h"}, {zSHL,".l"}, {zSHL,"[.hl]"}, {zSHL,".a"}, + {zSHRA,".b"}, {zSHRA,".c"}, {zSHRA,".d"}, {zSHRA,".e"}, + {zSHRA,".h"}, {zSHRA,".l"}, {zSHRA,"[.hl]"}, {zSHRA,".a"}, + // 30 - 3F + {zSHL,".b"}, {zSHL,".c"}, {zSHL,".d"}, {zSHL,".e"}, + {zSHL,".h"}, {zSHL,".l"}, {zSHL,"[.hl]"}, {zSHL,".a"}, + {zSHR,".b"}, {zSHR,".c"}, {zSHR,".d"}, {zSHR,".e"}, + {zSHR,".h"}, {zSHR,".l"}, {zSHR,"[.hl]"}, {zSHR,".a"}, + // 40 - 4F + {zBIT,"0,.b"}, {zBIT,"0,.c"}, {zBIT,"0,.d"}, {zBIT,"0,.e"}, + {zBIT,"0,.h"}, {zBIT,"0,.l"}, {zBIT,"0,[.hl]"}, {zBIT,"0,.a"}, + {zBIT,"1,.b"}, {zBIT,"1,.c"}, {zBIT,"1,.d"}, {zBIT,"1,.e"}, + {zBIT,"1,.h"}, {zBIT,"1,.l"}, {zBIT,"1,[.hl]"}, {zBIT,"1,.a"}, + // 50 - 5F + {zBIT,"2,.b"}, {zBIT,"2,.c"}, {zBIT,"2,.d"}, {zBIT,"2,.e"}, + {zBIT,"2,.h"}, {zBIT,"2,.l"}, {zBIT,"2,[.hl]"}, {zBIT,"2,.a"}, + {zBIT,"3,.b"}, {zBIT,"3,.c"}, {zBIT,"3,.d"}, {zBIT,"3,.e"}, + {zBIT,"3,.h"}, {zBIT,"3,.l"}, {zBIT,"3,[.hl]"}, {zBIT,"3,.a"}, + // 60 - 6F + {zBIT,"4,.b"}, {zBIT,"4,.c"}, {zBIT,"4,.d"}, {zBIT,"4,.e"}, + {zBIT,"4,.h"}, {zBIT,"4,.l"}, {zBIT,"4,[.hl]"}, {zBIT,"4,.a"}, + {zBIT,"5,.b"}, {zBIT,"5,.c"}, {zBIT,"5,.d"}, {zBIT,"5,.e"}, + {zBIT,"5,.h"}, {zBIT,"5,.l"}, {zBIT,"5,[.hl]"}, {zBIT,"5,.a"}, + // 70 - 7F + {zBIT,"6,.b"}, {zBIT,"6,.c"}, {zBIT,"6,.d"}, {zBIT,"6,.e"}, + {zBIT,"6,.h"}, {zBIT,"6,.l"}, {zBIT,"6,[.hl]"}, {zBIT,"6,.a"}, + {zBIT,"7,.b"}, {zBIT,"7,.c"}, {zBIT,"7,.d"}, {zBIT,"7,.e"}, + {zBIT,"7,.h"}, {zBIT,"7,.l"}, {zBIT,"7,[.hl]"}, {zBIT,"7,.a"}, + // 80 - 8F + {zCLR,"0,.b"}, {zCLR,"0,.c"}, {zCLR,"0,.d"}, {zCLR,"0,.e"}, + {zCLR,"0,.h"}, {zCLR,"0,.l"}, {zCLR,"0,[.hl]"}, {zCLR,"0,.a"}, + {zCLR,"1,.b"}, {zCLR,"1,.c"}, {zCLR,"1,.d"}, {zCLR,"1,.e"}, + {zCLR,"1,.h"}, {zCLR,"1,.l"}, {zCLR,"1,[.hl]"}, {zCLR,"1,.a"}, + // 90 - 9F + {zCLR,"2,.b"}, {zCLR,"2,.c"}, {zCLR,"2,.d"}, {zCLR,"2,.e"}, + {zCLR,"2,.h"}, {zCLR,"2,.l"}, {zCLR,"2,[.hl]"}, {zCLR,"2,.a"}, + {zCLR,"3,.b"}, {zCLR,"3,.c"}, {zCLR,"3,.d"}, {zCLR,"3,.e"}, + {zCLR,"3,.h"}, {zCLR,"3,.l"}, {zCLR,"3,[.hl]"}, {zCLR,"3,.a"}, + // A0 - AF + {zCLR,"4,.b"}, {zCLR,"4,.c"}, {zCLR,"4,.d"}, {zCLR,"4,.e"}, + {zCLR,"4,.h"}, {zCLR,"4,.l"}, {zCLR,"4,[.hl]"}, {zCLR,"4,.a"}, + {zCLR,"5,.b"}, {zCLR,"5,.c"}, {zCLR,"5,.d"}, {zCLR,"5,.e"}, + {zCLR,"5,.h"}, {zCLR,"5,.l"}, {zCLR,"5,[.hl]"}, {zCLR,"5,.a"}, + // B0 - BF + {zCLR,"6,.b"}, {zCLR,"6,.c"}, {zCLR,"6,.d"}, {zCLR,"6,.e"}, + {zCLR,"6,.h"}, {zCLR,"6,.l"}, {zCLR,"6,[.hl]"}, {zCLR,"6,.a"}, + {zCLR,"7,.b"}, {zCLR,"7,.c"}, {zCLR,"7,.d"}, {zCLR,"7,.e"}, + {zCLR,"7,.h"}, {zCLR,"7,.l"}, {zCLR,"7,[.hl]"}, {zCLR,"7,.a"}, + // C0 - CF + {zSET,"0,.b"}, {zSET,"0,.c"}, {zSET,"0,.d"}, {zSET,"0,.e"}, + {zSET,"0,.h"}, {zSET,"0,.l"}, {zSET,"0,[.hl]"}, {zSET,"0,.a"}, + {zSET,"1,.b"}, {zSET,"1,.c"}, {zSET,"1,.d"}, {zSET,"1,.e"}, + {zSET,"1,.h"}, {zSET,"1,.l"}, {zSET,"1,[.hl]"}, {zSET,"1,.a"}, + // D0 - DF + {zSET,"2,.b"}, {zSET,"2,.c"}, {zSET,"2,.d"}, {zSET,"2,.e"}, + {zSET,"2,.h"}, {zSET,"2,.l"}, {zSET,"2,[.hl]"}, {zSET,"2,.a"}, + {zSET,"3,.b"}, {zSET,"3,.c"}, {zSET,"3,.d"}, {zSET,"3,.e"}, + {zSET,"3,.h"}, {zSET,"3,.l"}, {zSET,"3,[.hl]"}, {zSET,"3,.a"}, + // E0 - EF + {zSET,"4,.b"}, {zSET,"4,.c"}, {zSET,"4,.d"}, {zSET,"4,.e"}, + {zSET,"4,.h"}, {zSET,"4,.l"}, {zSET,"4,[.hl]"}, {zSET,"4,.a"}, + {zSET,"5,.b"}, {zSET,"5,.c"}, {zSET,"5,.d"}, {zSET,"5,.e"}, + {zSET,"5,.h"}, {zSET,"5,.l"}, {zSET,"5,[.hl]"}, {zSET,"5,.a"}, + // F0 - FF + {zSET,"6,.b"}, {zSET,"6,.c"}, {zSET,"6,.d"}, {zSET,"6,.e"}, + {zSET,"6,.h"}, {zSET,"6,.l"}, {zSET,"6,[.hl]"}, {zSET,"6,.a"}, + {zSET,"7,.b"}, {zSET,"7,.c"}, {zSET,"7,.d"}, {zSET,"7,.e"}, + {zSET,"7,.h"}, {zSET,"7,.l"}, {zSET,"7,[.hl]"}, {zSET,"7,.a"} +}; + +const r800_disassembler::r800dasm r800_disassembler::mnemonic_ed[256] = +{ + // 00 - 0F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 10 - 1F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 20 - 2F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 30 - 3F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 40 - 4F + {zIN,".b,[.c]"}, {zOUT,"[.c],.b"}, {zSUBC,".hl,.bc"}, {zLD,"(W),.bc"}, + {zNEG,".a"}, {zRETN,nullptr}, {zIM,"0"}, {zLD,".i,.a"}, + {zIN,".c,[.c]"}, {zOUT,"[.c],.c"}, {zADDC,".hl,.bc"}, {zLD,".bc,(W)"}, + {zDB,"?"}, {zRETI,nullptr}, {zDB,"?"}, {zLD,".r,.a"}, + // 50 - 5F + {zIN,".d,[.c]"}, {zOUT,"[.c],.d"}, {zSUBC,".hl,.de"}, {zLD,"(W),.de"}, + {zDB,"?"}, {zDB,"?"}, {zIM,"1"}, {zLD,".a,.i"}, + {zIN,".e,[.c]"}, {zOUT,"[.c],.e"}, {zADDC,".hl,.de"}, {zLD,".de,(W)"}, + {zDB,"?"}, {zDB,"?"}, {zIM,"2"}, {zLD,".a,.r"}, + // 60 - 6F + {zIN,".h,[.c]"}, {zOUT,"[.c],.h"}, {zSUBC,".hl,.hl"}, {zLD,"(W),.hl"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zROR4,"[.hl]"}, + {zIN,".l,[.c]"}, {zOUT,"[.c],.l"}, {zADDC,".hl,.hl"}, {zLD,".hl,(W)"}, + {zDB,"?"}, {zRETI,nullptr}, {zIM,"0"}, {zROL4,"[.hl]"}, + // 70 - 7F + {zIN,".f,[.c]"}, {zDB,"?"}, {zSUBC,".hl,.sp"}, {zLD,"(W),.sp"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zIN,".a,[.c]"}, {zOUT,"[.c],.a"}, {zADDC,".hl,.sp"}, {zLD,".sp,(W)"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 80 - 8F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 90 - 9F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // A0 - AF + {zMOVE,"[.hl++],[.de++]"}, {zCMP,".a,[.hl++]"}, {zIN,"[.c],[.hl++]"}, {zOUT,"[.c],[.hl++]"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zMOVE,"[.hl--],[.de--]"}, {zCMP,".a,[.hl--]"}, {zIN,"[.c],[.hl--]"}, {zOUT,"[.c],[.hl--]"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // B0 - BF + {zMOVEM,"[.hl++],[.de++]"}, {zCMPM,".a,[.hl++]"}, {zINM,"[.c],[.hl++]"}, {zOUTM,"[.c],[.hl++]"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zMOVEM,"[.hl--],[.de--]"}, {zCMPM,".a,[.hl--]"}, {zINM,"[.c],[.hl--]"}, {zOUTM,"[.c],[.hl--]"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // C0 - CF + {zDB,"?"}, {zMULUB,".a,.b"}, {zDB,"?"}, {zMULUW,".hl,.bc"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zMULUB,".a,.c"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // D0 - DF + {zDB,"?"}, {zMULUB,".a,.d"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zMULUB,".a,.e"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // E0 - EF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // F0 - FF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zMULUW,".hl,.sp"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"} +}; + +const r800_disassembler::r800dasm r800_disassembler::mnemonic_xx[256] = +{ + // 00 - 0F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zADD,".I,.bc"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 10 - 1F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zADD,".I,.de"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 20 - 2F + {zDB,"?"}, {zLD,".I,N"}, {zLD,"(W),.I"}, {zINC,".I"}, + {zINC,".Ih"}, {zDEC,".Ih"}, {zLD,".Ih,B"}, {zDB,"?"}, + {zDB,"?"}, {zADD,".I,.I"}, {zLD,".I,(W)"}, {zDEC,".I"}, + {zINC,".Il"}, {zDEC,".Il"}, {zLD,".Il,B"}, {zDB,"?"}, + // 30 - 3F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zINC,"X"}, {zDEC,"X"}, {zLD,"X,B"}, {zDB,"?"}, + {zDB,"?"}, {zADD,".I,.sp"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // 40 - 4F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLD,".b,.Ih"}, {zLD,".b,.Il"}, {zLD,".b,X"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLD,".c,.Ih"}, {zLD,".c,.Il"}, {zLD,".c,X"}, {zDB,"?"}, + // 50 - 5F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLD,".d,.Ih"}, {zLD,".d,.Il"}, {zLD,".d,X"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLD,".e,.Ih"}, {zLD,".e,.Il"}, {zLD,".e,X"}, {zDB,"?"}, + // 60 - 6F + {zLD,".Ih,.b"}, {zLD,".Ih,.c"}, {zLD,".Ih,.d"}, {zLD,".Ih,.e"}, + {zLD,".Ih,.Ih"}, {zLD,".Ih,.Il"}, {zLD,".h,X"}, {zLD,".Ih,.a"}, + {zLD,".Il,.b"}, {zLD,".Il,.c"}, {zLD,".Il,.d"}, {zLD,".Il,.e"}, + {zLD,".Il,.Ih"}, {zLD,".Il,.Il"}, {zLD,".l,X"}, {zLD,".Il,.a"}, + // 70 - 7F + {zLD,"X,.b"}, {zLD,"X,.c"}, {zLD,"X,.d"}, {zLD,"X,.e"}, + {zLD,"X,.h"}, {zLD,"X,.l"}, {zDB,"?"}, {zLD,"X,.a"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLD,".a,.Ih"}, {zLD,".a,Il"}, {zLD,".a,X"}, {zDB,"?"}, + // 80 - 8F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zADD,".a,.Ih"}, {zADD,".a,.Il"}, {zADD,".a,X"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zADDC,".a,.Ih"}, {zADDC,".a,.Il"}, {zADDC,".a,X"}, {zDB,"?"}, + // 90 - 9F + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zSUB,".a,.Ih"}, {zSUB,".a,.Il"}, {zSUB,".a,X"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zSUBC,".a,.Ih"}, {zSUBC,".a,.Il"}, {zSUBC,".a,X"}, {zDB,"?"}, + // A0 - AF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zAND,".a,.Ih"}, {zAND,".a,.Il"}, {zAND,".a,X"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zXOR,".a,.Ih"}, {zXOR,".a,.Il"}, {zXOR,".a,X"}, {zDB,"?"}, + // B0 - BF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zOR,".a,.Ih"}, {zOR,".a,.Il"}, {zOR,".a,X"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zCMP,".a,.Ih"}, {zCMP,".a,.Il"}, {zCMP,".a,X"}, {zDB,"?"}, + // C0 - CF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"cb"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // D0 - DF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // E0 - EF + {zDB,"?"}, {zPOP,".I"}, {zDB,"?"}, {zXCH,"[.sp],.I"}, + {zDB,"?"}, {zPUSH,".I"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zBR,"[.I]"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + // F0 - FF + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zLD,".sp,I"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"} +}; + +const r800_disassembler::r800dasm r800_disassembler::mnemonic_main[256] = +{ + // 00 - 0F + {zNOP,nullptr}, {zLD,".bc,N"}, {zLD,"[.bc],.a"}, {zINC,".bc"}, + {zINC,".b"}, {zDEC,".b"}, {zLD,".b,B"}, {zROLCA,nullptr}, + {zXCH,".af,.af'"}, {zADD,".hl,.bc"}, {zLD,".a,[.bc]"}, {zDEC,".bc"}, + {zINC,".c"}, {zDEC,".c"}, {zLD,".c,B"}, {zRORCA,nullptr}, + // 10 - 1F + {zDBNZ,"O"}, {zLD,".de,N"}, {zLD,"[.de],.a"}, {zINC,".de"}, + {zINC,".d"}, {zDEC,".d"}, {zLD,".d,B"}, {zROLA,nullptr}, + {zSHORT,"br O"}, {zADD,".hl,.de"}, {zLD,".a,[.de]"}, {zDEC,".de"}, + {zINC,".e"}, {zDEC,".e"}, {zLD,".e,B"}, {zRORA,nullptr}, + // 20 - 2F + {zSHORT,"bnz O"}, {zLD,".hl,N"}, {zLD,"(W),.hl"}, {zINC,".hl"}, + {zINC,".h"}, {zDEC,".h"}, {zLD,".h,B"}, {zADJ,".a"}, + {zSHORT,"bz O"}, {zADD,".hl,.hl"}, {zLD,".hl,(W)"}, {zDEC,".hl"}, + {zINC,".l"}, {zDEC,".l"}, {zLD,".l,B"}, {zNOT,".a"}, + // 30 - 3F + {zSHORT,"bnc O"}, {zLD,".sp,N"}, {zLD,"(W),.a"}, {zINC,".sp"}, + {zINC,"[.hl]"}, {zDEC,"[.hl]"}, {zLD,"[.hl],B"}, {zSETC,nullptr}, + {zSHORT,"bc O"}, {zADD,".hl,.sp"}, {zLD,".a,(W)"}, {zDEC,".sp"}, + {zINC,".a"}, {zDEC,".a"}, {zLD,".a,B"}, {zNOTC,nullptr}, + // 40 - 4F + {zLD,".b,.b"}, {zLD,".b,.c"}, {zLD,".b,.d"}, {zLD,".b,.e"}, + {zLD,".b,.h"}, {zLD,".b,.l"}, {zLD,".b,[.hl]"}, {zLD,".b,.a"}, + {zLD,".c,.b"}, {zLD,".c,.c"}, {zLD,".c,.d"}, {zLD,".c,.e"}, + {zLD,".c,.h"}, {zLD,".c,.l"}, {zLD,".c,[.hl]"}, {zLD,".c,.a"}, + // 50 - 5F + {zLD,".d,.b"}, {zLD,".d,.c"}, {zLD,".d,.d"}, {zLD,".d,.e"}, + {zLD,".d,.h"}, {zLD,".d,.l"}, {zLD,".d,[.hl]"}, {zLD,".d,.a"}, + {zLD,".e,.b"}, {zLD,".e,.c"}, {zLD,".e,.d"}, {zLD,".e,.e"}, + {zLD,".e,.h"}, {zLD,".e,.l"}, {zLD,".e,[.hl]"}, {zLD,".e,.a"}, + // 60 - 6F + {zLD,".h,.b"}, {zLD,".h,.c"}, {zLD,".h,.d"}, {zLD,".h,.e"}, + {zLD,".h,.h"}, {zLD,".h,.l"}, {zLD,".h,[.hl]"}, {zLD,".h,.a"}, + {zLD,".l,.b"}, {zLD,".l,.c"}, {zLD,".l,.d"}, {zLD,".l,.e"}, + {zLD,".l,.h"}, {zLD,".l,.l"}, {zLD,".l,[.hl]"}, {zLD,".l,.a"}, + // 70 - 7F + {zLD,"[.hl],.b"}, {zLD,"[.hl],.c"}, {zLD,"[.hl],.d"}, {zLD,"[.hl],.e"}, + {zLD,"[.hl],.h"}, {zLD,"[.hl],.l"}, {zHALT,nullptr}, {zLD,"[.hl],.a"}, + {zLD,".a,.b"}, {zLD,".a,.c"}, {zLD,".a,.d"}, {zLD,".a,.e"}, + {zLD,".a,.h"}, {zLD,".a,.l"}, {zLD,".a,[.hl]"}, {zLD,".a,.a"}, + // 80 - BF + {zADD,".a,.b"}, {zADD,".a,.c"}, {zADD,".a,.d"}, {zADD,".a,.e"}, + {zADD,".a,.h"}, {zADD,".a,.l"}, {zADD,".a,[.hl]"}, {zADD,".a,.a"}, + {zADDC,".a,.b"}, {zADDC,".a,.c"}, {zADDC,".a,.d"}, {zADDC,".a,.e"}, + {zADDC,".a,.h"}, {zADDC,".a,.l"}, {zADDC,".a,[.hl]"}, {zADDC,".a,.a"}, + // 90 - 9F + {zSUB,".a,.b"}, {zSUB,".a,.c"}, {zSUB,".a,.d"}, {zSUB,".a,.e"}, + {zSUB,".a,.h"}, {zSUB,".a,.l"}, {zSUB,".a,[.hl]"}, {zSUB,".a,.a"}, + {zSUBC,".a,.b"}, {zSUBC,".a,.c"}, {zSUBC,".a,.d"}, {zSUBC,".a,.e"}, + {zSUBC,".a,.h"}, {zSUBC,".a,.l"}, {zSUBC,".a,[.hl]"}, {zSUBC,".a,.a"}, + // A0 - AF + {zAND,".a,.b"}, {zAND,".a,.c"}, {zAND,".a,.d"}, {zAND,".a,.e"}, + {zAND,".a,.h"}, {zAND,".a,.l"}, {zAND,".a,[.hl]"}, {zAND,".a,.a"}, + {zXOR,".a,.b"}, {zXOR,".a,.c"}, {zXOR,".a,.d"}, {zXOR,".a,.e"}, + {zXOR,".a,.h"}, {zXOR,".a,.l"}, {zXOR,".a,[.hl]"}, {zXOR,".a,.a"}, + // B0 - BF + {zOR,".a,.b"}, {zOR,".a,.c"}, {zOR,".a,.d"}, {zOR,".a,.e"}, + {zOR,".a,.h"}, {zOR,".a,.l"}, {zOR,".a,[.hl]"}, {zOR,".a,.a"}, + {zCMP,".a,.b"}, {zCMP,".a,.c"}, {zCMP,".d"}, {zCMP,".a,.e"}, + {zCMP,".a,.h"}, {zCMP,".a,.l"}, {zCMP,".a,[.hl]"}, {zCMP,".a,.a"}, + // C0 - CF + {zRET,"nz"}, {zPOP,".bc"}, {zBNZ,"A"}, {zBP,"A"}, + {zCALL,"nz,A"}, {zPUSH,".bc"}, {zADD,".a,B"}, {zBRK,"V"}, + {zRET,"z"}, {zRET,nullptr}, {zBZ,"A"}, {zDB,"cb"}, + {zCALL,"z,A"}, {zCALL,"A"}, {zADDC,".a,B"}, {zBRK,"V"}, + // D0 - DF + {zRET,"nc"}, {zPOP,".de"}, {zBNC,"A"}, {zOUT,"[P],[.a]"}, + {zCALL,"nc,A"}, {zPUSH,".de"}, {zSUB,".a,B"}, {zBRK,"V"}, + {zRET,"c"}, {zXCHX,nullptr}, {zBC,"A"}, {zIN,".a,[P]"}, + {zCALL,"c,A"}, {zDB,"dd"}, {zSUBC,".a,B"}, {zBRK,"V"}, + // E0 - EF + {zRET,"po"}, {zPOP,".hl"}, {zBPO,"A"}, {zXCH,"[.sp],.hl"}, + {zCALL,"po,A"}, {zPUSH,".hl"}, {zAND,".a,B"}, {zBRK,"V"}, + {zRET,"pe"}, {zBR,"[.hl]"}, {zBPE,"A"}, {zXCH,".de,.hl"}, + {zCALL,"pe,A"}, {zDB,"ed"}, {zXOR,".a,B"}, {zBRK,"V"}, + // F0 - FF + {zRET,"p"}, {zPOP,".af"}, {zBP,"A"}, {zDI,nullptr}, + {zCALL,"p,A"}, {zPUSH,".af"}, {zOR,".a,B"}, {zBRK,"V"}, + {zRET,"m"}, {zLD,".sp,.hl"}, {zBM,"A"}, {zEI,nullptr}, + {zCALL,"m,A"}, {zDB,"fd"}, {zCMP,".a,B"}, {zBRK,"V"} +}; + +char r800_disassembler::sign(s8 offset) +{ + return (offset < 0) ? '-' : '+'; +} + +u32 r800_disassembler::offs(s8 offset) +{ + if (offset < 0) + return -offset; + return offset; +} + +r800_disassembler::r800_disassembler() +{ +} + +u32 r800_disassembler::opcode_alignment() const +{ + return 1; +} + +offs_t r800_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) +{ + s8 offset = 0; + + offs_t pos = pc; + std::string ixy = "oops!!"; + + const r800dasm *d = nullptr; + u8 op = opcodes.r8(pos++); + switch (op) + { + case 0xcb: + op = opcodes.r8(pos++); + d = &mnemonic_cb[op]; + break; + case 0xed: + d = &mnemonic_ed[opcodes.r8(pos++)]; + if (d->mnemonic == zDB) + pos--; + break; + case 0xdd: + case 0xfd: + { + ixy = (op == 0xdd) ? "ix" : "iy"; + u8 op1 = opcodes.r8(pos++); + if (op1 == 0xcb) + { + offset = params.r8(pos++); + op1 = params.r8(pos++); + d = &mnemonic_xx_cb[op1]; + } + else + { + d = &mnemonic_xx[op1]; + if (d->mnemonic == zDB) + pos--; + } + break; + } + default: + d = &mnemonic_main[op]; + break; + } + + uint32_t flags = s_flags[d->mnemonic]; + if (d->arguments) + { + util::stream_format(stream, "%-5s ", s_mnemonic[d->mnemonic]); + const char *src = d->arguments; + while (*src) + { + switch (*src) + { + case '?': // illegal opcode + util::stream_format(stream, "$%02x", op); + break; + case 'A': + util::stream_format(stream, "$%04X", params.r16(pos)); + pos += 2; + if (src != d->arguments) + flags |= STEP_COND; + break; + case 'B': // Byte op arg + util::stream_format(stream, "$%02X", params.r8(pos++)); + break; + case 'N': // Immediate 16 bit + util::stream_format(stream, "$%04X", params.r16(pos)); + pos += 2; + break; + case 'O': // Offset relative to PC + util::stream_format(stream, "$%04X", (pc + s8(params.r8(pos++)) + 2) & 0xffff); + if (src != d->arguments) + flags |= STEP_COND; + break; + case 'P': // Port number + util::stream_format(stream, "$%02X", params.r8(pos++)); + break; + case 'V': // Break vector + util::stream_format(stream, "$%02X", op & 0x38); + break; + case 'W': // Memory address word + util::stream_format(stream, "$%04X", params.r16(pos)); + pos += 2; + break; + case 'X': + offset = params.r8(pos++); + [[fallthrough]]; + case 'Y': + util::stream_format(stream,"[.%s%c$%02x]", ixy, sign(offset), offs(offset)); + break; + case 'I': + util::stream_format(stream, "%s", ixy); + break; + default: + stream << *src; + break; + } + src++; + } + if (d->mnemonic == zRET) + flags |= STEP_COND; + } + else + { + util::stream_format(stream, "%s", s_mnemonic[d->mnemonic]); + } + + return (pos - pc) | flags | SUPPORTED; +} diff --git a/src/devices/cpu/z80/r800dasm.h b/src/devices/cpu/z80/r800dasm.h new file mode 100644 index 00000000000..c08b6aa90de --- /dev/null +++ b/src/devices/cpu/z80/r800dasm.h @@ -0,0 +1,39 @@ +// license:BSD-3-Clause +// copyright-holders:Wilbert Pol +/***************************************************************************** + * + * r800dasm.h + * Disassembler for ASCII R800 based on portable Z80 disassembler. + * + *****************************************************************************/ + +#ifndef MAME_CPU_Z80_R800DASM_H +#define MAME_CPU_Z80_R800DASM_H + +#pragma once + +class r800_disassembler : public util::disasm_interface +{ +public: + r800_disassembler(); + virtual ~r800_disassembler() = default; + + virtual u32 opcode_alignment() const override; + virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; + +protected: + enum e_mnemonics : unsigned; + struct r800dasm; + + static const u32 s_flags[]; + static const r800dasm mnemonic_xx_cb[256]; + static const r800dasm mnemonic_cb[256]; + static const r800dasm mnemonic_ed[256]; + static const r800dasm mnemonic_xx[256]; + static const r800dasm mnemonic_main[256]; + + static inline char sign(s8 offset); + static inline u32 offs(s8 offset); +}; + +#endif diff --git a/src/devices/cpu/z80/t6a84.cpp b/src/devices/cpu/z80/t6a84.cpp new file mode 100644 index 00000000000..a3d2e5d1fb0 --- /dev/null +++ b/src/devices/cpu/z80/t6a84.cpp @@ -0,0 +1,237 @@ +// license:BSD-3-Clause +// copyright-holders:QUFB +/*************************************************************************** + + Toshiba T6A84, TLCS-Z80 ASSP Family + +***************************************************************************/ + +#include "emu.h" +#include "t6a84.h" + +#include "z80.inc" + +#define LOG_INT (1U << 1) // z80.lst +#define LOG_UNDOC (1U << 2) +#define LOG_PAGE_R (1U << 3) +#define LOG_PAGE_W (1U << 4) +#define LOG_MEM (1U << 5) + +//#define VERBOSE (LOG_PAGE_R | LOG_PAGE_W | LOG_MEM) +#include "logmacro.h" + + +DEFINE_DEVICE_TYPE(T6A84, t6a84_device, "t6a84", "Toshiba T6A84") + +void t6a84_device::internal_io_map(address_map &map) const +{ + map.global_mask(0xff); + map(0xfc, 0xfc).rw(FUNC(t6a84_device::stack_page_r), FUNC(t6a84_device::stack_page_w)); + map(0xfd, 0xfd).rw(FUNC(t6a84_device::data_page_r), FUNC(t6a84_device::data_page_w)); + map(0xfe, 0xfe).rw(FUNC(t6a84_device::code_page_r), FUNC(t6a84_device::code_page_w)); + map(0xff, 0xff).rw(FUNC(t6a84_device::vector_page_r), FUNC(t6a84_device::vector_page_w)); +} + +t6a84_device::t6a84_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + t6a84_device(mconfig, T6A84, tag, owner, clock, address_map_constructor(FUNC(t6a84_device::internal_io_map), this)) +{ } + +t6a84_device::t6a84_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor io_map) + : z80_device(mconfig, type, tag, owner, clock) + , m_program_space_config("program", ENDIANNESS_LITTLE, 8, 20, 0, 16, 0) + , m_data_space_config("data", ENDIANNESS_LITTLE, 8, 20, 0, 16, 0) + , m_stack_space_config("stack", ENDIANNESS_LITTLE, 8, 20, 0, 16, 0) + , m_io_space_config("io", ENDIANNESS_LITTLE, 8, 16, 0, io_map) + , m_code_page(0) + , m_delay_code_page(0) + , m_is_delay_code_page_set(false) + , m_prev_code_page(0) + , m_data_page(8) + , m_stack_page(8) + , m_vector_page(0) +{ +} + +// Interrupt vectors need to be fetched and executed from their corresponding page. +// For simplicity, we switch pages via callbacks, instead of using a dedicated address space. +// TODO: Find a better way to solve this, at least these hacks are isolated to t6a84.cpp for now. +void t6a84_device::paged_irqfetch() +{ + LOGMASKED(LOG_PAGE_W, "IRQ FETCH %02x => %02x\n", m_code_page, m_vector_page); + m_prev_code_page = m_code_page; + m_code_page = m_vector_page; +} + +void t6a84_device::paged_reti() +{ + LOGMASKED(LOG_PAGE_W, "IRQ RET %02x => %02x\n", m_code_page, m_prev_code_page); + m_code_page = m_prev_code_page; +} + +void t6a84_device::paged_jump() +{ + /* + When setting a code page, it only becomes effective after jumping to a far address in that page. + Any instructions fetched and executed before that jump still use the previous code page. + This can be seen in Sega Ferie Kitten, when test program at page 7 gets mapped, as we are still + executing on page 0, but we expect to start executing that program when jumping to RST0: + + ROM_00::1ea9 3e 07 LD A,0x7 + ROM_00::1eab d3 fe OUT (DAT_io_00fe),A + ROM_00::1ead c3 00 00 JP RST0 + */ + if (!machine().side_effects_disabled() && m_is_delay_code_page_set) { + LOGMASKED(LOG_PAGE_W, "BRANCH %02x => %02x\n", m_code_page, m_prev_code_page); + m_code_page = m_delay_code_page; + m_is_delay_code_page_set = false; + } +} + +void t6a84_device::execute_run() +{ + #include "cpu/z80/t6a84.hxx" +} + +void t6a84_device::device_start() +{ + z80_device::device_start(); + + space(AS_PROGRAM).cache(m_args); + space(AS_DATA).specific(m_data); + space(AS_STACK).specific(m_stack); + + save_item(NAME(m_code_page)); + save_item(NAME(m_delay_code_page)); + save_item(NAME(m_is_delay_code_page_set)); + save_item(NAME(m_prev_code_page)); + save_item(NAME(m_data_page)); + save_item(NAME(m_stack_page)); + save_item(NAME(m_vector_page)); +} + +void t6a84_device::device_reset() +{ + m_code_page = 0; + m_delay_code_page = 0; + m_is_delay_code_page_set = false; + m_prev_code_page = 0; + m_data_page = 8; + m_stack_page = 8; + m_vector_page = 0; + + z80_device::device_reset(); +} + +device_memory_interface::space_config_vector t6a84_device::memory_space_config() const +{ + auto r = z80_device::memory_space_config(); + r.emplace_back(AS_DATA, &m_data_space_config); + r.emplace_back(AS_STACK, &m_stack_space_config); + for (auto it = r.begin(); it != r.end(); ++it) { + if ((*it).first == AS_IO) { + (*it).second = &m_io_space_config; + } else if ((*it).first == AS_PROGRAM) { + (*it).second = &m_program_space_config; + } + } + + return r; +} + +bool t6a84_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) +{ + if (spacenum == AS_PROGRAM) { + address = code_address(address); + } else if (spacenum == AS_DATA) { + address = data_address(address); + } else if (spacenum == AS_STACK) { + address = stack_address(address); + } + + target_space = &space(spacenum); + + return true; +} + +uint32_t t6a84_device::code_address(uint16_t address) +{ + const uint32_t page_address = m_code_page << 16 | address; + LOGMASKED(LOG_MEM, "CODE @ %06x => %06x\n", address, page_address); + + return page_address; +} + +uint32_t t6a84_device::data_address(uint16_t address) +{ + const uint32_t page_address = m_data_page << 16 | address; + LOGMASKED(LOG_MEM, "DATA @ %06x => %06x\n", address, page_address); + + return page_address; +} + +uint32_t t6a84_device::stack_address(uint16_t address) +{ + const uint32_t page_address = m_stack_page << 16 | address; + LOGMASKED(LOG_MEM, "STACK @ %06x => %06x\n", address, page_address); + + return page_address; +} + +uint8_t t6a84_device::stack_read(uint16_t addr) +{ + return m_stack.read_byte(addr); +} + +void t6a84_device::stack_write(uint16_t addr, uint8_t value) +{ + m_stack.write_byte(addr, value); +} + +uint8_t t6a84_device::data_page_r() +{ + LOGMASKED(LOG_PAGE_R, "data_page_r: %02x @ %06x\n", m_data_page, pc()); + return m_data_page; +} + +uint8_t t6a84_device::stack_page_r() +{ + LOGMASKED(LOG_PAGE_R, "stack_page_r: %02x @ %06x\n", m_stack_page, pc()); + return m_stack_page; +} + +uint8_t t6a84_device::code_page_r() +{ + LOGMASKED(LOG_PAGE_R, "code_page_r: %02x @ %06x\n", m_code_page, pc()); + return m_code_page; +} + +uint8_t t6a84_device::vector_page_r() +{ + LOGMASKED(LOG_PAGE_R, "vector_page_r: %02x @ %06x\n", m_vector_page, pc()); + return m_vector_page; +} + +void t6a84_device::data_page_w(uint8_t page) +{ + LOGMASKED(LOG_PAGE_W, "data_page_w: %02x @ %06x\n", page, pc()); + m_data_page = page; +} + +void t6a84_device::stack_page_w(uint8_t page) +{ + LOGMASKED(LOG_PAGE_W, "stack_page_w: %02x @ %06x\n", page, pc()); + m_stack_page = page; +} + +void t6a84_device::code_page_w(uint8_t page) +{ + LOGMASKED(LOG_PAGE_W, "code_page_w: %02x @ %06x\n", page, pc()); + m_delay_code_page = page; + m_is_delay_code_page_set = true; +} + +void t6a84_device::vector_page_w(uint8_t page) +{ + LOGMASKED(LOG_PAGE_W, "vector_page_w: %02x @ %06x\n", page, pc()); + m_vector_page = page; +} diff --git a/src/devices/cpu/z80/t6a84.h b/src/devices/cpu/z80/t6a84.h new file mode 100644 index 00000000000..730b799bcc2 --- /dev/null +++ b/src/devices/cpu/z80/t6a84.h @@ -0,0 +1,96 @@ +// license:BSD-3-Clause +// copyright-holders:QUFB +/*************************************************************************** + + Toshiba T6A84, TLCS-Z80 ASSP Family + + Unknown specs. Disassembled code suggests that this processor uses + separate code and data address spaces. Mapped pages on each space are + configured by writing to I/O ports. Values 0 to 7 map the corresponding + 0x10000 sized page from ROM offset 0 to 0x7ffff, while value 8 seems to + map full contents of RAM. + + Pinout: https://patents.google.com/patent/CN2280961Y/en + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_T6A84_H +#define MAME_CPU_Z80_T6A84_H + +#pragma once + +#include "z80.h" + + +/*************************************************************************** + TYPE DEFINITIONS +***************************************************************************/ + +class t6a84_device : public z80_device +{ +public: + enum address_spaces : uint8_t + { + AS_STACK = AS_OPCODES + 1 + }; + + t6a84_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + uint32_t code_address(uint16_t address); + uint32_t data_address(uint16_t address); + uint32_t stack_address(uint16_t address); + +protected: + t6a84_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor io_map); + + // device-level overrides + virtual void device_start() override; + virtual void device_reset() override; + + // device_execute_interface implementation + virtual void execute_run() override; + + // z80 overrides + virtual uint8_t stack_read(uint16_t addr) override; + virtual void stack_write(uint16_t addr, uint8_t value) override; + + uint8_t code_page_r(); + uint8_t data_page_r(); + uint8_t stack_page_r(); + uint8_t vector_page_r(); + void code_page_w(uint8_t page); + void data_page_w(uint8_t page); + void stack_page_w(uint8_t page); + void vector_page_w(uint8_t page); + + void paged_irqfetch(); + void paged_reti(); + void paged_jump(); + + void internal_io_map(address_map &map) const; + virtual space_config_vector memory_space_config() const override; + virtual bool memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) override; + + const address_space_config m_program_space_config; + const address_space_config m_data_space_config; + const address_space_config m_stack_space_config; + const address_space_config m_io_space_config; + + memory_access<16, 0, 0, ENDIANNESS_LITTLE>::specific m_stack; + +private: + uint8_t m_code_page; + uint8_t m_delay_code_page; + bool m_is_delay_code_page_set; + uint8_t m_prev_code_page; + uint8_t m_data_page; + uint8_t m_stack_page; + uint8_t m_vector_page; +}; + + +// device type definition +DECLARE_DEVICE_TYPE(T6A84, t6a84_device) + + +#endif // MAME_CPU_Z80_T6A84_H diff --git a/src/devices/cpu/z80/tmpz84c011.cpp b/src/devices/cpu/z80/tmpz84c011.cpp index 5dd354a1f19..e7925ac74d5 100644 --- a/src/devices/cpu/z80/tmpz84c011.cpp +++ b/src/devices/cpu/z80/tmpz84c011.cpp @@ -41,11 +41,11 @@ tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char * m_outportsc(*this), m_outportsd(*this), m_outportse(*this), - m_inportsa(*this), - m_inportsb(*this), - m_inportsc(*this), - m_inportsd(*this), - m_inportse(*this), + m_inportsa(*this, 0), + m_inportsb(*this, 0), + m_inportsc(*this, 0), + m_inportsd(*this, 0), + m_inportse(*this, 0), m_zc0_cb(*this), m_zc1_cb(*this), m_zc2_cb(*this) @@ -69,23 +69,6 @@ void tmpz84c011_device::device_start() { z80_device::device_start(); - // resolve callbacks - m_outportsa.resolve_safe(); - m_outportsb.resolve_safe(); - m_outportsc.resolve_safe(); - m_outportsd.resolve_safe(); - m_outportse.resolve_safe(); - - m_inportsa.resolve_safe(0); - m_inportsb.resolve_safe(0); - m_inportsc.resolve_safe(0); - m_inportsd.resolve_safe(0); - m_inportse.resolve_safe(0); - - m_zc0_cb.resolve_safe(); - m_zc1_cb.resolve_safe(); - m_zc2_cb.resolve_safe(); - // register for save states save_item(NAME(m_pio_dir[0])); save_item(NAME(m_pio_latch[0])); @@ -109,11 +92,11 @@ void tmpz84c011_device::device_reset() z80_device::device_reset(); // initialize I/O - tmpz84c011_dir_pa_w(*m_io, 0, 0); tmpz84c011_pa_w(*m_io, 0, 0); - tmpz84c011_dir_pb_w(*m_io, 0, 0); tmpz84c011_pb_w(*m_io, 0, 0); - tmpz84c011_dir_pc_w(*m_io, 0, 0); tmpz84c011_pc_w(*m_io, 0, 0); - tmpz84c011_dir_pd_w(*m_io, 0, 0); tmpz84c011_pd_w(*m_io, 0, 0); - tmpz84c011_dir_pe_w(*m_io, 0, 0); tmpz84c011_pe_w(*m_io, 0, 0); + tmpz84c011_dir_pa_w(0); tmpz84c011_pa_w(0); + tmpz84c011_dir_pb_w(0); tmpz84c011_pb_w(0); + tmpz84c011_dir_pc_w(0); tmpz84c011_pc_w(0); + tmpz84c011_dir_pd_w(0); tmpz84c011_pd_w(0); + tmpz84c011_dir_pe_w(0); tmpz84c011_pe_w(0); } diff --git a/src/devices/cpu/z80/tmpz84c011.h b/src/devices/cpu/z80/tmpz84c011.h index 013416cbd9e..a6909e0d697 100644 --- a/src/devices/cpu/z80/tmpz84c011.h +++ b/src/devices/cpu/z80/tmpz84c011.h @@ -30,7 +30,7 @@ class tmpz84c011_device : public z80_device { public: - tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t); + tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); // configuration helpers auto zc0_callback() { return m_zc0_cb.bind(); } @@ -50,41 +50,41 @@ public: auto in_pe_callback() { return m_inportse.bind(); } // CTC public interface - DECLARE_WRITE_LINE_MEMBER( trg0 ) { m_ctc->trg0(state); } - DECLARE_WRITE_LINE_MEMBER( trg1 ) { m_ctc->trg1(state); } - DECLARE_WRITE_LINE_MEMBER( trg2 ) { m_ctc->trg2(state); } - DECLARE_WRITE_LINE_MEMBER( trg3 ) { m_ctc->trg3(state); } + void trg0(int state) { m_ctc->trg0(state); } + void trg1(int state) { m_ctc->trg1(state); } + void trg2(int state) { m_ctc->trg2(state); } + void trg3(int state) { m_ctc->trg3(state); } ///////////////////////////////////////////////////////// - DECLARE_READ8_MEMBER( tmpz84c011_pa_r ) { return (m_inportsa() & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]); } - DECLARE_READ8_MEMBER( tmpz84c011_pb_r ) { return (m_inportsb() & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]); } - DECLARE_READ8_MEMBER( tmpz84c011_pc_r ) { return (m_inportsc() & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]); } - DECLARE_READ8_MEMBER( tmpz84c011_pd_r ) { return (m_inportsd() & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]); } - DECLARE_READ8_MEMBER( tmpz84c011_pe_r ) { return (m_inportse() & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]); } - DECLARE_WRITE8_MEMBER( tmpz84c011_pa_w ) { m_pio_latch[0] = data; m_outportsa(data & m_pio_dir[0]); } - DECLARE_WRITE8_MEMBER( tmpz84c011_pb_w ) { m_pio_latch[1] = data; m_outportsb(data & m_pio_dir[1]); } - DECLARE_WRITE8_MEMBER( tmpz84c011_pc_w ) { m_pio_latch[2] = data; m_outportsc(data & m_pio_dir[2]); } - DECLARE_WRITE8_MEMBER( tmpz84c011_pd_w ) { m_pio_latch[3] = data; m_outportsd(data & m_pio_dir[3]); } - DECLARE_WRITE8_MEMBER( tmpz84c011_pe_w ) { m_pio_latch[4] = data; m_outportse(data & m_pio_dir[4]); } - - DECLARE_READ8_MEMBER( tmpz84c011_dir_pa_r ) { return m_pio_dir[0]; } - DECLARE_READ8_MEMBER( tmpz84c011_dir_pb_r ) { return m_pio_dir[1]; } - DECLARE_READ8_MEMBER( tmpz84c011_dir_pc_r ) { return m_pio_dir[2]; } - DECLARE_READ8_MEMBER( tmpz84c011_dir_pd_r ) { return m_pio_dir[3]; } - DECLARE_READ8_MEMBER( tmpz84c011_dir_pe_r ) { return m_pio_dir[4]; } - DECLARE_WRITE8_MEMBER( tmpz84c011_dir_pa_w ) { m_pio_dir[0] = data; } - DECLARE_WRITE8_MEMBER( tmpz84c011_dir_pb_w ) { m_pio_dir[1] = data; } - DECLARE_WRITE8_MEMBER( tmpz84c011_dir_pc_w ) { m_pio_dir[2] = data; } - DECLARE_WRITE8_MEMBER( tmpz84c011_dir_pd_w ) { m_pio_dir[3] = data; } - DECLARE_WRITE8_MEMBER( tmpz84c011_dir_pe_w ) { m_pio_dir[4] = data; } - - void tmpz84c011_internal_io_map(address_map &map); + uint8_t tmpz84c011_pa_r() { return (m_inportsa() & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]); } + uint8_t tmpz84c011_pb_r() { return (m_inportsb() & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]); } + uint8_t tmpz84c011_pc_r() { return (m_inportsc() & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]); } + uint8_t tmpz84c011_pd_r() { return (m_inportsd() & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]); } + uint8_t tmpz84c011_pe_r() { return (m_inportse() & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]); } + void tmpz84c011_pa_w(uint8_t data) { m_pio_latch[0] = data; m_outportsa(data & m_pio_dir[0]); } + void tmpz84c011_pb_w(uint8_t data) { m_pio_latch[1] = data; m_outportsb(data & m_pio_dir[1]); } + void tmpz84c011_pc_w(uint8_t data) { m_pio_latch[2] = data; m_outportsc(data & m_pio_dir[2]); } + void tmpz84c011_pd_w(uint8_t data) { m_pio_latch[3] = data; m_outportsd(data & m_pio_dir[3]); } + void tmpz84c011_pe_w(uint8_t data) { m_pio_latch[4] = data; m_outportse(data & m_pio_dir[4]); } + + uint8_t tmpz84c011_dir_pa_r() { return m_pio_dir[0]; } + uint8_t tmpz84c011_dir_pb_r() { return m_pio_dir[1]; } + uint8_t tmpz84c011_dir_pc_r() { return m_pio_dir[2]; } + uint8_t tmpz84c011_dir_pd_r() { return m_pio_dir[3]; } + uint8_t tmpz84c011_dir_pe_r() { return m_pio_dir[4]; } + void tmpz84c011_dir_pa_w(uint8_t data) { m_pio_dir[0] = data; } + void tmpz84c011_dir_pb_w(uint8_t data) { m_pio_dir[1] = data; } + void tmpz84c011_dir_pc_w(uint8_t data) { m_pio_dir[2] = data; } + void tmpz84c011_dir_pd_w(uint8_t data) { m_pio_dir[3] = data; } + void tmpz84c011_dir_pe_w(uint8_t data) { m_pio_dir[4] = data; } + + void tmpz84c011_internal_io_map(address_map &map) ATTR_COLD; protected: // device-level overrides - virtual void device_add_mconfig(machine_config &config) override; - virtual void device_start() override; - virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; const address_space_config m_io_space_config; @@ -115,9 +115,9 @@ private: devcb_write_line m_zc1_cb; devcb_write_line m_zc2_cb; - DECLARE_WRITE_LINE_MEMBER( zc0_cb_trampoline_w ) { m_zc0_cb(state); } - DECLARE_WRITE_LINE_MEMBER( zc1_cb_trampoline_w ) { m_zc1_cb(state); } - DECLARE_WRITE_LINE_MEMBER( zc2_cb_trampoline_w ) { m_zc2_cb(state); } + void zc0_cb_trampoline_w(int state) { m_zc0_cb(state); } + void zc1_cb_trampoline_w(int state) { m_zc1_cb(state); } + void zc2_cb_trampoline_w(int state) { m_zc2_cb(state); } }; diff --git a/src/devices/cpu/z80/tmpz84c015.cpp b/src/devices/cpu/z80/tmpz84c015.cpp index a6a0f773adb..765ec6af6c9 100644 --- a/src/devices/cpu/z80/tmpz84c015.cpp +++ b/src/devices/cpu/z80/tmpz84c015.cpp @@ -8,7 +8,7 @@ TODO: - SIO configuration, or should that be up to the driver? - CGC (clock generator/controller) - - WDT (watchdog timer) + - Halt modes ***************************************************************************/ @@ -17,22 +17,30 @@ DEFINE_DEVICE_TYPE(TMPZ84C015, tmpz84c015_device, "tmpz84c015", "Toshiba TMPZ84C015") -void tmpz84c015_device::tmpz84c015_internal_io_map(address_map &map) +void tmpz84c015_device::internal_io_map(address_map &map) const { map(0x10, 0x13).mirror(0xff00).rw(m_ctc, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write)); - map(0x18, 0x1b).mirror(0xff00).rw(m_sio, FUNC(z80dart_device::ba_cd_r), FUNC(z80dart_device::ba_cd_w)); + map(0x18, 0x1b).mirror(0xff00).rw(m_sio, FUNC(z80sio_device::ba_cd_r), FUNC(z80sio_device::ba_cd_w)); map(0x1c, 0x1f).mirror(0xff00).rw(m_pio, FUNC(z80pio_device::read_alt), FUNC(z80pio_device::write_alt)); + map(0xf0, 0xf0).mirror(0xff00).rw(FUNC(tmpz84c015_device::wdtmr_r), FUNC(tmpz84c015_device::wdtmr_w)); + map(0xf1, 0xf1).mirror(0xff00).w(FUNC(tmpz84c015_device::wdtcr_w)); map(0xf4, 0xf4).mirror(0xff00).w(FUNC(tmpz84c015_device::irq_priority_w)); } +tmpz84c015_device::tmpz84c015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + tmpz84c015_device(mconfig, TMPZ84C015, tag, owner, clock, address_map_constructor(FUNC(tmpz84c015_device::internal_io_map), this)) +{ +} -tmpz84c015_device::tmpz84c015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : z80_device(mconfig, TMPZ84C015, tag, owner, clock), - m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, address_map_constructor(FUNC(tmpz84c015_device::tmpz84c015_internal_io_map), this)), +tmpz84c015_device::tmpz84c015_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor io_map) : + z80_device(mconfig, type, tag, owner, clock), + m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, io_map), m_ctc(*this, "tmpz84c015_ctc"), m_sio(*this, "tmpz84c015_sio"), m_pio(*this, "tmpz84c015_pio"), m_irq_priority(-1), // ! + m_wdtmr(0xfb), + m_watchdog_timer(nullptr), m_out_txda_cb(*this), m_out_dtra_cb(*this), @@ -51,15 +59,17 @@ tmpz84c015_device::tmpz84c015_device(const machine_config &mconfig, const char * m_out_rxdrqb_cb(*this), m_out_txdrqb_cb(*this), - m_zc_cb{ {*this}, {*this}, {*this}, {*this} }, + m_zc_cb(*this), - m_in_pa_cb(*this), + m_in_pa_cb(*this, 0), m_out_pa_cb(*this), m_out_ardy_cb(*this), - m_in_pb_cb(*this), + m_in_pb_cb(*this, 0), m_out_pb_cb(*this), - m_out_brdy_cb(*this) + m_out_brdy_cb(*this), + + m_wdtout_cb(*this) { } @@ -79,37 +89,12 @@ void tmpz84c015_device::device_start() { z80_device::device_start(); - // resolve callbacks - m_out_txda_cb.resolve_safe(); - m_out_dtra_cb.resolve_safe(); - m_out_rtsa_cb.resolve_safe(); - m_out_wrdya_cb.resolve_safe(); - m_out_synca_cb.resolve_safe(); - - m_out_txdb_cb.resolve_safe(); - m_out_dtrb_cb.resolve_safe(); - m_out_rtsb_cb.resolve_safe(); - m_out_wrdyb_cb.resolve_safe(); - m_out_syncb_cb.resolve_safe(); - - m_out_rxdrqa_cb.resolve_safe(); - m_out_txdrqa_cb.resolve_safe(); - m_out_rxdrqb_cb.resolve_safe(); - m_out_txdrqb_cb.resolve_safe(); - - for (unsigned i = 0; i < 4; i++) - m_zc_cb[i].resolve_safe(); - - m_in_pa_cb.resolve_safe(0); - m_out_pa_cb.resolve_safe(); - m_out_ardy_cb.resolve_safe(); - - m_in_pb_cb.resolve_safe(0); - m_out_pb_cb.resolve_safe(); - m_out_brdy_cb.resolve_safe(); + // setup watchdog timer + m_watchdog_timer = timer_alloc(FUNC(tmpz84c015_device::watchdog_timeout), this); // register for save states save_item(NAME(m_irq_priority)); + save_item(NAME(m_wdtmr)); } @@ -119,7 +104,10 @@ void tmpz84c015_device::device_start() void tmpz84c015_device::device_reset() { - irq_priority_w(*m_io, 0, 0); + irq_priority_w(0); + m_wdtmr = 0xfb; + watchdog_clear(); + z80_device::device_reset(); } @@ -133,12 +121,12 @@ void tmpz84c015_device::device_post_load() // reinit irq priority uint8_t prio = m_irq_priority; m_irq_priority = -1; - irq_priority_w(*m_io, 0, prio); + irq_priority_w(prio); } /* CPU interface */ -WRITE8_MEMBER(tmpz84c015_device::irq_priority_w) +void tmpz84c015_device::irq_priority_w(uint8_t data) { data &= 7; @@ -177,10 +165,66 @@ WRITE8_MEMBER(tmpz84c015_device::irq_priority_w) } } + +uint8_t tmpz84c015_device::wdtmr_r() +{ + return m_wdtmr; +} + +void tmpz84c015_device::wdtmr_w(uint8_t data) +{ + if ((data & 0x07) != 0x03) + logerror("%s: Writing %d%d%d to WDTMR reserved bits\n", machine().describe_context(), BIT(data, 2), BIT(data, 1), BIT(data, 0)); + + // check for watchdog timer enable + uint8_t old_data = std::exchange(m_wdtmr, data); + if (!BIT(old_data, 7) && BIT(data, 7)) + watchdog_clear(); +} + +void tmpz84c015_device::wdtcr_w(uint8_t data) +{ + // write specific values only + switch (data) + { + case 0x4e: + watchdog_clear(); + break; + + case 0xb1: + // WDTER must be cleared first + if (!BIT(m_wdtmr, 7)) + { + logerror("%s: Watchdog timer disabled\n", machine().describe_context()); + m_watchdog_timer->adjust(attotime::never); + } + break; + + default: + logerror("%s: Writing %02X to WDTCR\n", machine().describe_context(), data); + break; + } +} + +void tmpz84c015_device::watchdog_clear() +{ + m_wdtout_cb(CLEAR_LINE); + + if (BIT(m_wdtmr, 7)) + m_watchdog_timer->adjust(cycles_to_attotime(0x10000 << (BIT(m_wdtmr, 5, 2) * 2))); +} + +TIMER_CALLBACK_MEMBER(tmpz84c015_device::watchdog_timeout) +{ + logerror("Watchdog timeout\n"); + m_wdtout_cb(ASSERT_LINE); +} + + void tmpz84c015_device::device_add_mconfig(machine_config &config) { /* basic machine hardware */ - Z80SIO0(config, m_sio, DERIVED_CLOCK(1,1)); + Z80SIO(config, m_sio, DERIVED_CLOCK(1,1)); m_sio->out_int_callback().set_inputline(DEVICE_SELF, INPUT_LINE_IRQ0); m_sio->out_txda_callback().set(FUNC(tmpz84c015_device::out_txda_cb_trampoline_w)); diff --git a/src/devices/cpu/z80/tmpz84c015.h b/src/devices/cpu/z80/tmpz84c015.h index 100a2743a71..03c688519bd 100644 --- a/src/devices/cpu/z80/tmpz84c015.h +++ b/src/devices/cpu/z80/tmpz84c015.h @@ -13,9 +13,9 @@ #pragma once #include "z80.h" -#include "machine/z80dart.h" #include "machine/z80ctc.h" #include "machine/z80pio.h" +#include "machine/z80sio.h" /*************************************************************************** @@ -25,9 +25,11 @@ class tmpz84c015_device : public z80_device { public: - tmpz84c015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t); + tmpz84c015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); // configuration helpers + template <int Channel> void set_clk_trg(u32 clock) { m_ctc.lookup()->set_clk<Channel>(clock); } + template <int Channel> void set_clk_trg(const XTAL &xtal) { m_ctc.lookup()->set_clk<Channel>(xtal); } // SIO callbacks auto out_txda_callback() { return m_out_txda_cb.bind(); } @@ -47,6 +49,8 @@ public: auto out_rxdrqb_callback() { return m_out_rxdrqb_cb.bind(); } auto out_txdrqb_callback() { return m_out_txdrqb_cb.bind(); } + auto wdtout_cb() { return m_wdtout_cb.bind(); } + // CTC callbacks template<unsigned N> auto zc_callback() { return m_zc_cb[N].bind(); } @@ -60,78 +64,78 @@ public: auto out_brdy_callback() { return m_out_brdy_cb.bind(); } // SIO public interface - DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_sio->rxa_w(state); } - DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_sio->rxb_w(state); } - DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { m_sio->ctsa_w(state); } - DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { m_sio->ctsb_w(state); } - DECLARE_WRITE_LINE_MEMBER( dcda_w ) { m_sio->dcda_w(state); } - DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { m_sio->dcdb_w(state); } - DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_sio->ria_w(state); } - DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_sio->rib_w(state); } - DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_sio->rxca_w(state); } - DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_sio->rxcb_w(state); } - DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_sio->txca_w(state); } - DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_sio->txcb_w(state); } - DECLARE_WRITE_LINE_MEMBER( synca_w ) { m_sio->synca_w(state); } - DECLARE_WRITE_LINE_MEMBER( syncb_w ) { m_sio->syncb_w(state); } + void rxa_w(int state) { m_sio->rxa_w(state); } + void rxb_w(int state) { m_sio->rxb_w(state); } + void ctsa_w(int state) { m_sio->ctsa_w(state); } + void ctsb_w(int state) { m_sio->ctsb_w(state); } + void dcda_w(int state) { m_sio->dcda_w(state); } + void dcdb_w(int state) { m_sio->dcdb_w(state); } + void rxca_w(int state) { m_sio->rxca_w(state); } + void rxcb_w(int state) { m_sio->rxcb_w(state); } + void txca_w(int state) { m_sio->txca_w(state); } + void txcb_w(int state) { m_sio->txcb_w(state); } + void synca_w(int state) { m_sio->synca_w(state); } + void syncb_w(int state) { m_sio->syncb_w(state); } // CTC public interface - DECLARE_WRITE_LINE_MEMBER( trg0 ) { m_ctc->trg0(state); } - DECLARE_WRITE_LINE_MEMBER( trg1 ) { m_ctc->trg1(state); } - DECLARE_WRITE_LINE_MEMBER( trg2 ) { m_ctc->trg2(state); } - DECLARE_WRITE_LINE_MEMBER( trg3 ) { m_ctc->trg3(state); } + void trg0(int state) { m_ctc->trg0(state); } + void trg1(int state) { m_ctc->trg1(state); } + void trg2(int state) { m_ctc->trg2(state); } + void trg3(int state) { m_ctc->trg3(state); } // PIO public interface - DECLARE_READ_LINE_MEMBER( rdy_a ) { return m_pio->rdy_a(); } - DECLARE_READ_LINE_MEMBER( rdy_b ) { return m_pio->rdy_b(); } - DECLARE_WRITE_LINE_MEMBER( strobe_a ) { m_pio->strobe_a(state); } - DECLARE_WRITE_LINE_MEMBER( strobe_b ) { m_pio->strobe_b(state); } - - DECLARE_WRITE8_MEMBER( pa_w ) { m_pio->port_a_write(data); } - DECLARE_READ8_MEMBER( pa_r ) { return m_pio->port_a_read(); } - DECLARE_WRITE8_MEMBER( pb_w ) { m_pio->port_b_write(data); } - DECLARE_READ8_MEMBER( pb_r ) { return m_pio->port_b_read(); } - DECLARE_WRITE_LINE_MEMBER( pa0_w ) { m_pio->pa0_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa1_w ) { m_pio->pa1_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa2_w ) { m_pio->pa2_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa3_w ) { m_pio->pa3_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa4_w ) { m_pio->pa4_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa5_w ) { m_pio->pa5_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa6_w ) { m_pio->pa6_w(state); } - DECLARE_WRITE_LINE_MEMBER( pa7_w ) { m_pio->pa7_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb0_w ) { m_pio->pb0_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb1_w ) { m_pio->pb1_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb2_w ) { m_pio->pb2_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb3_w ) { m_pio->pb3_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb4_w ) { m_pio->pb4_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb5_w ) { m_pio->pb5_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb6_w ) { m_pio->pb6_w(state); } - DECLARE_WRITE_LINE_MEMBER( pb7_w ) { m_pio->pb7_w(state); } + int rdy_a() { return m_pio->rdy_a(); } + int rdy_b() { return m_pio->rdy_b(); } + void strobe_a(int state) { m_pio->strobe_a(state); } + void strobe_b(int state) { m_pio->strobe_b(state); } + + void pa_w(uint8_t data) { m_pio->port_a_write(data); } + uint8_t pa_r() { return m_pio->port_a_read(); } + void pb_w(uint8_t data) { m_pio->port_b_write(data); } + uint8_t pb_r() { return m_pio->port_b_read(); } + void pa0_w(int state) { m_pio->pa0_w(state); } + void pa1_w(int state) { m_pio->pa1_w(state); } + void pa2_w(int state) { m_pio->pa2_w(state); } + void pa3_w(int state) { m_pio->pa3_w(state); } + void pa4_w(int state) { m_pio->pa4_w(state); } + void pa5_w(int state) { m_pio->pa5_w(state); } + void pa6_w(int state) { m_pio->pa6_w(state); } + void pa7_w(int state) { m_pio->pa7_w(state); } + void pb0_w(int state) { m_pio->pb0_w(state); } + void pb1_w(int state) { m_pio->pb1_w(state); } + void pb2_w(int state) { m_pio->pb2_w(state); } + void pb3_w(int state) { m_pio->pb3_w(state); } + void pb4_w(int state) { m_pio->pb4_w(state); } + void pb5_w(int state) { m_pio->pb5_w(state); } + void pb6_w(int state) { m_pio->pb6_w(state); } + void pb7_w(int state) { m_pio->pb7_w(state); } ///////////////////////////////////////////////////////// - DECLARE_WRITE8_MEMBER( irq_priority_w ); - - void tmpz84c015_internal_io_map(address_map &map); protected: + tmpz84c015_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor io_map); + // device-level overrides - virtual void device_add_mconfig(machine_config &config) override; - virtual void device_start() override; - virtual void device_reset() override; + virtual void device_add_mconfig(machine_config &config) override ATTR_COLD; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; virtual void device_post_load() override; const address_space_config m_io_space_config; + void internal_io_map(address_map &map) const; virtual space_config_vector memory_space_config() const override; private: // devices/pointers required_device<z80ctc_device> m_ctc; - required_device<z80dart_device> m_sio; + required_device<z80sio_device> m_sio; required_device<z80pio_device> m_pio; // internal state uint8_t m_irq_priority; + uint8_t m_wdtmr; + emu_timer *m_watchdog_timer; // callbacks devcb_write_line m_out_txda_cb; @@ -151,7 +155,7 @@ private: devcb_write_line m_out_rxdrqb_cb; devcb_write_line m_out_txdrqb_cb; - devcb_write_line m_zc_cb[4]; + devcb_write_line::array<4> m_zc_cb; devcb_read8 m_in_pa_cb; devcb_write8 m_out_pa_cb; @@ -161,32 +165,42 @@ private: devcb_write8 m_out_pb_cb; devcb_write_line m_out_brdy_cb; - DECLARE_WRITE_LINE_MEMBER( out_txda_cb_trampoline_w ) { m_out_txda_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_dtra_cb_trampoline_w ) { m_out_dtra_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_rtsa_cb_trampoline_w ) { m_out_rtsa_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_wrdya_cb_trampoline_w ) { m_out_wrdya_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_synca_cb_trampoline_w ) { m_out_synca_cb(state); } + devcb_write_line m_wdtout_cb; + + uint8_t wdtmr_r(); + void wdtmr_w(uint8_t data); + void wdtcr_w(uint8_t data); + void watchdog_clear(); + TIMER_CALLBACK_MEMBER(watchdog_timeout); + + void irq_priority_w(uint8_t data); + + void out_txda_cb_trampoline_w(int state) { m_out_txda_cb(state); } + void out_dtra_cb_trampoline_w(int state) { m_out_dtra_cb(state); } + void out_rtsa_cb_trampoline_w(int state) { m_out_rtsa_cb(state); } + void out_wrdya_cb_trampoline_w(int state) { m_out_wrdya_cb(state); } + void out_synca_cb_trampoline_w(int state) { m_out_synca_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_txdb_cb_trampoline_w ) { m_out_txdb_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_dtrb_cb_trampoline_w ) { m_out_dtrb_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_rtsb_cb_trampoline_w ) { m_out_rtsb_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_wrdyb_cb_trampoline_w ) { m_out_wrdyb_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_syncb_cb_trampoline_w ) { m_out_syncb_cb(state); } + void out_txdb_cb_trampoline_w(int state) { m_out_txdb_cb(state); } + void out_dtrb_cb_trampoline_w(int state) { m_out_dtrb_cb(state); } + void out_rtsb_cb_trampoline_w(int state) { m_out_rtsb_cb(state); } + void out_wrdyb_cb_trampoline_w(int state) { m_out_wrdyb_cb(state); } + void out_syncb_cb_trampoline_w(int state) { m_out_syncb_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_rxdrqa_cb_trampoline_w ) { m_out_rxdrqa_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_txdrqa_cb_trampoline_w ) { m_out_txdrqa_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_rxdrqb_cb_trampoline_w ) { m_out_rxdrqb_cb(state); } - DECLARE_WRITE_LINE_MEMBER( out_txdrqb_cb_trampoline_w ) { m_out_txdrqb_cb(state); } + void out_rxdrqa_cb_trampoline_w(int state) { m_out_rxdrqa_cb(state); } + void out_txdrqa_cb_trampoline_w(int state) { m_out_txdrqa_cb(state); } + void out_rxdrqb_cb_trampoline_w(int state) { m_out_rxdrqb_cb(state); } + void out_txdrqb_cb_trampoline_w(int state) { m_out_txdrqb_cb(state); } - template<unsigned N> DECLARE_WRITE_LINE_MEMBER( zc_cb_trampoline_w ) { m_zc_cb[N](state); } + template<unsigned N> void zc_cb_trampoline_w(int state) { m_zc_cb[N](state); } - DECLARE_READ8_MEMBER( in_pa_cb_trampoline_r ) { return m_in_pa_cb(); } - DECLARE_WRITE8_MEMBER( out_pa_cb_trampoline_w ) { m_out_pa_cb(data); } - DECLARE_WRITE_LINE_MEMBER( out_ardy_cb_trampoline_w ) { m_out_ardy_cb(state); } + uint8_t in_pa_cb_trampoline_r() { return m_in_pa_cb(); } + void out_pa_cb_trampoline_w(uint8_t data) { m_out_pa_cb(data); } + void out_ardy_cb_trampoline_w(int state) { m_out_ardy_cb(state); } - DECLARE_READ8_MEMBER( in_pb_cb_trampoline_r ) { return m_in_pb_cb(); } - DECLARE_WRITE8_MEMBER( out_pb_cb_trampoline_w ) { m_out_pb_cb(data); } - DECLARE_WRITE_LINE_MEMBER( out_brdy_cb_trampoline_w ) { m_out_brdy_cb(state); } + uint8_t in_pb_cb_trampoline_r() { return m_in_pb_cb(); } + void out_pb_cb_trampoline_w(uint8_t data) { m_out_pb_cb(data); } + void out_brdy_cb_trampoline_w(int state) { m_out_brdy_cb(state); } }; diff --git a/src/devices/cpu/z80/z80.cpp b/src/devices/cpu/z80/z80.cpp index 8e1e29a8a1f..9d2c5958dd7 100644 --- a/src/devices/cpu/z80/z80.cpp +++ b/src/devices/cpu/z80/z80.cpp @@ -1,409 +1,56 @@ // license:BSD-3-Clause // copyright-holders:Juergen Buchmueller /***************************************************************************** - * - * z80.cpp - * Portable Z80 emulator V3.9 - * - * TODO: - * - Interrupt mode 0 should be able to execute arbitrary opcodes - * - If LD A,I or LD A,R is interrupted, P/V flag gets reset, even if IFF2 - * was set before this instruction (implemented, but not enabled: we need - * document Z80 types first, see below) - * - WAIT only stalls between instructions now, it should stall immediately. - * - Ideally, the tiny differences between Z80 types should be supported, - * currently known differences: - * - LD A,I/R P/V flag reset glitch is fixed on CMOS Z80 - * - OUT (C),0 outputs 0 on NMOS Z80, $FF on CMOS Z80 - * - SCF/CCF X/Y flags is ((flags | A) & 0x28) on SGS/SHARP/ZiLOG NMOS Z80, - * (flags & A & 0x28) on NEC NMOS Z80, other models unknown. - * However, recent findings say that SCF/CCF X/Y results depend on whether - * or not the previous instruction touched the flag register. And the exact - * behaviour on NEC Z80 is still unknown. - * This Z80 emulator assumes a ZiLOG NMOS model. - * - * Changes in 3.9: - * - Fixed cycle counts for LD IYL/IXL/IYH/IXH,n [Marshmellow] - * - Fixed X/Y flags in CCF/SCF/BIT, ZEXALL is happy now [hap] - * - Simplified DAA, renamed MEMPTR (3.8) to WZ, added TODO [hap] - * - Fixed IM2 interrupt cycles [eke] - * Changes in 3.8 [Miodrag Milanovic]: - * - Added MEMPTR register (according to informations provided - * by Vladimir Kladov - * - BIT n,(HL) now return valid values due to use of MEMPTR - * - Fixed BIT 6,(XY+o) undocumented instructions - * Changes in 3.7 [Aaron Giles]: - * - Changed NMI handling. NMIs are now latched in set_irq_state - * but are not taken there. Instead they are taken at the start of the - * execute loop. - * - Changed IRQ handling. IRQ state is set in set_irq_state but not taken - * except during the inner execute loop. - * - Removed x86 assembly hacks and obsolete timing loop catchers. - * Changes in 3.6: - * - Got rid of the code that would inexactly emulate a Z80, i.e. removed - * all the #if Z80_EXACT #else branches. - * - Removed leading underscores from local register name shortcuts as - * this violates the C99 standard. - * - Renamed the registers inside the Z80 context to lower case to avoid - * ambiguities (shortcuts would have had the same names as the fields - * of the structure). - * Changes in 3.5: - * - Implemented OTIR, INIR, etc. without look-up table for PF flag. - * [Ramsoft, Sean Young] - * Changes in 3.4: - * - Removed Z80-MSX specific code as it's not needed any more. - * - Implemented DAA without look-up table [Ramsoft, Sean Young] - * Changes in 3.3: - * - Fixed undocumented flags XF & YF in the non-asm versions of CP, - * and all the 16 bit arithmetic instructions. [Sean Young] - * Changes in 3.2: - * - Fixed undocumented flags XF & YF of RRCA, and CF and HF of - * INI/IND/OUTI/OUTD/INIR/INDR/OTIR/OTDR [Sean Young] - * Changes in 3.1: - * - removed the REPEAT_AT_ONCE execution of LDIR/CPIR etc. opcodes - * for readabilities sake and because the implementation was buggy - * (and i was not able to find the difference) - * Changes in 3.0: - * - 'finished' switch to dynamically overrideable cycle count tables - * Changes in 2.9: - * - added methods to access and override the cycle count tables - * - fixed handling and timing of multiple DD/FD prefixed opcodes - * Changes in 2.8: - * - OUTI/OUTD/OTIR/OTDR also pre-decrement the B register now. - * This was wrong because of a bug fix on the wrong side - * (astrocade sound driver). - * Changes in 2.7: - * - removed z80_vm specific code, it's not needed (and never was). - * Changes in 2.6: - * - BUSY_LOOP_HACKS needed to call change_pc() earlier, before - * checking the opcodes at the new address, because otherwise they - * might access the old (wrong or even nullptr) banked memory region. - * Thanks to Sean Young for finding this nasty bug. - * Changes in 2.5: - * - Burning cycles always adjusts the ICount by a multiple of 4. - * - In REPEAT_AT_ONCE cases the r register wasn't incremented twice - * per repetition as it should have been. Those repeated opcodes - * could also underflow the ICount. - * - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL - * timing loops. i think those hacks weren't endian safe before too. - * Changes in 2.4: - * - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and - * sets the Z flag. With these changes the Tehkan World Cup driver - * _seems_ to work again. - * Changes in 2.3: - * - External termination of the execution loop calls z80_burn() and - * z80_vm_burn() to burn an amount of cycles (r adjustment) - * - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS) - * now also adjust the r register depending on the skipped opcodes. - * Changes in 2.2: - * - Fixed bugs in CPL, SCF and CCF instructions flag handling. - * - Changed variable ea and arg16() function to uint32_t; this - * produces slightly more efficient code. - * - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E - * are changed to calls to the X6/XE opcodes to reduce object size. - * They're hardly ever used so this should not yield a speed penalty. - * New in 2.0: - * - Optional more exact Z80 emulation (#define Z80_EXACT 1) according - * to a detailed description by Sean Young which can be found at: - * http://www.msxnet.org/tech/z80-documented.pdf - *****************************************************************************/ + + ZiLOG Z80 emulator + +TODO: +- Interrupt mode 0 should be able to execute arbitrary opcodes +- If LD A,I or LD A,R is interrupted, P/V flag gets reset, even if IFF2 + was set before this instruction (implemented, but not enabled: we need + document Z80 types first, see below) +- Ideally, the tiny differences between Z80 types should be supported, + currently known differences: + - LD A,I/R P/V flag reset glitch is fixed on CMOS Z80 + - OUT (C),0 outputs 0 on NMOS Z80, $FF on CMOS Z80 + - SCF/CCF X/Y flags is ((flags | A) & 0x28) on SGS/SHARP/ZiLOG NMOS Z80, + (flags & A & 0x28). + However, recent findings say that SCF/CCF X/Y results depend on whether + or not the previous instruction touched the flag register. + This Z80 emulator assumes a ZiLOG NMOS model. + +*****************************************************************************/ #include "emu.h" -#include "debugger.h" #include "z80.h" #include "z80dasm.h" -#define VERBOSE 0 - -/* On an NMOS Z80, if LD A,I or LD A,R is interrupted, P/V flag gets reset, - even if IFF2 was set before this instruction. This issue was fixed on - the CMOS Z80, so until knowing (most) Z80 types on hardware, it's disabled */ -#define HAS_LDAIR_QUIRK 0 - -#define LOG(x) do { if (VERBOSE) logerror x; } while (0) - - -/****************************************************************************/ -/* The Z80 registers. halt is set to 1 when the CPU is halted, the refresh */ -/* register is calculated as follows: refresh=(r&127)|(r2&128) */ -/****************************************************************************/ - -#define CF 0x01 -#define NF 0x02 -#define PF 0x04 -#define VF PF -#define XF 0x08 -#define HF 0x10 -#define YF 0x20 -#define ZF 0x40 -#define SF 0x80 - -#define INT_IRQ 0x01 -#define NMI_IRQ 0x02 - -#define PRVPC m_prvpc.d /* previous program counter */ - -#define PCD m_pc.d -#define PC m_pc.w.l - -#define SPD m_sp.d -#define SP m_sp.w.l - -#define AFD m_af.d -#define AF m_af.w.l -#define A m_af.b.h -#define F m_af.b.l - -#define BCD m_bc.d -#define BC m_bc.w.l -#define B m_bc.b.h -#define C m_bc.b.l - -#define DED m_de.d -#define DE m_de.w.l -#define D m_de.b.h -#define E m_de.b.l - -#define HLD m_hl.d -#define HL m_hl.w.l -#define H m_hl.b.h -#define L m_hl.b.l - -#define IXD m_ix.d -#define IX m_ix.w.l -#define HX m_ix.b.h -#define LX m_ix.b.l - -#define IYD m_iy.d -#define IY m_iy.w.l -#define HY m_iy.b.h -#define LY m_iy.b.l - -#define WZ m_wz.w.l -#define WZ_H m_wz.b.h -#define WZ_L m_wz.b.l - - -static bool tables_initialised = false; -static uint8_t SZ[256]; /* zero and sign flags */ -static uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */ -static uint8_t SZP[256]; /* zero, sign and parity flags */ -static uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */ -static uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */ - -static uint8_t SZHVC_add[2*256*256]; -static uint8_t SZHVC_sub[2*256*256]; - -static const uint8_t cc_op[0x100] = { - 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4, - 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4, - 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4, - 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11, /* cb -> cc_cb */ - 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11, /* dd -> cc_xy */ - 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11, /* ed -> cc_ed */ - 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11 /* fd -> cc_xy */ -}; - -static const uint8_t cc_cb[0x100] = { - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8 -}; - -static const uint8_t cc_ed[0x100] = { - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 12,12,15,20,8,14, 8, 9,12,12,15,20, 8,14, 8, 9, - 12,12,15,20,8,14, 8, 9,12,12,15,20, 8,14, 8, 9, - 12,12,15,20,8,14, 8,18,12,12,15,20, 8,14, 8,18, - 12,12,15,20,8,14, 8, 8,12,12,15,20, 8,14, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 16,16,16,16,8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, - 16,16,16,16,8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 -}; - -/* ix/iy: with the exception of (i+offset) opcodes, t-states are main_opcode_table + 4 */ -static const uint8_t cc_xy[0x100] = { - 4+4,10+4, 7+4, 6+4, 4+4, 4+4, 7+4, 4+4, 4+4,11+4, 7+4, 6+4, 4+4, 4+4, 7+4, 4+4, - 8+4,10+4, 7+4, 6+4, 4+4, 4+4, 7+4, 4+4,12+4,11+4, 7+4, 6+4, 4+4, 4+4, 7+4, 4+4, - 7+4,10+4,16+4, 6+4, 4+4, 4+4, 7+4, 4+4, 7+4,11+4,16+4, 6+4, 4+4, 4+4, 7+4, 4+4, - 7+4,10+4,13+4, 6+4,23 ,23 ,19 , 4+4, 7+4,11+4,13+4, 6+4, 4+4, 4+4, 7+4, 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 19 ,19 ,19 ,19 ,19 ,19 , 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, 4+4, 4+4, 4+4, 4+4, 4+4, 4+4,19 , 4+4, - 5+4,10+4,10+4,10+4,10+4,11+4, 7+4,11+4, 5+4,10+4,10+4, 0 ,10+4,17+4, 7+4,11+4, /* cb -> cc_xycb */ - 5+4,10+4,10+4,11+4,10+4,11+4, 7+4,11+4, 5+4, 4+4,10+4,11+4,10+4, 4 , 7+4,11+4, /* dd -> cc_xy again */ - 5+4,10+4,10+4,19+4,10+4,11+4, 7+4,11+4, 5+4, 4+4,10+4, 4+4,10+4, 4 , 7+4,11+4, /* ed -> cc_ed */ - 5+4,10+4,10+4, 4+4,10+4,11+4, 7+4,11+4, 5+4, 6+4,10+4, 4+4,10+4, 4 , 7+4,11+4 /* fd -> cc_xy again */ -}; - -static const uint8_t cc_xycb[0x100] = { - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, - 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, - 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, - 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, - 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23 -}; - -/* extra cycles if jr/jp/call taken and 'interrupt latency' on rst 0-7 */ -static const uint8_t cc_ex[0x100] = { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* DJNZ */ - 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NZ/JR Z */ - 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NC/JR C */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 5, 5, 5, 5, 0, 0, 0, 0, 5, 5, 5, 5, 0, 0, 0, 0, /* LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR */ - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2 -}; - -#define m_cc_dd m_cc_xy -#define m_cc_fd m_cc_xy +#include "z80.inc" -/*************************************************************** - * define an opcode function - ***************************************************************/ -#define OP(prefix,opcode) inline void z80_device::prefix##_##opcode() +#define LOG_INT (1U << 1) // z80.lst +#define LOG_UNDOC (1U << 2) + +#define VERBOSE (LOG_UNDOC) +#include "logmacro.h" + + +bool z80_device::tables_initialised = false; +u8 z80_device::SZ[] = {}; // zero and sign flags +u8 z80_device::SZ_BIT[] = {}; // zero, sign and parity/overflow (=zero) flags for BIT opcode +u8 z80_device::SZP[] = {}; // zero, sign and parity flags +u8 z80_device::SZHV_inc[] = {}; // zero, sign, half carry and overflow flags INC r8 +u8 z80_device::SZHV_dec[] = {}; // zero, sign, half carry and overflow flags DEC r8 -/*************************************************************** - * adjust cycle count by n T-states - ***************************************************************/ -#define CC(prefix,opcode) do { m_icount -= m_cc_##prefix[opcode]; } while (0) - -#define EXEC(prefix,opcode) do { \ - unsigned op = opcode; \ - CC(prefix,op); \ - switch(op) \ - { \ - case 0x00:prefix##_##00();break; case 0x01:prefix##_##01();break; case 0x02:prefix##_##02();break; case 0x03:prefix##_##03();break; \ - case 0x04:prefix##_##04();break; case 0x05:prefix##_##05();break; case 0x06:prefix##_##06();break; case 0x07:prefix##_##07();break; \ - case 0x08:prefix##_##08();break; case 0x09:prefix##_##09();break; case 0x0a:prefix##_##0a();break; case 0x0b:prefix##_##0b();break; \ - case 0x0c:prefix##_##0c();break; case 0x0d:prefix##_##0d();break; case 0x0e:prefix##_##0e();break; case 0x0f:prefix##_##0f();break; \ - case 0x10:prefix##_##10();break; case 0x11:prefix##_##11();break; case 0x12:prefix##_##12();break; case 0x13:prefix##_##13();break; \ - case 0x14:prefix##_##14();break; case 0x15:prefix##_##15();break; case 0x16:prefix##_##16();break; case 0x17:prefix##_##17();break; \ - case 0x18:prefix##_##18();break; case 0x19:prefix##_##19();break; case 0x1a:prefix##_##1a();break; case 0x1b:prefix##_##1b();break; \ - case 0x1c:prefix##_##1c();break; case 0x1d:prefix##_##1d();break; case 0x1e:prefix##_##1e();break; case 0x1f:prefix##_##1f();break; \ - case 0x20:prefix##_##20();break; case 0x21:prefix##_##21();break; case 0x22:prefix##_##22();break; case 0x23:prefix##_##23();break; \ - case 0x24:prefix##_##24();break; case 0x25:prefix##_##25();break; case 0x26:prefix##_##26();break; case 0x27:prefix##_##27();break; \ - case 0x28:prefix##_##28();break; case 0x29:prefix##_##29();break; case 0x2a:prefix##_##2a();break; case 0x2b:prefix##_##2b();break; \ - case 0x2c:prefix##_##2c();break; case 0x2d:prefix##_##2d();break; case 0x2e:prefix##_##2e();break; case 0x2f:prefix##_##2f();break; \ - case 0x30:prefix##_##30();break; case 0x31:prefix##_##31();break; case 0x32:prefix##_##32();break; case 0x33:prefix##_##33();break; \ - case 0x34:prefix##_##34();break; case 0x35:prefix##_##35();break; case 0x36:prefix##_##36();break; case 0x37:prefix##_##37();break; \ - case 0x38:prefix##_##38();break; case 0x39:prefix##_##39();break; case 0x3a:prefix##_##3a();break; case 0x3b:prefix##_##3b();break; \ - case 0x3c:prefix##_##3c();break; case 0x3d:prefix##_##3d();break; case 0x3e:prefix##_##3e();break; case 0x3f:prefix##_##3f();break; \ - case 0x40:prefix##_##40();break; case 0x41:prefix##_##41();break; case 0x42:prefix##_##42();break; case 0x43:prefix##_##43();break; \ - case 0x44:prefix##_##44();break; case 0x45:prefix##_##45();break; case 0x46:prefix##_##46();break; case 0x47:prefix##_##47();break; \ - case 0x48:prefix##_##48();break; case 0x49:prefix##_##49();break; case 0x4a:prefix##_##4a();break; case 0x4b:prefix##_##4b();break; \ - case 0x4c:prefix##_##4c();break; case 0x4d:prefix##_##4d();break; case 0x4e:prefix##_##4e();break; case 0x4f:prefix##_##4f();break; \ - case 0x50:prefix##_##50();break; case 0x51:prefix##_##51();break; case 0x52:prefix##_##52();break; case 0x53:prefix##_##53();break; \ - case 0x54:prefix##_##54();break; case 0x55:prefix##_##55();break; case 0x56:prefix##_##56();break; case 0x57:prefix##_##57();break; \ - case 0x58:prefix##_##58();break; case 0x59:prefix##_##59();break; case 0x5a:prefix##_##5a();break; case 0x5b:prefix##_##5b();break; \ - case 0x5c:prefix##_##5c();break; case 0x5d:prefix##_##5d();break; case 0x5e:prefix##_##5e();break; case 0x5f:prefix##_##5f();break; \ - case 0x60:prefix##_##60();break; case 0x61:prefix##_##61();break; case 0x62:prefix##_##62();break; case 0x63:prefix##_##63();break; \ - case 0x64:prefix##_##64();break; case 0x65:prefix##_##65();break; case 0x66:prefix##_##66();break; case 0x67:prefix##_##67();break; \ - case 0x68:prefix##_##68();break; case 0x69:prefix##_##69();break; case 0x6a:prefix##_##6a();break; case 0x6b:prefix##_##6b();break; \ - case 0x6c:prefix##_##6c();break; case 0x6d:prefix##_##6d();break; case 0x6e:prefix##_##6e();break; case 0x6f:prefix##_##6f();break; \ - case 0x70:prefix##_##70();break; case 0x71:prefix##_##71();break; case 0x72:prefix##_##72();break; case 0x73:prefix##_##73();break; \ - case 0x74:prefix##_##74();break; case 0x75:prefix##_##75();break; case 0x76:prefix##_##76();break; case 0x77:prefix##_##77();break; \ - case 0x78:prefix##_##78();break; case 0x79:prefix##_##79();break; case 0x7a:prefix##_##7a();break; case 0x7b:prefix##_##7b();break; \ - case 0x7c:prefix##_##7c();break; case 0x7d:prefix##_##7d();break; case 0x7e:prefix##_##7e();break; case 0x7f:prefix##_##7f();break; \ - case 0x80:prefix##_##80();break; case 0x81:prefix##_##81();break; case 0x82:prefix##_##82();break; case 0x83:prefix##_##83();break; \ - case 0x84:prefix##_##84();break; case 0x85:prefix##_##85();break; case 0x86:prefix##_##86();break; case 0x87:prefix##_##87();break; \ - case 0x88:prefix##_##88();break; case 0x89:prefix##_##89();break; case 0x8a:prefix##_##8a();break; case 0x8b:prefix##_##8b();break; \ - case 0x8c:prefix##_##8c();break; case 0x8d:prefix##_##8d();break; case 0x8e:prefix##_##8e();break; case 0x8f:prefix##_##8f();break; \ - case 0x90:prefix##_##90();break; case 0x91:prefix##_##91();break; case 0x92:prefix##_##92();break; case 0x93:prefix##_##93();break; \ - case 0x94:prefix##_##94();break; case 0x95:prefix##_##95();break; case 0x96:prefix##_##96();break; case 0x97:prefix##_##97();break; \ - case 0x98:prefix##_##98();break; case 0x99:prefix##_##99();break; case 0x9a:prefix##_##9a();break; case 0x9b:prefix##_##9b();break; \ - case 0x9c:prefix##_##9c();break; case 0x9d:prefix##_##9d();break; case 0x9e:prefix##_##9e();break; case 0x9f:prefix##_##9f();break; \ - case 0xa0:prefix##_##a0();break; case 0xa1:prefix##_##a1();break; case 0xa2:prefix##_##a2();break; case 0xa3:prefix##_##a3();break; \ - case 0xa4:prefix##_##a4();break; case 0xa5:prefix##_##a5();break; case 0xa6:prefix##_##a6();break; case 0xa7:prefix##_##a7();break; \ - case 0xa8:prefix##_##a8();break; case 0xa9:prefix##_##a9();break; case 0xaa:prefix##_##aa();break; case 0xab:prefix##_##ab();break; \ - case 0xac:prefix##_##ac();break; case 0xad:prefix##_##ad();break; case 0xae:prefix##_##ae();break; case 0xaf:prefix##_##af();break; \ - case 0xb0:prefix##_##b0();break; case 0xb1:prefix##_##b1();break; case 0xb2:prefix##_##b2();break; case 0xb3:prefix##_##b3();break; \ - case 0xb4:prefix##_##b4();break; case 0xb5:prefix##_##b5();break; case 0xb6:prefix##_##b6();break; case 0xb7:prefix##_##b7();break; \ - case 0xb8:prefix##_##b8();break; case 0xb9:prefix##_##b9();break; case 0xba:prefix##_##ba();break; case 0xbb:prefix##_##bb();break; \ - case 0xbc:prefix##_##bc();break; case 0xbd:prefix##_##bd();break; case 0xbe:prefix##_##be();break; case 0xbf:prefix##_##bf();break; \ - case 0xc0:prefix##_##c0();break; case 0xc1:prefix##_##c1();break; case 0xc2:prefix##_##c2();break; case 0xc3:prefix##_##c3();break; \ - case 0xc4:prefix##_##c4();break; case 0xc5:prefix##_##c5();break; case 0xc6:prefix##_##c6();break; case 0xc7:prefix##_##c7();break; \ - case 0xc8:prefix##_##c8();break; case 0xc9:prefix##_##c9();break; case 0xca:prefix##_##ca();break; case 0xcb:prefix##_##cb();break; \ - case 0xcc:prefix##_##cc();break; case 0xcd:prefix##_##cd();break; case 0xce:prefix##_##ce();break; case 0xcf:prefix##_##cf();break; \ - case 0xd0:prefix##_##d0();break; case 0xd1:prefix##_##d1();break; case 0xd2:prefix##_##d2();break; case 0xd3:prefix##_##d3();break; \ - case 0xd4:prefix##_##d4();break; case 0xd5:prefix##_##d5();break; case 0xd6:prefix##_##d6();break; case 0xd7:prefix##_##d7();break; \ - case 0xd8:prefix##_##d8();break; case 0xd9:prefix##_##d9();break; case 0xda:prefix##_##da();break; case 0xdb:prefix##_##db();break; \ - case 0xdc:prefix##_##dc();break; case 0xdd:prefix##_##dd();break; case 0xde:prefix##_##de();break; case 0xdf:prefix##_##df();break; \ - case 0xe0:prefix##_##e0();break; case 0xe1:prefix##_##e1();break; case 0xe2:prefix##_##e2();break; case 0xe3:prefix##_##e3();break; \ - case 0xe4:prefix##_##e4();break; case 0xe5:prefix##_##e5();break; case 0xe6:prefix##_##e6();break; case 0xe7:prefix##_##e7();break; \ - case 0xe8:prefix##_##e8();break; case 0xe9:prefix##_##e9();break; case 0xea:prefix##_##ea();break; case 0xeb:prefix##_##eb();break; \ - case 0xec:prefix##_##ec();break; case 0xed:prefix##_##ed();break; case 0xee:prefix##_##ee();break; case 0xef:prefix##_##ef();break; \ - case 0xf0:prefix##_##f0();break; case 0xf1:prefix##_##f1();break; case 0xf2:prefix##_##f2();break; case 0xf3:prefix##_##f3();break; \ - case 0xf4:prefix##_##f4();break; case 0xf5:prefix##_##f5();break; case 0xf6:prefix##_##f6();break; case 0xf7:prefix##_##f7();break; \ - case 0xf8:prefix##_##f8();break; case 0xf9:prefix##_##f9();break; case 0xfa:prefix##_##fa();break; case 0xfb:prefix##_##fb();break; \ - case 0xfc:prefix##_##fc();break; case 0xfd:prefix##_##fd();break; case 0xfe:prefix##_##fe();break; case 0xff:prefix##_##ff();break; \ - } \ -} while (0) /*************************************************************** * Enter halt state; write 1 to callback on first execution ***************************************************************/ -inline void z80_device::halt() +void z80_device::halt() { - PC--; if (!m_halt) { m_halt = 1; + set_service_attention<SA_HALT, 1>(); m_halt_cb(1); } } @@ -411,64 +58,30 @@ inline void z80_device::halt() /*************************************************************** * Leave halt state; write 0 to callback ***************************************************************/ -inline void z80_device::leave_halt() +void z80_device::leave_halt() { - if( m_halt ) + if (m_halt) { m_halt = 0; + set_service_attention<SA_HALT, 0>(); m_halt_cb(0); - PC++; } } /*************************************************************** - * Input a byte from given I/O port - ***************************************************************/ -inline uint8_t z80_device::in(uint16_t port) -{ - return m_io->read_byte(port); -} - -/*************************************************************** - * Output a byte to given I/O port - ***************************************************************/ -inline void z80_device::out(uint16_t port, uint8_t value) -{ - m_io->write_byte(port, value); -} - -/*************************************************************** * Read a byte from given memory location ***************************************************************/ -inline uint8_t z80_device::rm(uint16_t addr) -{ - return m_program->read_byte(addr); -} - -/*************************************************************** - * Read a word from given memory location - ***************************************************************/ -inline void z80_device::rm16(uint16_t addr, PAIR &r) +u8 z80_device::data_read(u16 addr) { - r.b.l = rm(addr); - r.b.h = rm((addr+1)); + return m_data.read_interruptible(addr); } /*************************************************************** * Write a byte to given memory location ***************************************************************/ -inline void z80_device::wm(uint16_t addr, uint8_t value) -{ - m_program->write_byte(addr, value); -} - -/*************************************************************** - * Write a word to given memory location - ***************************************************************/ -inline void z80_device::wm16(uint16_t addr, PAIR &r) +void z80_device::data_write(u16 addr, u8 value) { - wm(addr, r.b.l); - wm((addr+1), r.b.h); + m_data.write_interruptible(addr, value); } /*************************************************************** @@ -476,15 +89,9 @@ inline void z80_device::wm16(uint16_t addr, PAIR &r) * reading opcodes. In case of system with memory mapped I/O, * this function can be used to greatly speed up emulation ***************************************************************/ -inline uint8_t z80_device::rop() +u8 z80_device::opcode_read() { - unsigned pc = PCD; - PC++; - uint8_t res = m_opcodes_cache->read_byte(pc); - m_icount -= 2; - m_refresh_cb((m_i << 8) | (m_r2 & 0x80) | ((m_r-1) & 0x7f), 0x00, 0xff); - m_icount += 2; - return res; + return m_opcodes.read_byte(PC); } /**************************************************************** @@ -492,252 +99,46 @@ inline uint8_t z80_device::rop() * for reading opcode arguments. This difference can be used to * support systems that use different encoding mechanisms for * opcodes and opcode arguments + * out: TDAT8 ***************************************************************/ -inline uint8_t z80_device::arg() -{ - unsigned pc = PCD; - PC++; - return m_cache->read_byte(pc); -} - -inline uint16_t z80_device::arg16() -{ - unsigned pc = PCD; - PC += 2; - return m_cache->read_byte(pc) | (m_cache->read_byte((pc+1)&0xffff) << 8); -} - -/*************************************************************** - * Calculate the effective address EA of an opcode using - * IX+offset resp. IY+offset addressing. - ***************************************************************/ -inline void z80_device::eax() -{ - m_ea = (uint32_t)(uint16_t)(IX + (int8_t)arg()); - WZ = m_ea; -} - -inline void z80_device::eay() -{ - m_ea = (uint32_t)(uint16_t)(IY + (int8_t)arg()); - WZ = m_ea; -} - -/*************************************************************** - * POP - ***************************************************************/ -inline void z80_device::pop(PAIR &r) -{ - rm16(SPD, r); - SP += 2; -} - -/*************************************************************** - * PUSH - ***************************************************************/ -inline void z80_device::push(PAIR &r) +u8 z80_device::arg_read() { - SP -= 2; - wm16(SPD, r); -} - -/*************************************************************** - * JP - ***************************************************************/ -inline void z80_device::jp(void) -{ - PCD = arg16(); - WZ = PCD; -} - -/*************************************************************** - * JP_COND - ***************************************************************/ -inline void z80_device::jp_cond(bool cond) -{ - if (cond) - { - PCD = arg16(); - WZ = PCD; - } - else - { - WZ = arg16(); /* implicit do PC += 2 */ - } -} - -/*************************************************************** - * JR - ***************************************************************/ -inline void z80_device::jr() -{ - int8_t a = (int8_t)arg(); /* arg() also increments PC */ - PC += a; /* so don't do PC += arg() */ - WZ = PC; -} - -/*************************************************************** - * JR_COND - ***************************************************************/ -inline void z80_device::jr_cond(bool cond, uint8_t opcode) -{ - if (cond) - { - jr(); - CC(ex, opcode); - } - else - PC++; -} - -/*************************************************************** - * CALL - ***************************************************************/ -inline void z80_device::call() -{ - m_ea = arg16(); - WZ = m_ea; - push(m_pc); - PCD = m_ea; -} - -/*************************************************************** - * CALL_COND - ***************************************************************/ -inline void z80_device::call_cond(bool cond, uint8_t opcode) -{ - if (cond) - { - m_ea = arg16(); - WZ = m_ea; - push(m_pc); - PCD = m_ea; - CC(ex, opcode); - } - else - { - WZ = arg16(); /* implicit call PC+=2; */ - } -} - -/*************************************************************** - * RET_COND - ***************************************************************/ -inline void z80_device::ret_cond(bool cond, uint8_t opcode) -{ - if (cond) - { - pop(m_pc); - WZ = PC; - CC(ex, opcode); - } -} - -/*************************************************************** - * RETN - ***************************************************************/ -inline void z80_device::retn() -{ - LOG(("Z80 RETN m_iff1:%d m_iff2:%d\n", - m_iff1, m_iff2)); - pop(m_pc); - WZ = PC; - m_iff1 = m_iff2; -} - -/*************************************************************** - * RETI - ***************************************************************/ -inline void z80_device::reti() -{ - pop(m_pc); - WZ = PC; - m_iff1 = m_iff2; - daisy_call_reti_device(); -} - -/*************************************************************** - * LD R,A - ***************************************************************/ -inline void z80_device::ld_r_a() -{ - m_r = A; - m_r2 = A & 0x80; /* keep bit 7 of r */ -} - -/*************************************************************** - * LD A,R - ***************************************************************/ -inline void z80_device::ld_a_r() -{ - A = (m_r & 0x7f) | m_r2; - F = (F & CF) | SZ[A] | (m_iff2 << 2); - m_after_ldair = true; -} - -/*************************************************************** - * LD I,A - ***************************************************************/ -inline void z80_device::ld_i_a() -{ - m_i = A; -} - -/*************************************************************** - * LD A,I - ***************************************************************/ -inline void z80_device::ld_a_i() -{ - A = m_i; - F = (F & CF) | SZ[A] | (m_iff2 << 2); - m_after_ldair = true; -} - -/*************************************************************** - * RST - ***************************************************************/ -inline void z80_device::rst(uint16_t addr) -{ - push(m_pc); - PCD = addr; - WZ = PC; + return m_args.read_byte(PC); } /*************************************************************** * INC r8 ***************************************************************/ -inline uint8_t z80_device::inc(uint8_t value) +void z80_device::inc(u8 &r) { - uint8_t res = value + 1; - F = (F & CF) | SZHV_inc[res]; - return (uint8_t)res; + ++r; + set_f((F & CF) | SZHV_inc[r]); } /*************************************************************** * DEC r8 ***************************************************************/ -inline uint8_t z80_device::dec(uint8_t value) +void z80_device::dec(u8 &r) { - uint8_t res = value - 1; - F = (F & CF) | SZHV_dec[res]; - return res; + --r; + set_f((F & CF) | SZHV_dec[r]); } /*************************************************************** * RLCA ***************************************************************/ -inline void z80_device::rlca() +void z80_device::rlca() { A = (A << 1) | (A >> 7); - F = (F & (SF | ZF | PF)) | (A & (YF | XF | CF)); + set_f((F & (SF | ZF | PF)) | (A & (YF | XF | CF))); } /*************************************************************** * RRCA ***************************************************************/ -inline void z80_device::rrca() +void z80_device::rrca() { - F = (F & (SF | ZF | PF)) | (A & CF); + set_f((F & (SF | ZF | PF)) | (A & CF)); A = (A >> 1) | (A << 7); F |= (A & (YF | XF)); } @@ -745,2608 +146,401 @@ inline void z80_device::rrca() /*************************************************************** * RLA ***************************************************************/ -inline void z80_device::rla() +void z80_device::rla() { - uint8_t res = (A << 1) | (F & CF); - uint8_t c = (A & 0x80) ? CF : 0; - F = (F & (SF | ZF | PF)) | c | (res & (YF | XF)); + u8 res = (A << 1) | (F & CF); + u8 c = (A & 0x80) ? CF : 0; + set_f((F & (SF | ZF | PF)) | c | (res & (YF | XF))); A = res; } /*************************************************************** * RRA ***************************************************************/ -inline void z80_device::rra() +void z80_device::rra() { - uint8_t res = (A >> 1) | (F << 7); - uint8_t c = (A & 0x01) ? CF : 0; - F = (F & (SF | ZF | PF)) | c | (res & (YF | XF)); + u8 res = (A >> 1) | (F << 7); + u8 c = (A & 0x01) ? CF : 0; + set_f((F & (SF | ZF | PF)) | c | (res & (YF | XF))); A = res; } /*************************************************************** - * RRD - ***************************************************************/ -inline void z80_device::rrd() -{ - uint8_t n = rm(HL); - WZ = HL+1; - wm(HL, (n >> 4) | (A << 4)); - A = (A & 0xf0) | (n & 0x0f); - F = (F & CF) | SZP[A]; -} - -/*************************************************************** - * RLD - ***************************************************************/ -inline void z80_device::rld() -{ - uint8_t n = rm(HL); - WZ = HL+1; - wm(HL, (n << 4) | (A & 0x0f)); - A = (A & 0xf0) | (n >> 4); - F = (F & CF) | SZP[A]; -} - -/*************************************************************** * ADD A,n ***************************************************************/ -inline void z80_device::add_a(uint8_t value) +void z80_device::add_a(u8 value) { - uint32_t ah = AFD & 0xff00; - uint32_t res = (uint8_t)((ah >> 8) + value); - F = SZHVC_add[ah | res]; + const u16 res = A + value; + u8 f = (((A ^ res) & (value ^ res)) >> 5) & VF; + f |= flags_szyxc(res); + f |= ((A & 0x0f) + (value & 0x0f)) & HF; + set_f(f); A = res; } /*************************************************************** * ADC A,n ***************************************************************/ -inline void z80_device::adc_a(uint8_t value) +void z80_device::adc_a(u8 value) { - uint32_t ah = AFD & 0xff00, c = AFD & 1; - uint32_t res = (uint8_t)((ah >> 8) + value + c); - F = SZHVC_add[(c << 16) | ah | res]; + const int c = F & CF; + const u16 res = A + value + c; + u8 f = (((A ^ res) & (value ^ res)) >> 5) & VF; + f |= flags_szyxc(res); + f |= ((A & 0x0f) + (value & 0x0f) + c) & HF; + + set_f(f); A = res; } /*************************************************************** - * SUB n + * SUB A,n ***************************************************************/ -inline void z80_device::sub(uint8_t value) +void z80_device::sub_a(u8 value) { - uint32_t ah = AFD & 0xff00; - uint32_t res = (uint8_t)((ah >> 8) - value); - F = SZHVC_sub[ah | res]; + const u16 res = A - value; + u8 f = (((A ^ value) & (A ^ res)) >> 5) & VF; + f |= NF | flags_szyxc(res); + f |= ((A & 0x0f) - (value & 0x0f)) & HF; + + set_f(f); A = res; } /*************************************************************** * SBC A,n ***************************************************************/ -inline void z80_device::sbc_a(uint8_t value) +void z80_device::sbc_a(u8 value) { - uint32_t ah = AFD & 0xff00, c = AFD & 1; - uint32_t res = (uint8_t)((ah >> 8) - value - c); - F = SZHVC_sub[(c<<16) | ah | res]; + const int c = F & CF; + const u16 res = A - value - c; + u8 f = (((A ^ value) & (A ^ res)) >> 5) & VF; + f |= NF | flags_szyxc(res); + f |= ((A & 0x0f) - (value & 0x0f) - c) & HF; + + set_f(f); A = res; } /*************************************************************** * NEG ***************************************************************/ -inline void z80_device::neg() +void z80_device::neg() { - uint8_t value = A; + u8 value = A; A = 0; - sub(value); + sub_a(value); } /*************************************************************** * DAA ***************************************************************/ -inline void z80_device::daa() +void z80_device::daa() { - uint8_t a = A; - if (F & NF) { + u8 a = A; + if (F & NF) + { if ((F&HF) | ((A&0xf)>9)) a-=6; if ((F&CF) | (A>0x99)) a-=0x60; } - else { + else + { if ((F&HF) | ((A&0xf)>9)) a+=6; if ((F&CF) | (A>0x99)) a+=0x60; } - F = (F&(CF|NF)) | (A>0x99) | ((A^a)&HF) | SZP[a]; + set_f((F&(CF|NF)) | (A>0x99) | ((A^a)&HF) | SZP[a]); A = a; } /*************************************************************** * AND n ***************************************************************/ -inline void z80_device::and_a(uint8_t value) +void z80_device::and_a(u8 value) { A &= value; - F = SZP[A] | HF; + set_f(SZP[A] | HF); } /*************************************************************** * OR n ***************************************************************/ -inline void z80_device::or_a(uint8_t value) +void z80_device::or_a(u8 value) { A |= value; - F = SZP[A]; + set_f(SZP[A]); } /*************************************************************** * XOR n ***************************************************************/ -inline void z80_device::xor_a(uint8_t value) +void z80_device::xor_a(u8 value) { A ^= value; - F = SZP[A]; + set_f(SZP[A]); } /*************************************************************** * CP n ***************************************************************/ -inline void z80_device::cp(uint8_t value) +void z80_device::cp(u8 value) { - unsigned val = value; - uint32_t ah = AFD & 0xff00; - uint32_t res = (uint8_t)((ah >> 8) - val); - F = (SZHVC_sub[ah | res] & ~(YF | XF)) | - (val & (YF | XF)); -} + const u16 res = A - value; + u8 f = (((A ^ value) & (A ^ res)) >> 5) & VF; + f |= NF | flags_szyxc(res); + f |= ((A & 0x0f) - (value & 0x0f)) & HF; -/*************************************************************** - * EX AF,AF' - ***************************************************************/ -inline void z80_device::ex_af() -{ - PAIR tmp; - tmp = m_af; m_af = m_af2; m_af2 = tmp; -} - -/*************************************************************** - * EX DE,HL - ***************************************************************/ -inline void z80_device::ex_de_hl() -{ - PAIR tmp; - tmp = m_de; m_de = m_hl; m_hl = tmp; + set_f((f & ~(YF | XF)) | (value & (YF | XF))); } /*************************************************************** * EXX ***************************************************************/ -inline void z80_device::exx() -{ - PAIR tmp; - tmp = m_bc; m_bc = m_bc2; m_bc2 = tmp; - tmp = m_de; m_de = m_de2; m_de2 = tmp; - tmp = m_hl; m_hl = m_hl2; m_hl2 = tmp; -} - -/*************************************************************** - * EX (SP),r16 - ***************************************************************/ -inline void z80_device::ex_sp(PAIR &r) -{ - PAIR tmp = { { 0, 0, 0, 0 } }; - rm16(SPD, tmp); - wm16(SPD, r); - r = tmp; - WZ = r.d; -} - -/*************************************************************** - * ADD16 - ***************************************************************/ -inline void z80_device::add16(PAIR &dr, PAIR &sr) +void z80_device::exx() { - uint32_t res = dr.d + sr.d; - WZ = dr.d + 1; - F = (F & (SF | ZF | VF)) | - (((dr.d ^ res ^ sr.d) >> 8) & HF) | - ((res >> 16) & CF) | ((res >> 8) & (YF | XF)); - dr.w.l = (uint16_t)res; -} - -/*************************************************************** - * ADC HL,r16 - ***************************************************************/ -inline void z80_device::adc_hl(PAIR &r) -{ - uint32_t res = HLD + r.d + (F & CF); - WZ = HL + 1; - F = (((HLD ^ res ^ r.d) >> 8) & HF) | - ((res >> 16) & CF) | - ((res >> 8) & (SF | YF | XF)) | - ((res & 0xffff) ? 0 : ZF) | - (((r.d ^ HLD ^ 0x8000) & (r.d ^ res) & 0x8000) >> 13); - HL = (uint16_t)res; -} - -/*************************************************************** - * SBC HL,r16 - ***************************************************************/ -inline void z80_device::sbc_hl(PAIR &r) -{ - uint32_t res = HLD - r.d - (F & CF); - WZ = HL + 1; - F = (((HLD ^ res ^ r.d) >> 8) & HF) | NF | - ((res >> 16) & CF) | - ((res >> 8) & (SF | YF | XF)) | - ((res & 0xffff) ? 0 : ZF) | - (((r.d ^ HLD) & (HLD ^ res) &0x8000) >> 13); - HL = (uint16_t)res; + using std::swap; + swap(m_bc, m_bc2); + swap(m_de, m_de2); + swap(m_hl, m_hl2); } /*************************************************************** * RLC r8 ***************************************************************/ -inline uint8_t z80_device::rlc(uint8_t value) +u8 z80_device::rlc(u8 value) { unsigned res = value; unsigned c = (res & 0x80) ? CF : 0; res = ((res << 1) | (res >> 7)) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * RRC r8 ***************************************************************/ -inline uint8_t z80_device::rrc(uint8_t value) +u8 z80_device::rrc(u8 value) { unsigned res = value; unsigned c = (res & 0x01) ? CF : 0; res = ((res >> 1) | (res << 7)) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * RL r8 ***************************************************************/ -inline uint8_t z80_device::rl(uint8_t value) +u8 z80_device::rl(u8 value) { unsigned res = value; unsigned c = (res & 0x80) ? CF : 0; res = ((res << 1) | (F & CF)) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * RR r8 ***************************************************************/ -inline uint8_t z80_device::rr(uint8_t value) +u8 z80_device::rr(u8 value) { unsigned res = value; unsigned c = (res & 0x01) ? CF : 0; res = ((res >> 1) | (F << 7)) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * SLA r8 ***************************************************************/ -inline uint8_t z80_device::sla(uint8_t value) +u8 z80_device::sla(u8 value) { unsigned res = value; unsigned c = (res & 0x80) ? CF : 0; res = (res << 1) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * SRA r8 ***************************************************************/ -inline uint8_t z80_device::sra(uint8_t value) +u8 z80_device::sra(u8 value) { unsigned res = value; unsigned c = (res & 0x01) ? CF : 0; res = ((res >> 1) | (res & 0x80)) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * SLL r8 ***************************************************************/ -inline uint8_t z80_device::sll(uint8_t value) +u8 z80_device::sll(u8 value) { unsigned res = value; unsigned c = (res & 0x80) ? CF : 0; res = ((res << 1) | 0x01) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * SRL r8 ***************************************************************/ -inline uint8_t z80_device::srl(uint8_t value) +u8 z80_device::srl(u8 value) { unsigned res = value; unsigned c = (res & 0x01) ? CF : 0; res = (res >> 1) & 0xff; - F = SZP[res] | c; + set_f(SZP[res] | c); return res; } /*************************************************************** * BIT bit,r8 ***************************************************************/ -inline void z80_device::bit(int bit, uint8_t value) +void z80_device::bit(int bit, u8 value) { - F = (F & CF) | HF | (SZ_BIT[value & (1<<bit)] & ~(YF|XF)) | (value & (YF|XF)); + set_f((F & CF) | HF | (SZ_BIT[value & (1 << bit)] & ~(YF | XF)) | (value & (YF | XF))); } /*************************************************************** * BIT bit,(HL) ***************************************************************/ -inline void z80_device::bit_hl(int bit, uint8_t value) +void z80_device::bit_hl(int bit, u8 value) { - F = (F & CF) | HF | (SZ_BIT[value & (1<<bit)] & ~(YF|XF)) | (WZ_H & (YF|XF)); + set_f((F & CF) | HF | (SZ_BIT[value & (1 << bit)] & ~(YF | XF)) | (WZ_H & (YF | XF))); } /*************************************************************** * BIT bit,(IX/Y+o) ***************************************************************/ -inline void z80_device::bit_xy(int bit, uint8_t value) +void z80_device::bit_xy(int bit, u8 value) { - F = (F & CF) | HF | (SZ_BIT[value & (1<<bit)] & ~(YF|XF)) | ((m_ea>>8) & (YF|XF)); + set_f((F & CF) | HF | (SZ_BIT[value & (1 << bit)] & ~(YF | XF)) | ((m_ea >> 8) & (YF | XF))); } /*************************************************************** * RES bit,r8 ***************************************************************/ -inline uint8_t z80_device::res(int bit, uint8_t value) +u8 z80_device::res(int bit, u8 value) { - return value & ~(1<<bit); + return value & ~(1 << bit); } /*************************************************************** * SET bit,r8 ***************************************************************/ -inline uint8_t z80_device::set(int bit, uint8_t value) -{ - return value | (1<<bit); -} - -/*************************************************************** - * LDI - ***************************************************************/ -inline void z80_device::ldi() -{ - uint8_t io = rm(HL); - wm(DE, io); - F &= SF | ZF | CF; - if ((A + io) & 0x02) F |= YF; /* bit 1 -> flag 5 */ - if ((A + io) & 0x08) F |= XF; /* bit 3 -> flag 3 */ - HL++; DE++; BC--; - if(BC) F |= VF; -} - -/*************************************************************** - * CPI - ***************************************************************/ -inline void z80_device::cpi() +u8 z80_device::set(int bit, u8 value) { - uint8_t val = rm(HL); - uint8_t res = A - val; - WZ++; - HL++; BC--; - F = (F & CF) | (SZ[res]&~(YF|XF)) | ((A^val^res)&HF) | NF; - if (F & HF) res -= 1; - if (res & 0x02) F |= YF; /* bit 1 -> flag 5 */ - if (res & 0x08) F |= XF; /* bit 3 -> flag 3 */ - if (BC) F |= VF; + return value | (1 << bit); } -/*************************************************************** - * INI - ***************************************************************/ -inline void z80_device::ini() +void z80_device::block_io_interrupted_flags() { - unsigned t; - uint8_t io = in(BC); - WZ = BC + 1; - B--; - wm(HL, io); - HL++; - F = SZ[B]; - t = (unsigned)((C + 1) & 0xff) + (unsigned)io; - if (io & SF) F |= NF; - if (t & 0x100) F |= HF | CF; - F |= SZP[(uint8_t)(t & 0x07) ^ B] & PF; -} - -/*************************************************************** - * OUTI - ***************************************************************/ -inline void z80_device::outi() -{ - unsigned t; - uint8_t io = rm(HL); - B--; - WZ = BC + 1; - out(BC, io); - HL++; - F = SZ[B]; - t = (unsigned)L + (unsigned)io; - if (io & SF) F |= NF; - if (t & 0x100) F |= HF | CF; - F |= SZP[(uint8_t)(t & 0x07) ^ B] & PF; -} - -/*************************************************************** - * LDD - ***************************************************************/ -inline void z80_device::ldd() -{ - uint8_t io = rm(HL); - wm(DE, io); - F &= SF | ZF | CF; - if ((A + io) & 0x02) F |= YF; /* bit 1 -> flag 5 */ - if ((A + io) & 0x08) F |= XF; /* bit 3 -> flag 3 */ - HL--; DE--; BC--; - if (BC) F |= VF; -} - -/*************************************************************** - * CPD - ***************************************************************/ -inline void z80_device::cpd() -{ - uint8_t val = rm(HL); - uint8_t res = A - val; - WZ--; - HL--; BC--; - F = (F & CF) | (SZ[res]&~(YF|XF)) | ((A^val^res)&HF) | NF; - if (F & HF) res -= 1; - if (res & 0x02) F |= YF; /* bit 1 -> flag 5 */ - if (res & 0x08) F |= XF; /* bit 3 -> flag 3 */ - if (BC) F |= VF; -} - -/*************************************************************** - * IND - ***************************************************************/ -inline void z80_device::ind() -{ - unsigned t; - uint8_t io = in(BC); - WZ = BC - 1; - B--; - wm(HL, io); - HL--; - F = SZ[B]; - t = ((unsigned)(C - 1) & 0xff) + (unsigned)io; - if (io & SF) F |= NF; - if (t & 0x100) F |= HF | CF; - F |= SZP[(uint8_t)(t & 0x07) ^ B] & PF; -} - -/*************************************************************** - * OUTD - ***************************************************************/ -inline void z80_device::outd() -{ - unsigned t; - uint8_t io = rm(HL); - B--; - WZ = BC - 1; - out(BC, io); - HL--; - F = SZ[B]; - t = (unsigned)L + (unsigned)io; - if (io & SF) F |= NF; - if (t & 0x100) F |= HF | CF; - F |= SZP[(uint8_t)(t & 0x07) ^ B] & PF; -} - -/*************************************************************** - * LDIR - ***************************************************************/ -inline void z80_device::ldir() -{ - ldi(); - if (BC != 0) + F &= ~(YF | XF); + F |= (PC >> 8) & (YF | XF); + if (F & CF) { - PC -= 2; - WZ = PC + 1; - CC(ex, 0xb0); - } -} - -/*************************************************************** - * CPIR - ***************************************************************/ -inline void z80_device::cpir() -{ - cpi(); - if (BC != 0 && !(F & ZF)) - { - PC -= 2; - WZ = PC + 1; - CC(ex, 0xb1); - } -} - -/*************************************************************** - * INIR - ***************************************************************/ -inline void z80_device::inir() -{ - ini(); - if (B != 0) - { - PC -= 2; - CC(ex, 0xb2); - } -} - -/*************************************************************** - * OTIR - ***************************************************************/ -inline void z80_device::otir() -{ - outi(); - if (B != 0) - { - PC -= 2; - CC(ex, 0xb3); - } -} - -/*************************************************************** - * LDDR - ***************************************************************/ -inline void z80_device::lddr() -{ - ldd(); - if (BC != 0) - { - PC -= 2; - WZ = PC + 1; - CC(ex, 0xb8); - } -} - -/*************************************************************** - * CPDR - ***************************************************************/ -inline void z80_device::cpdr() -{ - cpd(); - if (BC != 0 && !(F & ZF)) - { - PC -= 2; - WZ = PC + 1; - CC(ex, 0xb9); - } -} - -/*************************************************************** - * INDR - ***************************************************************/ -inline void z80_device::indr() -{ - ind(); - if (B != 0) - { - PC -= 2; - CC(ex, 0xba); + F &= ~HF; + if (TDAT8 & 0x80) + { + F ^= (SZP[(B - 1) & 0x07] ^ PF) & PF; + if ((B & 0x0f) == 0x00) F |= HF; + } + else + { + F ^= (SZP[(B + 1) & 0x07] ^ PF) & PF; + if ((B & 0x0f) == 0x0f) F |= HF; + } } -} - -/*************************************************************** - * OTDR - ***************************************************************/ -inline void z80_device::otdr() -{ - outd(); - if (B != 0) + else { - PC -= 2; - CC(ex, 0xbb); + F ^=(SZP[B & 0x07] ^ PF) & PF; } } /*************************************************************** * EI ***************************************************************/ -inline void z80_device::ei() +void z80_device::ei() { m_iff1 = m_iff2 = 1; - m_after_ei = true; -} - -/********************************************************** - * opcodes with CB prefix - * rotate, shift and bit operations - **********************************************************/ -OP(cb,00) { B = rlc(B); } /* RLC B */ -OP(cb,01) { C = rlc(C); } /* RLC C */ -OP(cb,02) { D = rlc(D); } /* RLC D */ -OP(cb,03) { E = rlc(E); } /* RLC E */ -OP(cb,04) { H = rlc(H); } /* RLC H */ -OP(cb,05) { L = rlc(L); } /* RLC L */ -OP(cb,06) { wm(HL, rlc(rm(HL))); } /* RLC (HL) */ -OP(cb,07) { A = rlc(A); } /* RLC A */ - -OP(cb,08) { B = rrc(B); } /* RRC B */ -OP(cb,09) { C = rrc(C); } /* RRC C */ -OP(cb,0a) { D = rrc(D); } /* RRC D */ -OP(cb,0b) { E = rrc(E); } /* RRC E */ -OP(cb,0c) { H = rrc(H); } /* RRC H */ -OP(cb,0d) { L = rrc(L); } /* RRC L */ -OP(cb,0e) { wm(HL, rrc(rm(HL))); } /* RRC (HL) */ -OP(cb,0f) { A = rrc(A); } /* RRC A */ - -OP(cb,10) { B = rl(B); } /* RL B */ -OP(cb,11) { C = rl(C); } /* RL C */ -OP(cb,12) { D = rl(D); } /* RL D */ -OP(cb,13) { E = rl(E); } /* RL E */ -OP(cb,14) { H = rl(H); } /* RL H */ -OP(cb,15) { L = rl(L); } /* RL L */ -OP(cb,16) { wm(HL, rl(rm(HL))); } /* RL (HL) */ -OP(cb,17) { A = rl(A); } /* RL A */ - -OP(cb,18) { B = rr(B); } /* RR B */ -OP(cb,19) { C = rr(C); } /* RR C */ -OP(cb,1a) { D = rr(D); } /* RR D */ -OP(cb,1b) { E = rr(E); } /* RR E */ -OP(cb,1c) { H = rr(H); } /* RR H */ -OP(cb,1d) { L = rr(L); } /* RR L */ -OP(cb,1e) { wm(HL, rr(rm(HL))); } /* RR (HL) */ -OP(cb,1f) { A = rr(A); } /* RR A */ - -OP(cb,20) { B = sla(B); } /* SLA B */ -OP(cb,21) { C = sla(C); } /* SLA C */ -OP(cb,22) { D = sla(D); } /* SLA D */ -OP(cb,23) { E = sla(E); } /* SLA E */ -OP(cb,24) { H = sla(H); } /* SLA H */ -OP(cb,25) { L = sla(L); } /* SLA L */ -OP(cb,26) { wm(HL, sla(rm(HL))); } /* SLA (HL) */ -OP(cb,27) { A = sla(A); } /* SLA A */ - -OP(cb,28) { B = sra(B); } /* SRA B */ -OP(cb,29) { C = sra(C); } /* SRA C */ -OP(cb,2a) { D = sra(D); } /* SRA D */ -OP(cb,2b) { E = sra(E); } /* SRA E */ -OP(cb,2c) { H = sra(H); } /* SRA H */ -OP(cb,2d) { L = sra(L); } /* SRA L */ -OP(cb,2e) { wm(HL, sra(rm(HL))); } /* SRA (HL) */ -OP(cb,2f) { A = sra(A); } /* SRA A */ - -OP(cb,30) { B = sll(B); } /* SLL B */ -OP(cb,31) { C = sll(C); } /* SLL C */ -OP(cb,32) { D = sll(D); } /* SLL D */ -OP(cb,33) { E = sll(E); } /* SLL E */ -OP(cb,34) { H = sll(H); } /* SLL H */ -OP(cb,35) { L = sll(L); } /* SLL L */ -OP(cb,36) { wm(HL, sll(rm(HL))); } /* SLL (HL) */ -OP(cb,37) { A = sll(A); } /* SLL A */ - -OP(cb,38) { B = srl(B); } /* SRL B */ -OP(cb,39) { C = srl(C); } /* SRL C */ -OP(cb,3a) { D = srl(D); } /* SRL D */ -OP(cb,3b) { E = srl(E); } /* SRL E */ -OP(cb,3c) { H = srl(H); } /* SRL H */ -OP(cb,3d) { L = srl(L); } /* SRL L */ -OP(cb,3e) { wm(HL, srl(rm(HL))); } /* SRL (HL) */ -OP(cb,3f) { A = srl(A); } /* SRL A */ - -OP(cb,40) { bit(0, B); } /* BIT 0,B */ -OP(cb,41) { bit(0, C); } /* BIT 0,C */ -OP(cb,42) { bit(0, D); } /* BIT 0,D */ -OP(cb,43) { bit(0, E); } /* BIT 0,E */ -OP(cb,44) { bit(0, H); } /* BIT 0,H */ -OP(cb,45) { bit(0, L); } /* BIT 0,L */ -OP(cb,46) { bit_hl(0, rm(HL)); } /* BIT 0,(HL) */ -OP(cb,47) { bit(0, A); } /* BIT 0,A */ - -OP(cb,48) { bit(1, B); } /* BIT 1,B */ -OP(cb,49) { bit(1, C); } /* BIT 1,C */ -OP(cb,4a) { bit(1, D); } /* BIT 1,D */ -OP(cb,4b) { bit(1, E); } /* BIT 1,E */ -OP(cb,4c) { bit(1, H); } /* BIT 1,H */ -OP(cb,4d) { bit(1, L); } /* BIT 1,L */ -OP(cb,4e) { bit_hl(1, rm(HL)); } /* BIT 1,(HL) */ -OP(cb,4f) { bit(1, A); } /* BIT 1,A */ - -OP(cb,50) { bit(2, B); } /* BIT 2,B */ -OP(cb,51) { bit(2, C); } /* BIT 2,C */ -OP(cb,52) { bit(2, D); } /* BIT 2,D */ -OP(cb,53) { bit(2, E); } /* BIT 2,E */ -OP(cb,54) { bit(2, H); } /* BIT 2,H */ -OP(cb,55) { bit(2, L); } /* BIT 2,L */ -OP(cb,56) { bit_hl(2, rm(HL)); } /* BIT 2,(HL) */ -OP(cb,57) { bit(2, A); } /* BIT 2,A */ - -OP(cb,58) { bit(3, B); } /* BIT 3,B */ -OP(cb,59) { bit(3, C); } /* BIT 3,C */ -OP(cb,5a) { bit(3, D); } /* BIT 3,D */ -OP(cb,5b) { bit(3, E); } /* BIT 3,E */ -OP(cb,5c) { bit(3, H); } /* BIT 3,H */ -OP(cb,5d) { bit(3, L); } /* BIT 3,L */ -OP(cb,5e) { bit_hl(3, rm(HL)); } /* BIT 3,(HL) */ -OP(cb,5f) { bit(3, A); } /* BIT 3,A */ - -OP(cb,60) { bit(4, B); } /* BIT 4,B */ -OP(cb,61) { bit(4, C); } /* BIT 4,C */ -OP(cb,62) { bit(4, D); } /* BIT 4,D */ -OP(cb,63) { bit(4, E); } /* BIT 4,E */ -OP(cb,64) { bit(4, H); } /* BIT 4,H */ -OP(cb,65) { bit(4, L); } /* BIT 4,L */ -OP(cb,66) { bit_hl(4, rm(HL)); } /* BIT 4,(HL) */ -OP(cb,67) { bit(4, A); } /* BIT 4,A */ - -OP(cb,68) { bit(5, B); } /* BIT 5,B */ -OP(cb,69) { bit(5, C); } /* BIT 5,C */ -OP(cb,6a) { bit(5, D); } /* BIT 5,D */ -OP(cb,6b) { bit(5, E); } /* BIT 5,E */ -OP(cb,6c) { bit(5, H); } /* BIT 5,H */ -OP(cb,6d) { bit(5, L); } /* BIT 5,L */ -OP(cb,6e) { bit_hl(5, rm(HL)); } /* BIT 5,(HL) */ -OP(cb,6f) { bit(5, A); } /* BIT 5,A */ - -OP(cb,70) { bit(6, B); } /* BIT 6,B */ -OP(cb,71) { bit(6, C); } /* BIT 6,C */ -OP(cb,72) { bit(6, D); } /* BIT 6,D */ -OP(cb,73) { bit(6, E); } /* BIT 6,E */ -OP(cb,74) { bit(6, H); } /* BIT 6,H */ -OP(cb,75) { bit(6, L); } /* BIT 6,L */ -OP(cb,76) { bit_hl(6, rm(HL)); } /* BIT 6,(HL) */ -OP(cb,77) { bit(6, A); } /* BIT 6,A */ - -OP(cb,78) { bit(7, B); } /* BIT 7,B */ -OP(cb,79) { bit(7, C); } /* BIT 7,C */ -OP(cb,7a) { bit(7, D); } /* BIT 7,D */ -OP(cb,7b) { bit(7, E); } /* BIT 7,E */ -OP(cb,7c) { bit(7, H); } /* BIT 7,H */ -OP(cb,7d) { bit(7, L); } /* BIT 7,L */ -OP(cb,7e) { bit_hl(7, rm(HL)); } /* BIT 7,(HL) */ -OP(cb,7f) { bit(7, A); } /* BIT 7,A */ - -OP(cb,80) { B = res(0, B); } /* RES 0,B */ -OP(cb,81) { C = res(0, C); } /* RES 0,C */ -OP(cb,82) { D = res(0, D); } /* RES 0,D */ -OP(cb,83) { E = res(0, E); } /* RES 0,E */ -OP(cb,84) { H = res(0, H); } /* RES 0,H */ -OP(cb,85) { L = res(0, L); } /* RES 0,L */ -OP(cb,86) { wm(HL, res(0, rm(HL))); } /* RES 0,(HL) */ -OP(cb,87) { A = res(0, A); } /* RES 0,A */ - -OP(cb,88) { B = res(1, B); } /* RES 1,B */ -OP(cb,89) { C = res(1, C); } /* RES 1,C */ -OP(cb,8a) { D = res(1, D); } /* RES 1,D */ -OP(cb,8b) { E = res(1, E); } /* RES 1,E */ -OP(cb,8c) { H = res(1, H); } /* RES 1,H */ -OP(cb,8d) { L = res(1, L); } /* RES 1,L */ -OP(cb,8e) { wm(HL, res(1, rm(HL))); } /* RES 1,(HL) */ -OP(cb,8f) { A = res(1, A); } /* RES 1,A */ - -OP(cb,90) { B = res(2, B); } /* RES 2,B */ -OP(cb,91) { C = res(2, C); } /* RES 2,C */ -OP(cb,92) { D = res(2, D); } /* RES 2,D */ -OP(cb,93) { E = res(2, E); } /* RES 2,E */ -OP(cb,94) { H = res(2, H); } /* RES 2,H */ -OP(cb,95) { L = res(2, L); } /* RES 2,L */ -OP(cb,96) { wm(HL, res(2, rm(HL))); } /* RES 2,(HL) */ -OP(cb,97) { A = res(2, A); } /* RES 2,A */ - -OP(cb,98) { B = res(3, B); } /* RES 3,B */ -OP(cb,99) { C = res(3, C); } /* RES 3,C */ -OP(cb,9a) { D = res(3, D); } /* RES 3,D */ -OP(cb,9b) { E = res(3, E); } /* RES 3,E */ -OP(cb,9c) { H = res(3, H); } /* RES 3,H */ -OP(cb,9d) { L = res(3, L); } /* RES 3,L */ -OP(cb,9e) { wm(HL, res(3, rm(HL))); } /* RES 3,(HL) */ -OP(cb,9f) { A = res(3, A); } /* RES 3,A */ - -OP(cb,a0) { B = res(4, B); } /* RES 4,B */ -OP(cb,a1) { C = res(4, C); } /* RES 4,C */ -OP(cb,a2) { D = res(4, D); } /* RES 4,D */ -OP(cb,a3) { E = res(4, E); } /* RES 4,E */ -OP(cb,a4) { H = res(4, H); } /* RES 4,H */ -OP(cb,a5) { L = res(4, L); } /* RES 4,L */ -OP(cb,a6) { wm(HL, res(4, rm(HL))); } /* RES 4,(HL) */ -OP(cb,a7) { A = res(4, A); } /* RES 4,A */ - -OP(cb,a8) { B = res(5, B); } /* RES 5,B */ -OP(cb,a9) { C = res(5, C); } /* RES 5,C */ -OP(cb,aa) { D = res(5, D); } /* RES 5,D */ -OP(cb,ab) { E = res(5, E); } /* RES 5,E */ -OP(cb,ac) { H = res(5, H); } /* RES 5,H */ -OP(cb,ad) { L = res(5, L); } /* RES 5,L */ -OP(cb,ae) { wm(HL, res(5, rm(HL))); } /* RES 5,(HL) */ -OP(cb,af) { A = res(5, A); } /* RES 5,A */ - -OP(cb,b0) { B = res(6, B); } /* RES 6,B */ -OP(cb,b1) { C = res(6, C); } /* RES 6,C */ -OP(cb,b2) { D = res(6, D); } /* RES 6,D */ -OP(cb,b3) { E = res(6, E); } /* RES 6,E */ -OP(cb,b4) { H = res(6, H); } /* RES 6,H */ -OP(cb,b5) { L = res(6, L); } /* RES 6,L */ -OP(cb,b6) { wm(HL, res(6, rm(HL))); } /* RES 6,(HL) */ -OP(cb,b7) { A = res(6, A); } /* RES 6,A */ - -OP(cb,b8) { B = res(7, B); } /* RES 7,B */ -OP(cb,b9) { C = res(7, C); } /* RES 7,C */ -OP(cb,ba) { D = res(7, D); } /* RES 7,D */ -OP(cb,bb) { E = res(7, E); } /* RES 7,E */ -OP(cb,bc) { H = res(7, H); } /* RES 7,H */ -OP(cb,bd) { L = res(7, L); } /* RES 7,L */ -OP(cb,be) { wm(HL, res(7, rm(HL))); } /* RES 7,(HL) */ -OP(cb,bf) { A = res(7, A); } /* RES 7,A */ - -OP(cb,c0) { B = set(0, B); } /* SET 0,B */ -OP(cb,c1) { C = set(0, C); } /* SET 0,C */ -OP(cb,c2) { D = set(0, D); } /* SET 0,D */ -OP(cb,c3) { E = set(0, E); } /* SET 0,E */ -OP(cb,c4) { H = set(0, H); } /* SET 0,H */ -OP(cb,c5) { L = set(0, L); } /* SET 0,L */ -OP(cb,c6) { wm(HL, set(0, rm(HL))); } /* SET 0,(HL) */ -OP(cb,c7) { A = set(0, A); } /* SET 0,A */ - -OP(cb,c8) { B = set(1, B); } /* SET 1,B */ -OP(cb,c9) { C = set(1, C); } /* SET 1,C */ -OP(cb,ca) { D = set(1, D); } /* SET 1,D */ -OP(cb,cb) { E = set(1, E); } /* SET 1,E */ -OP(cb,cc) { H = set(1, H); } /* SET 1,H */ -OP(cb,cd) { L = set(1, L); } /* SET 1,L */ -OP(cb,ce) { wm(HL, set(1, rm(HL))); } /* SET 1,(HL) */ -OP(cb,cf) { A = set(1, A); } /* SET 1,A */ - -OP(cb,d0) { B = set(2, B); } /* SET 2,B */ -OP(cb,d1) { C = set(2, C); } /* SET 2,C */ -OP(cb,d2) { D = set(2, D); } /* SET 2,D */ -OP(cb,d3) { E = set(2, E); } /* SET 2,E */ -OP(cb,d4) { H = set(2, H); } /* SET 2,H */ -OP(cb,d5) { L = set(2, L); } /* SET 2,L */ -OP(cb,d6) { wm(HL, set(2, rm(HL))); } /* SET 2,(HL) */ -OP(cb,d7) { A = set(2, A); } /* SET 2,A */ - -OP(cb,d8) { B = set(3, B); } /* SET 3,B */ -OP(cb,d9) { C = set(3, C); } /* SET 3,C */ -OP(cb,da) { D = set(3, D); } /* SET 3,D */ -OP(cb,db) { E = set(3, E); } /* SET 3,E */ -OP(cb,dc) { H = set(3, H); } /* SET 3,H */ -OP(cb,dd) { L = set(3, L); } /* SET 3,L */ -OP(cb,de) { wm(HL, set(3, rm(HL))); } /* SET 3,(HL) */ -OP(cb,df) { A = set(3, A); } /* SET 3,A */ - -OP(cb,e0) { B = set(4, B); } /* SET 4,B */ -OP(cb,e1) { C = set(4, C); } /* SET 4,C */ -OP(cb,e2) { D = set(4, D); } /* SET 4,D */ -OP(cb,e3) { E = set(4, E); } /* SET 4,E */ -OP(cb,e4) { H = set(4, H); } /* SET 4,H */ -OP(cb,e5) { L = set(4, L); } /* SET 4,L */ -OP(cb,e6) { wm(HL, set(4, rm(HL))); } /* SET 4,(HL) */ -OP(cb,e7) { A = set(4, A); } /* SET 4,A */ - -OP(cb,e8) { B = set(5, B); } /* SET 5,B */ -OP(cb,e9) { C = set(5, C); } /* SET 5,C */ -OP(cb,ea) { D = set(5, D); } /* SET 5,D */ -OP(cb,eb) { E = set(5, E); } /* SET 5,E */ -OP(cb,ec) { H = set(5, H); } /* SET 5,H */ -OP(cb,ed) { L = set(5, L); } /* SET 5,L */ -OP(cb,ee) { wm(HL, set(5, rm(HL))); } /* SET 5,(HL) */ -OP(cb,ef) { A = set(5, A); } /* SET 5,A */ - -OP(cb,f0) { B = set(6, B); } /* SET 6,B */ -OP(cb,f1) { C = set(6, C); } /* SET 6,C */ -OP(cb,f2) { D = set(6, D); } /* SET 6,D */ -OP(cb,f3) { E = set(6, E); } /* SET 6,E */ -OP(cb,f4) { H = set(6, H); } /* SET 6,H */ -OP(cb,f5) { L = set(6, L); } /* SET 6,L */ -OP(cb,f6) { wm(HL, set(6, rm(HL))); } /* SET 6,(HL) */ -OP(cb,f7) { A = set(6, A); } /* SET 6,A */ - -OP(cb,f8) { B = set(7, B); } /* SET 7,B */ -OP(cb,f9) { C = set(7, C); } /* SET 7,C */ -OP(cb,fa) { D = set(7, D); } /* SET 7,D */ -OP(cb,fb) { E = set(7, E); } /* SET 7,E */ -OP(cb,fc) { H = set(7, H); } /* SET 7,H */ -OP(cb,fd) { L = set(7, L); } /* SET 7,L */ -OP(cb,fe) { wm(HL, set(7, rm(HL))); } /* SET 7,(HL) */ -OP(cb,ff) { A = set(7, A); } /* SET 7,A */ - - -/********************************************************** -* opcodes with DD/FD CB prefix -* rotate, shift and bit operations with (IX+o) -**********************************************************/ -OP(xycb,00) { B = rlc(rm(m_ea)); wm(m_ea, B); } /* RLC B=(XY+o) */ -OP(xycb,01) { C = rlc(rm(m_ea)); wm(m_ea, C); } /* RLC C=(XY+o) */ -OP(xycb,02) { D = rlc(rm(m_ea)); wm(m_ea, D); } /* RLC D=(XY+o) */ -OP(xycb,03) { E = rlc(rm(m_ea)); wm(m_ea, E); } /* RLC E=(XY+o) */ -OP(xycb,04) { H = rlc(rm(m_ea)); wm(m_ea, H); } /* RLC H=(XY+o) */ -OP(xycb,05) { L = rlc(rm(m_ea)); wm(m_ea, L); } /* RLC L=(XY+o) */ -OP(xycb,06) { wm(m_ea, rlc(rm(m_ea))); } /* RLC (XY+o) */ -OP(xycb,07) { A = rlc(rm(m_ea)); wm(m_ea, A); } /* RLC A=(XY+o) */ - -OP(xycb,08) { B = rrc(rm(m_ea)); wm(m_ea, B); } /* RRC B=(XY+o) */ -OP(xycb,09) { C = rrc(rm(m_ea)); wm(m_ea, C); } /* RRC C=(XY+o) */ -OP(xycb,0a) { D = rrc(rm(m_ea)); wm(m_ea, D); } /* RRC D=(XY+o) */ -OP(xycb,0b) { E = rrc(rm(m_ea)); wm(m_ea, E); } /* RRC E=(XY+o) */ -OP(xycb,0c) { H = rrc(rm(m_ea)); wm(m_ea, H); } /* RRC H=(XY+o) */ -OP(xycb,0d) { L = rrc(rm(m_ea)); wm(m_ea, L); } /* RRC L=(XY+o) */ -OP(xycb,0e) { wm(m_ea,rrc(rm(m_ea))); } /* RRC (XY+o) */ -OP(xycb,0f) { A = rrc(rm(m_ea)); wm(m_ea, A); } /* RRC A=(XY+o) */ - -OP(xycb,10) { B = rl(rm(m_ea)); wm(m_ea, B); } /* RL B=(XY+o) */ -OP(xycb,11) { C = rl(rm(m_ea)); wm(m_ea, C); } /* RL C=(XY+o) */ -OP(xycb,12) { D = rl(rm(m_ea)); wm(m_ea, D); } /* RL D=(XY+o) */ -OP(xycb,13) { E = rl(rm(m_ea)); wm(m_ea, E); } /* RL E=(XY+o) */ -OP(xycb,14) { H = rl(rm(m_ea)); wm(m_ea, H); } /* RL H=(XY+o) */ -OP(xycb,15) { L = rl(rm(m_ea)); wm(m_ea, L); } /* RL L=(XY+o) */ -OP(xycb,16) { wm(m_ea,rl(rm(m_ea))); } /* RL (XY+o) */ -OP(xycb,17) { A = rl(rm(m_ea)); wm(m_ea, A); } /* RL A=(XY+o) */ - -OP(xycb,18) { B = rr(rm(m_ea)); wm(m_ea, B); } /* RR B=(XY+o) */ -OP(xycb,19) { C = rr(rm(m_ea)); wm(m_ea, C); } /* RR C=(XY+o) */ -OP(xycb,1a) { D = rr(rm(m_ea)); wm(m_ea, D); } /* RR D=(XY+o) */ -OP(xycb,1b) { E = rr(rm(m_ea)); wm(m_ea, E); } /* RR E=(XY+o) */ -OP(xycb,1c) { H = rr(rm(m_ea)); wm(m_ea, H); } /* RR H=(XY+o) */ -OP(xycb,1d) { L = rr(rm(m_ea)); wm(m_ea, L); } /* RR L=(XY+o) */ -OP(xycb,1e) { wm(m_ea, rr(rm(m_ea))); } /* RR (XY+o) */ -OP(xycb,1f) { A = rr(rm(m_ea)); wm(m_ea, A); } /* RR A=(XY+o) */ - -OP(xycb,20) { B = sla(rm(m_ea)); wm(m_ea, B); } /* SLA B=(XY+o) */ -OP(xycb,21) { C = sla(rm(m_ea)); wm(m_ea, C); } /* SLA C=(XY+o) */ -OP(xycb,22) { D = sla(rm(m_ea)); wm(m_ea, D); } /* SLA D=(XY+o) */ -OP(xycb,23) { E = sla(rm(m_ea)); wm(m_ea, E); } /* SLA E=(XY+o) */ -OP(xycb,24) { H = sla(rm(m_ea)); wm(m_ea, H); } /* SLA H=(XY+o) */ -OP(xycb,25) { L = sla(rm(m_ea)); wm(m_ea, L); } /* SLA L=(XY+o) */ -OP(xycb,26) { wm(m_ea, sla(rm(m_ea))); } /* SLA (XY+o) */ -OP(xycb,27) { A = sla(rm(m_ea)); wm(m_ea, A); } /* SLA A=(XY+o) */ - -OP(xycb,28) { B = sra(rm(m_ea)); wm(m_ea, B); } /* SRA B=(XY+o) */ -OP(xycb,29) { C = sra(rm(m_ea)); wm(m_ea, C); } /* SRA C=(XY+o) */ -OP(xycb,2a) { D = sra(rm(m_ea)); wm(m_ea, D); } /* SRA D=(XY+o) */ -OP(xycb,2b) { E = sra(rm(m_ea)); wm(m_ea, E); } /* SRA E=(XY+o) */ -OP(xycb,2c) { H = sra(rm(m_ea)); wm(m_ea, H); } /* SRA H=(XY+o) */ -OP(xycb,2d) { L = sra(rm(m_ea)); wm(m_ea, L); } /* SRA L=(XY+o) */ -OP(xycb,2e) { wm(m_ea, sra(rm(m_ea))); } /* SRA (XY+o) */ -OP(xycb,2f) { A = sra(rm(m_ea)); wm(m_ea, A); } /* SRA A=(XY+o) */ - -OP(xycb,30) { B = sll(rm(m_ea)); wm(m_ea, B); } /* SLL B=(XY+o) */ -OP(xycb,31) { C = sll(rm(m_ea)); wm(m_ea, C); } /* SLL C=(XY+o) */ -OP(xycb,32) { D = sll(rm(m_ea)); wm(m_ea, D); } /* SLL D=(XY+o) */ -OP(xycb,33) { E = sll(rm(m_ea)); wm(m_ea, E); } /* SLL E=(XY+o) */ -OP(xycb,34) { H = sll(rm(m_ea)); wm(m_ea, H); } /* SLL H=(XY+o) */ -OP(xycb,35) { L = sll(rm(m_ea)); wm(m_ea, L); } /* SLL L=(XY+o) */ -OP(xycb,36) { wm(m_ea, sll(rm(m_ea))); } /* SLL (XY+o) */ -OP(xycb,37) { A = sll(rm(m_ea)); wm(m_ea, A); } /* SLL A=(XY+o) */ - -OP(xycb,38) { B = srl(rm(m_ea)); wm(m_ea, B); } /* SRL B=(XY+o) */ -OP(xycb,39) { C = srl(rm(m_ea)); wm(m_ea, C); } /* SRL C=(XY+o) */ -OP(xycb,3a) { D = srl(rm(m_ea)); wm(m_ea, D); } /* SRL D=(XY+o) */ -OP(xycb,3b) { E = srl(rm(m_ea)); wm(m_ea, E); } /* SRL E=(XY+o) */ -OP(xycb,3c) { H = srl(rm(m_ea)); wm(m_ea, H); } /* SRL H=(XY+o) */ -OP(xycb,3d) { L = srl(rm(m_ea)); wm(m_ea, L); } /* SRL L=(XY+o) */ -OP(xycb,3e) { wm(m_ea, srl(rm(m_ea))); } /* SRL (XY+o) */ -OP(xycb,3f) { A = srl(rm(m_ea)); wm(m_ea, A); } /* SRL A=(XY+o) */ - -OP(xycb,40) { xycb_46(); } /* BIT 0,(XY+o) */ -OP(xycb,41) { xycb_46(); } /* BIT 0,(XY+o) */ -OP(xycb,42) { xycb_46(); } /* BIT 0,(XY+o) */ -OP(xycb,43) { xycb_46(); } /* BIT 0,(XY+o) */ -OP(xycb,44) { xycb_46(); } /* BIT 0,(XY+o) */ -OP(xycb,45) { xycb_46(); } /* BIT 0,(XY+o) */ -OP(xycb,46) { bit_xy(0, rm(m_ea)); } /* BIT 0,(XY+o) */ -OP(xycb,47) { xycb_46(); } /* BIT 0,(XY+o) */ - -OP(xycb,48) { xycb_4e(); } /* BIT 1,(XY+o) */ -OP(xycb,49) { xycb_4e(); } /* BIT 1,(XY+o) */ -OP(xycb,4a) { xycb_4e(); } /* BIT 1,(XY+o) */ -OP(xycb,4b) { xycb_4e(); } /* BIT 1,(XY+o) */ -OP(xycb,4c) { xycb_4e(); } /* BIT 1,(XY+o) */ -OP(xycb,4d) { xycb_4e(); } /* BIT 1,(XY+o) */ -OP(xycb,4e) { bit_xy(1, rm(m_ea)); } /* BIT 1,(XY+o) */ -OP(xycb,4f) { xycb_4e(); } /* BIT 1,(XY+o) */ - -OP(xycb,50) { xycb_56(); } /* BIT 2,(XY+o) */ -OP(xycb,51) { xycb_56(); } /* BIT 2,(XY+o) */ -OP(xycb,52) { xycb_56(); } /* BIT 2,(XY+o) */ -OP(xycb,53) { xycb_56(); } /* BIT 2,(XY+o) */ -OP(xycb,54) { xycb_56(); } /* BIT 2,(XY+o) */ -OP(xycb,55) { xycb_56(); } /* BIT 2,(XY+o) */ -OP(xycb,56) { bit_xy(2, rm(m_ea)); } /* BIT 2,(XY+o) */ -OP(xycb,57) { xycb_56(); } /* BIT 2,(XY+o) */ - -OP(xycb,58) { xycb_5e(); } /* BIT 3,(XY+o) */ -OP(xycb,59) { xycb_5e(); } /* BIT 3,(XY+o) */ -OP(xycb,5a) { xycb_5e(); } /* BIT 3,(XY+o) */ -OP(xycb,5b) { xycb_5e(); } /* BIT 3,(XY+o) */ -OP(xycb,5c) { xycb_5e(); } /* BIT 3,(XY+o) */ -OP(xycb,5d) { xycb_5e(); } /* BIT 3,(XY+o) */ -OP(xycb,5e) { bit_xy(3, rm(m_ea)); } /* BIT 3,(XY+o) */ -OP(xycb,5f) { xycb_5e(); } /* BIT 3,(XY+o) */ - -OP(xycb,60) { xycb_66(); } /* BIT 4,(XY+o) */ -OP(xycb,61) { xycb_66(); } /* BIT 4,(XY+o) */ -OP(xycb,62) { xycb_66(); } /* BIT 4,(XY+o) */ -OP(xycb,63) { xycb_66(); } /* BIT 4,(XY+o) */ -OP(xycb,64) { xycb_66(); } /* BIT 4,(XY+o) */ -OP(xycb,65) { xycb_66(); } /* BIT 4,(XY+o) */ -OP(xycb,66) { bit_xy(4, rm(m_ea)); } /* BIT 4,(XY+o) */ -OP(xycb,67) { xycb_66(); } /* BIT 4,(XY+o) */ - -OP(xycb,68) { xycb_6e(); } /* BIT 5,(XY+o) */ -OP(xycb,69) { xycb_6e(); } /* BIT 5,(XY+o) */ -OP(xycb,6a) { xycb_6e(); } /* BIT 5,(XY+o) */ -OP(xycb,6b) { xycb_6e(); } /* BIT 5,(XY+o) */ -OP(xycb,6c) { xycb_6e(); } /* BIT 5,(XY+o) */ -OP(xycb,6d) { xycb_6e(); } /* BIT 5,(XY+o) */ -OP(xycb,6e) { bit_xy(5, rm(m_ea)); } /* BIT 5,(XY+o) */ -OP(xycb,6f) { xycb_6e(); } /* BIT 5,(XY+o) */ - -OP(xycb,70) { xycb_76(); } /* BIT 6,(XY+o) */ -OP(xycb,71) { xycb_76(); } /* BIT 6,(XY+o) */ -OP(xycb,72) { xycb_76(); } /* BIT 6,(XY+o) */ -OP(xycb,73) { xycb_76(); } /* BIT 6,(XY+o) */ -OP(xycb,74) { xycb_76(); } /* BIT 6,(XY+o) */ -OP(xycb,75) { xycb_76(); } /* BIT 6,(XY+o) */ -OP(xycb,76) { bit_xy(6, rm(m_ea)); } /* BIT 6,(XY+o) */ -OP(xycb,77) { xycb_76(); } /* BIT 6,(XY+o) */ - -OP(xycb,78) { xycb_7e(); } /* BIT 7,(XY+o) */ -OP(xycb,79) { xycb_7e(); } /* BIT 7,(XY+o) */ -OP(xycb,7a) { xycb_7e(); } /* BIT 7,(XY+o) */ -OP(xycb,7b) { xycb_7e(); } /* BIT 7,(XY+o) */ -OP(xycb,7c) { xycb_7e(); } /* BIT 7,(XY+o) */ -OP(xycb,7d) { xycb_7e(); } /* BIT 7,(XY+o) */ -OP(xycb,7e) { bit_xy(7, rm(m_ea)); } /* BIT 7,(XY+o) */ -OP(xycb,7f) { xycb_7e(); } /* BIT 7,(XY+o) */ - -OP(xycb,80) { B = res(0, rm(m_ea)); wm(m_ea, B); } /* RES 0,B=(XY+o) */ -OP(xycb,81) { C = res(0, rm(m_ea)); wm(m_ea, C); } /* RES 0,C=(XY+o) */ -OP(xycb,82) { D = res(0, rm(m_ea)); wm(m_ea, D); } /* RES 0,D=(XY+o) */ -OP(xycb,83) { E = res(0, rm(m_ea)); wm(m_ea, E); } /* RES 0,E=(XY+o) */ -OP(xycb,84) { H = res(0, rm(m_ea)); wm(m_ea, H); } /* RES 0,H=(XY+o) */ -OP(xycb,85) { L = res(0, rm(m_ea)); wm(m_ea, L); } /* RES 0,L=(XY+o) */ -OP(xycb,86) { wm(m_ea, res(0, rm(m_ea))); } /* RES 0,(XY+o) */ -OP(xycb,87) { A = res(0, rm(m_ea)); wm(m_ea, A); } /* RES 0,A=(XY+o) */ - -OP(xycb,88) { B = res(1, rm(m_ea)); wm(m_ea, B); } /* RES 1,B=(XY+o) */ -OP(xycb,89) { C = res(1, rm(m_ea)); wm(m_ea, C); } /* RES 1,C=(XY+o) */ -OP(xycb,8a) { D = res(1, rm(m_ea)); wm(m_ea, D); } /* RES 1,D=(XY+o) */ -OP(xycb,8b) { E = res(1, rm(m_ea)); wm(m_ea, E); } /* RES 1,E=(XY+o) */ -OP(xycb,8c) { H = res(1, rm(m_ea)); wm(m_ea, H); } /* RES 1,H=(XY+o) */ -OP(xycb,8d) { L = res(1, rm(m_ea)); wm(m_ea, L); } /* RES 1,L=(XY+o) */ -OP(xycb,8e) { wm(m_ea, res(1, rm(m_ea))); } /* RES 1,(XY+o) */ -OP(xycb,8f) { A = res(1, rm(m_ea)); wm(m_ea, A); } /* RES 1,A=(XY+o) */ - -OP(xycb,90) { B = res(2, rm(m_ea)); wm(m_ea, B); } /* RES 2,B=(XY+o) */ -OP(xycb,91) { C = res(2, rm(m_ea)); wm(m_ea, C); } /* RES 2,C=(XY+o) */ -OP(xycb,92) { D = res(2, rm(m_ea)); wm(m_ea, D); } /* RES 2,D=(XY+o) */ -OP(xycb,93) { E = res(2, rm(m_ea)); wm(m_ea, E); } /* RES 2,E=(XY+o) */ -OP(xycb,94) { H = res(2, rm(m_ea)); wm(m_ea, H); } /* RES 2,H=(XY+o) */ -OP(xycb,95) { L = res(2, rm(m_ea)); wm(m_ea, L); } /* RES 2,L=(XY+o) */ -OP(xycb,96) { wm(m_ea, res(2, rm(m_ea))); } /* RES 2,(XY+o) */ -OP(xycb,97) { A = res(2, rm(m_ea)); wm(m_ea, A); } /* RES 2,A=(XY+o) */ - -OP(xycb,98) { B = res(3, rm(m_ea)); wm(m_ea, B); } /* RES 3,B=(XY+o) */ -OP(xycb,99) { C = res(3, rm(m_ea)); wm(m_ea, C); } /* RES 3,C=(XY+o) */ -OP(xycb,9a) { D = res(3, rm(m_ea)); wm(m_ea, D); } /* RES 3,D=(XY+o) */ -OP(xycb,9b) { E = res(3, rm(m_ea)); wm(m_ea, E); } /* RES 3,E=(XY+o) */ -OP(xycb,9c) { H = res(3, rm(m_ea)); wm(m_ea, H); } /* RES 3,H=(XY+o) */ -OP(xycb,9d) { L = res(3, rm(m_ea)); wm(m_ea, L); } /* RES 3,L=(XY+o) */ -OP(xycb,9e) { wm(m_ea, res(3, rm(m_ea))); } /* RES 3,(XY+o) */ -OP(xycb,9f) { A = res(3, rm(m_ea)); wm(m_ea, A); } /* RES 3,A=(XY+o) */ - -OP(xycb,a0) { B = res(4, rm(m_ea)); wm(m_ea, B); } /* RES 4,B=(XY+o) */ -OP(xycb,a1) { C = res(4, rm(m_ea)); wm(m_ea, C); } /* RES 4,C=(XY+o) */ -OP(xycb,a2) { D = res(4, rm(m_ea)); wm(m_ea, D); } /* RES 4,D=(XY+o) */ -OP(xycb,a3) { E = res(4, rm(m_ea)); wm(m_ea, E); } /* RES 4,E=(XY+o) */ -OP(xycb,a4) { H = res(4, rm(m_ea)); wm(m_ea, H); } /* RES 4,H=(XY+o) */ -OP(xycb,a5) { L = res(4, rm(m_ea)); wm(m_ea, L); } /* RES 4,L=(XY+o) */ -OP(xycb,a6) { wm(m_ea, res(4, rm(m_ea))); } /* RES 4,(XY+o) */ -OP(xycb,a7) { A = res(4, rm(m_ea)); wm(m_ea, A); } /* RES 4,A=(XY+o) */ - -OP(xycb,a8) { B = res(5, rm(m_ea)); wm(m_ea, B); } /* RES 5,B=(XY+o) */ -OP(xycb,a9) { C = res(5, rm(m_ea)); wm(m_ea, C); } /* RES 5,C=(XY+o) */ -OP(xycb,aa) { D = res(5, rm(m_ea)); wm(m_ea, D); } /* RES 5,D=(XY+o) */ -OP(xycb,ab) { E = res(5, rm(m_ea)); wm(m_ea, E); } /* RES 5,E=(XY+o) */ -OP(xycb,ac) { H = res(5, rm(m_ea)); wm(m_ea, H); } /* RES 5,H=(XY+o) */ -OP(xycb,ad) { L = res(5, rm(m_ea)); wm(m_ea, L); } /* RES 5,L=(XY+o) */ -OP(xycb,ae) { wm(m_ea, res(5, rm(m_ea))); } /* RES 5,(XY+o) */ -OP(xycb,af) { A = res(5, rm(m_ea)); wm(m_ea, A); } /* RES 5,A=(XY+o) */ - -OP(xycb,b0) { B = res(6, rm(m_ea)); wm(m_ea, B); } /* RES 6,B=(XY+o) */ -OP(xycb,b1) { C = res(6, rm(m_ea)); wm(m_ea, C); } /* RES 6,C=(XY+o) */ -OP(xycb,b2) { D = res(6, rm(m_ea)); wm(m_ea, D); } /* RES 6,D=(XY+o) */ -OP(xycb,b3) { E = res(6, rm(m_ea)); wm(m_ea, E); } /* RES 6,E=(XY+o) */ -OP(xycb,b4) { H = res(6, rm(m_ea)); wm(m_ea, H); } /* RES 6,H=(XY+o) */ -OP(xycb,b5) { L = res(6, rm(m_ea)); wm(m_ea, L); } /* RES 6,L=(XY+o) */ -OP(xycb,b6) { wm(m_ea, res(6, rm(m_ea))); } /* RES 6,(XY+o) */ -OP(xycb,b7) { A = res(6, rm(m_ea)); wm(m_ea, A); } /* RES 6,A=(XY+o) */ - -OP(xycb,b8) { B = res(7, rm(m_ea)); wm(m_ea, B); } /* RES 7,B=(XY+o) */ -OP(xycb,b9) { C = res(7, rm(m_ea)); wm(m_ea, C); } /* RES 7,C=(XY+o) */ -OP(xycb,ba) { D = res(7, rm(m_ea)); wm(m_ea, D); } /* RES 7,D=(XY+o) */ -OP(xycb,bb) { E = res(7, rm(m_ea)); wm(m_ea, E); } /* RES 7,E=(XY+o) */ -OP(xycb,bc) { H = res(7, rm(m_ea)); wm(m_ea, H); } /* RES 7,H=(XY+o) */ -OP(xycb,bd) { L = res(7, rm(m_ea)); wm(m_ea, L); } /* RES 7,L=(XY+o) */ -OP(xycb,be) { wm(m_ea, res(7, rm(m_ea))); } /* RES 7,(XY+o) */ -OP(xycb,bf) { A = res(7, rm(m_ea)); wm(m_ea, A); } /* RES 7,A=(XY+o) */ - -OP(xycb,c0) { B = set(0, rm(m_ea)); wm(m_ea, B); } /* SET 0,B=(XY+o) */ -OP(xycb,c1) { C = set(0, rm(m_ea)); wm(m_ea, C); } /* SET 0,C=(XY+o) */ -OP(xycb,c2) { D = set(0, rm(m_ea)); wm(m_ea, D); } /* SET 0,D=(XY+o) */ -OP(xycb,c3) { E = set(0, rm(m_ea)); wm(m_ea, E); } /* SET 0,E=(XY+o) */ -OP(xycb,c4) { H = set(0, rm(m_ea)); wm(m_ea, H); } /* SET 0,H=(XY+o) */ -OP(xycb,c5) { L = set(0, rm(m_ea)); wm(m_ea, L); } /* SET 0,L=(XY+o) */ -OP(xycb,c6) { wm(m_ea, set(0, rm(m_ea))); } /* SET 0,(XY+o) */ -OP(xycb,c7) { A = set(0, rm(m_ea)); wm(m_ea, A); } /* SET 0,A=(XY+o) */ - -OP(xycb,c8) { B = set(1, rm(m_ea)); wm(m_ea, B); } /* SET 1,B=(XY+o) */ -OP(xycb,c9) { C = set(1, rm(m_ea)); wm(m_ea, C); } /* SET 1,C=(XY+o) */ -OP(xycb,ca) { D = set(1, rm(m_ea)); wm(m_ea, D); } /* SET 1,D=(XY+o) */ -OP(xycb,cb) { E = set(1, rm(m_ea)); wm(m_ea, E); } /* SET 1,E=(XY+o) */ -OP(xycb,cc) { H = set(1, rm(m_ea)); wm(m_ea, H); } /* SET 1,H=(XY+o) */ -OP(xycb,cd) { L = set(1, rm(m_ea)); wm(m_ea, L); } /* SET 1,L=(XY+o) */ -OP(xycb,ce) { wm(m_ea, set(1, rm(m_ea))); } /* SET 1,(XY+o) */ -OP(xycb,cf) { A = set(1, rm(m_ea)); wm(m_ea, A); } /* SET 1,A=(XY+o) */ - -OP(xycb,d0) { B = set(2, rm(m_ea)); wm(m_ea, B); } /* SET 2,B=(XY+o) */ -OP(xycb,d1) { C = set(2, rm(m_ea)); wm(m_ea, C); } /* SET 2,C=(XY+o) */ -OP(xycb,d2) { D = set(2, rm(m_ea)); wm(m_ea, D); } /* SET 2,D=(XY+o) */ -OP(xycb,d3) { E = set(2, rm(m_ea)); wm(m_ea, E); } /* SET 2,E=(XY+o) */ -OP(xycb,d4) { H = set(2, rm(m_ea)); wm(m_ea, H); } /* SET 2,H=(XY+o) */ -OP(xycb,d5) { L = set(2, rm(m_ea)); wm(m_ea, L); } /* SET 2,L=(XY+o) */ -OP(xycb,d6) { wm(m_ea, set(2, rm(m_ea))); } /* SET 2,(XY+o) */ -OP(xycb,d7) { A = set(2, rm(m_ea)); wm(m_ea, A); } /* SET 2,A=(XY+o) */ - -OP(xycb,d8) { B = set(3, rm(m_ea)); wm(m_ea, B); } /* SET 3,B=(XY+o) */ -OP(xycb,d9) { C = set(3, rm(m_ea)); wm(m_ea, C); } /* SET 3,C=(XY+o) */ -OP(xycb,da) { D = set(3, rm(m_ea)); wm(m_ea, D); } /* SET 3,D=(XY+o) */ -OP(xycb,db) { E = set(3, rm(m_ea)); wm(m_ea, E); } /* SET 3,E=(XY+o) */ -OP(xycb,dc) { H = set(3, rm(m_ea)); wm(m_ea, H); } /* SET 3,H=(XY+o) */ -OP(xycb,dd) { L = set(3, rm(m_ea)); wm(m_ea, L); } /* SET 3,L=(XY+o) */ -OP(xycb,de) { wm(m_ea, set(3, rm(m_ea))); } /* SET 3,(XY+o) */ -OP(xycb,df) { A = set(3, rm(m_ea)); wm(m_ea, A); } /* SET 3,A=(XY+o) */ - -OP(xycb,e0) { B = set(4, rm(m_ea)); wm(m_ea, B); } /* SET 4,B=(XY+o) */ -OP(xycb,e1) { C = set(4, rm(m_ea)); wm(m_ea, C); } /* SET 4,C=(XY+o) */ -OP(xycb,e2) { D = set(4, rm(m_ea)); wm(m_ea, D); } /* SET 4,D=(XY+o) */ -OP(xycb,e3) { E = set(4, rm(m_ea)); wm(m_ea, E); } /* SET 4,E=(XY+o) */ -OP(xycb,e4) { H = set(4, rm(m_ea)); wm(m_ea, H); } /* SET 4,H=(XY+o) */ -OP(xycb,e5) { L = set(4, rm(m_ea)); wm(m_ea, L); } /* SET 4,L=(XY+o) */ -OP(xycb,e6) { wm(m_ea, set(4, rm(m_ea))); } /* SET 4,(XY+o) */ -OP(xycb,e7) { A = set(4, rm(m_ea)); wm(m_ea, A); } /* SET 4,A=(XY+o) */ - -OP(xycb,e8) { B = set(5, rm(m_ea)); wm(m_ea, B); } /* SET 5,B=(XY+o) */ -OP(xycb,e9) { C = set(5, rm(m_ea)); wm(m_ea, C); } /* SET 5,C=(XY+o) */ -OP(xycb,ea) { D = set(5, rm(m_ea)); wm(m_ea, D); } /* SET 5,D=(XY+o) */ -OP(xycb,eb) { E = set(5, rm(m_ea)); wm(m_ea, E); } /* SET 5,E=(XY+o) */ -OP(xycb,ec) { H = set(5, rm(m_ea)); wm(m_ea, H); } /* SET 5,H=(XY+o) */ -OP(xycb,ed) { L = set(5, rm(m_ea)); wm(m_ea, L); } /* SET 5,L=(XY+o) */ -OP(xycb,ee) { wm(m_ea, set(5, rm(m_ea))); } /* SET 5,(XY+o) */ -OP(xycb,ef) { A = set(5, rm(m_ea)); wm(m_ea, A); } /* SET 5,A=(XY+o) */ - -OP(xycb,f0) { B = set(6, rm(m_ea)); wm(m_ea, B); } /* SET 6,B=(XY+o) */ -OP(xycb,f1) { C = set(6, rm(m_ea)); wm(m_ea, C); } /* SET 6,C=(XY+o) */ -OP(xycb,f2) { D = set(6, rm(m_ea)); wm(m_ea, D); } /* SET 6,D=(XY+o) */ -OP(xycb,f3) { E = set(6, rm(m_ea)); wm(m_ea, E); } /* SET 6,E=(XY+o) */ -OP(xycb,f4) { H = set(6, rm(m_ea)); wm(m_ea, H); } /* SET 6,H=(XY+o) */ -OP(xycb,f5) { L = set(6, rm(m_ea)); wm(m_ea, L); } /* SET 6,L=(XY+o) */ -OP(xycb,f6) { wm(m_ea, set(6, rm(m_ea))); } /* SET 6,(XY+o) */ -OP(xycb,f7) { A = set(6, rm(m_ea)); wm(m_ea, A); } /* SET 6,A=(XY+o) */ - -OP(xycb,f8) { B = set(7, rm(m_ea)); wm(m_ea, B); } /* SET 7,B=(XY+o) */ -OP(xycb,f9) { C = set(7, rm(m_ea)); wm(m_ea, C); } /* SET 7,C=(XY+o) */ -OP(xycb,fa) { D = set(7, rm(m_ea)); wm(m_ea, D); } /* SET 7,D=(XY+o) */ -OP(xycb,fb) { E = set(7, rm(m_ea)); wm(m_ea, E); } /* SET 7,E=(XY+o) */ -OP(xycb,fc) { H = set(7, rm(m_ea)); wm(m_ea, H); } /* SET 7,H=(XY+o) */ -OP(xycb,fd) { L = set(7, rm(m_ea)); wm(m_ea, L); } /* SET 7,L=(XY+o) */ -OP(xycb,fe) { wm(m_ea, set(7, rm(m_ea))); } /* SET 7,(XY+o) */ -OP(xycb,ff) { A = set(7, rm(m_ea)); wm(m_ea, A); } /* SET 7,A=(XY+o) */ - -OP(illegal,1) { - logerror("Z80 ill. opcode $%02x $%02x ($%04x)\n", - m_opcodes_cache->read_byte((PCD-1)&0xffff), m_opcodes_cache->read_byte(PCD), PCD-1); + set_service_attention<SA_AFTER_EI, 1>(); } -/********************************************************** - * IX register related opcodes (DD prefix) - **********************************************************/ -OP(dd,00) { illegal_1(); op_00(); } /* DB DD */ -OP(dd,01) { illegal_1(); op_01(); } /* DB DD */ -OP(dd,02) { illegal_1(); op_02(); } /* DB DD */ -OP(dd,03) { illegal_1(); op_03(); } /* DB DD */ -OP(dd,04) { illegal_1(); op_04(); } /* DB DD */ -OP(dd,05) { illegal_1(); op_05(); } /* DB DD */ -OP(dd,06) { illegal_1(); op_06(); } /* DB DD */ -OP(dd,07) { illegal_1(); op_07(); } /* DB DD */ - -OP(dd,08) { illegal_1(); op_08(); } /* DB DD */ -OP(dd,09) { add16(m_ix, m_bc); } /* ADD IX,BC */ -OP(dd,0a) { illegal_1(); op_0a(); } /* DB DD */ -OP(dd,0b) { illegal_1(); op_0b(); } /* DB DD */ -OP(dd,0c) { illegal_1(); op_0c(); } /* DB DD */ -OP(dd,0d) { illegal_1(); op_0d(); } /* DB DD */ -OP(dd,0e) { illegal_1(); op_0e(); } /* DB DD */ -OP(dd,0f) { illegal_1(); op_0f(); } /* DB DD */ - -OP(dd,10) { illegal_1(); op_10(); } /* DB DD */ -OP(dd,11) { illegal_1(); op_11(); } /* DB DD */ -OP(dd,12) { illegal_1(); op_12(); } /* DB DD */ -OP(dd,13) { illegal_1(); op_13(); } /* DB DD */ -OP(dd,14) { illegal_1(); op_14(); } /* DB DD */ -OP(dd,15) { illegal_1(); op_15(); } /* DB DD */ -OP(dd,16) { illegal_1(); op_16(); } /* DB DD */ -OP(dd,17) { illegal_1(); op_17(); } /* DB DD */ - -OP(dd,18) { illegal_1(); op_18(); } /* DB DD */ -OP(dd,19) { add16(m_ix, m_de); } /* ADD IX,DE */ -OP(dd,1a) { illegal_1(); op_1a(); } /* DB DD */ -OP(dd,1b) { illegal_1(); op_1b(); } /* DB DD */ -OP(dd,1c) { illegal_1(); op_1c(); } /* DB DD */ -OP(dd,1d) { illegal_1(); op_1d(); } /* DB DD */ -OP(dd,1e) { illegal_1(); op_1e(); } /* DB DD */ -OP(dd,1f) { illegal_1(); op_1f(); } /* DB DD */ - -OP(dd,20) { illegal_1(); op_20(); } /* DB DD */ -OP(dd,21) { IX = arg16(); } /* LD IX,w */ -OP(dd,22) { m_ea = arg16(); wm16(m_ea, m_ix); WZ = m_ea + 1; } /* LD (w),IX */ -OP(dd,23) { IX++; } /* INC IX */ -OP(dd,24) { HX = inc(HX); } /* INC HX */ -OP(dd,25) { HX = dec(HX); } /* DEC HX */ -OP(dd,26) { HX = arg(); } /* LD HX,n */ -OP(dd,27) { illegal_1(); op_27(); } /* DB DD */ - -OP(dd,28) { illegal_1(); op_28(); } /* DB DD */ -OP(dd,29) { add16(m_ix, m_ix); } /* ADD IX,IX */ -OP(dd,2a) { m_ea = arg16(); rm16(m_ea, m_ix); WZ = m_ea + 1; } /* LD IX,(w) */ -OP(dd,2b) { IX--; } /* DEC IX */ -OP(dd,2c) { LX = inc(LX); } /* INC LX */ -OP(dd,2d) { LX = dec(LX); } /* DEC LX */ -OP(dd,2e) { LX = arg(); } /* LD LX,n */ -OP(dd,2f) { illegal_1(); op_2f(); } /* DB DD */ - -OP(dd,30) { illegal_1(); op_30(); } /* DB DD */ -OP(dd,31) { illegal_1(); op_31(); } /* DB DD */ -OP(dd,32) { illegal_1(); op_32(); } /* DB DD */ -OP(dd,33) { illegal_1(); op_33(); } /* DB DD */ -OP(dd,34) { eax(); wm(m_ea, inc(rm(m_ea))); } /* INC (IX+o) */ -OP(dd,35) { eax(); wm(m_ea, dec(rm(m_ea))); } /* DEC (IX+o) */ -OP(dd,36) { eax(); wm(m_ea, arg()); } /* LD (IX+o),n */ -OP(dd,37) { illegal_1(); op_37(); } /* DB DD */ - -OP(dd,38) { illegal_1(); op_38(); } /* DB DD */ -OP(dd,39) { add16(m_ix, m_sp); } /* ADD IX,SP */ -OP(dd,3a) { illegal_1(); op_3a(); } /* DB DD */ -OP(dd,3b) { illegal_1(); op_3b(); } /* DB DD */ -OP(dd,3c) { illegal_1(); op_3c(); } /* DB DD */ -OP(dd,3d) { illegal_1(); op_3d(); } /* DB DD */ -OP(dd,3e) { illegal_1(); op_3e(); } /* DB DD */ -OP(dd,3f) { illegal_1(); op_3f(); } /* DB DD */ - -OP(dd,40) { illegal_1(); op_40(); } /* DB DD */ -OP(dd,41) { illegal_1(); op_41(); } /* DB DD */ -OP(dd,42) { illegal_1(); op_42(); } /* DB DD */ -OP(dd,43) { illegal_1(); op_43(); } /* DB DD */ -OP(dd,44) { B = HX; } /* LD B,HX */ -OP(dd,45) { B = LX; } /* LD B,LX */ -OP(dd,46) { eax(); B = rm(m_ea); } /* LD B,(IX+o) */ -OP(dd,47) { illegal_1(); op_47(); } /* DB DD */ - -OP(dd,48) { illegal_1(); op_48(); } /* DB DD */ -OP(dd,49) { illegal_1(); op_49(); } /* DB DD */ -OP(dd,4a) { illegal_1(); op_4a(); } /* DB DD */ -OP(dd,4b) { illegal_1(); op_4b(); } /* DB DD */ -OP(dd,4c) { C = HX; } /* LD C,HX */ -OP(dd,4d) { C = LX; } /* LD C,LX */ -OP(dd,4e) { eax(); C = rm(m_ea); } /* LD C,(IX+o) */ -OP(dd,4f) { illegal_1(); op_4f(); } /* DB DD */ - -OP(dd,50) { illegal_1(); op_50(); } /* DB DD */ -OP(dd,51) { illegal_1(); op_51(); } /* DB DD */ -OP(dd,52) { illegal_1(); op_52(); } /* DB DD */ -OP(dd,53) { illegal_1(); op_53(); } /* DB DD */ -OP(dd,54) { D = HX; } /* LD D,HX */ -OP(dd,55) { D = LX; } /* LD D,LX */ -OP(dd,56) { eax(); D = rm(m_ea); } /* LD D,(IX+o) */ -OP(dd,57) { illegal_1(); op_57(); } /* DB DD */ - -OP(dd,58) { illegal_1(); op_58(); } /* DB DD */ -OP(dd,59) { illegal_1(); op_59(); } /* DB DD */ -OP(dd,5a) { illegal_1(); op_5a(); } /* DB DD */ -OP(dd,5b) { illegal_1(); op_5b(); } /* DB DD */ -OP(dd,5c) { E = HX; } /* LD E,HX */ -OP(dd,5d) { E = LX; } /* LD E,LX */ -OP(dd,5e) { eax(); E = rm(m_ea); } /* LD E,(IX+o) */ -OP(dd,5f) { illegal_1(); op_5f(); } /* DB DD */ - -OP(dd,60) { HX = B; } /* LD HX,B */ -OP(dd,61) { HX = C; } /* LD HX,C */ -OP(dd,62) { HX = D; } /* LD HX,D */ -OP(dd,63) { HX = E; } /* LD HX,E */ -OP(dd,64) { } /* LD HX,HX */ -OP(dd,65) { HX = LX; } /* LD HX,LX */ -OP(dd,66) { eax(); H = rm(m_ea); } /* LD H,(IX+o) */ -OP(dd,67) { HX = A; } /* LD HX,A */ - -OP(dd,68) { LX = B; } /* LD LX,B */ -OP(dd,69) { LX = C; } /* LD LX,C */ -OP(dd,6a) { LX = D; } /* LD LX,D */ -OP(dd,6b) { LX = E; } /* LD LX,E */ -OP(dd,6c) { LX = HX; } /* LD LX,HX */ -OP(dd,6d) { } /* LD LX,LX */ -OP(dd,6e) { eax(); L = rm(m_ea); } /* LD L,(IX+o) */ -OP(dd,6f) { LX = A; } /* LD LX,A */ - -OP(dd,70) { eax(); wm(m_ea, B); } /* LD (IX+o),B */ -OP(dd,71) { eax(); wm(m_ea, C); } /* LD (IX+o),C */ -OP(dd,72) { eax(); wm(m_ea, D); } /* LD (IX+o),D */ -OP(dd,73) { eax(); wm(m_ea, E); } /* LD (IX+o),E */ -OP(dd,74) { eax(); wm(m_ea, H); } /* LD (IX+o),H */ -OP(dd,75) { eax(); wm(m_ea, L); } /* LD (IX+o),L */ -OP(dd,76) { illegal_1(); op_76(); } /* DB DD */ -OP(dd,77) { eax(); wm(m_ea, A); } /* LD (IX+o),A */ - -OP(dd,78) { illegal_1(); op_78(); } /* DB DD */ -OP(dd,79) { illegal_1(); op_79(); } /* DB DD */ -OP(dd,7a) { illegal_1(); op_7a(); } /* DB DD */ -OP(dd,7b) { illegal_1(); op_7b(); } /* DB DD */ -OP(dd,7c) { A = HX; } /* LD A,HX */ -OP(dd,7d) { A = LX; } /* LD A,LX */ -OP(dd,7e) { eax(); A = rm(m_ea); } /* LD A,(IX+o) */ -OP(dd,7f) { illegal_1(); op_7f(); } /* DB DD */ - -OP(dd,80) { illegal_1(); op_80(); } /* DB DD */ -OP(dd,81) { illegal_1(); op_81(); } /* DB DD */ -OP(dd,82) { illegal_1(); op_82(); } /* DB DD */ -OP(dd,83) { illegal_1(); op_83(); } /* DB DD */ -OP(dd,84) { add_a(HX); } /* ADD A,HX */ -OP(dd,85) { add_a(LX); } /* ADD A,LX */ -OP(dd,86) { eax(); add_a(rm(m_ea)); } /* ADD A,(IX+o) */ -OP(dd,87) { illegal_1(); op_87(); } /* DB DD */ - -OP(dd,88) { illegal_1(); op_88(); } /* DB DD */ -OP(dd,89) { illegal_1(); op_89(); } /* DB DD */ -OP(dd,8a) { illegal_1(); op_8a(); } /* DB DD */ -OP(dd,8b) { illegal_1(); op_8b(); } /* DB DD */ -OP(dd,8c) { adc_a(HX); } /* ADC A,HX */ -OP(dd,8d) { adc_a(LX); } /* ADC A,LX */ -OP(dd,8e) { eax(); adc_a(rm(m_ea)); } /* ADC A,(IX+o) */ -OP(dd,8f) { illegal_1(); op_8f(); } /* DB DD */ - -OP(dd,90) { illegal_1(); op_90(); } /* DB DD */ -OP(dd,91) { illegal_1(); op_91(); } /* DB DD */ -OP(dd,92) { illegal_1(); op_92(); } /* DB DD */ -OP(dd,93) { illegal_1(); op_93(); } /* DB DD */ -OP(dd,94) { sub(HX); } /* SUB HX */ -OP(dd,95) { sub(LX); } /* SUB LX */ -OP(dd,96) { eax(); sub(rm(m_ea)); } /* SUB (IX+o) */ -OP(dd,97) { illegal_1(); op_97(); } /* DB DD */ - -OP(dd,98) { illegal_1(); op_98(); } /* DB DD */ -OP(dd,99) { illegal_1(); op_99(); } /* DB DD */ -OP(dd,9a) { illegal_1(); op_9a(); } /* DB DD */ -OP(dd,9b) { illegal_1(); op_9b(); } /* DB DD */ -OP(dd,9c) { sbc_a(HX); } /* SBC A,HX */ -OP(dd,9d) { sbc_a(LX); } /* SBC A,LX */ -OP(dd,9e) { eax(); sbc_a(rm(m_ea)); } /* SBC A,(IX+o) */ -OP(dd,9f) { illegal_1(); op_9f(); } /* DB DD */ - -OP(dd,a0) { illegal_1(); op_a0(); } /* DB DD */ -OP(dd,a1) { illegal_1(); op_a1(); } /* DB DD */ -OP(dd,a2) { illegal_1(); op_a2(); } /* DB DD */ -OP(dd,a3) { illegal_1(); op_a3(); } /* DB DD */ -OP(dd,a4) { and_a(HX); } /* AND HX */ -OP(dd,a5) { and_a(LX); } /* AND LX */ -OP(dd,a6) { eax(); and_a(rm(m_ea)); } /* AND (IX+o) */ -OP(dd,a7) { illegal_1(); op_a7(); } /* DB DD */ - -OP(dd,a8) { illegal_1(); op_a8(); } /* DB DD */ -OP(dd,a9) { illegal_1(); op_a9(); } /* DB DD */ -OP(dd,aa) { illegal_1(); op_aa(); } /* DB DD */ -OP(dd,ab) { illegal_1(); op_ab(); } /* DB DD */ -OP(dd,ac) { xor_a(HX); } /* XOR HX */ -OP(dd,ad) { xor_a(LX); } /* XOR LX */ -OP(dd,ae) { eax(); xor_a(rm(m_ea)); } /* XOR (IX+o) */ -OP(dd,af) { illegal_1(); op_af(); } /* DB DD */ - -OP(dd,b0) { illegal_1(); op_b0(); } /* DB DD */ -OP(dd,b1) { illegal_1(); op_b1(); } /* DB DD */ -OP(dd,b2) { illegal_1(); op_b2(); } /* DB DD */ -OP(dd,b3) { illegal_1(); op_b3(); } /* DB DD */ -OP(dd,b4) { or_a(HX); } /* OR HX */ -OP(dd,b5) { or_a(LX); } /* OR LX */ -OP(dd,b6) { eax(); or_a(rm(m_ea)); } /* OR (IX+o) */ -OP(dd,b7) { illegal_1(); op_b7(); } /* DB DD */ - -OP(dd,b8) { illegal_1(); op_b8(); } /* DB DD */ -OP(dd,b9) { illegal_1(); op_b9(); } /* DB DD */ -OP(dd,ba) { illegal_1(); op_ba(); } /* DB DD */ -OP(dd,bb) { illegal_1(); op_bb(); } /* DB DD */ -OP(dd,bc) { cp(HX); } /* CP HX */ -OP(dd,bd) { cp(LX); } /* CP LX */ -OP(dd,be) { eax(); cp(rm(m_ea)); } /* CP (IX+o) */ -OP(dd,bf) { illegal_1(); op_bf(); } /* DB DD */ - -OP(dd,c0) { illegal_1(); op_c0(); } /* DB DD */ -OP(dd,c1) { illegal_1(); op_c1(); } /* DB DD */ -OP(dd,c2) { illegal_1(); op_c2(); } /* DB DD */ -OP(dd,c3) { illegal_1(); op_c3(); } /* DB DD */ -OP(dd,c4) { illegal_1(); op_c4(); } /* DB DD */ -OP(dd,c5) { illegal_1(); op_c5(); } /* DB DD */ -OP(dd,c6) { illegal_1(); op_c6(); } /* DB DD */ -OP(dd,c7) { illegal_1(); op_c7(); } /* DB DD */ - -OP(dd,c8) { illegal_1(); op_c8(); } /* DB DD */ -OP(dd,c9) { illegal_1(); op_c9(); } /* DB DD */ -OP(dd,ca) { illegal_1(); op_ca(); } /* DB DD */ -OP(dd,cb) { eax(); EXEC(xycb,arg()); } /* ** DD CB xx */ -OP(dd,cc) { illegal_1(); op_cc(); } /* DB DD */ -OP(dd,cd) { illegal_1(); op_cd(); } /* DB DD */ -OP(dd,ce) { illegal_1(); op_ce(); } /* DB DD */ -OP(dd,cf) { illegal_1(); op_cf(); } /* DB DD */ - -OP(dd,d0) { illegal_1(); op_d0(); } /* DB DD */ -OP(dd,d1) { illegal_1(); op_d1(); } /* DB DD */ -OP(dd,d2) { illegal_1(); op_d2(); } /* DB DD */ -OP(dd,d3) { illegal_1(); op_d3(); } /* DB DD */ -OP(dd,d4) { illegal_1(); op_d4(); } /* DB DD */ -OP(dd,d5) { illegal_1(); op_d5(); } /* DB DD */ -OP(dd,d6) { illegal_1(); op_d6(); } /* DB DD */ -OP(dd,d7) { illegal_1(); op_d7(); } /* DB DD */ - -OP(dd,d8) { illegal_1(); op_d8(); } /* DB DD */ -OP(dd,d9) { illegal_1(); op_d9(); } /* DB DD */ -OP(dd,da) { illegal_1(); op_da(); } /* DB DD */ -OP(dd,db) { illegal_1(); op_db(); } /* DB DD */ -OP(dd,dc) { illegal_1(); op_dc(); } /* DB DD */ -OP(dd,dd) { illegal_1(); op_dd(); } /* DB DD */ -OP(dd,de) { illegal_1(); op_de(); } /* DB DD */ -OP(dd,df) { illegal_1(); op_df(); } /* DB DD */ - -OP(dd,e0) { illegal_1(); op_e0(); } /* DB DD */ -OP(dd,e1) { pop(m_ix); } /* POP IX */ -OP(dd,e2) { illegal_1(); op_e2(); } /* DB DD */ -OP(dd,e3) { ex_sp(m_ix); } /* EX (SP),IX */ -OP(dd,e4) { illegal_1(); op_e4(); } /* DB DD */ -OP(dd,e5) { push(m_ix); } /* PUSH IX */ -OP(dd,e6) { illegal_1(); op_e6(); } /* DB DD */ -OP(dd,e7) { illegal_1(); op_e7(); } /* DB DD */ - -OP(dd,e8) { illegal_1(); op_e8(); } /* DB DD */ -OP(dd,e9) { PC = IX; } /* JP (IX) */ -OP(dd,ea) { illegal_1(); op_ea(); } /* DB DD */ -OP(dd,eb) { illegal_1(); op_eb(); } /* DB DD */ -OP(dd,ec) { illegal_1(); op_ec(); } /* DB DD */ -OP(dd,ed) { illegal_1(); op_ed(); } /* DB DD */ -OP(dd,ee) { illegal_1(); op_ee(); } /* DB DD */ -OP(dd,ef) { illegal_1(); op_ef(); } /* DB DD */ - -OP(dd,f0) { illegal_1(); op_f0(); } /* DB DD */ -OP(dd,f1) { illegal_1(); op_f1(); } /* DB DD */ -OP(dd,f2) { illegal_1(); op_f2(); } /* DB DD */ -OP(dd,f3) { illegal_1(); op_f3(); } /* DB DD */ -OP(dd,f4) { illegal_1(); op_f4(); } /* DB DD */ -OP(dd,f5) { illegal_1(); op_f5(); } /* DB DD */ -OP(dd,f6) { illegal_1(); op_f6(); } /* DB DD */ -OP(dd,f7) { illegal_1(); op_f7(); } /* DB DD */ - -OP(dd,f8) { illegal_1(); op_f8(); } /* DB DD */ -OP(dd,f9) { SP = IX; } /* LD SP,IX */ -OP(dd,fa) { illegal_1(); op_fa(); } /* DB DD */ -OP(dd,fb) { illegal_1(); op_fb(); } /* DB DD */ -OP(dd,fc) { illegal_1(); op_fc(); } /* DB DD */ -OP(dd,fd) { illegal_1(); op_fd(); } /* DB DD */ -OP(dd,fe) { illegal_1(); op_fe(); } /* DB DD */ -OP(dd,ff) { illegal_1(); op_ff(); } /* DB DD */ - -/********************************************************** - * IY register related opcodes (FD prefix) - **********************************************************/ -OP(fd,00) { illegal_1(); op_00(); } /* DB FD */ -OP(fd,01) { illegal_1(); op_01(); } /* DB FD */ -OP(fd,02) { illegal_1(); op_02(); } /* DB FD */ -OP(fd,03) { illegal_1(); op_03(); } /* DB FD */ -OP(fd,04) { illegal_1(); op_04(); } /* DB FD */ -OP(fd,05) { illegal_1(); op_05(); } /* DB FD */ -OP(fd,06) { illegal_1(); op_06(); } /* DB FD */ -OP(fd,07) { illegal_1(); op_07(); } /* DB FD */ - -OP(fd,08) { illegal_1(); op_08(); } /* DB FD */ -OP(fd,09) { add16(m_iy, m_bc); } /* ADD IY,BC */ -OP(fd,0a) { illegal_1(); op_0a(); } /* DB FD */ -OP(fd,0b) { illegal_1(); op_0b(); } /* DB FD */ -OP(fd,0c) { illegal_1(); op_0c(); } /* DB FD */ -OP(fd,0d) { illegal_1(); op_0d(); } /* DB FD */ -OP(fd,0e) { illegal_1(); op_0e(); } /* DB FD */ -OP(fd,0f) { illegal_1(); op_0f(); } /* DB FD */ - -OP(fd,10) { illegal_1(); op_10(); } /* DB FD */ -OP(fd,11) { illegal_1(); op_11(); } /* DB FD */ -OP(fd,12) { illegal_1(); op_12(); } /* DB FD */ -OP(fd,13) { illegal_1(); op_13(); } /* DB FD */ -OP(fd,14) { illegal_1(); op_14(); } /* DB FD */ -OP(fd,15) { illegal_1(); op_15(); } /* DB FD */ -OP(fd,16) { illegal_1(); op_16(); } /* DB FD */ -OP(fd,17) { illegal_1(); op_17(); } /* DB FD */ - -OP(fd,18) { illegal_1(); op_18(); } /* DB FD */ -OP(fd,19) { add16(m_iy, m_de); } /* ADD IY,DE */ -OP(fd,1a) { illegal_1(); op_1a(); } /* DB FD */ -OP(fd,1b) { illegal_1(); op_1b(); } /* DB FD */ -OP(fd,1c) { illegal_1(); op_1c(); } /* DB FD */ -OP(fd,1d) { illegal_1(); op_1d(); } /* DB FD */ -OP(fd,1e) { illegal_1(); op_1e(); } /* DB FD */ -OP(fd,1f) { illegal_1(); op_1f(); } /* DB FD */ - -OP(fd,20) { illegal_1(); op_20(); } /* DB FD */ -OP(fd,21) { IY = arg16(); } /* LD IY,w */ -OP(fd,22) { m_ea = arg16(); wm16(m_ea, m_iy); WZ = m_ea + 1; } /* LD (w),IY */ -OP(fd,23) { IY++; } /* INC IY */ -OP(fd,24) { HY = inc(HY); } /* INC HY */ -OP(fd,25) { HY = dec(HY); } /* DEC HY */ -OP(fd,26) { HY = arg(); } /* LD HY,n */ -OP(fd,27) { illegal_1(); op_27(); } /* DB FD */ - -OP(fd,28) { illegal_1(); op_28(); } /* DB FD */ -OP(fd,29) { add16(m_iy, m_iy); } /* ADD IY,IY */ -OP(fd,2a) { m_ea = arg16(); rm16(m_ea, m_iy); WZ = m_ea + 1; } /* LD IY,(w) */ -OP(fd,2b) { IY--; } /* DEC IY */ -OP(fd,2c) { LY = inc(LY); } /* INC LY */ -OP(fd,2d) { LY = dec(LY); } /* DEC LY */ -OP(fd,2e) { LY = arg(); } /* LD LY,n */ -OP(fd,2f) { illegal_1(); op_2f(); } /* DB FD */ - -OP(fd,30) { illegal_1(); op_30(); } /* DB FD */ -OP(fd,31) { illegal_1(); op_31(); } /* DB FD */ -OP(fd,32) { illegal_1(); op_32(); } /* DB FD */ -OP(fd,33) { illegal_1(); op_33(); } /* DB FD */ -OP(fd,34) { eay(); wm(m_ea, inc(rm(m_ea))); } /* INC (IY+o) */ -OP(fd,35) { eay(); wm(m_ea, dec(rm(m_ea))); } /* DEC (IY+o) */ -OP(fd,36) { eay(); wm(m_ea, arg()); } /* LD (IY+o),n */ -OP(fd,37) { illegal_1(); op_37(); } /* DB FD */ - -OP(fd,38) { illegal_1(); op_38(); } /* DB FD */ -OP(fd,39) { add16(m_iy, m_sp); } /* ADD IY,SP */ -OP(fd,3a) { illegal_1(); op_3a(); } /* DB FD */ -OP(fd,3b) { illegal_1(); op_3b(); } /* DB FD */ -OP(fd,3c) { illegal_1(); op_3c(); } /* DB FD */ -OP(fd,3d) { illegal_1(); op_3d(); } /* DB FD */ -OP(fd,3e) { illegal_1(); op_3e(); } /* DB FD */ -OP(fd,3f) { illegal_1(); op_3f(); } /* DB FD */ - -OP(fd,40) { illegal_1(); op_40(); } /* DB FD */ -OP(fd,41) { illegal_1(); op_41(); } /* DB FD */ -OP(fd,42) { illegal_1(); op_42(); } /* DB FD */ -OP(fd,43) { illegal_1(); op_43(); } /* DB FD */ -OP(fd,44) { B = HY; } /* LD B,HY */ -OP(fd,45) { B = LY; } /* LD B,LY */ -OP(fd,46) { eay(); B = rm(m_ea); } /* LD B,(IY+o) */ -OP(fd,47) { illegal_1(); op_47(); } /* DB FD */ - -OP(fd,48) { illegal_1(); op_48(); } /* DB FD */ -OP(fd,49) { illegal_1(); op_49(); } /* DB FD */ -OP(fd,4a) { illegal_1(); op_4a(); } /* DB FD */ -OP(fd,4b) { illegal_1(); op_4b(); } /* DB FD */ -OP(fd,4c) { C = HY; } /* LD C,HY */ -OP(fd,4d) { C = LY; } /* LD C,LY */ -OP(fd,4e) { eay(); C = rm(m_ea); } /* LD C,(IY+o) */ -OP(fd,4f) { illegal_1(); op_4f(); } /* DB FD */ - -OP(fd,50) { illegal_1(); op_50(); } /* DB FD */ -OP(fd,51) { illegal_1(); op_51(); } /* DB FD */ -OP(fd,52) { illegal_1(); op_52(); } /* DB FD */ -OP(fd,53) { illegal_1(); op_53(); } /* DB FD */ -OP(fd,54) { D = HY; } /* LD D,HY */ -OP(fd,55) { D = LY; } /* LD D,LY */ -OP(fd,56) { eay(); D = rm(m_ea); } /* LD D,(IY+o) */ -OP(fd,57) { illegal_1(); op_57(); } /* DB FD */ - -OP(fd,58) { illegal_1(); op_58(); } /* DB FD */ -OP(fd,59) { illegal_1(); op_59(); } /* DB FD */ -OP(fd,5a) { illegal_1(); op_5a(); } /* DB FD */ -OP(fd,5b) { illegal_1(); op_5b(); } /* DB FD */ -OP(fd,5c) { E = HY; } /* LD E,HY */ -OP(fd,5d) { E = LY; } /* LD E,LY */ -OP(fd,5e) { eay(); E = rm(m_ea); } /* LD E,(IY+o) */ -OP(fd,5f) { illegal_1(); op_5f(); } /* DB FD */ - -OP(fd,60) { HY = B; } /* LD HY,B */ -OP(fd,61) { HY = C; } /* LD HY,C */ -OP(fd,62) { HY = D; } /* LD HY,D */ -OP(fd,63) { HY = E; } /* LD HY,E */ -OP(fd,64) { } /* LD HY,HY */ -OP(fd,65) { HY = LY; } /* LD HY,LY */ -OP(fd,66) { eay(); H = rm(m_ea); } /* LD H,(IY+o) */ -OP(fd,67) { HY = A; } /* LD HY,A */ - -OP(fd,68) { LY = B; } /* LD LY,B */ -OP(fd,69) { LY = C; } /* LD LY,C */ -OP(fd,6a) { LY = D; } /* LD LY,D */ -OP(fd,6b) { LY = E; } /* LD LY,E */ -OP(fd,6c) { LY = HY; } /* LD LY,HY */ -OP(fd,6d) { } /* LD LY,LY */ -OP(fd,6e) { eay(); L = rm(m_ea); } /* LD L,(IY+o) */ -OP(fd,6f) { LY = A; } /* LD LY,A */ - -OP(fd,70) { eay(); wm(m_ea, B); } /* LD (IY+o),B */ -OP(fd,71) { eay(); wm(m_ea, C); } /* LD (IY+o),C */ -OP(fd,72) { eay(); wm(m_ea, D); } /* LD (IY+o),D */ -OP(fd,73) { eay(); wm(m_ea, E); } /* LD (IY+o),E */ -OP(fd,74) { eay(); wm(m_ea, H); } /* LD (IY+o),H */ -OP(fd,75) { eay(); wm(m_ea, L); } /* LD (IY+o),L */ -OP(fd,76) { illegal_1(); op_76(); } /* DB FD */ -OP(fd,77) { eay(); wm(m_ea, A); } /* LD (IY+o),A */ - -OP(fd,78) { illegal_1(); op_78(); } /* DB FD */ -OP(fd,79) { illegal_1(); op_79(); } /* DB FD */ -OP(fd,7a) { illegal_1(); op_7a(); } /* DB FD */ -OP(fd,7b) { illegal_1(); op_7b(); } /* DB FD */ -OP(fd,7c) { A = HY; } /* LD A,HY */ -OP(fd,7d) { A = LY; } /* LD A,LY */ -OP(fd,7e) { eay(); A = rm(m_ea); } /* LD A,(IY+o) */ -OP(fd,7f) { illegal_1(); op_7f(); } /* DB FD */ - -OP(fd,80) { illegal_1(); op_80(); } /* DB FD */ -OP(fd,81) { illegal_1(); op_81(); } /* DB FD */ -OP(fd,82) { illegal_1(); op_82(); } /* DB FD */ -OP(fd,83) { illegal_1(); op_83(); } /* DB FD */ -OP(fd,84) { add_a(HY); } /* ADD A,HY */ -OP(fd,85) { add_a(LY); } /* ADD A,LY */ -OP(fd,86) { eay(); add_a(rm(m_ea)); } /* ADD A,(IY+o) */ -OP(fd,87) { illegal_1(); op_87(); } /* DB FD */ - -OP(fd,88) { illegal_1(); op_88(); } /* DB FD */ -OP(fd,89) { illegal_1(); op_89(); } /* DB FD */ -OP(fd,8a) { illegal_1(); op_8a(); } /* DB FD */ -OP(fd,8b) { illegal_1(); op_8b(); } /* DB FD */ -OP(fd,8c) { adc_a(HY); } /* ADC A,HY */ -OP(fd,8d) { adc_a(LY); } /* ADC A,LY */ -OP(fd,8e) { eay(); adc_a(rm(m_ea)); } /* ADC A,(IY+o) */ -OP(fd,8f) { illegal_1(); op_8f(); } /* DB FD */ - -OP(fd,90) { illegal_1(); op_90(); } /* DB FD */ -OP(fd,91) { illegal_1(); op_91(); } /* DB FD */ -OP(fd,92) { illegal_1(); op_92(); } /* DB FD */ -OP(fd,93) { illegal_1(); op_93(); } /* DB FD */ -OP(fd,94) { sub(HY); } /* SUB HY */ -OP(fd,95) { sub(LY); } /* SUB LY */ -OP(fd,96) { eay(); sub(rm(m_ea)); } /* SUB (IY+o) */ -OP(fd,97) { illegal_1(); op_97(); } /* DB FD */ - -OP(fd,98) { illegal_1(); op_98(); } /* DB FD */ -OP(fd,99) { illegal_1(); op_99(); } /* DB FD */ -OP(fd,9a) { illegal_1(); op_9a(); } /* DB FD */ -OP(fd,9b) { illegal_1(); op_9b(); } /* DB FD */ -OP(fd,9c) { sbc_a(HY); } /* SBC A,HY */ -OP(fd,9d) { sbc_a(LY); } /* SBC A,LY */ -OP(fd,9e) { eay(); sbc_a(rm(m_ea)); } /* SBC A,(IY+o) */ -OP(fd,9f) { illegal_1(); op_9f(); } /* DB FD */ - -OP(fd,a0) { illegal_1(); op_a0(); } /* DB FD */ -OP(fd,a1) { illegal_1(); op_a1(); } /* DB FD */ -OP(fd,a2) { illegal_1(); op_a2(); } /* DB FD */ -OP(fd,a3) { illegal_1(); op_a3(); } /* DB FD */ -OP(fd,a4) { and_a(HY); } /* AND HY */ -OP(fd,a5) { and_a(LY); } /* AND LY */ -OP(fd,a6) { eay(); and_a(rm(m_ea)); } /* AND (IY+o) */ -OP(fd,a7) { illegal_1(); op_a7(); } /* DB FD */ - -OP(fd,a8) { illegal_1(); op_a8(); } /* DB FD */ -OP(fd,a9) { illegal_1(); op_a9(); } /* DB FD */ -OP(fd,aa) { illegal_1(); op_aa(); } /* DB FD */ -OP(fd,ab) { illegal_1(); op_ab(); } /* DB FD */ -OP(fd,ac) { xor_a(HY); } /* XOR HY */ -OP(fd,ad) { xor_a(LY); } /* XOR LY */ -OP(fd,ae) { eay(); xor_a(rm(m_ea)); } /* XOR (IY+o) */ -OP(fd,af) { illegal_1(); op_af(); } /* DB FD */ - -OP(fd,b0) { illegal_1(); op_b0(); } /* DB FD */ -OP(fd,b1) { illegal_1(); op_b1(); } /* DB FD */ -OP(fd,b2) { illegal_1(); op_b2(); } /* DB FD */ -OP(fd,b3) { illegal_1(); op_b3(); } /* DB FD */ -OP(fd,b4) { or_a(HY); } /* OR HY */ -OP(fd,b5) { or_a(LY); } /* OR LY */ -OP(fd,b6) { eay(); or_a(rm(m_ea)); } /* OR (IY+o) */ -OP(fd,b7) { illegal_1(); op_b7(); } /* DB FD */ - -OP(fd,b8) { illegal_1(); op_b8(); } /* DB FD */ -OP(fd,b9) { illegal_1(); op_b9(); } /* DB FD */ -OP(fd,ba) { illegal_1(); op_ba(); } /* DB FD */ -OP(fd,bb) { illegal_1(); op_bb(); } /* DB FD */ -OP(fd,bc) { cp(HY); } /* CP HY */ -OP(fd,bd) { cp(LY); } /* CP LY */ -OP(fd,be) { eay(); cp(rm(m_ea)); } /* CP (IY+o) */ -OP(fd,bf) { illegal_1(); op_bf(); } /* DB FD */ - -OP(fd,c0) { illegal_1(); op_c0(); } /* DB FD */ -OP(fd,c1) { illegal_1(); op_c1(); } /* DB FD */ -OP(fd,c2) { illegal_1(); op_c2(); } /* DB FD */ -OP(fd,c3) { illegal_1(); op_c3(); } /* DB FD */ -OP(fd,c4) { illegal_1(); op_c4(); } /* DB FD */ -OP(fd,c5) { illegal_1(); op_c5(); } /* DB FD */ -OP(fd,c6) { illegal_1(); op_c6(); } /* DB FD */ -OP(fd,c7) { illegal_1(); op_c7(); } /* DB FD */ - -OP(fd,c8) { illegal_1(); op_c8(); } /* DB FD */ -OP(fd,c9) { illegal_1(); op_c9(); } /* DB FD */ -OP(fd,ca) { illegal_1(); op_ca(); } /* DB FD */ -OP(fd,cb) { eay(); EXEC(xycb,arg()); } /* ** FD CB xx */ -OP(fd,cc) { illegal_1(); op_cc(); } /* DB FD */ -OP(fd,cd) { illegal_1(); op_cd(); } /* DB FD */ -OP(fd,ce) { illegal_1(); op_ce(); } /* DB FD */ -OP(fd,cf) { illegal_1(); op_cf(); } /* DB FD */ - -OP(fd,d0) { illegal_1(); op_d0(); } /* DB FD */ -OP(fd,d1) { illegal_1(); op_d1(); } /* DB FD */ -OP(fd,d2) { illegal_1(); op_d2(); } /* DB FD */ -OP(fd,d3) { illegal_1(); op_d3(); } /* DB FD */ -OP(fd,d4) { illegal_1(); op_d4(); } /* DB FD */ -OP(fd,d5) { illegal_1(); op_d5(); } /* DB FD */ -OP(fd,d6) { illegal_1(); op_d6(); } /* DB FD */ -OP(fd,d7) { illegal_1(); op_d7(); } /* DB FD */ - -OP(fd,d8) { illegal_1(); op_d8(); } /* DB FD */ -OP(fd,d9) { illegal_1(); op_d9(); } /* DB FD */ -OP(fd,da) { illegal_1(); op_da(); } /* DB FD */ -OP(fd,db) { illegal_1(); op_db(); } /* DB FD */ -OP(fd,dc) { illegal_1(); op_dc(); } /* DB FD */ -OP(fd,dd) { illegal_1(); op_dd(); } /* DB FD */ -OP(fd,de) { illegal_1(); op_de(); } /* DB FD */ -OP(fd,df) { illegal_1(); op_df(); } /* DB FD */ - -OP(fd,e0) { illegal_1(); op_e0(); } /* DB FD */ -OP(fd,e1) { pop(m_iy); } /* POP IY */ -OP(fd,e2) { illegal_1(); op_e2(); } /* DB FD */ -OP(fd,e3) { ex_sp(m_iy); } /* EX (SP),IY */ -OP(fd,e4) { illegal_1(); op_e4(); } /* DB FD */ -OP(fd,e5) { push(m_iy); } /* PUSH IY */ -OP(fd,e6) { illegal_1(); op_e6(); } /* DB FD */ -OP(fd,e7) { illegal_1(); op_e7(); } /* DB FD */ - -OP(fd,e8) { illegal_1(); op_e8(); } /* DB FD */ -OP(fd,e9) { PC = IY; } /* JP (IY) */ -OP(fd,ea) { illegal_1(); op_ea(); } /* DB FD */ -OP(fd,eb) { illegal_1(); op_eb(); } /* DB FD */ -OP(fd,ec) { illegal_1(); op_ec(); } /* DB FD */ -OP(fd,ed) { illegal_1(); op_ed(); } /* DB FD */ -OP(fd,ee) { illegal_1(); op_ee(); } /* DB FD */ -OP(fd,ef) { illegal_1(); op_ef(); } /* DB FD */ - -OP(fd,f0) { illegal_1(); op_f0(); } /* DB FD */ -OP(fd,f1) { illegal_1(); op_f1(); } /* DB FD */ -OP(fd,f2) { illegal_1(); op_f2(); } /* DB FD */ -OP(fd,f3) { illegal_1(); op_f3(); } /* DB FD */ -OP(fd,f4) { illegal_1(); op_f4(); } /* DB FD */ -OP(fd,f5) { illegal_1(); op_f5(); } /* DB FD */ -OP(fd,f6) { illegal_1(); op_f6(); } /* DB FD */ -OP(fd,f7) { illegal_1(); op_f7(); } /* DB FD */ - -OP(fd,f8) { illegal_1(); op_f8(); } /* DB FD */ -OP(fd,f9) { SP = IY; } /* LD SP,IY */ -OP(fd,fa) { illegal_1(); op_fa(); } /* DB FD */ -OP(fd,fb) { illegal_1(); op_fb(); } /* DB FD */ -OP(fd,fc) { illegal_1(); op_fc(); } /* DB FD */ -OP(fd,fd) { illegal_1(); op_fd(); } /* DB FD */ -OP(fd,fe) { illegal_1(); op_fe(); } /* DB FD */ -OP(fd,ff) { illegal_1(); op_ff(); } /* DB FD */ - -OP(illegal,2) +void z80_device::set_f(u8 f) { - logerror("Z80 ill. opcode $ed $%02x\n", - m_opcodes_cache->read_byte((PCD-1)&0xffff)); + QT = 0; + F = f; } -/********************************************************** - * special opcodes (ED prefix) - **********************************************************/ -OP(ed,00) { illegal_2(); } /* DB ED */ -OP(ed,01) { illegal_2(); } /* DB ED */ -OP(ed,02) { illegal_2(); } /* DB ED */ -OP(ed,03) { illegal_2(); } /* DB ED */ -OP(ed,04) { illegal_2(); } /* DB ED */ -OP(ed,05) { illegal_2(); } /* DB ED */ -OP(ed,06) { illegal_2(); } /* DB ED */ -OP(ed,07) { illegal_2(); } /* DB ED */ - -OP(ed,08) { illegal_2(); } /* DB ED */ -OP(ed,09) { illegal_2(); } /* DB ED */ -OP(ed,0a) { illegal_2(); } /* DB ED */ -OP(ed,0b) { illegal_2(); } /* DB ED */ -OP(ed,0c) { illegal_2(); } /* DB ED */ -OP(ed,0d) { illegal_2(); } /* DB ED */ -OP(ed,0e) { illegal_2(); } /* DB ED */ -OP(ed,0f) { illegal_2(); } /* DB ED */ - -OP(ed,10) { illegal_2(); } /* DB ED */ -OP(ed,11) { illegal_2(); } /* DB ED */ -OP(ed,12) { illegal_2(); } /* DB ED */ -OP(ed,13) { illegal_2(); } /* DB ED */ -OP(ed,14) { illegal_2(); } /* DB ED */ -OP(ed,15) { illegal_2(); } /* DB ED */ -OP(ed,16) { illegal_2(); } /* DB ED */ -OP(ed,17) { illegal_2(); } /* DB ED */ - -OP(ed,18) { illegal_2(); } /* DB ED */ -OP(ed,19) { illegal_2(); } /* DB ED */ -OP(ed,1a) { illegal_2(); } /* DB ED */ -OP(ed,1b) { illegal_2(); } /* DB ED */ -OP(ed,1c) { illegal_2(); } /* DB ED */ -OP(ed,1d) { illegal_2(); } /* DB ED */ -OP(ed,1e) { illegal_2(); } /* DB ED */ -OP(ed,1f) { illegal_2(); } /* DB ED */ - -OP(ed,20) { illegal_2(); } /* DB ED */ -OP(ed,21) { illegal_2(); } /* DB ED */ -OP(ed,22) { illegal_2(); } /* DB ED */ -OP(ed,23) { illegal_2(); } /* DB ED */ -OP(ed,24) { illegal_2(); } /* DB ED */ -OP(ed,25) { illegal_2(); } /* DB ED */ -OP(ed,26) { illegal_2(); } /* DB ED */ -OP(ed,27) { illegal_2(); } /* DB ED */ - -OP(ed,28) { illegal_2(); } /* DB ED */ -OP(ed,29) { illegal_2(); } /* DB ED */ -OP(ed,2a) { illegal_2(); } /* DB ED */ -OP(ed,2b) { illegal_2(); } /* DB ED */ -OP(ed,2c) { illegal_2(); } /* DB ED */ -OP(ed,2d) { illegal_2(); } /* DB ED */ -OP(ed,2e) { illegal_2(); } /* DB ED */ -OP(ed,2f) { illegal_2(); } /* DB ED */ - -OP(ed,30) { illegal_2(); } /* DB ED */ -OP(ed,31) { illegal_2(); } /* DB ED */ -OP(ed,32) { illegal_2(); } /* DB ED */ -OP(ed,33) { illegal_2(); } /* DB ED */ -OP(ed,34) { illegal_2(); } /* DB ED */ -OP(ed,35) { illegal_2(); } /* DB ED */ -OP(ed,36) { illegal_2(); } /* DB ED */ -OP(ed,37) { illegal_2(); } /* DB ED */ - -OP(ed,38) { illegal_2(); } /* DB ED */ -OP(ed,39) { illegal_2(); } /* DB ED */ -OP(ed,3a) { illegal_2(); } /* DB ED */ -OP(ed,3b) { illegal_2(); } /* DB ED */ -OP(ed,3c) { illegal_2(); } /* DB ED */ -OP(ed,3d) { illegal_2(); } /* DB ED */ -OP(ed,3e) { illegal_2(); } /* DB ED */ -OP(ed,3f) { illegal_2(); } /* DB ED */ - -OP(ed,40) { B = in(BC); F = (F & CF) | SZP[B]; } /* IN B,(C) */ -OP(ed,41) { out(BC, B); } /* OUT (C),B */ -OP(ed,42) { sbc_hl(m_bc); } /* SBC HL,BC */ -OP(ed,43) { m_ea = arg16(); wm16(m_ea, m_bc); WZ = m_ea + 1; } /* LD (w),BC */ -OP(ed,44) { neg(); } /* NEG */ -OP(ed,45) { retn(); } /* RETN */ -OP(ed,46) { m_im = 0; } /* IM 0 */ -OP(ed,47) { ld_i_a(); } /* LD i,A */ - -OP(ed,48) { C = in(BC); F = (F & CF) | SZP[C]; } /* IN C,(C) */ -OP(ed,49) { out(BC, C); } /* OUT (C),C */ -OP(ed,4a) { adc_hl(m_bc); } /* ADC HL,BC */ -OP(ed,4b) { m_ea = arg16(); rm16(m_ea, m_bc); WZ = m_ea + 1; } /* LD BC,(w) */ -OP(ed,4c) { neg(); } /* NEG */ -OP(ed,4d) { reti(); } /* RETI */ -OP(ed,4e) { m_im = 0; } /* IM 0 */ -OP(ed,4f) { ld_r_a(); } /* LD r,A */ - -OP(ed,50) { D = in(BC); F = (F & CF) | SZP[D]; } /* IN D,(C) */ -OP(ed,51) { out(BC, D); } /* OUT (C),D */ -OP(ed,52) { sbc_hl(m_de); } /* SBC HL,DE */ -OP(ed,53) { m_ea = arg16(); wm16(m_ea, m_de); WZ = m_ea + 1; } /* LD (w),DE */ -OP(ed,54) { neg(); } /* NEG */ -OP(ed,55) { retn(); } /* RETN */ -OP(ed,56) { m_im = 1; } /* IM 1 */ -OP(ed,57) { ld_a_i(); } /* LD A,i */ - -OP(ed,58) { E = in(BC); F = (F & CF) | SZP[E]; } /* IN E,(C) */ -OP(ed,59) { out(BC, E); } /* OUT (C),E */ -OP(ed,5a) { adc_hl(m_de); } /* ADC HL,DE */ -OP(ed,5b) { m_ea = arg16(); rm16(m_ea, m_de); WZ = m_ea + 1; } /* LD DE,(w) */ -OP(ed,5c) { neg(); } /* NEG */ -OP(ed,5d) { reti(); } /* RETI */ -OP(ed,5e) { m_im = 2; } /* IM 2 */ -OP(ed,5f) { ld_a_r(); } /* LD A,r */ - -OP(ed,60) { H = in(BC); F = (F & CF) | SZP[H]; } /* IN H,(C) */ -OP(ed,61) { out(BC, H); } /* OUT (C),H */ -OP(ed,62) { sbc_hl(m_hl); } /* SBC HL,HL */ -OP(ed,63) { m_ea = arg16(); wm16(m_ea, m_hl); WZ = m_ea + 1; } /* LD (w),HL */ -OP(ed,64) { neg(); } /* NEG */ -OP(ed,65) { retn(); } /* RETN */ -OP(ed,66) { m_im = 0; } /* IM 0 */ -OP(ed,67) { rrd(); } /* RRD (HL) */ - -OP(ed,68) { L = in(BC); F = (F & CF) | SZP[L]; } /* IN L,(C) */ -OP(ed,69) { out(BC, L); } /* OUT (C),L */ -OP(ed,6a) { adc_hl(m_hl); } /* ADC HL,HL */ -OP(ed,6b) { m_ea = arg16(); rm16(m_ea, m_hl); WZ = m_ea + 1; } /* LD HL,(w) */ -OP(ed,6c) { neg(); } /* NEG */ -OP(ed,6d) { reti(); } /* RETI */ -OP(ed,6e) { m_im = 0; } /* IM 0 */ -OP(ed,6f) { rld(); } /* RLD (HL) */ - -OP(ed,70) { uint8_t res = in(BC); F = (F & CF) | SZP[res]; } /* IN 0,(C) */ -OP(ed,71) { out(BC, 0); } /* OUT (C),0 */ -OP(ed,72) { sbc_hl(m_sp); } /* SBC HL,SP */ -OP(ed,73) { m_ea = arg16(); wm16(m_ea, m_sp); WZ = m_ea + 1; } /* LD (w),SP */ -OP(ed,74) { neg(); } /* NEG */ -OP(ed,75) { retn(); } /* RETN */ -OP(ed,76) { m_im = 1; } /* IM 1 */ -OP(ed,77) { illegal_2(); } /* DB ED,77 */ - -OP(ed,78) { A = in(BC); F = (F & CF) | SZP[A]; WZ = BC + 1; } /* IN A,(C) */ -OP(ed,79) { out(BC, A); WZ = BC + 1; } /* OUT (C),A */ -OP(ed,7a) { adc_hl(m_sp); } /* ADC HL,SP */ -OP(ed,7b) { m_ea = arg16(); rm16(m_ea, m_sp); WZ = m_ea + 1; } /* LD SP,(w) */ -OP(ed,7c) { neg(); } /* NEG */ -OP(ed,7d) { reti(); } /* RETI */ -OP(ed,7e) { m_im = 2; } /* IM 2 */ -OP(ed,7f) { illegal_2(); } /* DB ED,7F */ - -OP(ed,80) { illegal_2(); } /* DB ED */ -OP(ed,81) { illegal_2(); } /* DB ED */ -OP(ed,82) { illegal_2(); } /* DB ED */ -OP(ed,83) { illegal_2(); } /* DB ED */ -OP(ed,84) { illegal_2(); } /* DB ED */ -OP(ed,85) { illegal_2(); } /* DB ED */ -OP(ed,86) { illegal_2(); } /* DB ED */ -OP(ed,87) { illegal_2(); } /* DB ED */ - -OP(ed,88) { illegal_2(); } /* DB ED */ -OP(ed,89) { illegal_2(); } /* DB ED */ -OP(ed,8a) { illegal_2(); } /* DB ED */ -OP(ed,8b) { illegal_2(); } /* DB ED */ -OP(ed,8c) { illegal_2(); } /* DB ED */ -OP(ed,8d) { illegal_2(); } /* DB ED */ -OP(ed,8e) { illegal_2(); } /* DB ED */ -OP(ed,8f) { illegal_2(); } /* DB ED */ - -OP(ed,90) { illegal_2(); } /* DB ED */ -OP(ed,91) { illegal_2(); } /* DB ED */ -OP(ed,92) { illegal_2(); } /* DB ED */ -OP(ed,93) { illegal_2(); } /* DB ED */ -OP(ed,94) { illegal_2(); } /* DB ED */ -OP(ed,95) { illegal_2(); } /* DB ED */ -OP(ed,96) { illegal_2(); } /* DB ED */ -OP(ed,97) { illegal_2(); } /* DB ED */ - -OP(ed,98) { illegal_2(); } /* DB ED */ -OP(ed,99) { illegal_2(); } /* DB ED */ -OP(ed,9a) { illegal_2(); } /* DB ED */ -OP(ed,9b) { illegal_2(); } /* DB ED */ -OP(ed,9c) { illegal_2(); } /* DB ED */ -OP(ed,9d) { illegal_2(); } /* DB ED */ -OP(ed,9e) { illegal_2(); } /* DB ED */ -OP(ed,9f) { illegal_2(); } /* DB ED */ - -OP(ed,a0) { ldi(); } /* LDI */ -OP(ed,a1) { cpi(); } /* CPI */ -OP(ed,a2) { ini(); } /* INI */ -OP(ed,a3) { outi(); } /* OUTI */ -OP(ed,a4) { illegal_2(); } /* DB ED */ -OP(ed,a5) { illegal_2(); } /* DB ED */ -OP(ed,a6) { illegal_2(); } /* DB ED */ -OP(ed,a7) { illegal_2(); } /* DB ED */ - -OP(ed,a8) { ldd(); } /* LDD */ -OP(ed,a9) { cpd(); } /* CPD */ -OP(ed,aa) { ind(); } /* IND */ -OP(ed,ab) { outd(); } /* OUTD */ -OP(ed,ac) { illegal_2(); } /* DB ED */ -OP(ed,ad) { illegal_2(); } /* DB ED */ -OP(ed,ae) { illegal_2(); } /* DB ED */ -OP(ed,af) { illegal_2(); } /* DB ED */ - -OP(ed,b0) { ldir(); } /* LDIR */ -OP(ed,b1) { cpir(); } /* CPIR */ -OP(ed,b2) { inir(); } /* INIR */ -OP(ed,b3) { otir(); } /* OTIR */ -OP(ed,b4) { illegal_2(); } /* DB ED */ -OP(ed,b5) { illegal_2(); } /* DB ED */ -OP(ed,b6) { illegal_2(); } /* DB ED */ -OP(ed,b7) { illegal_2(); } /* DB ED */ - -OP(ed,b8) { lddr(); } /* LDDR */ -OP(ed,b9) { cpdr(); } /* CPDR */ -OP(ed,ba) { indr(); } /* INDR */ -OP(ed,bb) { otdr(); } /* OTDR */ -OP(ed,bc) { illegal_2(); } /* DB ED */ -OP(ed,bd) { illegal_2(); } /* DB ED */ -OP(ed,be) { illegal_2(); } /* DB ED */ -OP(ed,bf) { illegal_2(); } /* DB ED */ - -OP(ed,c0) { illegal_2(); } /* DB ED */ -OP(ed,c1) { illegal_2(); } /* DB ED */ -OP(ed,c2) { illegal_2(); } /* DB ED */ -OP(ed,c3) { illegal_2(); } /* DB ED */ -OP(ed,c4) { illegal_2(); } /* DB ED */ -OP(ed,c5) { illegal_2(); } /* DB ED */ -OP(ed,c6) { illegal_2(); } /* DB ED */ -OP(ed,c7) { illegal_2(); } /* DB ED */ - -OP(ed,c8) { illegal_2(); } /* DB ED */ -OP(ed,c9) { illegal_2(); } /* DB ED */ -OP(ed,ca) { illegal_2(); } /* DB ED */ -OP(ed,cb) { illegal_2(); } /* DB ED */ -OP(ed,cc) { illegal_2(); } /* DB ED */ -OP(ed,cd) { illegal_2(); } /* DB ED */ -OP(ed,ce) { illegal_2(); } /* DB ED */ -OP(ed,cf) { illegal_2(); } /* DB ED */ - -OP(ed,d0) { illegal_2(); } /* DB ED */ -OP(ed,d1) { illegal_2(); } /* DB ED */ -OP(ed,d2) { illegal_2(); } /* DB ED */ -OP(ed,d3) { illegal_2(); } /* DB ED */ -OP(ed,d4) { illegal_2(); } /* DB ED */ -OP(ed,d5) { illegal_2(); } /* DB ED */ -OP(ed,d6) { illegal_2(); } /* DB ED */ -OP(ed,d7) { illegal_2(); } /* DB ED */ - -OP(ed,d8) { illegal_2(); } /* DB ED */ -OP(ed,d9) { illegal_2(); } /* DB ED */ -OP(ed,da) { illegal_2(); } /* DB ED */ -OP(ed,db) { illegal_2(); } /* DB ED */ -OP(ed,dc) { illegal_2(); } /* DB ED */ -OP(ed,dd) { illegal_2(); } /* DB ED */ -OP(ed,de) { illegal_2(); } /* DB ED */ -OP(ed,df) { illegal_2(); } /* DB ED */ - -OP(ed,e0) { illegal_2(); } /* DB ED */ -OP(ed,e1) { illegal_2(); } /* DB ED */ -OP(ed,e2) { illegal_2(); } /* DB ED */ -OP(ed,e3) { illegal_2(); } /* DB ED */ -OP(ed,e4) { illegal_2(); } /* DB ED */ -OP(ed,e5) { illegal_2(); } /* DB ED */ -OP(ed,e6) { illegal_2(); } /* DB ED */ -OP(ed,e7) { illegal_2(); } /* DB ED */ - -OP(ed,e8) { illegal_2(); } /* DB ED */ -OP(ed,e9) { illegal_2(); } /* DB ED */ -OP(ed,ea) { illegal_2(); } /* DB ED */ -OP(ed,eb) { illegal_2(); } /* DB ED */ -OP(ed,ec) { illegal_2(); } /* DB ED */ -OP(ed,ed) { illegal_2(); } /* DB ED */ -OP(ed,ee) { illegal_2(); } /* DB ED */ -OP(ed,ef) { illegal_2(); } /* DB ED */ - -OP(ed,f0) { illegal_2(); } /* DB ED */ -OP(ed,f1) { illegal_2(); } /* DB ED */ -OP(ed,f2) { illegal_2(); } /* DB ED */ -OP(ed,f3) { illegal_2(); } /* DB ED */ -OP(ed,f4) { illegal_2(); } /* DB ED */ -OP(ed,f5) { illegal_2(); } /* DB ED */ -OP(ed,f6) { illegal_2(); } /* DB ED */ -OP(ed,f7) { illegal_2(); } /* DB ED */ - -OP(ed,f8) { illegal_2(); } /* DB ED */ -OP(ed,f9) { illegal_2(); } /* DB ED */ -OP(ed,fa) { illegal_2(); } /* DB ED */ -OP(ed,fb) { illegal_2(); } /* DB ED */ -OP(ed,fc) { illegal_2(); } /* DB ED */ -OP(ed,fd) { illegal_2(); } /* DB ED */ -OP(ed,fe) { illegal_2(); } /* DB ED */ -OP(ed,ff) { illegal_2(); } /* DB ED */ - - -/********************************************************** - * main opcodes - **********************************************************/ -OP(op,00) { } /* NOP */ -OP(op,01) { BC = arg16(); } /* LD BC,w */ -OP(op,02) { wm(BC,A); WZ_L = (BC + 1) & 0xFF; WZ_H = A; } /* LD (BC),A */ -OP(op,03) { BC++; } /* INC BC */ -OP(op,04) { B = inc(B); } /* INC B */ -OP(op,05) { B = dec(B); } /* DEC B */ -OP(op,06) { B = arg(); } /* LD B,n */ -OP(op,07) { rlca(); } /* RLCA */ - -OP(op,08) { ex_af(); } /* EX AF,AF' */ -OP(op,09) { add16(m_hl, m_bc); } /* ADD HL,BC */ -OP(op,0a) { A = rm(BC); WZ=BC+1; } /* LD A,(BC) */ -OP(op,0b) { BC--; } /* DEC BC */ -OP(op,0c) { C = inc(C); } /* INC C */ -OP(op,0d) { C = dec(C); } /* DEC C */ -OP(op,0e) { C = arg(); } /* LD C,n */ -OP(op,0f) { rrca(); } /* RRCA */ - -OP(op,10) { B--; jr_cond(B, 0x10); } /* DJNZ o */ -OP(op,11) { DE = arg16(); } /* LD DE,w */ -OP(op,12) { wm(DE,A); WZ_L = (DE + 1) & 0xFF; WZ_H = A; } /* LD (DE),A */ -OP(op,13) { DE++; } /* INC DE */ -OP(op,14) { D = inc(D); } /* INC D */ -OP(op,15) { D = dec(D); } /* DEC D */ -OP(op,16) { D = arg(); } /* LD D,n */ -OP(op,17) { rla(); } /* RLA */ - -OP(op,18) { jr(); } /* JR o */ -OP(op,19) { add16(m_hl, m_de); } /* ADD HL,DE */ -OP(op,1a) { A = rm(DE); WZ = DE + 1; } /* LD A,(DE) */ -OP(op,1b) { DE--; } /* DEC DE */ -OP(op,1c) { E = inc(E); } /* INC E */ -OP(op,1d) { E = dec(E); } /* DEC E */ -OP(op,1e) { E = arg(); } /* LD E,n */ -OP(op,1f) { rra(); } /* RRA */ - -OP(op,20) { jr_cond(!(F & ZF), 0x20); } /* JR NZ,o */ -OP(op,21) { HL = arg16(); } /* LD HL,w */ -OP(op,22) { m_ea = arg16(); wm16(m_ea, m_hl); WZ = m_ea + 1; } /* LD (w),HL */ -OP(op,23) { HL++; } /* INC HL */ -OP(op,24) { H = inc(H); } /* INC H */ -OP(op,25) { H = dec(H); } /* DEC H */ -OP(op,26) { H = arg(); } /* LD H,n */ -OP(op,27) { daa(); } /* DAA */ - -OP(op,28) { jr_cond(F & ZF, 0x28); } /* JR Z,o */ -OP(op,29) { add16(m_hl, m_hl); } /* ADD HL,HL */ -OP(op,2a) { m_ea = arg16(); rm16(m_ea, m_hl); WZ = m_ea+1; } /* LD HL,(w) */ -OP(op,2b) { HL--; } /* DEC HL */ -OP(op,2c) { L = inc(L); } /* INC L */ -OP(op,2d) { L = dec(L); } /* DEC L */ -OP(op,2e) { L = arg(); } /* LD L,n */ -OP(op,2f) { A ^= 0xff; F = (F & (SF | ZF | PF | CF)) | HF | NF | (A & (YF | XF)); } /* CPL */ - -OP(op,30) { jr_cond(!(F & CF), 0x30); } /* JR NC,o */ -OP(op,31) { SP = arg16(); } /* LD SP,w */ -OP(op,32) { m_ea = arg16(); wm(m_ea, A); WZ_L = (m_ea + 1) & 0xFF; WZ_H = A; } /* LD (w),A */ -OP(op,33) { SP++; } /* INC SP */ -OP(op,34) { wm(HL, inc(rm(HL))); } /* INC (HL) */ -OP(op,35) { wm(HL, dec(rm(HL))); } /* DEC (HL) */ -OP(op,36) { wm(HL, arg()); } /* LD (HL),n */ -OP(op,37) { F = (F & (SF | ZF | YF | XF | PF)) | CF | (A & (YF | XF)); } /* SCF */ - -OP(op,38) { jr_cond(F & CF, 0x38); } /* JR C,o */ -OP(op,39) { add16(m_hl, m_sp); } /* ADD HL,SP */ -OP(op,3a) { m_ea = arg16(); A = rm(m_ea); WZ = m_ea + 1; } /* LD A,(w) */ -OP(op,3b) { SP--; } /* DEC SP */ -OP(op,3c) { A = inc(A); } /* INC A */ -OP(op,3d) { A = dec(A); } /* DEC A */ -OP(op,3e) { A = arg(); } /* LD A,n */ -OP(op,3f) { F = ((F&(SF|ZF|YF|XF|PF|CF))|((F&CF)<<4)|(A&(YF|XF)))^CF; } /* CCF */ - -OP(op,40) { } /* LD B,B */ -OP(op,41) { B = C; } /* LD B,C */ -OP(op,42) { B = D; } /* LD B,D */ -OP(op,43) { B = E; } /* LD B,E */ -OP(op,44) { B = H; } /* LD B,H */ -OP(op,45) { B = L; } /* LD B,L */ -OP(op,46) { B = rm(HL); } /* LD B,(HL) */ -OP(op,47) { B = A; } /* LD B,A */ - -OP(op,48) { C = B; } /* LD C,B */ -OP(op,49) { } /* LD C,C */ -OP(op,4a) { C = D; } /* LD C,D */ -OP(op,4b) { C = E; } /* LD C,E */ -OP(op,4c) { C = H; } /* LD C,H */ -OP(op,4d) { C = L; } /* LD C,L */ -OP(op,4e) { C = rm(HL); } /* LD C,(HL) */ -OP(op,4f) { C = A; } /* LD C,A */ - -OP(op,50) { D = B; } /* LD D,B */ -OP(op,51) { D = C; } /* LD D,C */ -OP(op,52) { } /* LD D,D */ -OP(op,53) { D = E; } /* LD D,E */ -OP(op,54) { D = H; } /* LD D,H */ -OP(op,55) { D = L; } /* LD D,L */ -OP(op,56) { D = rm(HL); } /* LD D,(HL) */ -OP(op,57) { D = A; } /* LD D,A */ - -OP(op,58) { E = B; } /* LD E,B */ -OP(op,59) { E = C; } /* LD E,C */ -OP(op,5a) { E = D; } /* LD E,D */ -OP(op,5b) { } /* LD E,E */ -OP(op,5c) { E = H; } /* LD E,H */ -OP(op,5d) { E = L; } /* LD E,L */ -OP(op,5e) { E = rm(HL); } /* LD E,(HL) */ -OP(op,5f) { E = A; } /* LD E,A */ - -OP(op,60) { H = B; } /* LD H,B */ -OP(op,61) { H = C; } /* LD H,C */ -OP(op,62) { H = D; } /* LD H,D */ -OP(op,63) { H = E; } /* LD H,E */ -OP(op,64) { } /* LD H,H */ -OP(op,65) { H = L; } /* LD H,L */ -OP(op,66) { H = rm(HL); } /* LD H,(HL) */ -OP(op,67) { H = A; } /* LD H,A */ - -OP(op,68) { L = B; } /* LD L,B */ -OP(op,69) { L = C; } /* LD L,C */ -OP(op,6a) { L = D; } /* LD L,D */ -OP(op,6b) { L = E; } /* LD L,E */ -OP(op,6c) { L = H; } /* LD L,H */ -OP(op,6d) { } /* LD L,L */ -OP(op,6e) { L = rm(HL); } /* LD L,(HL) */ -OP(op,6f) { L = A; } /* LD L,A */ - -OP(op,70) { wm(HL, B); } /* LD (HL),B */ -OP(op,71) { wm(HL, C); } /* LD (HL),C */ -OP(op,72) { wm(HL, D); } /* LD (HL),D */ -OP(op,73) { wm(HL, E); } /* LD (HL),E */ -OP(op,74) { wm(HL, H); } /* LD (HL),H */ -OP(op,75) { wm(HL, L); } /* LD (HL),L */ -OP(op,76) { halt(); } /* halt */ -OP(op,77) { wm(HL, A); } /* LD (HL),A */ - -OP(op,78) { A = B; } /* LD A,B */ -OP(op,79) { A = C; } /* LD A,C */ -OP(op,7a) { A = D; } /* LD A,D */ -OP(op,7b) { A = E; } /* LD A,E */ -OP(op,7c) { A = H; } /* LD A,H */ -OP(op,7d) { A = L; } /* LD A,L */ -OP(op,7e) { A = rm(HL); } /* LD A,(HL) */ -OP(op,7f) { } /* LD A,A */ - -OP(op,80) { add_a(B); } /* ADD A,B */ -OP(op,81) { add_a(C); } /* ADD A,C */ -OP(op,82) { add_a(D); } /* ADD A,D */ -OP(op,83) { add_a(E); } /* ADD A,E */ -OP(op,84) { add_a(H); } /* ADD A,H */ -OP(op,85) { add_a(L); } /* ADD A,L */ -OP(op,86) { add_a(rm(HL)); } /* ADD A,(HL) */ -OP(op,87) { add_a(A); } /* ADD A,A */ - -OP(op,88) { adc_a(B); } /* ADC A,B */ -OP(op,89) { adc_a(C); } /* ADC A,C */ -OP(op,8a) { adc_a(D); } /* ADC A,D */ -OP(op,8b) { adc_a(E); } /* ADC A,E */ -OP(op,8c) { adc_a(H); } /* ADC A,H */ -OP(op,8d) { adc_a(L); } /* ADC A,L */ -OP(op,8e) { adc_a(rm(HL)); } /* ADC A,(HL) */ -OP(op,8f) { adc_a(A); } /* ADC A,A */ - -OP(op,90) { sub(B); } /* SUB B */ -OP(op,91) { sub(C); } /* SUB C */ -OP(op,92) { sub(D); } /* SUB D */ -OP(op,93) { sub(E); } /* SUB E */ -OP(op,94) { sub(H); } /* SUB H */ -OP(op,95) { sub(L); } /* SUB L */ -OP(op,96) { sub(rm(HL)); } /* SUB (HL) */ -OP(op,97) { sub(A); } /* SUB A */ - -OP(op,98) { sbc_a(B); } /* SBC A,B */ -OP(op,99) { sbc_a(C); } /* SBC A,C */ -OP(op,9a) { sbc_a(D); } /* SBC A,D */ -OP(op,9b) { sbc_a(E); } /* SBC A,E */ -OP(op,9c) { sbc_a(H); } /* SBC A,H */ -OP(op,9d) { sbc_a(L); } /* SBC A,L */ -OP(op,9e) { sbc_a(rm(HL)); } /* SBC A,(HL) */ -OP(op,9f) { sbc_a(A); } /* SBC A,A */ - -OP(op,a0) { and_a(B); } /* AND B */ -OP(op,a1) { and_a(C); } /* AND C */ -OP(op,a2) { and_a(D); } /* AND D */ -OP(op,a3) { and_a(E); } /* AND E */ -OP(op,a4) { and_a(H); } /* AND H */ -OP(op,a5) { and_a(L); } /* AND L */ -OP(op,a6) { and_a(rm(HL)); } /* AND (HL) */ -OP(op,a7) { and_a(A); } /* AND A */ - -OP(op,a8) { xor_a(B); } /* XOR B */ -OP(op,a9) { xor_a(C); } /* XOR C */ -OP(op,aa) { xor_a(D); } /* XOR D */ -OP(op,ab) { xor_a(E); } /* XOR E */ -OP(op,ac) { xor_a(H); } /* XOR H */ -OP(op,ad) { xor_a(L); } /* XOR L */ -OP(op,ae) { xor_a(rm(HL)); } /* XOR (HL) */ -OP(op,af) { xor_a(A); } /* XOR A */ - -OP(op,b0) { or_a(B); } /* OR B */ -OP(op,b1) { or_a(C); } /* OR C */ -OP(op,b2) { or_a(D); } /* OR D */ -OP(op,b3) { or_a(E); } /* OR E */ -OP(op,b4) { or_a(H); } /* OR H */ -OP(op,b5) { or_a(L); } /* OR L */ -OP(op,b6) { or_a(rm(HL)); } /* OR (HL) */ -OP(op,b7) { or_a(A); } /* OR A */ - -OP(op,b8) { cp(B); } /* CP B */ -OP(op,b9) { cp(C); } /* CP C */ -OP(op,ba) { cp(D); } /* CP D */ -OP(op,bb) { cp(E); } /* CP E */ -OP(op,bc) { cp(H); } /* CP H */ -OP(op,bd) { cp(L); } /* CP L */ -OP(op,be) { cp(rm(HL)); } /* CP (HL) */ -OP(op,bf) { cp(A); } /* CP A */ - -OP(op,c0) { ret_cond(!(F & ZF), 0xc0); } /* RET NZ */ -OP(op,c1) { pop(m_bc); } /* POP BC */ -OP(op,c2) { jp_cond(!(F & ZF)); } /* JP NZ,a */ -OP(op,c3) { jp(); } /* JP a */ -OP(op,c4) { call_cond(!(F & ZF), 0xc4); } /* CALL NZ,a */ -OP(op,c5) { push(m_bc); } /* PUSH BC */ -OP(op,c6) { add_a(arg()); } /* ADD A,n */ -OP(op,c7) { rst(0x00); } /* RST 0 */ - -OP(op,c8) { ret_cond(F & ZF, 0xc8); } /* RET Z */ -OP(op,c9) { pop(m_pc); WZ = PCD; } /* RET */ -OP(op,ca) { jp_cond(F & ZF); } /* JP Z,a */ -OP(op,cb) { m_r++; EXEC(cb,rop()); } /* **** CB xx */ -OP(op,cc) { call_cond(F & ZF, 0xcc); } /* CALL Z,a */ -OP(op,cd) { call(); } /* CALL a */ -OP(op,ce) { adc_a(arg()); } /* ADC A,n */ -OP(op,cf) { rst(0x08); } /* RST 1 */ - -OP(op,d0) { ret_cond(!(F & CF), 0xd0); } /* RET NC */ -OP(op,d1) { pop(m_de); } /* POP DE */ -OP(op,d2) { jp_cond(!(F & CF)); } /* JP NC,a */ -OP(op,d3) { unsigned n = arg() | (A << 8); out(n, A); WZ_L = ((n & 0xff) + 1) & 0xff; WZ_H = A; } /* OUT (n),A */ -OP(op,d4) { call_cond(!(F & CF), 0xd4); } /* CALL NC,a */ -OP(op,d5) { push(m_de); } /* PUSH DE */ -OP(op,d6) { sub(arg()); } /* SUB n */ -OP(op,d7) { rst(0x10); } /* RST 2 */ - -OP(op,d8) { ret_cond(F & CF, 0xd8); } /* RET C */ -OP(op,d9) { exx(); } /* EXX */ -OP(op,da) { jp_cond(F & CF); } /* JP C,a */ -OP(op,db) { unsigned n = arg() | (A << 8); A = in(n); WZ = n + 1; } /* IN A,(n) */ -OP(op,dc) { call_cond(F & CF, 0xdc); } /* CALL C,a */ -OP(op,dd) { m_r++; EXEC(dd,rop()); } /* **** DD xx */ -OP(op,de) { sbc_a(arg()); } /* SBC A,n */ -OP(op,df) { rst(0x18); } /* RST 3 */ - -OP(op,e0) { ret_cond(!(F & PF), 0xe0); } /* RET PO */ -OP(op,e1) { pop(m_hl); } /* POP HL */ -OP(op,e2) { jp_cond(!(F & PF)); } /* JP PO,a */ -OP(op,e3) { ex_sp(m_hl); } /* EX HL,(SP) */ -OP(op,e4) { call_cond(!(F & PF), 0xe4); } /* CALL PO,a */ -OP(op,e5) { push(m_hl); } /* PUSH HL */ -OP(op,e6) { and_a(arg()); } /* AND n */ -OP(op,e7) { rst(0x20); } /* RST 4 */ - -OP(op,e8) { ret_cond(F & PF, 0xe8); } /* RET PE */ -OP(op,e9) { PC = HL; } /* JP (HL) */ -OP(op,ea) { jp_cond(F & PF); } /* JP PE,a */ -OP(op,eb) { ex_de_hl(); } /* EX DE,HL */ -OP(op,ec) { call_cond(F & PF, 0xec); } /* CALL PE,a */ -OP(op,ed) { m_r++; EXEC(ed,rop()); } /* **** ED xx */ -OP(op,ee) { xor_a(arg()); } /* XOR n */ -OP(op,ef) { rst(0x28); } /* RST 5 */ - -OP(op,f0) { ret_cond(!(F & SF), 0xf0); } /* RET P */ -OP(op,f1) { pop(m_af); } /* POP AF */ -OP(op,f2) { jp_cond(!(F & SF)); } /* JP P,a */ -OP(op,f3) { m_iff1 = m_iff2 = 0; } /* DI */ -OP(op,f4) { call_cond(!(F & SF), 0xf4); } /* CALL P,a */ -OP(op,f5) { push(m_af); } /* PUSH AF */ -OP(op,f6) { or_a(arg()); } /* OR n */ -OP(op,f7) { rst(0x30); } /* RST 6 */ - -OP(op,f8) { ret_cond(F & SF, 0xf8); } /* RET M */ -OP(op,f9) { SP = HL; } /* LD SP,HL */ -OP(op,fa) { jp_cond(F & SF); } /* JP M,a */ -OP(op,fb) { ei(); } /* EI */ -OP(op,fc) { call_cond(F & SF, 0xfc); } /* CALL M,a */ -OP(op,fd) { m_r++; EXEC(fd,rop()); } /* **** FD xx */ -OP(op,fe) { cp(arg()); } /* CP n */ -OP(op,ff) { rst(0x38); } /* RST 7 */ - - -void z80_device::take_nmi() +void z80_device::illegal_1() { - /* Check if processor was halted */ - leave_halt(); - -#if HAS_LDAIR_QUIRK - /* reset parity flag after LD A,I or LD A,R */ - if (m_after_ldair) F &= ~PF; -#endif - - m_iff1 = 0; - push(m_pc); - PCD = 0x0066; - WZ=PCD; - m_icount -= 11; - m_nmi_pending = false; + LOGMASKED(LOG_UNDOC, "ill. opcode $%02x $%02x ($%04x)\n", + m_opcodes.read_byte((PC - 1) & 0xffff), m_opcodes.read_byte(PC), PC - 1); } -void z80_device::take_interrupt() +void z80_device::illegal_2() { - // check if processor was halted - leave_halt(); - - // clear both interrupt flip flops - m_iff1 = m_iff2 = 0; - - // say hi - m_irqack_cb(true); - - // fetch the IRQ vector - device_z80daisy_interface *intf = daisy_get_irq_device(); - int irq_vector = (intf != nullptr) ? intf->z80daisy_irq_ack() : standard_irq_callback_member(*this, 0); - LOG(("Z80 single int. irq_vector $%02x\n", irq_vector)); - - /* Interrupt mode 2. Call [i:databyte] */ - if( m_im == 2 ) - { - // Zilog's datasheet claims that "the least-significant bit must be a zero." - // However, experiments have confirmed that IM 2 vectors do not have to be - // even, and all 8 bits will be used; even $FF is handled normally. - irq_vector = (irq_vector & 0xff) | (m_i << 8); - push(m_pc); - rm16(irq_vector, m_pc); - LOG(("Z80 IM2 [$%04x] = $%04x\n", irq_vector, PCD)); - /* CALL opcode timing + 'interrupt latency' cycles */ - m_icount -= m_cc_op[0xcd] + m_cc_ex[0xff]; - } - else - /* Interrupt mode 1. RST 38h */ - if( m_im == 1 ) - { - LOG(("Z80 '%s' IM1 $0038\n", tag())); - push(m_pc); - PCD = 0x0038; - /* RST $38 + 'interrupt latency' cycles */ - m_icount -= m_cc_op[0xff] + cc_ex[0xff]; - } - else - { - /* Interrupt mode 0. We check for CALL and JP instructions, */ - /* if neither of these were found we assume a 1 byte opcode */ - /* was placed on the databus */ - LOG(("Z80 IM0 $%04x\n", irq_vector)); - - /* check for nop */ - if (irq_vector != 0x00) - { - switch (irq_vector & 0xff0000) - { - case 0xcd0000: /* call */ - push(m_pc); - PCD = irq_vector & 0xffff; - /* CALL $xxxx cycles */ - m_icount -= m_cc_op[0xcd]; - break; - case 0xc30000: /* jump */ - PCD = irq_vector & 0xffff; - /* JP $xxxx cycles */ - m_icount -= m_cc_op[0xc3]; - break; - default: /* rst (or other opcodes?) */ - push(m_pc); - PCD = irq_vector & 0x0038; - /* RST $xx cycles */ - m_icount -= m_cc_op[0xff]; - break; - } - } - - /* 'interrupt latency' cycles */ - m_icount -= m_cc_ex[0xff]; - } - WZ=PCD; - -#if HAS_LDAIR_QUIRK - /* reset parity flag after LD A,I or LD A,R */ - if (m_after_ldair) F &= ~PF; -#endif + LOGMASKED(LOG_UNDOC, "ill. opcode $ed $%02x\n", + m_opcodes.read_byte((PC - 1) & 0xffff)); } -void nsc800_device::take_interrupt_nsc800() +u8 z80_device::flags_szyxc(u16 value) { - /* Check if processor was halted */ - leave_halt(); - - /* Clear both interrupt flip flops */ - m_iff1 = m_iff2 = 0; - - if (m_nsc800_irq_state[NSC800_RSTA]) - { - push(m_pc); - PCD = 0x003c; - } - else if (m_nsc800_irq_state[NSC800_RSTB]) - { - push(m_pc); - PCD = 0x0034; - } - else if (m_nsc800_irq_state[NSC800_RSTC]) - { - push(m_pc); - PCD = 0x002c; - } - - /* 'interrupt latency' cycles */ - m_icount -= m_cc_op[0xff] + cc_ex[0xff]; - - WZ=PCD; - -#if HAS_LDAIR_QUIRK - /* reset parity flag after LD A,I or LD A,R */ - if (m_after_ldair) F &= ~PF; -#endif + u8 f = value & (SF | YF | XF); // SF + undocumented flag bits 5+3 + f |= u8(value) ? 0 : ZF; + f |= (value >> 8) & CF; + return f; } + /**************************************************************************** * Processor initialization ****************************************************************************/ +void z80_device::device_validity_check(validity_checker &valid) const +{ + cpu_device::device_validity_check(valid); + + if (4 > m_m1_cycles) + osd_printf_error("M1 cycles %u is less than minimum 4\n", m_m1_cycles); + if (3 > m_memrq_cycles) + osd_printf_error("MEMRQ cycles %u is less than minimum 3\n", m_memrq_cycles); + if (4 > m_iorq_cycles) + osd_printf_error("IORQ cycles %u is less than minimum 4\n", m_iorq_cycles); +} + void z80_device::device_start() { - if( !tables_initialised ) + if (!tables_initialised) { - uint8_t *padd = &SZHVC_add[ 0*256]; - uint8_t *padc = &SZHVC_add[256*256]; - uint8_t *psub = &SZHVC_sub[ 0*256]; - uint8_t *psbc = &SZHVC_sub[256*256]; - for (int oldval = 0; oldval < 256; oldval++) - { - for (int newval = 0; newval < 256; newval++) - { - /* add or adc w/o carry set */ - int val = newval - oldval; - *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; - *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ - if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF; - if( newval < oldval ) *padd |= CF; - if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF; - padd++; - - /* adc with carry set */ - val = newval - oldval - 1; - *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; - *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ - if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF; - if( newval <= oldval ) *padc |= CF; - if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF; - padc++; - - /* cp, sub or sbc w/o carry set */ - val = oldval - newval; - *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); - *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ - if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF; - if( newval > oldval ) *psub |= CF; - if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF; - psub++; - - /* sbc with carry set */ - val = oldval - newval - 1; - *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); - *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ - if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF; - if( newval >= oldval ) *psbc |= CF; - if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF; - psbc++; - } - } - for (int i = 0; i < 256; i++) { int p = 0; - if( i&0x01 ) ++p; - if( i&0x02 ) ++p; - if( i&0x04 ) ++p; - if( i&0x08 ) ++p; - if( i&0x10 ) ++p; - if( i&0x20 ) ++p; - if( i&0x40 ) ++p; - if( i&0x80 ) ++p; + for (int b = 0; b < 8; b++) + p += BIT(i, b); SZ[i] = i ? i & SF : ZF; - SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ + SZ[i] |= (i & (YF | XF)); // undocumented flag bits 5+3 SZ_BIT[i] = i ? i & SF : ZF | PF; - SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ + SZ_BIT[i] |= (i & (YF | XF)); // undocumented flag bits 5+3 SZP[i] = SZ[i] | ((p & 1) ? 0 : PF); SZHV_inc[i] = SZ[i]; - if( i == 0x80 ) SZHV_inc[i] |= VF; - if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF; + if (i == 0x80) SZHV_inc[i] |= VF; + if ((i & 0x0f) == 0x00) SZHV_inc[i] |= HF; SZHV_dec[i] = SZ[i] | NF; - if( i == 0x7f ) SZHV_dec[i] |= VF; - if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF; + if (i == 0x7f) SZHV_dec[i] |= VF; + if ((i & 0x0f) == 0x0f) SZHV_dec[i] |= HF; } tables_initialised = true; } - save_item(NAME(m_prvpc.w.l)); + save_item(NAME(PRVPC)); save_item(NAME(PC)); save_item(NAME(SP)); save_item(NAME(AF)); @@ -3356,70 +550,77 @@ void z80_device::device_start() save_item(NAME(IX)); save_item(NAME(IY)); save_item(NAME(WZ)); - save_item(NAME(m_af2.w.l)); - save_item(NAME(m_bc2.w.l)); - save_item(NAME(m_de2.w.l)); - save_item(NAME(m_hl2.w.l)); - save_item(NAME(m_r)); - save_item(NAME(m_r2)); + save_item(NAME(m_af2.w)); + save_item(NAME(m_bc2.w)); + save_item(NAME(m_de2.w)); + save_item(NAME(m_hl2.w)); + save_item(NAME(QT)); + save_item(NAME(Q)); + save_item(NAME(R)); + save_item(NAME(R2)); save_item(NAME(m_iff1)); save_item(NAME(m_iff2)); save_item(NAME(m_halt)); save_item(NAME(m_im)); save_item(NAME(m_i)); save_item(NAME(m_nmi_state)); - save_item(NAME(m_nmi_pending)); save_item(NAME(m_irq_state)); save_item(NAME(m_wait_state)); save_item(NAME(m_busrq_state)); - save_item(NAME(m_after_ei)); - save_item(NAME(m_after_ldair)); - - /* Reset registers to their initial values */ + save_item(NAME(m_busack_state)); + save_item(NAME(m_ea)); + save_item(NAME(m_service_attention)); + save_item(NAME(m_tmp_irq_vector)); + save_item(NAME(m_shared_data.w)); + save_item(NAME(m_shared_data2.w)); + save_item(NAME(m_rtemp)); + save_item(NAME(m_ref)); + + // Reset registers to their initial values PRVPC = 0; - PCD = 0; - SPD = 0; - AFD = 0; - BCD = 0; - DED = 0; - HLD = 0; - IXD = 0; - IYD = 0; + PC = 0; + SP = 0; + AF = 0; + BC = 0; + DE = 0; + HL = 0; + IX = 0; + IY = 0; WZ = 0; - m_af2.d = 0; - m_bc2.d = 0; - m_de2.d = 0; - m_hl2.d = 0; - m_r = 0; - m_r2 = 0; + m_af2.w = 0; + m_bc2.w = 0; + m_de2.w = 0; + m_hl2.w = 0; + QT = 0; + Q = 0; + R = 0; + R2 = 0; m_iff1 = 0; m_iff2 = 0; m_halt = 0; m_im = 0; m_i = 0; m_nmi_state = 0; - m_nmi_pending = 0; m_irq_state = 0; m_wait_state = 0; m_busrq_state = 0; - m_after_ei = 0; - m_after_ldair = 0; + m_busack_state = 0; m_ea = 0; + m_service_attention = 0; + m_rtemp = 0; - m_program = &space(AS_PROGRAM); - m_opcodes = has_space(AS_OPCODES) ? &space(AS_OPCODES) : m_program; - m_cache = m_program->cache<0, 0, ENDIANNESS_LITTLE>(); - m_opcodes_cache = m_opcodes->cache<0, 0, ENDIANNESS_LITTLE>(); - m_io = &space(AS_IO); + space(AS_PROGRAM).cache(m_args); + space(has_space(AS_OPCODES) ? AS_OPCODES : AS_PROGRAM).cache(m_opcodes); + space(AS_PROGRAM).specific(m_data); + space(AS_IO).specific(m_io); - IX = IY = 0xffff; /* IX and IY are FFFF after a reset! */ - F = ZF; /* Zero flag is set */ + IX = IY = 0xffff; // IX and IY are FFFF after a reset! + set_f(ZF); // Zero flag is set - /* set up the state table */ - state_add(STATE_GENPC, "PC", m_pc.w.l).callimport(); - state_add(STATE_GENPCBASE, "CURPC", m_prvpc.w.l).callimport().noshow(); + // set up the state table + state_add(STATE_GENPC, "PC", m_pc.w).callimport(); + state_add(STATE_GENPCBASE, "CURPC", m_prvpc.w).callimport().noshow(); state_add(Z80_SP, "SP", SP); - state_add(STATE_GENSP, "GENSP", SP).noshow(); state_add(STATE_GENFLAGS, "GENFLAGS", F).noshow().formatstr("%8s"); state_add(Z80_A, "A", A).noshow(); state_add(Z80_B, "B", B).noshow(); @@ -3434,10 +635,10 @@ void z80_device::device_start() state_add(Z80_HL, "HL", HL); state_add(Z80_IX, "IX", IX); state_add(Z80_IY, "IY", IY); - state_add(Z80_AF2, "AF2", m_af2.w.l); - state_add(Z80_BC2, "BC2", m_bc2.w.l); - state_add(Z80_DE2, "DE2", m_de2.w.l); - state_add(Z80_HL2, "HL2", m_hl2.w.l); + state_add(Z80_AF2, "AF2", m_af2.w); + state_add(Z80_BC2, "BC2", m_bc2.w); + state_add(Z80_DE2, "DE2", m_de2.w); + state_add(Z80_HL2, "HL2", m_hl2.w); state_add(Z80_WZ, "WZ", WZ); state_add(Z80_R, "R", m_rtemp).callimport().callexport(); state_add(Z80_I, "I", m_i); @@ -3448,24 +649,6 @@ void z80_device::device_start() // set our instruction counter set_icountptr(m_icount); - - /* setup cycle tables */ - m_cc_op = cc_op; - m_cc_cb = cc_cb; - m_cc_ed = cc_ed; - m_cc_xy = cc_xy; - m_cc_xycb = cc_xycb; - m_cc_ex = cc_ex; - - m_irqack_cb.resolve_safe(); - m_refresh_cb.resolve_safe(); - m_halt_cb.resolve_safe(); -} - -void nsc800_device::device_start() -{ - z80_device::device_start(); - save_item(NAME(m_nsc800_irq_state)); } /**************************************************************************** @@ -3475,23 +658,15 @@ void z80_device::device_reset() { leave_halt(); + m_ref = 0xffff00; PC = 0x0000; + WZ = PC; m_i = 0; m_r = 0; m_r2 = 0; - m_nmi_pending = false; - m_after_ei = false; - m_after_ldair = false; m_iff1 = 0; m_iff2 = 0; - - WZ=PCD; -} - -void nsc800_device::device_reset() -{ - z80_device::device_reset(); - memset(m_nsc800_irq_state, 0, sizeof(m_nsc800_irq_state)); + m_service_attention = 0; } /**************************************************************************** @@ -3499,58 +674,7 @@ void nsc800_device::device_reset() ****************************************************************************/ void z80_device::execute_run() { - do - { - if (m_wait_state) - { - // stalled - m_icount = 0; - return; - } - - // check for interrupts before each instruction - if (m_nmi_pending) - take_nmi(); - else if (m_irq_state != CLEAR_LINE && m_iff1 && !m_after_ei) - take_interrupt(); - - m_after_ei = false; - m_after_ldair = false; - - PRVPC = PCD; - debugger_instruction_hook(PCD); - m_r++; - EXEC(op,rop()); - } while (m_icount > 0); -} - -void nsc800_device::execute_run() -{ - do - { - if (m_wait_state) - { - // stalled - m_icount = 0; - return; - } - - // check for interrupts before each instruction - if (m_nmi_pending) - take_nmi(); - else if ((m_nsc800_irq_state[NSC800_RSTA] != CLEAR_LINE || m_nsc800_irq_state[NSC800_RSTB] != CLEAR_LINE || m_nsc800_irq_state[NSC800_RSTC] != CLEAR_LINE) && m_iff1 && !m_after_ei) - take_interrupt_nsc800(); - else if (m_irq_state != CLEAR_LINE && m_iff1 && !m_after_ei) - take_interrupt(); - - m_after_ei = false; - m_after_ldair = false; - - PRVPC = PCD; - debugger_instruction_hook(PCD); - m_r++; - EXEC(op,rop()); - } while (m_icount > 0); + #include "cpu/z80/z80.hxx" } void z80_device::execute_set_input(int inputnum, int state) @@ -3559,22 +683,32 @@ void z80_device::execute_set_input(int inputnum, int state) { case Z80_INPUT_LINE_BUSRQ: m_busrq_state = state; + if (state != CLEAR_LINE) + set_service_attention<SA_BUSRQ, 1>(); + else + set_service_attention<SA_BUSRQ, 0>(); break; case INPUT_LINE_NMI: - /* mark an NMI pending on the rising edge */ + // mark an NMI pending on the rising edge if (m_nmi_state == CLEAR_LINE && state != CLEAR_LINE) - m_nmi_pending = true; + { + set_service_attention<SA_NMI_PENDING, 1>(); + } m_nmi_state = state; break; case INPUT_LINE_IRQ0: - /* update the IRQ state via the daisy chain */ + // update the IRQ state via the daisy chain m_irq_state = state; if (daisy_chain_present()) - m_irq_state = (daisy_update_irq_state() == ASSERT_LINE ) ? ASSERT_LINE : m_irq_state; + m_irq_state = (daisy_update_irq_state() == ASSERT_LINE) ? ASSERT_LINE : m_irq_state; + if (state != CLEAR_LINE) + set_service_attention<SA_IRQ_ON, 1>(); + else + set_service_attention<SA_IRQ_ON, 0>(); - /* the main execute loop will take the interrupt */ + // the main execute loop will take the interrupt break; case Z80_INPUT_LINE_WAIT: @@ -3586,67 +720,44 @@ void z80_device::execute_set_input(int inputnum, int state) } } -void nsc800_device::execute_set_input(int inputnum, int state) -{ - switch (inputnum) - { - case NSC800_RSTA: - m_nsc800_irq_state[NSC800_RSTA] = state; - break; - - case NSC800_RSTB: - m_nsc800_irq_state[NSC800_RSTB] = state; - break; - - case NSC800_RSTC: - m_nsc800_irq_state[NSC800_RSTC] = state; - break; - - default: - z80_device::execute_set_input(inputnum, state); - break; - } -} - - - /************************************************************************** * STATE IMPORT/EXPORT **************************************************************************/ - -void z80_device::state_import( const device_state_entry &entry ) +void z80_device::state_import(const device_state_entry &entry) { switch (entry.index()) { - case STATE_GENPC: - m_prvpc = m_pc; - break; - - case STATE_GENPCBASE: - m_pc = m_prvpc; - break; + case STATE_GENPCBASE: + m_pc = m_prvpc; + [[fallthrough]]; + case STATE_GENPC: + m_prvpc = m_pc; + m_ref = 0xffff00; + set_service_attention<SA_AFTER_EI, 0>(); + if (HAS_LDAIR_QUIRK) + set_service_attention<SA_AFTER_LDAIR, 0>(); + break; - case Z80_R: - m_r = m_rtemp & 0x7f; - m_r2 = m_rtemp & 0x80; - break; + case Z80_R: + m_r = m_rtemp & 0x7f; + m_r2 = m_rtemp & 0x80; + break; - default: - fatalerror("CPU_IMPORT_STATE() called for unexpected value\n"); + default: + fatalerror("CPU_IMPORT_STATE() called for unexpected value\n"); } } - -void z80_device::state_export( const device_state_entry &entry ) +void z80_device::state_export(const device_state_entry &entry) { switch (entry.index()) { - case Z80_R: - m_rtemp = (m_r & 0x7f) | (m_r2 & 0x80); - break; + case Z80_R: + m_rtemp = (m_r & 0x7f) | (m_r2 & 0x80); + break; - default: - fatalerror("CPU_EXPORT_STATE() called for unexpected value\n"); + default: + fatalerror("CPU_EXPORT_STATE() called for unexpected value\n"); } } @@ -3668,38 +779,20 @@ void z80_device::state_string_export(const device_state_entry &entry, std::strin } } -//------------------------------------------------- -// disassemble - call the disassembly -// helper function -//------------------------------------------------- - -std::unique_ptr<util::disasm_interface> z80_device::create_disassembler() -{ - return std::make_unique<z80_disassembler>(); -} - - /************************************************************************** - * Generic set_info + * disassemble - call the disassembly helper function **************************************************************************/ - -void z80_device::z80_set_cycle_tables(const uint8_t *op, const uint8_t *cb, const uint8_t *ed, const uint8_t *xy, const uint8_t *xycb, const uint8_t *ex) +std::unique_ptr<util::disasm_interface> z80_device::create_disassembler() { - m_cc_op = (op != nullptr) ? op : cc_op; - m_cc_cb = (cb != nullptr) ? cb : cc_cb; - m_cc_ed = (ed != nullptr) ? ed : cc_ed; - m_cc_xy = (xy != nullptr) ? xy : cc_xy; - m_cc_xycb = (xycb != nullptr) ? xycb : cc_xycb; - m_cc_ex = (ex != nullptr) ? ex : cc_ex; + return std::make_unique<z80_disassembler>(); } - -z80_device::z80_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : - z80_device(mconfig, Z80, tag, owner, clock) +z80_device::z80_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : z80_device(mconfig, Z80, tag, owner, clock) { } -z80_device::z80_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) : +z80_device::z80_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) : cpu_device(mconfig, type, tag, owner, clock), z80_daisy_chain_interface(mconfig, *this), m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0), @@ -3707,30 +800,30 @@ z80_device::z80_device(const machine_config &mconfig, device_type type, const ch m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0), m_irqack_cb(*this), m_refresh_cb(*this), - m_halt_cb(*this) + m_nomreq_cb(*this), + m_halt_cb(*this), + m_busack_cb(*this), + m_m1_cycles(4), + m_memrq_cycles(3), + m_iorq_cycles(4) { } device_memory_interface::space_config_vector z80_device::memory_space_config() const { - if(has_configured_map(AS_OPCODES)) + if (has_configured_map(AS_OPCODES)) + { return space_config_vector { - std::make_pair(AS_PROGRAM, &m_program_config), - std::make_pair(AS_OPCODES, &m_opcodes_config), - std::make_pair(AS_IO, &m_io_config) - }; + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_OPCODES, &m_opcodes_config), + std::make_pair(AS_IO, &m_io_config) }; + } else + { return space_config_vector { - std::make_pair(AS_PROGRAM, &m_program_config), - std::make_pair(AS_IO, &m_io_config) - }; + std::make_pair(AS_PROGRAM, &m_program_config), + std::make_pair(AS_IO, &m_io_config) }; + } } DEFINE_DEVICE_TYPE(Z80, z80_device, "z80", "Zilog Z80") - -nsc800_device::nsc800_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : z80_device(mconfig, NSC800, tag, owner, clock) -{ -} - -DEFINE_DEVICE_TYPE(NSC800, nsc800_device, "nsc800", "National Semiconductor NSC800") diff --git a/src/devices/cpu/z80/z80.h b/src/devices/cpu/z80/z80.h index 55de3771f7a..3498f100dcd 100644 --- a/src/devices/cpu/z80/z80.h +++ b/src/devices/cpu/z80/z80.h @@ -9,12 +9,10 @@ enum { - NSC800_RSTA = INPUT_LINE_IRQ0 + 1, - NSC800_RSTB, - NSC800_RSTC, - Z80_INPUT_LINE_WAIT, - Z80_INPUT_LINE_BOGUSWAIT, /* WAIT pin implementation used to be nonexistent, please remove this when all drivers are updated with Z80_INPUT_LINE_WAIT */ - Z80_INPUT_LINE_BUSRQ + Z80_INPUT_LINE_WAIT = INPUT_LINE_IRQ0 + 1, + Z80_INPUT_LINE_BUSRQ, + + Z80_INPUT_LINE_MAX }; enum @@ -30,283 +28,177 @@ enum class z80_device : public cpu_device, public z80_daisy_chain_interface { public: - z80_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + z80_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + void z80_set_m1_cycles(u8 m1_cycles) { m_m1_cycles = m1_cycles; } + void z80_set_memrq_cycles(u8 memrq_cycles) { m_memrq_cycles = memrq_cycles; } + void z80_set_iorq_cycles(u8 iorq_cycles) { m_iorq_cycles = iorq_cycles; } - void z80_set_cycle_tables(const uint8_t *op, const uint8_t *cb, const uint8_t *ed, const uint8_t *xy, const uint8_t *xycb, const uint8_t *ex); template <typename... T> void set_memory_map(T &&... args) { set_addrmap(AS_PROGRAM, std::forward<T>(args)...); } template <typename... T> void set_m1_map(T &&... args) { set_addrmap(AS_OPCODES, std::forward<T>(args)...); } template <typename... T> void set_io_map(T &&... args) { set_addrmap(AS_IO, std::forward<T>(args)...); } auto irqack_cb() { return m_irqack_cb.bind(); } auto refresh_cb() { return m_refresh_cb.bind(); } + auto nomreq_cb() { return m_nomreq_cb.bind(); } auto halt_cb() { return m_halt_cb.bind(); } + auto busack_cb() { return m_busack_cb.bind(); } -protected: - z80_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); - - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; + // output pins state + int halt_r() { return m_halt; } + int busack_r() { return m_busack_state; } - // device_execute_interface overrides - virtual uint32_t execute_min_cycles() const override { return 2; } - virtual uint32_t execute_max_cycles() const override { return 16; } - virtual uint32_t execute_input_lines() const override { return 4; } - virtual uint32_t execute_default_irq_vector(int inputnum) const override { return 0xff; } - virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == INPUT_LINE_NMI; } +protected: + z80_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock); + + // device_t implementation + virtual void device_validity_check(validity_checker &valid) const override; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + + // device_execute_interface implementation + virtual bool cpu_is_interruptible() const override { return true; } + virtual u32 execute_min_cycles() const noexcept override { return 1; } + virtual u32 execute_max_cycles() const noexcept override { return 16; } + virtual u32 execute_default_irq_vector(int inputnum) const noexcept override { return 0xff; } + virtual bool execute_input_edge_triggered(int inputnum) const noexcept override { return inputnum == INPUT_LINE_NMI; } virtual void execute_run() override; virtual void execute_set_input(int inputnum, int state) override; - // device_memory_interface overrides + // device_memory_interface implementation virtual space_config_vector memory_space_config() const override; - // device_state_interface overrides + // device_state_interface implementation virtual void state_import(const device_state_entry &entry) override; virtual void state_export(const device_state_entry &entry) override; virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; - // device_disasm_interface overrides + // device_disasm_interface implementation virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; -#undef PROTOTYPES -#define PROTOTYPES(prefix) \ - void prefix##_00(); void prefix##_01(); void prefix##_02(); void prefix##_03(); \ - void prefix##_04(); void prefix##_05(); void prefix##_06(); void prefix##_07(); \ - void prefix##_08(); void prefix##_09(); void prefix##_0a(); void prefix##_0b(); \ - void prefix##_0c(); void prefix##_0d(); void prefix##_0e(); void prefix##_0f(); \ - void prefix##_10(); void prefix##_11(); void prefix##_12(); void prefix##_13(); \ - void prefix##_14(); void prefix##_15(); void prefix##_16(); void prefix##_17(); \ - void prefix##_18(); void prefix##_19(); void prefix##_1a(); void prefix##_1b(); \ - void prefix##_1c(); void prefix##_1d(); void prefix##_1e(); void prefix##_1f(); \ - void prefix##_20(); void prefix##_21(); void prefix##_22(); void prefix##_23(); \ - void prefix##_24(); void prefix##_25(); void prefix##_26(); void prefix##_27(); \ - void prefix##_28(); void prefix##_29(); void prefix##_2a(); void prefix##_2b(); \ - void prefix##_2c(); void prefix##_2d(); void prefix##_2e(); void prefix##_2f(); \ - void prefix##_30(); void prefix##_31(); void prefix##_32(); void prefix##_33(); \ - void prefix##_34(); void prefix##_35(); void prefix##_36(); void prefix##_37(); \ - void prefix##_38(); void prefix##_39(); void prefix##_3a(); void prefix##_3b(); \ - void prefix##_3c(); void prefix##_3d(); void prefix##_3e(); void prefix##_3f(); \ - void prefix##_40(); void prefix##_41(); void prefix##_42(); void prefix##_43(); \ - void prefix##_44(); void prefix##_45(); void prefix##_46(); void prefix##_47(); \ - void prefix##_48(); void prefix##_49(); void prefix##_4a(); void prefix##_4b(); \ - void prefix##_4c(); void prefix##_4d(); void prefix##_4e(); void prefix##_4f(); \ - void prefix##_50(); void prefix##_51(); void prefix##_52(); void prefix##_53(); \ - void prefix##_54(); void prefix##_55(); void prefix##_56(); void prefix##_57(); \ - void prefix##_58(); void prefix##_59(); void prefix##_5a(); void prefix##_5b(); \ - void prefix##_5c(); void prefix##_5d(); void prefix##_5e(); void prefix##_5f(); \ - void prefix##_60(); void prefix##_61(); void prefix##_62(); void prefix##_63(); \ - void prefix##_64(); void prefix##_65(); void prefix##_66(); void prefix##_67(); \ - void prefix##_68(); void prefix##_69(); void prefix##_6a(); void prefix##_6b(); \ - void prefix##_6c(); void prefix##_6d(); void prefix##_6e(); void prefix##_6f(); \ - void prefix##_70(); void prefix##_71(); void prefix##_72(); void prefix##_73(); \ - void prefix##_74(); void prefix##_75(); void prefix##_76(); void prefix##_77(); \ - void prefix##_78(); void prefix##_79(); void prefix##_7a(); void prefix##_7b(); \ - void prefix##_7c(); void prefix##_7d(); void prefix##_7e(); void prefix##_7f(); \ - void prefix##_80(); void prefix##_81(); void prefix##_82(); void prefix##_83(); \ - void prefix##_84(); void prefix##_85(); void prefix##_86(); void prefix##_87(); \ - void prefix##_88(); void prefix##_89(); void prefix##_8a(); void prefix##_8b(); \ - void prefix##_8c(); void prefix##_8d(); void prefix##_8e(); void prefix##_8f(); \ - void prefix##_90(); void prefix##_91(); void prefix##_92(); void prefix##_93(); \ - void prefix##_94(); void prefix##_95(); void prefix##_96(); void prefix##_97(); \ - void prefix##_98(); void prefix##_99(); void prefix##_9a(); void prefix##_9b(); \ - void prefix##_9c(); void prefix##_9d(); void prefix##_9e(); void prefix##_9f(); \ - void prefix##_a0(); void prefix##_a1(); void prefix##_a2(); void prefix##_a3(); \ - void prefix##_a4(); void prefix##_a5(); void prefix##_a6(); void prefix##_a7(); \ - void prefix##_a8(); void prefix##_a9(); void prefix##_aa(); void prefix##_ab(); \ - void prefix##_ac(); void prefix##_ad(); void prefix##_ae(); void prefix##_af(); \ - void prefix##_b0(); void prefix##_b1(); void prefix##_b2(); void prefix##_b3(); \ - void prefix##_b4(); void prefix##_b5(); void prefix##_b6(); void prefix##_b7(); \ - void prefix##_b8(); void prefix##_b9(); void prefix##_ba(); void prefix##_bb(); \ - void prefix##_bc(); void prefix##_bd(); void prefix##_be(); void prefix##_bf(); \ - void prefix##_c0(); void prefix##_c1(); void prefix##_c2(); void prefix##_c3(); \ - void prefix##_c4(); void prefix##_c5(); void prefix##_c6(); void prefix##_c7(); \ - void prefix##_c8(); void prefix##_c9(); void prefix##_ca(); void prefix##_cb(); \ - void prefix##_cc(); void prefix##_cd(); void prefix##_ce(); void prefix##_cf(); \ - void prefix##_d0(); void prefix##_d1(); void prefix##_d2(); void prefix##_d3(); \ - void prefix##_d4(); void prefix##_d5(); void prefix##_d6(); void prefix##_d7(); \ - void prefix##_d8(); void prefix##_d9(); void prefix##_da(); void prefix##_db(); \ - void prefix##_dc(); void prefix##_dd(); void prefix##_de(); void prefix##_df(); \ - void prefix##_e0(); void prefix##_e1(); void prefix##_e2(); void prefix##_e3(); \ - void prefix##_e4(); void prefix##_e5(); void prefix##_e6(); void prefix##_e7(); \ - void prefix##_e8(); void prefix##_e9(); void prefix##_ea(); void prefix##_eb(); \ - void prefix##_ec(); void prefix##_ed(); void prefix##_ee(); void prefix##_ef(); \ - void prefix##_f0(); void prefix##_f1(); void prefix##_f2(); void prefix##_f3(); \ - void prefix##_f4(); void prefix##_f5(); void prefix##_f6(); void prefix##_f7(); \ - void prefix##_f8(); void prefix##_f9(); void prefix##_fa(); void prefix##_fb(); \ - void prefix##_fc(); void prefix##_fd(); void prefix##_fe(); void prefix##_ff(); - void illegal_1(); void illegal_2(); - - PROTOTYPES(op) - PROTOTYPES(cb) - PROTOTYPES(dd) - PROTOTYPES(ed) - PROTOTYPES(fd) - PROTOTYPES(xycb) + u8 flags_szyxc(u16 value); + template <u8 Bit, bool State> void set_service_attention() { static_assert(Bit < 8, "out of range bit index"); if (State) m_service_attention |= (1 << Bit); else m_service_attention &= ~(1 << Bit); }; + template <u8 Bit> bool get_service_attention() { static_assert(Bit < 8, "out of range bit index"); return m_service_attention & (1 << Bit); }; void halt(); void leave_halt(); - uint8_t in(uint16_t port); - void out(uint16_t port, uint8_t value); - uint8_t rm(uint16_t addr); - void rm16(uint16_t addr, PAIR &r); - void wm(uint16_t addr, uint8_t value); - void wm16(uint16_t addr, PAIR &r); - uint8_t rop(); - uint8_t arg(); - uint16_t arg16(); - void eax(); - void eay(); - void pop(PAIR &r); - void push(PAIR &r); - void jp(void); - void jp_cond(bool cond); - void jr(); - void jr_cond(bool cond, uint8_t opcode); - void call(); - void call_cond(bool cond, uint8_t opcode); - void ret_cond(bool cond, uint8_t opcode); - void retn(); - void reti(); - void ld_r_a(); - void ld_a_r(); - void ld_i_a(); - void ld_a_i(); - void rst(uint16_t addr); - uint8_t inc(uint8_t value); - uint8_t dec(uint8_t value); + void inc(u8 &r); + void dec(u8 &r); void rlca(); void rrca(); void rla(); void rra(); - void rrd(); - void rld(); - void add_a(uint8_t value); - void adc_a(uint8_t value); - void sub(uint8_t value); - void sbc_a(uint8_t value); + void add_a(u8 value); + void adc_a(u8 value); + void sub_a(u8 value); + void sbc_a(u8 value); void neg(); void daa(); - void and_a(uint8_t value); - void or_a(uint8_t value); - void xor_a(uint8_t value); - void cp(uint8_t value); - void ex_af(); - void ex_de_hl(); + void and_a(u8 value); + void or_a(u8 value); + void xor_a(u8 value); + void cp(u8 value); void exx(); - void ex_sp(PAIR &r); - void add16(PAIR &dr, PAIR &sr); - void adc_hl(PAIR &r); - void sbc_hl(PAIR &r); - uint8_t rlc(uint8_t value); - uint8_t rrc(uint8_t value); - uint8_t rl(uint8_t value); - uint8_t rr(uint8_t value); - uint8_t sla(uint8_t value); - uint8_t sra(uint8_t value); - uint8_t sll(uint8_t value); - uint8_t srl(uint8_t value); - void bit(int bit, uint8_t value); - void bit_hl(int bit, uint8_t value); - void bit_xy(int bit, uint8_t value); - uint8_t res(int bit, uint8_t value); - uint8_t set(int bit, uint8_t value); - void ldi(); - void cpi(); - void ini(); - void outi(); - void ldd(); - void cpd(); - void ind(); - void outd(); - void ldir(); - void cpir(); - void inir(); - void otir(); - void lddr(); - void cpdr(); - void indr(); - void otdr(); + u8 rlc(u8 value); + u8 rrc(u8 value); + u8 rl(u8 value); + u8 rr(u8 value); + u8 sla(u8 value); + u8 sra(u8 value); + u8 sll(u8 value); + u8 srl(u8 value); + void bit(int bit, u8 value); + void bit_hl(int bit, u8 value); + void bit_xy(int bit, u8 value); + u8 res(int bit, u8 value); + u8 set(int bit, u8 value); void ei(); + void set_f(u8 f); + void block_io_interrupted_flags(); - void take_interrupt(); - void take_nmi(); + virtual u8 data_read(u16 addr); + virtual void data_write(u16 addr, u8 value); + virtual u8 stack_read(u16 addr) { return data_read(addr); } + virtual void stack_write(u16 addr, u8 value) { return data_write(addr, value); } + virtual u8 opcode_read(); + virtual u8 arg_read(); // address spaces const address_space_config m_program_config; const address_space_config m_opcodes_config; const address_space_config m_io_config; - address_space *m_program; - address_space *m_opcodes; - address_space *m_io; - memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_cache; - memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_opcodes_cache; + memory_access<16, 0, 0, ENDIANNESS_LITTLE>::cache m_args; + memory_access<16, 0, 0, ENDIANNESS_LITTLE>::cache m_opcodes; + memory_access<16, 0, 0, ENDIANNESS_LITTLE>::specific m_data; + memory_access<16, 0, 0, ENDIANNESS_LITTLE>::specific m_io; + devcb_write_line m_irqack_cb; devcb_write8 m_refresh_cb; + devcb_write8 m_nomreq_cb; devcb_write_line m_halt_cb; - - PAIR m_prvpc; - PAIR m_pc; - PAIR m_sp; - PAIR m_af; - PAIR m_bc; - PAIR m_de; - PAIR m_hl; - PAIR m_ix; - PAIR m_iy; - PAIR m_wz; - PAIR m_af2; - PAIR m_bc2; - PAIR m_de2; - PAIR m_hl2; - uint8_t m_r; - uint8_t m_r2; - uint8_t m_iff1; - uint8_t m_iff2; - uint8_t m_halt; - uint8_t m_im; - uint8_t m_i; - uint8_t m_nmi_state; /* nmi line state */ - uint8_t m_nmi_pending; /* nmi pending */ - uint8_t m_irq_state; /* irq line state */ - int m_wait_state; // wait line state - int m_busrq_state; // bus request line state - uint8_t m_after_ei; /* are we in the EI shadow? */ - uint8_t m_after_ldair; /* same, but for LD A,I or LD A,R */ - uint32_t m_ea; - - int m_icount; - uint8_t m_rtemp; - const uint8_t * m_cc_op; - const uint8_t * m_cc_cb; - const uint8_t * m_cc_ed; - const uint8_t * m_cc_xy; - const uint8_t * m_cc_xycb; - const uint8_t * m_cc_ex; + devcb_write_line m_busack_cb; + + static constexpr u8 SA_BUSRQ = 0; + static constexpr u8 SA_BUSACK = 1; + static constexpr u8 SA_NMI_PENDING = 2; + static constexpr u8 SA_IRQ_ON = 3; + static constexpr u8 SA_HALT = 4; + static constexpr u8 SA_AFTER_EI = 5; + static constexpr u8 SA_AFTER_LDAIR = 6; + static constexpr u8 SA_NSC800_IRQ_ON = 7; + u8 m_service_attention; // bitmap for required handling in service step + + PAIR16 m_prvpc; + PAIR16 m_pc; + PAIR16 m_sp; + PAIR16 m_af; + PAIR16 m_bc; + PAIR16 m_de; + PAIR16 m_hl; + PAIR16 m_ix; + PAIR16 m_iy; + PAIR16 m_wz; + PAIR16 m_af2; + PAIR16 m_bc2; + PAIR16 m_de2; + PAIR16 m_hl2; + u8 m_qtemp; + u8 m_q; + u8 m_r; + u8 m_r2; + u8 m_iff1; + u8 m_iff2; + u8 m_halt; + u8 m_im; + u8 m_i; + u8 m_nmi_state; // nmi pin state + u8 m_irq_state; // irq pin state + int m_wait_state; // wait pin state + int m_busrq_state; // bus request pin state + u8 m_busack_state; // bus acknowledge pin state + u16 m_ea; + + int m_icount; + int m_tmp_irq_vector; + PAIR16 m_shared_data; + PAIR16 m_shared_data2; + u8 m_rtemp; + + u32 m_ref; + u8 m_m1_cycles; + u8 m_memrq_cycles; + u8 m_iorq_cycles; + + static bool tables_initialised; + static u8 SZ[0x100]; // zero and sign flags + static u8 SZ_BIT[0x100]; // zero, sign and parity/overflow (=zero) flags for BIT opcode + static u8 SZP[0x100]; // zero, sign and parity flags + static u8 SZHV_inc[0x100]; // zero, sign, half carry and overflow flags INC r8 + static u8 SZHV_dec[0x100]; // zero, sign, half carry and overflow flags DEC r8 }; DECLARE_DEVICE_TYPE(Z80, z80_device) -class nsc800_device : public z80_device -{ -public: - nsc800_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - -protected: - // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; - - // device_execute_interface overrides - virtual uint32_t execute_input_lines() const override { return 7; } - virtual void execute_run() override; - virtual void execute_set_input(int inputnum, int state) override; - - void take_interrupt_nsc800(); - uint8_t m_nsc800_irq_state[4]; /* state of NSC800 restart interrupts A, B, C */ -}; - -DECLARE_DEVICE_TYPE(NSC800, nsc800_device) - #endif // MAME_CPU_Z80_Z80_H diff --git a/src/devices/cpu/z80/z80.inc b/src/devices/cpu/z80/z80.inc new file mode 100644 index 00000000000..1c7dd7843a0 --- /dev/null +++ b/src/devices/cpu/z80/z80.inc @@ -0,0 +1,67 @@ +/* On an NMOS Z80, if LD A,I or LD A,R is interrupted, P/V flag gets reset, + even if IFF2 was set before this instruction. This issue was fixed on + the CMOS Z80, so until knowing (most) Z80 types on hardware, it's disabled */ +#define HAS_LDAIR_QUIRK 0 + + +/**************************************************************************** + * The Z80 registers. halt is set to 1 when the CPU is halted, the refresh + * register is calculated as follows: refresh = (r & 127) | (r2 & 128) + ****************************************************************************/ +#define CF 0x01 +#define NF 0x02 +#define PF 0x04 +#define VF PF +#define XF 0x08 +#define HF 0x10 +#define YF 0x20 +#define ZF 0x40 +#define SF 0x80 + +#define INT_IRQ 0x01 +#define NMI_IRQ 0x02 + +#define PRVPC m_prvpc.w // previous program counter +#define PC m_pc.w + +#define SP m_sp.w + +#define AF m_af.w +#define A m_af.b.h +#define F m_af.b.l +#define Q m_q +#define QT m_qtemp +#define I m_i +#define R m_r +#define R2 m_r2 + +#define BC m_bc.w +#define B m_bc.b.h +#define C m_bc.b.l + +#define DE m_de.w +#define D m_de.b.h +#define E m_de.b.l + +#define HL m_hl.w +#define H m_hl.b.h +#define L m_hl.b.l + +#define IX m_ix.w +#define HX m_ix.b.h +#define LX m_ix.b.l + +#define IY m_iy.w +#define HY m_iy.b.h +#define LY m_iy.b.l + +#define WZ m_wz.w +#define WZ_H m_wz.b.h +#define WZ_L m_wz.b.l + + +#define TDAT m_shared_data.w // 16bit input(if use as second parameter) or output in steps. +#define TDAT2 m_shared_data2.w +#define TDAT_H m_shared_data.b.h +#define TDAT_L m_shared_data.b.l +#define TDAT8 m_shared_data.b.l // Typically represents values from D0..8 pins. 8bit input or output in steps. diff --git a/src/devices/cpu/z80/z80.lst b/src/devices/cpu/z80/z80.lst new file mode 100644 index 00000000000..b1aa31aa12d --- /dev/null +++ b/src/devices/cpu/z80/z80.lst @@ -0,0 +1,8474 @@ +# license:BSD-3-Clause +# copyright-holders:Juergen Buchmueller, Andrei I. Holub +########################################################## +# macros +########################################################## +macro nomreq_addr %addr + if (nomemrq_en) + m_nomreq_cb(%addr, 0x00, 0xff); + + 1 + +macro nomreq_ir %cycles + %cycles * call nomreq_addr (m_i << 8) | (m_r2 & 0x80) | (m_r & 0x7f) + +macro in %port + m_iorq_cycles !! TDAT8 = m_io.read_interruptible(%port); + +macro out %port + m_iorq_cycles !! m_io.write_interruptible(%port, TDAT8); + +macro rm %addr + m_memrq_cycles !! TDAT8 = data_read(%addr); + +macro rm_reg %addr + call rm %addr + call nomreq_addr %addr + +macro rm16 %addr + call rm %addr + TDAT_H = TDAT_L; + call rm %addr+1 + using std::swap; std::swap(TDAT_H, TDAT_L); + +macro wm %addr + m_memrq_cycles !! data_write(%addr, TDAT8); + +macro wm16 %addr + call wm %addr + TDAT8 = TDAT_H; + call wm %addr+1 + +macro wm16_sp %d16 + SP--; + m_memrq_cycles !! stack_write(SP, (%d16) >> 8); + SP--; + m_memrq_cycles !! stack_write(SP, %d16); + +macro rop + m_m1_cycles-2 !! TDAT8 = opcode_read(); + if (refresh_en) + m_refresh_cb((I << 8) | (R2 & 0x80) | (R & 0x7f), 0x00, 0xff); + + 2 + PC++; R++; Q = QT; QT = YF | XF; + +macro r800:rop + m_m1_cycles !! TDAT8 = opcode_read(); + PC++; R++; Q = QT; QT = YF | XF; + +macro arg + m_memrq_cycles !! TDAT8 = arg_read(); + PC++; + +macro arg16 + call arg + TDAT_H = TDAT_L; + call arg + using std::swap; swap(TDAT_H, TDAT_L); + +macro eax + call arg + m_ea = (u16)(IX + (s8)TDAT8); WZ = m_ea; + +macro eay + call arg + m_ea = (u16)(IY + (s8)TDAT8); WZ = m_ea; + +macro pop + m_memrq_cycles !! TDAT_L = stack_read(SP); + SP++; + m_memrq_cycles !! TDAT_H = stack_read(SP); + SP++; + +macro push %d16 + call nomreq_ir 1 + call wm16_sp %d16 + +macro jp + call arg16 + PC = TDAT; WZ = PC; + +macro t6a84:jp + call arg16 + PC = TDAT; WZ = PC; + paged_jump(); + +macro jp_cond + if (TDAT8) { + call arg16 + PC = TDAT; WZ = PC; + } else { + // implicit do PC += 2 + call arg16 + WZ = TDAT; + } + +macro t6a84:jp_cond + if (TDAT8) { + call arg16 + PC = TDAT; WZ = PC; + paged_jump(); + } else { + // implicit do PC += 2 + call arg16 + WZ = TDAT; + } + +macro jr + call arg + 5 * call nomreq_addr PC-1 + PC += (s8)TDAT8; WZ = PC; + +macro t6a84:jr + call arg + 5 * call nomreq_addr PC-1 + PC += (s8)TDAT8; WZ = PC; + paged_jump(); + +macro r800:jr + call arg + + 1 + PC += (s8)TDAT8; WZ = PC; + +macro jr_cond + if (TDAT8) { + call jr + } else { + call arg + } + +macro arg16_call + call arg16 + m_ea = TDAT; + call nomreq_addr PC-1 + WZ = m_ea; + call wm16_sp PC + PC = m_ea; + +macro r800:arg16_call + call arg16 + m_ea = TDAT; + call nomreq_addr PC-1 + WZ = m_ea; + call wm16_sp PC + PC = m_ea; + +macro call_cond + if (TDAT8) { + call arg16_call + } else { + call arg16 + WZ = TDAT; + } + +macro ret_cond + call nomreq_ir 1 + if (TDAT8) { + call pop + PC = TDAT; WZ = PC; + } + +macro retn + call pop + PC = TDAT; LOGMASKED(LOG_INT, "RETN m_iff1:%d m_iff2:%d\n", m_iff1, m_iff2); WZ = PC; m_iff1 = m_iff2; + +macro z80n:retn + m_out_retn_seen_cb(0); + call pop + if (m_stackless) { + m_pc.b.l = m_in_nextreg_cb(0xc2); + m_pc.b.h = m_in_nextreg_cb(0xc3); + } else { + PC = TDAT; + } + LOGMASKED(LOG_INT, "RETN m_iff1:%d m_iff2:%d\n", m_iff1, m_iff2); WZ = PC; m_iff1 = m_iff2; + +macro reti + call pop + PC = TDAT; WZ = PC; m_iff1 = m_iff2; + daisy_call_reti_device(); + +macro t6a84:reti + call pop + PC = TDAT; WZ = PC; m_iff1 = m_iff2; + paged_reti(); + daisy_call_reti_device(); + +macro ld_r_a + call nomreq_ir 1 + m_r = A; m_r2 = A & 0x80; // keep bit 7 of r + +macro r800:ld_r_a + m_r = A; m_r2 = A & 0x80; // keep bit 7 of r + +macro ld_a_r + call nomreq_ir 1 + A = (m_r & 0x7f) | m_r2; set_f((F & CF) | SZ[A] | (m_iff2 << 2)); + if (HAS_LDAIR_QUIRK) + set_service_attention<SA_AFTER_LDAIR, 1>(); + +macro r800:ld_a_r + A = (m_r & 0x7f) | m_r2; set_f((F & CF) | SZ[A] | (m_iff2 << 2)); + if (HAS_LDAIR_QUIRK) + set_service_attention<SA_AFTER_LDAIR, 1>(); + +macro ld_i_a + call nomreq_ir 1 + m_i = A; + +macro r800:ld_i_a + m_i = A; + +macro ld_a_i + call nomreq_ir 1 + A = m_i; set_f((F & CF) | SZ[A] | (m_iff2 << 2)); + if (HAS_LDAIR_QUIRK) + set_service_attention<SA_AFTER_LDAIR, 1>(); + +macro r800:ld_a_i + A = m_i; set_f((F & CF) | SZ[A] | (m_iff2 << 2)); + if (HAS_LDAIR_QUIRK) + set_service_attention<SA_AFTER_LDAIR, 1>(); + +macro rst addr + call push PC + PC = addr; WZ = PC; + +macro rrd + call rm HL + WZ = HL+1; + 4 * call nomreq_addr HL + TDAT_H = TDAT8; TDAT8 = (TDAT8 >> 4) | (A << 4); + call wm HL + A = (A & 0xf0) | (TDAT_H & 0x0f); set_f((F & CF) | SZP[A]); + +macro rld + call rm HL + WZ = HL+1; + 4 * call nomreq_addr HL + TDAT_H = TDAT8; TDAT8 = (TDAT8 << 4) | (A & 0x0f); + call wm HL + A = (A & 0xf0) | (TDAT_H >> 4); set_f((F & CF) | SZP[A]); + +macro ex_sp %d16 + call pop + call nomreq_addr SP-1 + call wm16_sp %d16 + %d16 = TDAT; + 2 * call nomreq_addr SP + WZ = TDAT; + +macro add16 + call nomreq_ir 7 + { u32 res = TDAT + TDAT2; WZ = TDAT + 1; set_f((F & (SF | ZF | VF)) | (((TDAT ^ res ^ TDAT2) >> 8) & HF) | ((res >> 16) & CF) | ((res >> 8) & (YF | XF))); TDAT = (u16)res; } + +macro r800:add16 + { u32 res = TDAT + TDAT2; WZ = TDAT + 1; set_f((F & (SF | ZF | VF)) | (((TDAT ^ res ^ TDAT2) >> 8) & HF) | ((res >> 16) & CF) | ((res >> 8) & (YF | XF))); TDAT = (u16)res; } + +macro adc_hl + call nomreq_ir 7 + { u32 res = HL + TDAT + (F & CF); WZ = HL + 1; set_f((((HL ^ res ^ TDAT) >> 8) & HF) | ((res >> 16) & CF) | ((res >> 8) & (SF | YF | XF)) | ((res & 0xffff) ? 0 : ZF) | (((TDAT ^ HL ^ 0x8000) & (TDAT ^ res) & 0x8000) >> 13)); HL = (u16)res; } + +macro r800:adc_hl + { u32 res = HL + TDAT + (F & CF); WZ = HL + 1; set_f((((HL ^ res ^ TDAT) >> 8) & HF) | ((res >> 16) & CF) | ((res >> 8) & (SF | YF | XF)) | ((res & 0xffff) ? 0 : ZF) | (((TDAT ^ HL ^ 0x8000) & (TDAT ^ res) & 0x8000) >> 13)); HL = (u16)res; } + +macro sbc_hl + call nomreq_ir 7 + { u32 res = HL - TDAT - (F & CF); WZ = HL + 1; set_f((((HL ^ res ^ TDAT) >> 8) & HF) | NF | ((res >> 16) & CF) | ((res >> 8) & (SF | YF | XF)) | ((res & 0xffff) ? 0 : ZF) | (((TDAT ^ HL) & (HL ^ res) &0x8000) >> 13)); HL = (u16)res; } + +macro r800:sbc_hl + { u32 res = HL - TDAT - (F & CF); WZ = HL + 1; set_f((((HL ^ res ^ TDAT) >> 8) & HF) | NF | ((res >> 16) & CF) | ((res >> 8) & (SF | YF | XF)) | ((res & 0xffff) ? 0 : ZF) | (((TDAT ^ HL) & (HL ^ res) &0x8000) >> 13)); HL = (u16)res; } + +macro ldi + call rm HL + call wm DE + 2 * call nomreq_addr DE + set_f(F & (SF | ZF | CF)); if ((A + TDAT8) & 0x02) F |= YF; if ((A + TDAT8) & 0x08) F |= XF; HL++; DE++; BC--; if(BC) F |= VF; + +macro r800:ldi + call rm HL + call wm DE + call nomreq_addr DE + set_f(F & (SF | ZF | CF)); if ((A + TDAT8) & 0x02) F |= YF; if ((A + TDAT8) & 0x08) F |= XF; HL++; DE++; BC--; if(BC) F |= VF; + +macro cpi + call rm HL + 5 * call nomreq_addr HL + { u8 res = A - TDAT8; WZ++; HL++; BC--; set_f((F & CF) | (SZ[res]&~(YF|XF)) | ((A^TDAT8^res)&HF) | NF); if (F & HF) res -= 1; if (res & 0x02) F |= YF; if (res & 0x08) F |= XF; if (BC) F |= VF; } + +macro r800:cpi + call rm HL + call nomreq_addr HL + { u8 res = A - TDAT8; WZ++; HL++; BC--; set_f((F & CF) | (SZ[res]&~(YF|XF)) | ((A^TDAT8^res)&HF) | NF); if (F & HF) res -= 1; if (res & 0x02) F |= YF; if (res & 0x08) F |= XF; if (BC) F |= VF; } + +macro ini + call nomreq_ir 1 + call in BC + WZ = BC + 1; B--; + call wm HL + { HL++; set_f(SZ[B]); unsigned t = (unsigned)((C + 1) & 0xff) + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro r800:ini + call in BC + WZ = BC + 1; B--; + call wm HL + { HL++; set_f(SZ[B]); unsigned t = (unsigned)((C + 1) & 0xff) + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro outi + call nomreq_ir 1 + call rm HL + B--; WZ = BC + 1; + call out BC + { HL++; set_f(SZ[B]); unsigned t = (unsigned)L + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro r800:outi + call rm HL + B--; WZ = BC + 1; + call out BC + { HL++; set_f(SZ[B]); unsigned t = (unsigned)L + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro ldd + call rm HL + call wm DE + 2 * call nomreq_addr DE + { set_f(F & (SF | ZF | CF)); if ((A + TDAT8) & 0x02) F |= YF; if ((A + TDAT8) & 0x08) F |= XF; HL--; DE--; BC--; if (BC) F |= VF; } + +macro r800:ldd + call rm HL + call wm DE + call nomreq_addr DE + { set_f(F & (SF | ZF | CF)); if ((A + TDAT8) & 0x02) F |= YF; if ((A + TDAT8) & 0x08) F |= XF; HL--; DE--; BC--; if (BC) F |= VF; } + +macro cpd + call rm HL + 5 * call nomreq_addr HL + { u8 res = A - TDAT8; WZ--; HL--; BC--; set_f((F & CF) | (SZ[res]&~(YF|XF)) | ((A^TDAT8^res)&HF) | NF); if (F & HF) res -= 1; if (res & 0x02) F |= YF; if (res & 0x08) F |= XF; if (BC) F |= VF; } + +macro r800:cpd + call rm HL + call nomreq_addr HL + { u8 res = A - TDAT8; WZ--; HL--; BC--; set_f((F & CF) | (SZ[res]&~(YF|XF)) | ((A^TDAT8^res)&HF) | NF); if (F & HF) res -= 1; if (res & 0x02) F |= YF; if (res & 0x08) F |= XF; if (BC) F |= VF; } + +macro ind + call nomreq_ir 1 + call in BC + WZ = BC - 1; B--; + call wm HL + { HL--; set_f(SZ[B]); unsigned t = ((unsigned)(C - 1) & 0xff) + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro r800:ind + call in BC + WZ = BC - 1; B--; + call wm HL + { HL--; set_f(SZ[B]); unsigned t = ((unsigned)(C - 1) & 0xff) + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro outd + call nomreq_ir 1 + call rm HL + B--; WZ = BC - 1; + call out BC + { HL--; set_f(SZ[B]); unsigned t = (unsigned)L + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro r800:outd + call rm HL + B--; WZ = BC - 1; + call out BC + { HL--; set_f(SZ[B]); unsigned t = (unsigned)L + (unsigned)TDAT8; if (TDAT8 & SF) F |= NF; if (t & 0x100) F |= HF | CF; F |= SZP[(u8)(t & 0x07) ^ B] & PF; } + +macro ldir + call ldi + if (BC != 0) { + 5 * call nomreq_addr DE + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro r800:ldir + call ldi + if (BC != 0) { + call nomreq_addr DE + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro cpir + call cpi + if (BC != 0 && !(F & ZF)) { + 5 * call nomreq_addr HL + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro r800:cpir + call cpi + call nomreq_addr HL + if (BC != 0 && !(F & ZF)) { + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro inir + call ini + if (B != 0) { + 5 * call nomreq_addr HL + PC -= 2; + block_io_interrupted_flags(); + } + +macro r800:inir + if (B == 1) + T(1); + call ini + if (B != 0) { + PC -= 2; + block_io_interrupted_flags(); + } + +macro otir + call outi + if (B != 0) { + 5 * call nomreq_addr BC + PC -= 2; + block_io_interrupted_flags(); + } + +macro r800:otir + if (B == 1) + T(1); + call outi + if (B != 0) { + 5 * call nomreq_addr BC + PC -= 2; + block_io_interrupted_flags(); + } + +macro lddr + call ldd + if (BC != 0) { + 5 * call nomreq_addr DE + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro r800:lddr + call ldd + if (BC != 0) { + call nomreq_addr DE + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro cpdr + call cpd + if (BC != 0 && !(F & ZF)) { + 5 * call nomreq_addr HL + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro r800:cpdr + call cpd + call nomreq_addr HL /* suspected wrong. must be inside if? */ + if (BC != 0 && !(F & ZF)) { + PC -= 2; WZ = PC + 1; F &= ~(YF | XF); F |= (PC >> 8) & (YF | XF); + } + +macro indr + call ind + if (B != 0) { + 5 * call nomreq_addr HL + PC -= 2; + block_io_interrupted_flags(); + } + +macro r800:indr + if (B == 1) + T(1); + call ind + if (B != 0) { + PC -= 2; + block_io_interrupted_flags(); + } + +macro otdr + call outd + if (B != 0) { + 5 * call nomreq_addr BC + PC -= 2; + block_io_interrupted_flags(); + } + +macro r800:otdr + if (B == 1) + T(1); + call outd + if (B != 0) { + PC -= 2; + block_io_interrupted_flags(); + } + +macro jump %po + m_ref = 0x%po00; + goto process; + +macro jump_prefixed %prefix + m_ref = (%prefix << 16) | (TDAT8 << 8); + goto process; + +macro take_nmi + // Check if processor was halted + leave_halt(); + if (HAS_LDAIR_QUIRK) + // reset parity flag after LD A,I or LD A,R + if (get_service_attention<SA_AFTER_LDAIR>()) F &= ~PF; + m_iff1 = 0; + m_r++; + + 5 + call wm16_sp PC + PC = 0x0066; + WZ = PC; + set_service_attention<SA_NMI_PENDING, 0>(); + +macro irqfetch + { + // fetch the IRQ vector + device_z80daisy_interface *intf = daisy_get_irq_device(); + m_tmp_irq_vector = (intf != nullptr) ? intf->z80daisy_irq_ack() : standard_irq_callback(0, m_pc.w); + LOGMASKED(LOG_INT, "single INT m_tmp_irq_vector $%02x\n", m_tmp_irq_vector); + } + +macro t6a84:irqfetch + { + // fetch the IRQ vector + paged_irqfetch(); + device_z80daisy_interface *intf = daisy_get_irq_device(); + m_tmp_irq_vector = (intf != nullptr) ? intf->z80daisy_irq_ack() : standard_irq_callback(0, m_pc.w); + LOGMASKED(LOG_INT, "single INT m_tmp_irq_vector $%02x\n", m_tmp_irq_vector); + } + +macro take_interrupt + // check if processor was halted + leave_halt(); + // clear both interrupt flip flops + m_iff1 = m_iff2 = 0; + // say hi + // Not precise in all cases. z80 must finish current instruction (NOP) to reach this state - in such case frame timings are shifter from cb event if calculated based on it. + m_irqack_cb(1); + m_r++; + call irqfetch + // 'interrupt latency' cycles + + 2 + // Interrupt mode 2. Call [i:databyte] + if (m_im == 2) { + // Zilog's datasheet claims that "the least-significant bit must be a zero." + // However, experiments have confirmed that IM 2 vectors do not have to be + // even, and all 8 bits will be used; even $FF is handled normally. + // CALL opcode timing + + 5 + call wm16_sp PC + m_tmp_irq_vector = (m_tmp_irq_vector & 0xff) | (m_i << 8); + call rm16 m_tmp_irq_vector + PC = TDAT; + LOGMASKED(LOG_INT, "IM2 [$%04x] = $%04x\n", m_tmp_irq_vector, PC); + } else if (m_im == 1) { + // Interrupt mode 1. RST 38h + LOGMASKED(LOG_INT, "'%s' IM1 $0038\n", tag()); + // RST $38 + + 5 + call wm16_sp PC + PC = 0x0038; + } else { + /* Interrupt mode 0. We check for CALL and JP instructions, + if neither of these were found we assume a 1 byte opcode + was placed on the databus */ + LOGMASKED(LOG_INT, "IM0 $%04x\n", m_tmp_irq_vector); + + // check for nop + if (m_tmp_irq_vector != 0x00) { + if ((m_tmp_irq_vector & 0xff0000) == 0xcd0000) { + // CALL $xxxx cycles + + 11 + call wm16_sp PC + PC = m_tmp_irq_vector & 0xffff; + } else if ((m_tmp_irq_vector & 0xff0000) == 0xc30000) { + // JP $xxxx cycles + + 10 + PC = m_tmp_irq_vector & 0xffff; + } else if ((m_tmp_irq_vector & 0xc7) == 0xc7) { + // RST $xx cycles + + 5 + call wm16_sp PC + PC = m_tmp_irq_vector & 0x0038; + } else if (m_tmp_irq_vector == 0xfb) { + // EI cycles + + 4 + ei(); + } else { + logerror("take_interrupt: unexpected opcode in im0 mode: 0x%02x\n", m_tmp_irq_vector); + } + } + } + WZ = PC; + if (HAS_LDAIR_QUIRK) + // reset parity flag after LD A,I or LD A,R + if (get_service_attention<SA_AFTER_LDAIR>()) F &= ~PF; + +macro check_interrupts + if (get_service_attention<SA_NMI_PENDING>()) { + call take_nmi + } else if (m_irq_state != CLEAR_LINE && m_iff1 && !get_service_attention<SA_AFTER_EI>()) { // SA_IRQ_ON + call take_interrupt + } + +macro z80n:check_interrupts + if (get_service_attention<SA_NMI_PENDING>()) { + if (m_stackless) { + // on take_nmi + m_out_nextreg_cb(0xc2, m_pc.b.l); + m_out_nextreg_cb(0xc3, m_pc.b.h); + } + call take_nmi + } else if (m_irq_state != CLEAR_LINE && m_iff1 && !get_service_attention<SA_AFTER_EI>()) { + call take_interrupt + } + +macro nsc800_take_interrupt + // Check if processor was halted + leave_halt(); + // Clear both interrupt flip flops + m_iff1 = m_iff2 = 0; + // 'interrupt latency' cycles + + 7 + if (m_nsc800_irq_state[0]) { + call wm16_sp PC + PC = 0x003c; + } else if (m_nsc800_irq_state[1]) { + call wm16_sp PC + PC = 0x0034; + } else if (m_nsc800_irq_state[2]) { + call wm16_sp PC + PC = 0x002c; + } else { + + 2 * m_memrq_cycles + ; + } + WZ = PC; + if (HAS_LDAIR_QUIRK) + // reset parity flag after LD A,I or LD A,R + if (get_service_attention<SA_AFTER_LDAIR>()) F &= ~PF; + +macro nsc800:check_interrupts + if (get_service_attention<SA_NMI_PENDING>()) { + call take_nmi + } else if (get_service_attention<SA_NSC800_IRQ_ON>() && m_iff1 && !get_service_attention<SA_AFTER_EI>()) { + call nsc800_take_interrupt + } else if (m_irq_state != CLEAR_LINE && m_iff1 && !get_service_attention<SA_AFTER_EI>()) { // SA_IRQ_ON + call take_interrupt + } + + +########################################################## +# ROP +########################################################## +ffff + if (m_icount <= 0) { + m_ref = 0xffff00; + return; + } + if (m_service_attention) { + if (m_busrq_state) { // SA_BUSRQ + if (!m_busack_state) { + m_busack_state = 1; + set_service_attention<SA_BUSACK, 1>(); + m_busack_cb(1); + } + if (m_icount > 0) + m_icount = 0; + m_ref = 0xffff00; + return; + } else if (m_busack_state) { // SA_BUSACK + m_busack_state = 0; + set_service_attention<SA_BUSACK, 0>(); + m_busack_cb(0); + } + call check_interrupts + set_service_attention<SA_AFTER_EI, 0>(); // SA_AFTER_EI + if (HAS_LDAIR_QUIRK) + set_service_attention<SA_AFTER_LDAIR, 0>(); // SA_AFTER_LDAIR + if (m_halt) { // SA_HALT + debugger_wait_hook(); + call rop + PC--; + continue; + } + } + PRVPC = PC; + debugger_instruction_hook(PC); + call rop + m_ref = (0x00 << 16) | (TDAT8 << 8); + goto process; + + +########################################################## +# opcodes with CB prefix +# rotate, shift and bit operations +########################################################## +cb00 # RLC B + B = rlc(B); + +cb01 # RLC C + C = rlc(C); + +cb02 # RLC D + D = rlc(D); + +cb03 # RLC E + E = rlc(E); + +cb04 # RLC H + H = rlc(H); + +cb05 # RLC L + L = rlc(L); + +cb06 # RLC (HL) + call rm_reg HL + TDAT8 = rlc(TDAT8); + call wm HL + +cb07 # RLC A + A = rlc(A); + +cb08 # RRC B + B = rrc(B); + +cb09 # RRC C + C = rrc(C); + +cb0a # RRC D + D = rrc(D); + +cb0b # RRC E + E = rrc(E); + +cb0c # RRC H + H = rrc(H); + +cb0d # RRC L + L = rrc(L); + +cb0e # RRC (HL) + call rm_reg HL + TDAT8 = rrc(TDAT8); + call wm HL + +cb0f # RRC A + A = rrc(A); + +cb10 # RL B + B = rl(B); + +cb11 # RL C + C = rl(C); + +cb12 # RL D + D = rl(D); + +cb13 # RL E + E = rl(E); + +cb14 # RL H + H = rl(H); + +cb15 # RL L + L = rl(L); + +cb16 # RL (HL) + call rm_reg HL + TDAT8 = rl(TDAT8); + call wm HL + +cb17 # RL A + A = rl(A); + +cb18 # RR B + B = rr(B); + +cb19 # RR C + C = rr(C); + +cb1a # RR D + D = rr(D); + +cb1b # RR E + E = rr(E); + +cb1c # RR H + H = rr(H); + +cb1d # RR L + L = rr(L); + +cb1e # RR (HL) + call rm_reg HL + TDAT8 = rr(TDAT8); + call wm HL + +cb1f # RR A + A = rr(A); + +cb20 # SLA B + B = sla(B); + +cb21 # SLA C + C = sla(C); + +cb22 # SLA D + D = sla(D); + +cb23 # SLA E + E = sla(E); + +cb24 # SLA H + H = sla(H); + +cb25 # SLA L + L = sla(L); + +cb26 # SLA (HL) + call rm_reg HL + TDAT8 = sla(TDAT8); + call wm HL + +cb27 # SLA A + A = sla(A); + +cb28 # SRA B + B = sra(B); + +cb29 # SRA C + C = sra(C); + +cb2a # SRA D + D = sra(D); + +cb2b # SRA E + E = sra(E); + +cb2c # SRA H + H = sra(H); + +cb2d # SRA L + L = sra(L); + +cb2e # SRA (HL) + call rm_reg HL + TDAT8 = sra(TDAT8); + call wm HL + +cb2f # SRA A + A = sra(A); + +cb30 # SLL B + B = sll(B); + +cb31 # SLL C + C = sll(C); + +cb32 # SLL D + D = sll(D); + +cb33 # SLL E + E = sll(E); + +cb34 # SLL H + H = sll(H); + +cb35 # SLL L + L = sll(L); + +cb36 # SLL (HL) + call rm_reg HL + TDAT8 = sll(TDAT8); + call wm HL + +cb37 # SLL A + A = sll(A); + +cb38 # SRL B + B = srl(B); + +cb39 # SRL C + C = srl(C); + +cb3a # SRL D + D = srl(D); + +cb3b # SRL E + E = srl(E); + +cb3c # SRL H + H = srl(H); + +cb3d # SRL L + L = srl(L); + +cb3e # SRL (HL) + call rm_reg HL + TDAT8 = srl(TDAT8); + call wm HL + +cb3f # SRL A + A = srl(A); + +cb40 # BIT 0,B + bit(0, B); + +cb41 # BIT 0,C + bit(0, C); + +cb42 # BIT 0,D + bit(0, D); + +cb43 # BIT 0,E + bit(0, E); + +cb44 # BIT 0,H + bit(0, H); + +cb45 # BIT 0,L + bit(0, L); + +cb46 # BIT 0,(HL) + call rm_reg HL + bit_hl(0, TDAT8); + +cb47 # BIT 0,A + bit(0, A); + +cb48 # BIT 1,B + bit(1, B); + +cb49 # BIT 1,C + bit(1, C); + +cb4a # BIT 1,D + bit(1, D); + +cb4b # BIT 1,E + bit(1, E); + +cb4c # BIT 1,H + bit(1, H); + +cb4d # BIT 1,L + bit(1, L); + +cb4e # BIT 1,(HL) + call rm_reg HL + bit_hl(1, TDAT8); + +cb4f # BIT 1,A + bit(1, A); + +cb50 # BIT 2,B + bit(2, B); + +cb51 # BIT 2,C + bit(2, C); + +cb52 # BIT 2,D + bit(2, D); + +cb53 # BIT 2,E + bit(2, E); + +cb54 # BIT 2,H + bit(2, H); + +cb55 # BIT 2,L + bit(2, L); + +cb56 # BIT 2,(HL) + call rm_reg HL + bit_hl(2, TDAT8); + +cb57 # BIT 2,A + bit(2, A); + +cb58 # BIT 3,B + bit(3, B); + +cb59 # BIT 3,C + bit(3, C); + +cb5a # BIT 3,D + bit(3, D); + +cb5b # BIT 3,E + bit(3, E); + +cb5c # BIT 3,H + bit(3, H); + +cb5d # BIT 3,L + bit(3, L); + +cb5e # BIT 3,(HL) + call rm_reg HL + bit_hl(3, TDAT8); + +cb5f # BIT 3,A + bit(3, A); + +cb60 # BIT 4,B + bit(4, B); + +cb61 # BIT 4,C + bit(4, C); + +cb62 # BIT 4,D + bit(4, D); + +cb63 # BIT 4,E + bit(4, E); + +cb64 # BIT 4,H + bit(4, H); + +cb65 # BIT 4,L + bit(4, L); + +cb66 # BIT 4,(HL) + call rm_reg HL + bit_hl(4, TDAT8); + +cb67 # BIT 4,A + bit(4, A); + +cb68 # BIT 5,B + bit(5, B); + +cb69 # BIT 5,C + bit(5, C); + +cb6a # BIT 5,D + bit(5, D); + +cb6b # BIT 5,E + bit(5, E); + +cb6c # BIT 5,H + bit(5, H); + +cb6d # BIT 5,L + bit(5, L); + +cb6e # BIT 5,(HL) + call rm_reg HL + bit_hl(5, TDAT8); + +cb6f # BIT 5,A + bit(5, A); + +cb70 # BIT 6,B + bit(6, B); + +cb71 # BIT 6,C + bit(6, C); + +cb72 # BIT 6,D + bit(6, D); + +cb73 # BIT 6,E + bit(6, E); + +cb74 # BIT 6,H + bit(6, H); + +cb75 # BIT 6,L + bit(6, L); + +cb76 # BIT 6,(HL) + call rm_reg HL + bit_hl(6, TDAT8); + +cb77 # BIT 6,A + bit(6, A); + +cb78 # BIT 7,B + bit(7, B); + +cb79 # BIT 7,C + bit(7, C); + +cb7a # BIT 7,D + bit(7, D); + +cb7b # BIT 7,E + bit(7, E); + +cb7c # BIT 7,H + bit(7, H); + +cb7d # BIT 7,L + bit(7, L); + +cb7e # BIT 7,(HL) + call rm_reg HL + bit_hl(7, TDAT8); + +cb7f # BIT 7,A + bit(7, A); + +cb80 # RES 0,B + B = res(0, B); + +cb81 # RES 0,C + C = res(0, C); + +cb82 # RES 0,D + D = res(0, D); + +cb83 # RES 0,E + E = res(0, E); + +cb84 # RES 0,H + H = res(0, H); + +cb85 # RES 0,L + L = res(0, L); + +cb86 # RES 0,(HL) + call rm_reg HL + TDAT8 = res(0, TDAT8); + call wm HL + +cb87 # RES 0,A + A = res(0, A); + +cb88 # RES 1,B + B = res(1, B); + +cb89 # RES 1,C + C = res(1, C); + +cb8a # RES 1,D + D = res(1, D); + +cb8b # RES 1,E + E = res(1, E); + +cb8c # RES 1,H + H = res(1, H); + +cb8d # RES 1,L + L = res(1, L); + +cb8e # RES 1,(HL) + call rm_reg HL + TDAT8 = res(1, TDAT8); + call wm HL + +cb8f # RES 1,A + A = res(1, A); + +cb90 # RES 2,B + B = res(2, B); + +cb91 # RES 2,C + C = res(2, C); + +cb92 # RES 2,D + D = res(2, D); + +cb93 # RES 2,E + E = res(2, E); + +cb94 # RES 2,H + H = res(2, H); + +cb95 # RES 2,L + L = res(2, L); + +cb96 # RES 2,(HL) + call rm_reg HL + TDAT8 = res(2, TDAT8); + call wm HL + +cb97 # RES 2,A + A = res(2, A); + +cb98 # RES 3,B + B = res(3, B); + +cb99 # RES 3,C + C = res(3, C); + +cb9a # RES 3,D + D = res(3, D); + +cb9b # RES 3,E + E = res(3, E); + +cb9c # RES 3,H + H = res(3, H); + +cb9d # RES 3,L + L = res(3, L); + +cb9e # RES 3,(HL) + call rm_reg HL + TDAT8 = res(3, TDAT8); + call wm HL + +cb9f # RES 3,A + A = res(3, A); + +cba0 # RES 4,B + B = res(4, B); + +cba1 # RES 4,C + C = res(4, C); + +cba2 # RES 4,D + D = res(4, D); + +cba3 # RES 4,E + E = res(4, E); + +cba4 # RES 4,H + H = res(4, H); + +cba5 # RES 4,L + L = res(4, L); + +cba6 # RES 4,(HL) + call rm_reg HL + TDAT8 = res(4, TDAT8); + call wm HL + +cba7 # RES 4,A + A = res(4, A); + +cba8 # RES 5,B + B = res(5, B); + +cba9 # RES 5,C + C = res(5, C); + +cbaa # RES 5,D + D = res(5, D); + +cbab # RES 5,E + E = res(5, E); + +cbac # RES 5,H + H = res(5, H); + +cbad # RES 5,L + L = res(5, L); + +cbae # RES 5,(HL) + call rm_reg HL + TDAT8 = res(5, TDAT8); + call wm HL + +cbaf # RES 5,A + A = res(5, A); + +cbb0 # RES 6,B + B = res(6, B); + +cbb1 # RES 6,C + C = res(6, C); + +cbb2 # RES 6,D + D = res(6, D); + +cbb3 # RES 6,E + E = res(6, E); + +cbb4 # RES 6,H + H = res(6, H); + +cbb5 # RES 6,L + L = res(6, L); + +cbb6 # RES 6,(HL) + call rm_reg HL + TDAT8 = res(6, TDAT8); + call wm HL + +cbb7 # RES 6,A + A = res(6, A); + +cbb8 # RES 7,B + B = res(7, B); + +cbb9 # RES 7,C + C = res(7, C); + +cbba # RES 7,D + D = res(7, D); + +cbbb # RES 7,E + E = res(7, E); + +cbbc # RES 7,H + H = res(7, H); + +cbbd # RES 7,L + L = res(7, L); + +cbbe # RES 7,(HL) + call rm_reg HL + TDAT8 = res(7, TDAT8); + call wm HL + +cbbf # RES 7,A + A = res(7, A); + +cbc0 # SET 0,B + B = set(0, B); + +cbc1 # SET 0,C + C = set(0, C); + +cbc2 # SET 0,D + D = set(0, D); + +cbc3 # SET 0,E + E = set(0, E); + +cbc4 # SET 0,H + H = set(0, H); + +cbc5 # SET 0,L + L = set(0, L); + +cbc6 # SET 0,(HL) + call rm_reg HL + TDAT8 = set(0, TDAT8); + call wm HL + +cbc7 # SET 0,A + A = set(0, A); + +cbc8 # SET 1,B + B = set(1, B); + +cbc9 # SET 1,C + C = set(1, C); + +cbca # SET 1,D + D = set(1, D); + +cbcb # SET 1,E + E = set(1, E); + +cbcc # SET 1,H + H = set(1, H); + +cbcd # SET 1,L + L = set(1, L); + +cbce # SET 1,(HL) + call rm_reg HL + TDAT8 = set(1, TDAT8); + call wm HL + +cbcf # SET 1,A + A = set(1, A); + +cbd0 # SET 2,B + B = set(2, B); + +cbd1 # SET 2,C + C = set(2, C); + +cbd2 # SET 2,D + D = set(2, D); + +cbd3 # SET 2,E + E = set(2, E); + +cbd4 # SET 2,H + H = set(2, H); + +cbd5 # SET 2,L + L = set(2, L); + +cbd6 # SET 2,(HL) + call rm_reg HL + TDAT8 = set(2, TDAT8); + call wm HL + +cbd7 # SET 2,A + A = set(2, A); + +cbd8 # SET 3,B + B = set(3, B); + +cbd9 # SET 3,C + C = set(3, C); + +cbda # SET 3,D + D = set(3, D); + +cbdb # SET 3,E + E = set(3, E); + +cbdc # SET 3,H + H = set(3, H); + +cbdd # SET 3,L + L = set(3, L); + +cbde # SET 3,(HL) + call rm_reg HL + TDAT8 = set(3, TDAT8); + call wm HL + +cbdf # SET 3,A + A = set(3, A); + +cbe0 # SET 4,B + B = set(4, B); + +cbe1 # SET 4,C + C = set(4, C); + +cbe2 # SET 4,D + D = set(4, D); + +cbe3 # SET 4,E + E = set(4, E); + +cbe4 # SET 4,H + H = set(4, H); + +cbe5 # SET 4,L + L = set(4, L); + +cbe6 # SET 4,(HL) + call rm_reg HL + TDAT8 = set(4, TDAT8); + call wm HL + +cbe7 # SET 4,A + A = set(4, A); + +cbe8 # SET 5,B + B = set(5, B); + +cbe9 # SET 5,C + C = set(5, C); + +cbea # SET 5,D + D = set(5, D); + +cbeb # SET 5,E + E = set(5, E); + +cbec # SET 5,H + H = set(5, H); + +cbed # SET 5,L + L = set(5, L); + +cbee # SET 5,(HL) + call rm_reg HL + TDAT8 = set(5, TDAT8); + call wm HL + +cbef # SET 5,A + A = set(5, A); + +cbf0 # SET 6,B + B = set(6, B); + +cbf1 # SET 6,C + C = set(6, C); + +cbf2 # SET 6,D + D = set(6, D); + +cbf3 # SET 6,E + E = set(6, E); + +cbf4 # SET 6,H + H = set(6, H); + +cbf5 # SET 6,L + L = set(6, L); + +cbf6 # SET 6,(HL) + call rm_reg HL + TDAT8 = set(6, TDAT8); + call wm HL + +cbf7 # SET 6,A + A = set(6, A); + +cbf8 # SET 7,B + B = set(7, B); + +cbf9 # SET 7,C + C = set(7, C); + +cbfa # SET 7,D + D = set(7, D); + +cbfb # SET 7,E + E = set(7, E); + +cbfc # SET 7,H + H = set(7, H); + +cbfd # SET 7,L + L = set(7, L); + +cbfe # SET 7,(HL) + call rm_reg HL + TDAT8 = set(7, TDAT8); + call wm HL + +cbff # SET 7,A + A = set(7, A); + + +########################################################## +# opcodes with DD/FD CB prefix +# rotate, shift and bit operations with (IX+o) +########################################################## +fe00 # RLC B = (XY+o) + call rm_reg m_ea + B = rlc(TDAT8); TDAT8 = B; + call wm m_ea + +fe01 # RLC C = (XY+o) + call rm_reg m_ea + C = rlc(TDAT8); TDAT8 = C; + call wm m_ea + +fe02 # RLC D = (XY+o) + call rm_reg m_ea + D = rlc(TDAT8); TDAT8 = D; + call wm m_ea + +fe03 # RLC E = (XY+o) + call rm_reg m_ea + E = rlc(TDAT8); TDAT8 = E; + call wm m_ea + +fe04 # RLC H = (XY+o) + call rm_reg m_ea + H = rlc(TDAT8); TDAT8 = H; + call wm m_ea + +fe05 # RLC L = (XY+o) + call rm_reg m_ea + L = rlc(TDAT8); TDAT8 = L; + call wm m_ea + +fe06 # RLC (XY+o) + call rm_reg m_ea + TDAT8 = rlc(TDAT8); + call wm m_ea + +fe07 # RLC A = (XY+o) + call rm_reg m_ea + A = rlc(TDAT8); TDAT8 = A; + call wm m_ea + +fe08 # RRC B = (XY+o) + call rm_reg m_ea + B = rrc(TDAT8); TDAT8 = B; + call wm m_ea + +fe09 # RRC C = (XY+o) + call rm_reg m_ea + C = rrc(TDAT8); TDAT8 = C; + call wm m_ea + +fe0a # RRC D = (XY+o) + call rm_reg m_ea + D = rrc(TDAT8); TDAT8 = D; + call wm m_ea + +fe0b # RRC E = (XY+o) + call rm_reg m_ea + E = rrc(TDAT8); TDAT8 = E; + call wm m_ea + +fe0c # RRC H = (XY+o) + call rm_reg m_ea + H = rrc(TDAT8); TDAT8 = H; + call wm m_ea + +fe0d # RRC L = (XY+o) + call rm_reg m_ea + L = rrc(TDAT8); TDAT8 = L; + call wm m_ea + +fe0e # RRC (XY+o) + call rm_reg m_ea + TDAT8 = rrc(TDAT8); + call wm m_ea + +fe0f # RRC A = (XY+o) + call rm_reg m_ea + A = rrc(TDAT8); TDAT8 = A; + call wm m_ea + +fe10 # RL B = (XY+o) + call rm_reg m_ea + B = rl(TDAT8); TDAT8 = B; + call wm m_ea + +fe11 # RL C = (XY+o) + call rm_reg m_ea + C = rl(TDAT8); TDAT8 = C; + call wm m_ea + +fe12 # RL D = (XY+o) + call rm_reg m_ea + D = rl(TDAT8); TDAT8 = D; + call wm m_ea + +fe13 # RL E = (XY+o) + call rm_reg m_ea + E = rl(TDAT8); TDAT8 = E; + call wm m_ea + +fe14 # RL H = (XY+o) + call rm_reg m_ea + H = rl(TDAT8); TDAT8 = H; + call wm m_ea + +fe15 # RL L = (XY+o) + call rm_reg m_ea + L = rl(TDAT8); TDAT8 = L; + call wm m_ea + +fe16 # RL (XY+o) + call rm_reg m_ea + TDAT8 = rl(TDAT8); + call wm m_ea + +fe17 # RL A = (XY+o) + call rm_reg m_ea + A = rl(TDAT8); TDAT8 = A; + call wm m_ea + +fe18 # RR B = (XY+o) + call rm_reg m_ea + B = rr(TDAT8); TDAT8 = B; + call wm m_ea + +fe19 # RR C = (XY+o) + call rm_reg m_ea + C = rr(TDAT8); TDAT8 = C; + call wm m_ea + +fe1a # RR D = (XY+o) + call rm_reg m_ea + D = rr(TDAT8); TDAT8 = D; + call wm m_ea + +fe1b # RR E = (XY+o) + call rm_reg m_ea + E = rr(TDAT8); TDAT8 = E; + call wm m_ea + +fe1c # RR H = (XY+o) + call rm_reg m_ea + H = rr(TDAT8); TDAT8 = H; + call wm m_ea + +fe1d # RR L = (XY+o) + call rm_reg m_ea + L = rr(TDAT8); TDAT8 = L; + call wm m_ea + +fe1e # RR (XY+o) + call rm_reg m_ea + TDAT8 = rr(TDAT8); + call wm m_ea + +fe1f # RR A = (XY+o) + call rm_reg m_ea + A = rr(TDAT8); TDAT8 = A; + call wm m_ea + +fe20 # SLA B = (XY+o) + call rm_reg m_ea + B = sla(TDAT8); TDAT8 = B; + call wm m_ea + +fe21 # SLA C = (XY+o) + call rm_reg m_ea + C = sla(TDAT8); TDAT8 = C; + call wm m_ea + +fe22 # SLA D = (XY+o) + call rm_reg m_ea + D = sla(TDAT8); TDAT8 = D; + call wm m_ea + +fe23 # SLA E = (XY+o) + call rm_reg m_ea + E = sla(TDAT8); TDAT8 = E; + call wm m_ea + +fe24 # SLA H = (XY+o) + call rm_reg m_ea + H = sla(TDAT8); TDAT8 = H; + call wm m_ea + +fe25 # SLA L = (XY+o) + call rm_reg m_ea + L = sla(TDAT8); TDAT8 = L; + call wm m_ea + +fe26 # SLA (XY+o) + call rm_reg m_ea + TDAT8 = sla(TDAT8); + call wm m_ea + +fe27 # SLA A = (XY+o) + call rm_reg m_ea + A = sla(TDAT8); TDAT8 = A; + call wm m_ea + +fe28 # SRA B = (XY+o) + call rm_reg m_ea + B = sra(TDAT8); TDAT8 = B; + call wm m_ea + +fe29 # SRA C = (XY+o) + call rm_reg m_ea + C = sra(TDAT8); TDAT8 = C; + call wm m_ea + +fe2a # SRA D = (XY+o) + call rm_reg m_ea + D = sra(TDAT8); TDAT8 = D; + call wm m_ea + +fe2b # SRA E = (XY+o) + call rm_reg m_ea + E = sra(TDAT8); TDAT8 = E; + call wm m_ea + +fe2c # SRA H = (XY+o) + call rm_reg m_ea + H = sra(TDAT8); TDAT8 = H; + call wm m_ea + +fe2d # SRA L = (XY+o) + call rm_reg m_ea + L = sra(TDAT8); TDAT8 = L; + call wm m_ea + +fe2e # SRA (XY+o) + call rm_reg m_ea + TDAT8 = sra(TDAT8); + call wm m_ea + +fe2f # SRA A = (XY+o) + call rm_reg m_ea + A = sra(TDAT8); TDAT8 = A; + call wm m_ea + +fe30 # SLL B = (XY+o) + call rm_reg m_ea + B = sll(TDAT8); TDAT8 = B; + call wm m_ea + +fe31 # SLL C = (XY+o) + call rm_reg m_ea + C = sll(TDAT8); TDAT8 = C; + call wm m_ea + +fe32 # SLL D = (XY+o) + call rm_reg m_ea + D = sll(TDAT8); TDAT8 = D; + call wm m_ea + +fe33 # SLL E = (XY+o) + call rm_reg m_ea + E = sll(TDAT8); TDAT8 = E; + call wm m_ea + +fe34 # SLL H = (XY+o) + call rm_reg m_ea + H = sll(TDAT8); TDAT8 = H; + call wm m_ea + +fe35 # SLL L = (XY+o) + call rm_reg m_ea + L = sll(TDAT8); TDAT8 = L; + call wm m_ea + +fe36 # SLL (XY+o) + call rm_reg m_ea + TDAT8 = sll(TDAT8); + call wm m_ea + +fe37 # SLL A = (XY+o) + call rm_reg m_ea + A = sll(TDAT8); TDAT8 = A; + call wm m_ea + +fe38 # SRL B = (XY+o) + call rm_reg m_ea + B = srl(TDAT8); TDAT8 = B; + call wm m_ea + +fe39 # SRL C = (XY+o) + call rm_reg m_ea + C = srl(TDAT8); TDAT8 = C; + call wm m_ea + +fe3a # SRL D = (XY+o) + call rm_reg m_ea + D = srl(TDAT8); TDAT8 = D; + call wm m_ea + +fe3b # SRL E = (XY+o) + call rm_reg m_ea + E = srl(TDAT8); TDAT8 = E; + call wm m_ea + +fe3c # SRL H = (XY+o) + call rm_reg m_ea + H = srl(TDAT8); TDAT8 = H; + call wm m_ea + +fe3d # SRL L = (XY+o) + call rm_reg m_ea + L = srl(TDAT8); TDAT8 = L; + call wm m_ea + +fe3e # SRL (XY+o) + call rm_reg m_ea + TDAT8 = srl(TDAT8); + call wm m_ea + +fe3f # SRL A = (XY+o) + call rm_reg m_ea + A = srl(TDAT8); TDAT8 = A; + call wm m_ea + +fe40 # BIT 0,(XY+o) + call jump fe46 + +fe41 # BIT 0,(XY+o) + call jump fe46 + +fe42 # BIT 0,(XY+o) + call jump fe46 + +fe43 # BIT 0,(XY+o) + call jump fe46 + +fe44 # BIT 0,(XY+o) + call jump fe46 + +fe45 # BIT 0,(XY+o) + call jump fe46 + +fe46 # BIT 0,(XY+o) + call rm_reg m_ea + bit_xy(0, TDAT8); + +fe47 # BIT 0,(XY+o) + call jump fe46 + +fe48 # BIT 1,(XY+o) + call jump fe4e + +fe49 # BIT 1,(XY+o) + call jump fe4e + +fe4a # BIT 1,(XY+o) + call jump fe4e + +fe4b # BIT 1,(XY+o) + call jump fe4e + +fe4c # BIT 1,(XY+o) + call jump fe4e + +fe4d # BIT 1,(XY+o) + call jump fe4e + +fe4e # BIT 1,(XY+o) + call rm_reg m_ea + bit_xy(1, TDAT8); + +fe4f # BIT 1,(XY+o) + call jump fe4e + +fe50 # BIT 2,(XY+o) + call jump fe56 + +fe51 # BIT 2,(XY+o) + call jump fe56 + +fe52 # BIT 2,(XY+o) + call jump fe56 + +fe53 # BIT 2,(XY+o) + call jump fe56 + +fe54 # BIT 2,(XY+o) + call jump fe56 + +fe55 # BIT 2,(XY+o) + call jump fe56 + +fe56 # BIT 2,(XY+o) + call rm_reg m_ea + bit_xy(2, TDAT8); + +fe57 # BIT 2,(XY+o) + call jump fe56 + +fe58 # BIT 3,(XY+o) + call jump fe5e + +fe59 # BIT 3,(XY+o) + call jump fe5e + +fe5a # BIT 3,(XY+o) + call jump fe5e + +fe5b # BIT 3,(XY+o) + call jump fe5e + +fe5c # BIT 3,(XY+o) + call jump fe5e + +fe5d # BIT 3,(XY+o) + call jump fe5e + +fe5e # BIT 3,(XY+o) + call rm_reg m_ea + bit_xy(3, TDAT8); + +fe5f # BIT 3,(XY+o) + call jump fe5e + +fe60 # BIT 4,(XY+o) + call jump fe66 + +fe61 # BIT 4,(XY+o) + call jump fe66 + +fe62 # BIT 4,(XY+o) + call jump fe66 + +fe63 # BIT 4,(XY+o) + call jump fe66 + +fe64 # BIT 4,(XY+o) + call jump fe66 + +fe65 # BIT 4,(XY+o) + call jump fe66 + +fe66 # BIT 4,(XY+o) + call rm_reg m_ea + bit_xy(4, TDAT8); + +fe67 # BIT 4,(XY+o) + call jump fe66 + +fe68 # BIT 5,(XY+o) + call jump fe6e + +fe69 # BIT 5,(XY+o) + call jump fe6e + +fe6a # BIT 5,(XY+o) + call jump fe6e + +fe6b # BIT 5,(XY+o) + call jump fe6e + +fe6c # BIT 5,(XY+o) + call jump fe6e + +fe6d # BIT 5,(XY+o) + call jump fe6e + +fe6e # BIT 5,(XY+o) + call rm_reg m_ea + bit_xy(5, TDAT8); + +fe6f # BIT 5,(XY+o) + call jump fe6e + +fe70 # BIT 6,(XY+o) + call jump fe76 + +fe71 # BIT 6,(XY+o) + call jump fe76 + +fe72 # BIT 6,(XY+o) + call jump fe76 + +fe73 # BIT 6,(XY+o) + call jump fe76 + +fe74 # BIT 6,(XY+o) + call jump fe76 + +fe75 # BIT 6,(XY+o) + call jump fe76 + +fe76 # BIT 6,(XY+o) + call rm_reg m_ea + bit_xy(6, TDAT8); + +fe77 # BIT 6,(XY+o) + call jump fe76 + +fe78 # BIT 7,(XY+o) + call jump fe7e + +fe79 # BIT 7,(XY+o) + call jump fe7e + +fe7a # BIT 7,(XY+o) + call jump fe7e + +fe7b # BIT 7,(XY+o) + call jump fe7e + +fe7c # BIT 7,(XY+o) + call jump fe7e + +fe7d # BIT 7,(XY+o) + call jump fe7e + +fe7e # BIT 7,(XY+o) + call rm_reg m_ea + bit_xy(7, TDAT8); + +fe7f # BIT 7,(XY+o) + call jump fe7e + +fe80 # RES 0,B = (XY+o) + call rm_reg m_ea + B = res(0, TDAT8); TDAT8 = B; + call wm m_ea + +fe81 # RES 0,C = (XY+o) + call rm_reg m_ea + C = res(0, TDAT8); TDAT8 = C; + call wm m_ea + +fe82 # RES 0,D = (XY+o) + call rm_reg m_ea + D = res(0, TDAT8); TDAT8 = D; + call wm m_ea + +fe83 # RES 0,E = (XY+o) + call rm_reg m_ea + E = res(0, TDAT8); TDAT8 = E; + call wm m_ea + +fe84 # RES 0,H = (XY+o) + call rm_reg m_ea + H = res(0, TDAT8); TDAT8 = H; + call wm m_ea + +fe85 # RES 0,L = (XY+o) + call rm_reg m_ea + L = res(0, TDAT8); TDAT8 = L; + call wm m_ea + +fe86 # RES 0,(XY+o) + call rm_reg m_ea + TDAT8 = res(0, TDAT8); + call wm m_ea + +fe87 # RES 0,A = (XY+o) + call rm_reg m_ea + A = res(0, TDAT8); TDAT8 = A; + call wm m_ea + +fe88 # RES 1,B = (XY+o) + call rm_reg m_ea + B = res(1, TDAT8); TDAT8 = B; + call wm m_ea + +fe89 # RES 1,C = (XY+o) + call rm_reg m_ea + C = res(1, TDAT8); TDAT8 = C; + call wm m_ea + +fe8a # RES 1,D = (XY+o) + call rm_reg m_ea + D = res(1, TDAT8); TDAT8 = D; + call wm m_ea + +fe8b # RES 1,E = (XY+o) + call rm_reg m_ea + E = res(1, TDAT8); TDAT8 = E; + call wm m_ea + +fe8c # RES 1,H = (XY+o) + call rm_reg m_ea + H = res(1, TDAT8); TDAT8 = H; + call wm m_ea + +fe8d # RES 1,L = (XY+o) + call rm_reg m_ea + L = res(1, TDAT8); TDAT8 = L; + call wm m_ea + +fe8e # RES 1,(XY+o) + call rm_reg m_ea + TDAT8 = res(1, TDAT8); + call wm m_ea + +fe8f # RES 1,A = (XY+o) + call rm_reg m_ea + A = res(1, TDAT8); TDAT8 = A; + call wm m_ea + +fe90 # RES 2,B = (XY+o) + call rm_reg m_ea + B = res(2, TDAT8); TDAT8 = B; + call wm m_ea + +fe91 # RES 2,C = (XY+o) + call rm_reg m_ea + C = res(2, TDAT8); TDAT8 = C; + call wm m_ea + +fe92 # RES 2,D = (XY+o) + call rm_reg m_ea + D = res(2, TDAT8); TDAT8 = D; + call wm m_ea + +fe93 # RES 2,E = (XY+o) + call rm_reg m_ea + E = res(2, TDAT8); TDAT8 = E; + call wm m_ea + +fe94 # RES 2,H = (XY+o) + call rm_reg m_ea + H = res(2, TDAT8); TDAT8 = H; + call wm m_ea + +fe95 # RES 2,L = (XY+o) + call rm_reg m_ea + L = res(2, TDAT8); TDAT8 = L; + call wm m_ea + +fe96 # RES 2,(XY+o) + call rm_reg m_ea + TDAT8 = res(2, TDAT8); + call wm m_ea + +fe97 # RES 2,A = (XY+o) + call rm_reg m_ea + A = res(2, TDAT8); TDAT8 = A; + call wm m_ea + +fe98 # RES 3,B = (XY+o) + call rm_reg m_ea + B = res(3, TDAT8); TDAT8 = B; + call wm m_ea + +fe99 # RES 3,C = (XY+o) + call rm_reg m_ea + C = res(3, TDAT8); TDAT8 = C; + call wm m_ea + +fe9a # RES 3,D = (XY+o) + call rm_reg m_ea + D = res(3, TDAT8); TDAT8 = D; + call wm m_ea + +fe9b # RES 3,E = (XY+o) + call rm_reg m_ea + E = res(3, TDAT8); TDAT8 = E; + call wm m_ea + +fe9c # RES 3,H = (XY+o) + call rm_reg m_ea + H = res(3, TDAT8); TDAT8 = H; + call wm m_ea + +fe9d # RES 3,L = (XY+o) + call rm_reg m_ea + L = res(3, TDAT8); TDAT8 = L; + call wm m_ea + +fe9e # RES 3,(XY+o) + call rm_reg m_ea + TDAT8 = res(3, TDAT8); + call wm m_ea + +fe9f # RES 3,A = (XY+o) + call rm_reg m_ea + A = res(3, TDAT8); TDAT8 = A; + call wm m_ea + +fea0 # RES 4,B = (XY+o) + call rm_reg m_ea + B = res(4, TDAT8); TDAT8 = B; + call wm m_ea + +fea1 # RES 4,C = (XY+o) + call rm_reg m_ea + C = res(4, TDAT8); TDAT8 = C; + call wm m_ea + +fea2 # RES 4,D = (XY+o) + call rm_reg m_ea + D = res(4, TDAT8); TDAT8 = D; + call wm m_ea + +fea3 # RES 4,E = (XY+o) + call rm_reg m_ea + E = res(4, TDAT8); TDAT8 = E; + call wm m_ea + +fea4 # RES 4,H = (XY+o) + call rm_reg m_ea + H = res(4, TDAT8); TDAT8 = H; + call wm m_ea + +fea5 # RES 4,L = (XY+o) + call rm_reg m_ea + L = res(4, TDAT8); TDAT8 = L; + call wm m_ea + +fea6 # RES 4,(XY+o) + call rm_reg m_ea + TDAT8 = res(4, TDAT8); + call wm m_ea + +fea7 # RES 4,A = (XY+o) + call rm_reg m_ea + A = res(4, TDAT8); TDAT8 = A; + call wm m_ea + +fea8 # RES 5,B = (XY+o) + call rm_reg m_ea + B = res(5, TDAT8); TDAT8 = B; + call wm m_ea + +fea9 # RES 5,C = (XY+o) + call rm_reg m_ea + C = res(5, TDAT8); TDAT8 = C; + call wm m_ea + +feaa # RES 5,D = (XY+o) + call rm_reg m_ea + D = res(5, TDAT8); TDAT8 = D; + call wm m_ea + +feab # RES 5,E = (XY+o) + call rm_reg m_ea + E = res(5, TDAT8); TDAT8 = E; + call wm m_ea + +feac # RES 5,H = (XY+o) + call rm_reg m_ea + H = res(5, TDAT8); TDAT8 = H; + call wm m_ea + +fead # RES 5,L = (XY+o) + call rm_reg m_ea + L = res(5, TDAT8); TDAT8 = L; + call wm m_ea + +feae # RES 5,(XY+o) + call rm_reg m_ea + TDAT8 = res(5, TDAT8); + call wm m_ea + +feaf # RES 5,A = (XY+o) + call rm_reg m_ea + A = res(5, TDAT8); TDAT8 = A; + call wm m_ea + +feb0 # RES 6,B = (XY+o) + call rm_reg m_ea + B = res(6, TDAT8); TDAT8 = B; + call wm m_ea + +feb1 # RES 6,C = (XY+o) + call rm_reg m_ea + C = res(6, TDAT8); TDAT8 = C; + call wm m_ea + +feb2 # RES 6,D = (XY+o) + call rm_reg m_ea + D = res(6, TDAT8); TDAT8 = D; + call wm m_ea + +feb3 # RES 6,E = (XY+o) + call rm_reg m_ea + E = res(6, TDAT8); TDAT8 = E; + call wm m_ea + +feb4 # RES 6,H = (XY+o) + call rm_reg m_ea + H = res(6, TDAT8); TDAT8 = H; + call wm m_ea + +feb5 # RES 6,L = (XY+o) + call rm_reg m_ea + L = res(6, TDAT8); TDAT8 = L; + call wm m_ea + +feb6 # RES 6,(XY+o) + call rm_reg m_ea + TDAT8 = res(6, TDAT8); + call wm m_ea + +feb7 # RES 6,A = (XY+o) + call rm_reg m_ea + A = res(6, TDAT8); TDAT8 = A; + call wm m_ea + +feb8 # RES 7,B = (XY+o) + call rm_reg m_ea + B = res(7, TDAT8); TDAT8 = B; + call wm m_ea + +feb9 # RES 7,C = (XY+o) + call rm_reg m_ea + C = res(7, TDAT8); TDAT8 = C; + call wm m_ea + +feba # RES 7,D = (XY+o) + call rm_reg m_ea + D = res(7, TDAT8); TDAT8 = D; + call wm m_ea + +febb # RES 7,E = (XY+o) + call rm_reg m_ea + E = res(7, TDAT8); TDAT8 = E; + call wm m_ea + +febc # RES 7,H = (XY+o) + call rm_reg m_ea + H = res(7, TDAT8); TDAT8 = H; + call wm m_ea + +febd # RES 7,L = (XY+o) + call rm_reg m_ea + L = res(7, TDAT8); TDAT8 = L; + call wm m_ea + +febe # RES 7,(XY+o) + call rm_reg m_ea + TDAT8 = res(7, TDAT8); + call wm m_ea + +febf # RES 7,A = (XY+o) + call rm_reg m_ea + A = res(7, TDAT8); TDAT8 = A; + call wm m_ea + +fec0 # SET 0,B = (XY+o) + call rm_reg m_ea + B = set(0, TDAT8); TDAT8 = B; + call wm m_ea + +fec1 # SET 0,C = (XY+o) + call rm_reg m_ea + C = set(0, TDAT8); TDAT8 = C; + call wm m_ea + +fec2 # SET 0,D = (XY+o) + call rm_reg m_ea + D = set(0, TDAT8); TDAT8 = D; + call wm m_ea + +fec3 # SET 0,E = (XY+o) + call rm_reg m_ea + E = set(0, TDAT8); TDAT8 = E; + call wm m_ea + +fec4 # SET 0,H = (XY+o) + call rm_reg m_ea + H = set(0, TDAT8); TDAT8 = H; + call wm m_ea + +fec5 # SET 0,L = (XY+o) + call rm_reg m_ea + L = set(0, TDAT8); TDAT8 = L; + call wm m_ea + +fec6 # SET 0,(XY+o) + call rm_reg m_ea + TDAT8 = set(0, TDAT8); + call wm m_ea + +fec7 # SET 0,A = (XY+o) + call rm_reg m_ea + A = set(0, TDAT8); TDAT8 = A; + call wm m_ea + +fec8 # SET 1,B = (XY+o) + call rm_reg m_ea + B = set(1, TDAT8); TDAT8 = B; + call wm m_ea + +fec9 # SET 1,C = (XY+o) + call rm_reg m_ea + C = set(1, TDAT8); TDAT8 = C; + call wm m_ea + +feca # SET 1,D = (XY+o) + call rm_reg m_ea + D = set(1, TDAT8); TDAT8 = D; + call wm m_ea + +fecb # SET 1,E = (XY+o) + call rm_reg m_ea + E = set(1, TDAT8); TDAT8 = E; + call wm m_ea + +fecc # SET 1,H = (XY+o) + call rm_reg m_ea + H = set(1, TDAT8); TDAT8 = H; + call wm m_ea + +fecd # SET 1,L = (XY+o) + call rm_reg m_ea + L = set(1, TDAT8); TDAT8 = L; + call wm m_ea + +fece # SET 1,(XY+o) + call rm_reg m_ea + TDAT8 = set(1, TDAT8); + call wm m_ea + +fecf # SET 1,A = (XY+o) + call rm_reg m_ea + A = set(1, TDAT8); TDAT8 = A; + call wm m_ea + +fed0 # SET 2,B = (XY+o) + call rm_reg m_ea + B = set(2, TDAT8); TDAT8 = B; + call wm m_ea + +fed1 # SET 2,C = (XY+o) + call rm_reg m_ea + C = set(2, TDAT8); TDAT8 = C; + call wm m_ea + +fed2 # SET 2,D = (XY+o) + call rm_reg m_ea + D = set(2, TDAT8); TDAT8 = D; + call wm m_ea + +fed3 # SET 2,E = (XY+o) + call rm_reg m_ea + E = set(2, TDAT8); TDAT8 = E; + call wm m_ea + +fed4 # SET 2,H = (XY+o) + call rm_reg m_ea + H = set(2, TDAT8); TDAT8 = H; + call wm m_ea + +fed5 # SET 2,L = (XY+o) + call rm_reg m_ea + L = set(2, TDAT8); TDAT8 = L; + call wm m_ea + +fed6 # SET 2,(XY+o) + call rm_reg m_ea + TDAT8 = set(2, TDAT8); + call wm m_ea + +fed7 # SET 2,A = (XY+o) + call rm_reg m_ea + A = set(2, TDAT8); TDAT8 = A; + call wm m_ea + +fed8 # SET 3,B = (XY+o) + call rm_reg m_ea + B = set(3, TDAT8); TDAT8 = B; + call wm m_ea + +fed9 # SET 3,C = (XY+o) + call rm_reg m_ea + C = set(3, TDAT8); TDAT8 = C; + call wm m_ea + +feda # SET 3,D = (XY+o) + call rm_reg m_ea + D = set(3, TDAT8); TDAT8 = D; + call wm m_ea + +fedb # SET 3,E = (XY+o) + call rm_reg m_ea + E = set(3, TDAT8); TDAT8 = E; + call wm m_ea + +fedc # SET 3,H = (XY+o) + call rm_reg m_ea + H = set(3, TDAT8); TDAT8 = H; + call wm m_ea + +fedd # SET 3,L = (XY+o) + call rm_reg m_ea + L = set(3, TDAT8); TDAT8 = L; + call wm m_ea + +fede # SET 3,(XY+o) + call rm_reg m_ea + TDAT8 = set(3, TDAT8); + call wm m_ea + +fedf # SET 3,A = (XY+o) + call rm_reg m_ea + A = set(3, TDAT8); TDAT8 = A; + call wm m_ea + +fee0 # SET 4,B = (XY+o) + call rm_reg m_ea + B = set(4, TDAT8); TDAT8 = B; + call wm m_ea + +fee1 # SET 4,C = (XY+o) + call rm_reg m_ea + C = set(4, TDAT8); TDAT8 = C; + call wm m_ea + +fee2 # SET 4,D = (XY+o) + call rm_reg m_ea + D = set(4, TDAT8); TDAT8 = D; + call wm m_ea + +fee3 # SET 4,E = (XY+o) + call rm_reg m_ea + E = set(4, TDAT8); TDAT8 = E; + call wm m_ea + +fee4 # SET 4,H = (XY+o) + call rm_reg m_ea + H = set(4, TDAT8); TDAT8 = H; + call wm m_ea + +fee5 # SET 4,L = (XY+o) + call rm_reg m_ea + L = set(4, TDAT8); TDAT8 = L; + call wm m_ea + +fee6 # SET 4,(XY+o) + call rm_reg m_ea + TDAT8 = set(4, TDAT8); + call wm m_ea + +fee7 # SET 4,A = (XY+o) + call rm_reg m_ea + A = set(4, TDAT8); TDAT8 = A; + call wm m_ea + +fee8 # SET 5,B = (XY+o) + call rm_reg m_ea + B = set(5, TDAT8); TDAT8 = B; + call wm m_ea + +fee9 # SET 5,C = (XY+o) + call rm_reg m_ea + C = set(5, TDAT8); TDAT8 = C; + call wm m_ea + +feea # SET 5,D = (XY+o) + call rm_reg m_ea + D = set(5, TDAT8); TDAT8 = D; + call wm m_ea + +feeb # SET 5,E = (XY+o) + call rm_reg m_ea + E = set(5, TDAT8); TDAT8 = E; + call wm m_ea + +feec # SET 5,H = (XY+o) + call rm_reg m_ea + H = set(5, TDAT8); TDAT8 = H; + call wm m_ea + +feed # SET 5,L = (XY+o) + call rm_reg m_ea + L = set(5, TDAT8); TDAT8 = L; + call wm m_ea + +feee # SET 5,(XY+o) + call rm_reg m_ea + TDAT8 = set(5, TDAT8); + call wm m_ea + +feef # SET 5,A = (XY+o) + call rm_reg m_ea + A = set(5, TDAT8); TDAT8 = A; + call wm m_ea + +fef0 # SET 6,B = (XY+o) + call rm_reg m_ea + B = set(6, TDAT8); TDAT8 = B; + call wm m_ea + +fef1 # SET 6,C = (XY+o) + call rm_reg m_ea + C = set(6, TDAT8); TDAT8 = C; + call wm m_ea + +fef2 # SET 6,D = (XY+o) + call rm_reg m_ea + D = set(6, TDAT8); TDAT8 = D; + call wm m_ea + +fef3 # SET 6,E = (XY+o) + call rm_reg m_ea + E = set(6, TDAT8); TDAT8 = E; + call wm m_ea + +fef4 # SET 6,H = (XY+o) + call rm_reg m_ea + H = set(6, TDAT8); TDAT8 = H; + call wm m_ea + +fef5 # SET 6,L = (XY+o) + call rm_reg m_ea + L = set(6, TDAT8); TDAT8 = L; + call wm m_ea + +fef6 # SET 6,(XY+o) + call rm_reg m_ea + TDAT8 = set(6, TDAT8); + call wm m_ea + +fef7 # SET 6,A = (XY+o) + call rm_reg m_ea + A = set(6, TDAT8); TDAT8 = A; + call wm m_ea + +fef8 # SET 7,B = (XY+o) + call rm_reg m_ea + B = set(7, TDAT8); TDAT8 = B; + call wm m_ea + +fef9 # SET 7,C = (XY+o) + call rm_reg m_ea + C = set(7, TDAT8); TDAT8 = C; + call wm m_ea + +fefa # SET 7,D = (XY+o) + call rm_reg m_ea + D = set(7, TDAT8); TDAT8 = D; + call wm m_ea + +fefb # SET 7,E = (XY+o) + call rm_reg m_ea + E = set(7, TDAT8); TDAT8 = E; + call wm m_ea + +fefc # SET 7,H = (XY+o) + call rm_reg m_ea + H = set(7, TDAT8); TDAT8 = H; + call wm m_ea + +fefd # SET 7,L = (XY+o) + call rm_reg m_ea + L = set(7, TDAT8); TDAT8 = L; + call wm m_ea + +fefe # SET 7,(XY+o) + call rm_reg m_ea + TDAT8 = set(7, TDAT8); + call wm m_ea + +feff # SET 7,A = (XY+o) + call rm_reg m_ea + A = set(7, TDAT8); TDAT8 = A; + call wm m_ea + + +########################################################## +# IX register related opcodes (DD prefix) +########################################################## +dd00 # DB DD + illegal_1(); + call jump 0000 + +dd01 # DB DD + illegal_1(); + call jump 0001 + +dd02 # DB DD + illegal_1(); + call jump 0002 + +dd03 # DB DD + illegal_1(); + call jump 0003 + +dd04 # DB DD + illegal_1(); + call jump 0004 + +dd05 # DB DD + illegal_1(); + call jump 0005 + +dd06 # DB DD + illegal_1(); + call jump 0006 + +dd07 # DB DD + illegal_1(); + call jump 0007 + +dd08 # DB DD + illegal_1(); + call jump 0008 + +dd09 # ADD IX,BC + TDAT = IX; TDAT2 = BC; + call add16 + IX = TDAT; + +dd0a # DB DD + illegal_1(); + call jump 000a + +dd0b # DB DD + illegal_1(); + call jump 000b + +dd0c # DB DD + illegal_1(); + call jump 000c + +dd0d # DB DD + illegal_1(); + call jump 000d + +dd0e # DB DD + illegal_1(); + call jump 000e + +dd0f # DB DD + illegal_1(); + call jump 000f + +dd10 # DB DD + illegal_1(); + call jump 0010 + +dd11 # DB DD + illegal_1(); + call jump 0011 + +dd12 # DB DD + illegal_1(); + call jump 0012 + +dd13 # DB DD + illegal_1(); + call jump 0013 + +dd14 # DB DD + illegal_1(); + call jump 0014 + +dd15 # DB DD + illegal_1(); + call jump 0015 + +dd16 # DB DD + illegal_1(); + call jump 0016 + +dd17 # DB DD + illegal_1(); + call jump 0017 + +dd18 # DB DD + illegal_1(); + call jump 0018 + +dd19 # ADD IX,DE + TDAT = IX; TDAT2 = DE; + call add16 + IX = TDAT; + +dd1a # DB DD + illegal_1(); + call jump 001a + +dd1b # DB DD + illegal_1(); + call jump 001b + +dd1c # DB DD + illegal_1(); + call jump 001c + +dd1d # DB DD + illegal_1(); + call jump 001d + +dd1e # DB DD + illegal_1(); + call jump 001e + +dd1f # DB DD + illegal_1(); + call jump 001f + +dd20 # DB DD + illegal_1(); + call jump 0020 + +dd21 # LD IX,w + call arg16 + IX = TDAT; + +dd22 # LD (w),IX + call arg16 + m_ea = TDAT; TDAT = IX; + call wm16 m_ea + WZ = m_ea + 1; + +dd23 # INC IX + call nomreq_ir 2 + IX++; + +dd24 # INC HX + inc(HX); + +dd25 # DEC HX + dec(HX); + +dd26 # LD HX,n + call arg + HX = TDAT8; + +dd27 # DB DD + illegal_1(); + call jump 0027 + +dd28 # DB DD + illegal_1(); + call jump 0028 + +dd29 # ADD IX,IX + TDAT = IX; TDAT2 = IX; + call add16 + IX = TDAT; + +dd2a # LD IX,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + IX = TDAT; WZ = m_ea + 1; + +dd2b # DEC IX + call nomreq_ir 2 + IX--; + +dd2c # INC LX + inc(LX); + +dd2d # DEC LX + dec(LX); + +dd2e # LD LX,n + call arg + LX = TDAT8; + +dd2f # DB DD + illegal_1(); + call jump 002f + +dd30 # DB DD + illegal_1(); + call jump 0030 + +dd31 # DB DD + illegal_1(); + call jump 0031 + +dd32 # DB DD + illegal_1(); + call jump 0032 + +dd33 # DB DD + illegal_1(); + call jump 0033 + +dd34 # INC (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm_reg m_ea + inc(TDAT8); + call wm m_ea + +dd35 # DEC (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm_reg m_ea + dec(TDAT8); + call wm m_ea + +dd36 # LD (IX+o),n + call eax + call arg + 2 * call nomreq_addr PC-1 + call wm m_ea + +dd37 # DB DD + illegal_1(); + call jump 0037 + +dd38 # DB DD + illegal_1(); + call jump 0038 + +dd39 # ADD IX,SP + TDAT = IX; TDAT2 = SP; + call add16 + IX = TDAT; + +dd3a # DB DD + illegal_1(); + call jump 003a + +dd3b # DB DD + illegal_1(); + call jump 003b + +dd3c # DB DD + illegal_1(); + call jump 003c + +dd3d # DB DD + illegal_1(); + call jump 003d + +dd3e # DB DD + illegal_1(); + call jump 003e + +dd3f # DB DD + illegal_1(); + call jump 003f + +dd40 # DB DD + illegal_1(); + call jump 0040 + +dd41 # DB DD + illegal_1(); + call jump 0041 + +dd42 # DB DD + illegal_1(); + call jump 0042 + +dd43 # DB DD + illegal_1(); + call jump 0043 + +dd44 # LD B,HX + B = HX; + +dd45 # LD B,LX + B = LX; + +dd46 # LD B,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + B = TDAT8; + +dd47 # DB DD + illegal_1(); + call jump 0047 + +dd48 # DB DD + illegal_1(); + call jump 0048 + +dd49 # DB DD + illegal_1(); + call jump 0049 + +dd4a # DB DD + illegal_1(); + call jump 004a + +dd4b # DB DD + illegal_1(); + call jump 004b + +dd4c # LD C,HX + C = HX; + +dd4d # LD C,LX + C = LX; + +dd4e # LD C,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + C = TDAT8; + +dd4f # DB DD + illegal_1(); + call jump 004f + +dd50 # DB DD + illegal_1(); + call jump 0050 + +dd51 # DB DD + illegal_1(); + call jump 0051 + +dd52 # DB DD + illegal_1(); + call jump 0052 + +dd53 # DB DD + illegal_1(); + call jump 0053 + +dd54 # LD D,HX + D = HX; + +dd55 # LD D,LX + D = LX; + +dd56 # LD D,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + D = TDAT8; + +dd57 # DB DD + illegal_1(); + call jump 0057 + +dd58 # DB DD + illegal_1(); + call jump 0058 + +dd59 # DB DD + illegal_1(); + call jump 0059 + +dd5a # DB DD + illegal_1(); + call jump 005a + +dd5b # DB DD + illegal_1(); + call jump 005b + +dd5c # LD E,HX + E = HX; + +dd5d # LD E,LX + E = LX; + +dd5e # LD E,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + E = TDAT8; + +dd5f # DB DD + illegal_1(); + call jump 005f + +dd60 # LD HX,B + HX = B; + +dd61 # LD HX,C + HX = C; + +dd62 # LD HX,D + HX = D; + +dd63 # LD HX,E + HX = E; + +dd64 # LD HX,HX + +dd65 # LD HX,LX + HX = LX; + +dd66 # LD H,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + H = TDAT8; + +dd67 # LD HX,A + HX = A; + +dd68 # LD LX,B + LX = B; + +dd69 # LD LX,C + LX = C; + +dd6a # LD LX,D + LX = D; + +dd6b # LD LX,E + LX = E; + +dd6c # LD LX,HX + LX = HX; + +dd6d # LD LX,LX + +dd6e # LD L,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + L = TDAT8; + +dd6f # LD LX,A + LX = A; + +dd70 # LD (IX+o),B + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = B; + call wm m_ea + +dd71 # LD (IX+o),C + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = C; + call wm m_ea + +dd72 # LD (IX+o),D + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = D; + call wm m_ea + +dd73 # LD (IX+o),E + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = E; + call wm m_ea + +dd74 # LD (IX+o),H + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = H; + call wm m_ea + +dd75 # LD (IX+o),L + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = L; + call wm m_ea + +dd76 # DB DD + illegal_1(); + call jump 0076 + +dd77 # LD (IX+o),A + call eax + 5 * call nomreq_addr PC-1 + TDAT8 = A; + call wm m_ea + +dd78 # DB DD + illegal_1(); + call jump 0078 + +dd79 # DB DD + illegal_1(); + call jump 0079 + +dd7a # DB DD + illegal_1(); + call jump 007a + +dd7b # DB DD + illegal_1(); + call jump 007b + +dd7c # LD A,HX + A = HX; + +dd7d # LD A,LX + A = LX; + +dd7e # LD A,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + A = TDAT8; + +dd7f # DB DD + illegal_1(); + call jump 007f + +dd80 # DB DD + illegal_1(); + call jump 0080 + +dd81 # DB DD + illegal_1(); + call jump 0081 + +dd82 # DB DD + illegal_1(); + call jump 0082 + +dd83 # DB DD + illegal_1(); + call jump 0083 + +dd84 # ADD A,HX + add_a(HX); + +dd85 # ADD A,LX + add_a(LX); + +dd86 # ADD A,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + add_a(TDAT8); + +dd87 # DB DD + illegal_1(); + call jump 0087 + +dd88 # DB DD + illegal_1(); + call jump 0088 + +dd89 # DB DD + illegal_1(); + call jump 0089 + +dd8a # DB DD + illegal_1(); + call jump 008a + +dd8b # DB DD + illegal_1(); + call jump 008b + +dd8c # ADC A,HX + adc_a(HX); + +dd8d # ADC A,LX + adc_a(LX); + +dd8e # ADC A,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + adc_a(TDAT8); + +dd8f # DB DD + illegal_1(); + call jump 008f + +dd90 # DB DD + illegal_1(); + call jump 0090 + +dd91 # DB DD + illegal_1(); + call jump 0091 + +dd92 # DB DD + illegal_1(); + call jump 0092 + +dd93 # DB DD + illegal_1(); + call jump 0093 + +dd94 # SUB HX + sub_a(HX); + +dd95 # SUB LX + sub_a(LX); + +dd96 # SUB (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + sub_a(TDAT8); + +dd97 # DB DD + illegal_1(); + call jump 0097 + +dd98 # DB DD + illegal_1(); + call jump 0098 + +dd99 # DB DD + illegal_1(); + call jump 0099 + +dd9a # DB DD + illegal_1(); + call jump 009a + +dd9b # DB DD + illegal_1(); + call jump 009b + +dd9c # SBC A,HX + sbc_a(HX); + +dd9d # SBC A,LX + sbc_a(LX); + +dd9e # SBC A,(IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + sbc_a(TDAT8); + +dd9f # DB DD + illegal_1(); + call jump 009f + +dda0 # DB DD + illegal_1(); + call jump 00a0 + +dda1 # DB DD + illegal_1(); + call jump 00a1 + +dda2 # DB DD + illegal_1(); + call jump 00a2 + +dda3 # DB DD + illegal_1(); + call jump 00a3 + +dda4 # AND HX + and_a(HX); + +dda5 # AND LX + and_a(LX); + +dda6 # AND (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + and_a(TDAT8); + +dda7 # DB DD + illegal_1(); + call jump 00a7 + +dda8 # DB DD + illegal_1(); + call jump 00a8 + +dda9 # DB DD + illegal_1(); + call jump 00a9 + +ddaa # DB DD + illegal_1(); + call jump 00aa + +ddab # DB DD + illegal_1(); + call jump 00ab + +ddac # XOR HX + xor_a(HX); + +ddad # XOR LX + xor_a(LX); + +ddae # XOR (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + xor_a(TDAT8); + +ddaf # DB DD + illegal_1(); + call jump 00af + +ddb0 # DB DD + illegal_1(); + call jump 00b0 + +ddb1 # DB DD + illegal_1(); + call jump 00b1 + +ddb2 # DB DD + illegal_1(); + call jump 00b2 + +ddb3 # DB DD + illegal_1(); + call jump 00b3 + +ddb4 # OR HX + or_a(HX); + +ddb5 # OR LX + or_a(LX); + +ddb6 # OR (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + or_a(TDAT8); + +ddb7 # DB DD + illegal_1(); + call jump 00b7 + +ddb8 # DB DD + illegal_1(); + call jump 00b8 + +ddb9 # DB DD + illegal_1(); + call jump 00b9 + +ddba # DB DD + illegal_1(); + call jump 00ba + +ddbb # DB DD + illegal_1(); + call jump 00bb + +ddbc # CP HX + cp(HX); + +ddbd # CP LX + cp(LX); + +ddbe # CP (IX+o) + call eax + 5 * call nomreq_addr PC-1 + call rm m_ea + cp(TDAT8); + +ddbf # DB DD + illegal_1(); + call jump 00bf + +ddc0 # DB DD + illegal_1(); + call jump 00c0 + +ddc1 # DB DD + illegal_1(); + call jump 00c1 + +ddc2 # DB DD + illegal_1(); + call jump 00c2 + +ddc3 # DB DD + illegal_1(); + call jump 00c3 + +ddc4 # DB DD + illegal_1(); + call jump 00c4 + +ddc5 # DB DD + illegal_1(); + call jump 00c5 + +ddc6 # DB DD + illegal_1(); + call jump 00c6 + +ddc7 # DB DD + illegal_1(); + call jump 00c7 + +ddc8 # DB DD + illegal_1(); + call jump 00c8 + +ddc9 # DB DD + illegal_1(); + call jump 00c9 + +ddca # DB DD + illegal_1(); + call jump 00ca + +ddcb # ** DD CB xx + call eax + call arg + 2 * call nomreq_addr PC-1 + call jump_prefixed 0xfe + +ddcc # DB DD + illegal_1(); + call jump 00cc + +ddcd # DB DD + illegal_1(); + call jump 00cd + +ddce # DB DD + illegal_1(); + call jump 00ce + +ddcf # DB DD + illegal_1(); + call jump 00cf + +ddd0 # DB DD + illegal_1(); + call jump 00d0 + +ddd1 # DB DD + illegal_1(); + call jump 00d1 + +ddd2 # DB DD + illegal_1(); + call jump 00d2 + +ddd3 # DB DD + illegal_1(); + call jump 00d3 + +ddd4 # DB DD + illegal_1(); + call jump 00d4 + +ddd5 # DB DD + illegal_1(); + call jump 00d5 + +ddd6 # DB DD + illegal_1(); + call jump 00d6 + +ddd7 # DB DD + illegal_1(); + call jump 00d7 + +ddd8 # DB DD + illegal_1(); + call jump 00d8 + +ddd9 # DB DD + illegal_1(); + call jump 00d9 + +ddda # DB DD + illegal_1(); + call jump 00da + +dddb # DB DD + illegal_1(); + call jump 00db + +dddc # DB DD + illegal_1(); + call jump 00dc + +dddd # DB DD + illegal_1(); + call jump 00dd + +ddde # DB DD + illegal_1(); + call jump 00de + +dddf # DB DD + illegal_1(); + call jump 00df + +dde0 # DB DD + illegal_1(); + call jump 00e0 + +dde1 # POP IX + call pop + IX = TDAT; + +dde2 # DB DD + illegal_1(); + call jump 00e2 + +dde3 # EX (SP),IX + call ex_sp IX + +dde4 # DB DD + illegal_1(); + call jump 00e4 + +dde5 # PUSH IX + call push IX + +dde6 # DB DD + illegal_1(); + call jump 00e6 + +dde7 # DB DD + illegal_1(); + call jump 00e7 + +dde8 # DB DD + illegal_1(); + call jump 00e8 + +dde9 # JP (IX) + PC = IX; + +ddea # DB DD + illegal_1(); + call jump 00ea + +ddeb # DB DD + illegal_1(); + call jump 00eb + +ddec # DB DD + illegal_1(); + call jump 00ec + +dded # DB DD + illegal_1(); + call jump 00ed + +ddee # DB DD + illegal_1(); + call jump 00ee + +ddef # DB DD + illegal_1(); + call jump 00ef + +ddf0 # DB DD + illegal_1(); + call jump 00f0 + +ddf1 # DB DD + illegal_1(); + call jump 00f1 + +ddf2 # DB DD + illegal_1(); + call jump 00f2 + +ddf3 # DB DD + illegal_1(); + call jump 00f3 + +ddf4 # DB DD + illegal_1(); + call jump 00f4 + +ddf5 # DB DD + illegal_1(); + call jump 00f5 + +ddf6 # DB DD + illegal_1(); + call jump 00f6 + +ddf7 # DB DD + illegal_1(); + call jump 00f7 + +ddf8 # DB DD + illegal_1(); + call jump 00f8 + +ddf9 # LD SP,IX + call nomreq_ir 2 + SP = IX; + +ddfa # DB DD + illegal_1(); + call jump 00fa + +ddfb # DB DD + illegal_1(); + call jump 00fb + +ddfc # DB DD + illegal_1(); + call jump 00fc + +ddfd # DB DD + illegal_1(); + call jump 00fd + +ddfe # DB DD + illegal_1(); + call jump 00fe + +ddff # DB DD + illegal_1(); + call jump 00ff + + +########################################################## +# IY register related opcodes (FD prefix) +########################################################## +fd00 # DB FD + illegal_1(); + call jump 0000 + +fd01 # DB FD + illegal_1(); + call jump 0001 + +fd02 # DB FD + illegal_1(); + call jump 0002 + +fd03 # DB FD + illegal_1(); + call jump 0003 + +fd04 # DB FD + illegal_1(); + call jump 0004 + +fd05 # DB FD + illegal_1(); + call jump 0005 + +fd06 # DB FD + illegal_1(); + call jump 0006 + +fd07 # DB FD + illegal_1(); + call jump 0007 + +fd08 # DB FD + illegal_1(); + call jump 0008 + +fd09 # ADD IY,BC + TDAT = IY; TDAT2 = BC; + call add16 + IY = TDAT; + +fd0a # DB FD + illegal_1(); + call jump 000a + +fd0b # DB FD + illegal_1(); + call jump 000b + +fd0c # DB FD + illegal_1(); + call jump 000c + +fd0d # DB FD + illegal_1(); + call jump 000d + +fd0e # DB FD + illegal_1(); + call jump 000e + +fd0f # DB FD + illegal_1(); + call jump 000f + +fd10 # DB FD + illegal_1(); + call jump 0010 + +fd11 # DB FD + illegal_1(); + call jump 0011 + +fd12 # DB FD + illegal_1(); + call jump 0012 + +fd13 # DB FD + illegal_1(); + call jump 0013 + +fd14 # DB FD + illegal_1(); + call jump 0014 + +fd15 # DB FD + illegal_1(); + call jump 0015 + +fd16 # DB FD + illegal_1(); + call jump 0016 + +fd17 # DB FD + illegal_1(); + call jump 0017 + +fd18 # DB FD + illegal_1(); + call jump 0018 + +fd19 # ADD IY,DE + TDAT = IY; TDAT2 = DE; + call add16 + IY = TDAT; + +fd1a # DB FD + illegal_1(); + call jump 001a + +fd1b # DB FD + illegal_1(); + call jump 001b + +fd1c # DB FD + illegal_1(); + call jump 001c + +fd1d # DB FD + illegal_1(); + call jump 001d + +fd1e # DB FD + illegal_1(); + call jump 001e + +fd1f # DB FD + illegal_1(); + call jump 001f + +fd20 # DB FD + illegal_1(); + call jump 0020 + +fd21 # LD IY,w + call arg16 + IY = TDAT; + +fd22 # LD (w),IY + call arg16 + m_ea = TDAT; TDAT = IY; + call wm16 m_ea + WZ = m_ea + 1; + +fd23 # INC IY + call nomreq_ir 2 + IY++; + +fd24 # INC HY + inc(HY); + +fd25 # DEC HY + dec(HY); + +fd26 # LD HY,n + call arg + HY = TDAT8; + +fd27 # DB FD + illegal_1(); + call jump 0027 + +fd28 # DB FD + illegal_1(); + call jump 0028 + +fd29 # ADD IY,IY + TDAT = IY; TDAT2 = IY; + call add16 + IY = TDAT; + +fd2a # LD IY,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + IY = TDAT; WZ = m_ea + 1; + +fd2b # DEC IY + call nomreq_ir 2 + IY--; + +fd2c # INC LY + inc(LY); + +fd2d # DEC LY + dec(LY); + +fd2e # LD LY,n + call arg + LY = TDAT8; + +fd2f # DB FD + illegal_1(); + call jump 002f + +fd30 # DB FD + illegal_1(); + call jump 0030 + +fd31 # DB FD + illegal_1(); + call jump 0031 + +fd32 # DB FD + illegal_1(); + call jump 0032 + +fd33 # DB FD + illegal_1(); + call jump 0033 + +fd34 # INC (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm_reg m_ea + inc(TDAT8); + call wm m_ea + +fd35 # DEC (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm_reg m_ea + dec(TDAT8); + call wm m_ea + +fd36 # LD (IY+o),n + call eay + call arg + 2 * call nomreq_addr PC-1 + call wm m_ea + +fd37 # DB FD + illegal_1(); + call jump 0037 + +fd38 # DB FD + illegal_1(); + call jump 0038 + +fd39 # ADD IY,SP + TDAT = IY; TDAT2 = SP; + call add16 + IY = TDAT; + +fd3a # DB FD + illegal_1(); + call jump 003a + +fd3b # DB FD + illegal_1(); + call jump 003b + +fd3c # DB FD + illegal_1(); + call jump 003c + +fd3d # DB FD + illegal_1(); + call jump 003d + +fd3e # DB FD + illegal_1(); + call jump 003e + +fd3f # DB FD + illegal_1(); + call jump 003f + +fd40 # DB FD + illegal_1(); + call jump 0040 + +fd41 # DB FD + illegal_1(); + call jump 0041 + +fd42 # DB FD + illegal_1(); + call jump 0042 + +fd43 # DB FD + illegal_1(); + call jump 0043 + +fd44 # LD B,HY + B = HY; + +fd45 # LD B,LY + B = LY; + +fd46 # LD B,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + B = TDAT8; + +fd47 # DB FD + illegal_1(); + call jump 0047 + +fd48 # DB FD + illegal_1(); + call jump 0048 + +fd49 # DB FD + illegal_1(); + call jump 0049 + +fd4a # DB FD + illegal_1(); + call jump 004a + +fd4b # DB FD + illegal_1(); + call jump 004b + +fd4c # LD C,HY + C = HY; + +fd4d # LD C,LY + C = LY; + +fd4e # LD C,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + C = TDAT8; + +fd4f # DB FD + illegal_1(); + call jump 004f + +fd50 # DB FD + illegal_1(); + call jump 0050 + +fd51 # DB FD + illegal_1(); + call jump 0051 + +fd52 # DB FD + illegal_1(); + call jump 0052 + +fd53 # DB FD + illegal_1(); + call jump 0053 + +fd54 # LD D,HY + D = HY; + +fd55 # LD D,LY + D = LY; + +fd56 # LD D,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + D = TDAT8; + +fd57 # DB FD + illegal_1(); + call jump 0057 + +fd58 # DB FD + illegal_1(); + call jump 0058 + +fd59 # DB FD + illegal_1(); + call jump 0059 + +fd5a # DB FD + illegal_1(); + call jump 005a + +fd5b # DB FD + illegal_1(); + call jump 005b + +fd5c # LD E,HY + E = HY; + +fd5d # LD E,LY + E = LY; + +fd5e # LD E,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + E = TDAT8; + +fd5f # DB FD + illegal_1(); + call jump 005f + +fd60 # LD HY,B + HY = B; + +fd61 # LD HY,C + HY = C; + +fd62 # LD HY,D + HY = D; + +fd63 # LD HY,E + HY = E; + +fd64 # LD HY,HY + +fd65 # LD HY,LY + HY = LY; + +fd66 # LD H,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + H = TDAT8; + +fd67 # LD HY,A + HY = A; + +fd68 # LD LY,B + LY = B; + +fd69 # LD LY,C + LY = C; + +fd6a # LD LY,D + LY = D; + +fd6b # LD LY,E + LY = E; + +fd6c # LD LY,HY + LY = HY; + +fd6d # LD LY,LY + +fd6e # LD L,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + L = TDAT8; + +fd6f # LD LY,A + LY = A; + +fd70 # LD (IY+o),B + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = B; + call wm m_ea + +fd71 # LD (IY+o),C + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = C; + call wm m_ea + +fd72 # LD (IY+o),D + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = D; + call wm m_ea + +fd73 # LD (IY+o),E + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = E; + call wm m_ea + +fd74 # LD (IY+o),H + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = H; + call wm m_ea + +fd75 # LD (IY+o),L + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = L; + call wm m_ea + +fd76 # DB FD + illegal_1(); + call jump 0076 + +fd77 # LD (IY+o),A + call eay + 5 * call nomreq_addr PC-1 + TDAT8 = A; + call wm m_ea + +fd78 # DB FD + illegal_1(); + call jump 0078 + +fd79 # DB FD + illegal_1(); + call jump 0079 + +fd7a # DB FD + illegal_1(); + call jump 007a + +fd7b # DB FD + illegal_1(); + call jump 007b + +fd7c # LD A,HY + A = HY; + +fd7d # LD A,LY + A = LY; + +fd7e # LD A,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + A = TDAT8; + +fd7f # DB FD + illegal_1(); + call jump 007f + +fd80 # DB FD + illegal_1(); + call jump 0080 + +fd81 # DB FD + illegal_1(); + call jump 0081 + +fd82 # DB FD + illegal_1(); + call jump 0082 + +fd83 # DB FD + illegal_1(); + call jump 0083 + +fd84 # ADD A,HY + add_a(HY); + +fd85 # ADD A,LY + add_a(LY); + +fd86 # ADD A,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + add_a(TDAT8); + +fd87 # DB FD + illegal_1(); + call jump 0087 + +fd88 # DB FD + illegal_1(); + call jump 0088 + +fd89 # DB FD + illegal_1(); + call jump 0089 + +fd8a # DB FD + illegal_1(); + call jump 008a + +fd8b # DB FD + illegal_1(); + call jump 008b + +fd8c # ADC A,HY + adc_a(HY); + +fd8d # ADC A,LY + adc_a(LY); + +fd8e # ADC A,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + adc_a(TDAT8); + +fd8f # DB FD + illegal_1(); + call jump 008f + +fd90 # DB FD + illegal_1(); + call jump 0090 + +fd91 # DB FD + illegal_1(); + call jump 0091 + +fd92 # DB FD + illegal_1(); + call jump 0092 + +fd93 # DB FD + illegal_1(); + call jump 0093 + +fd94 # SUB HY + sub_a(HY); + +fd95 # SUB LY + sub_a(LY); + +fd96 # SUB (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + sub_a(TDAT8); + +fd97 # DB FD + illegal_1(); + call jump 0097 + +fd98 # DB FD + illegal_1(); + call jump 0098 + +fd99 # DB FD + illegal_1(); + call jump 0099 + +fd9a # DB FD + illegal_1(); + call jump 009a + +fd9b # DB FD + illegal_1(); + call jump 009b + +fd9c # SBC A,HY + sbc_a(HY); + +fd9d # SBC A,LY + sbc_a(LY); + +fd9e # SBC A,(IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + sbc_a(TDAT8); + +fd9f # DB FD + illegal_1(); + call jump 009f + +fda0 # DB FD + illegal_1(); + call jump 00a0 + +fda1 # DB FD + illegal_1(); + call jump 00a1 + +fda2 # DB FD + illegal_1(); + call jump 00a2 + +fda3 # DB FD + illegal_1(); + call jump 00a3 + +fda4 # AND HY + and_a(HY); + +fda5 # AND LY + and_a(LY); + +fda6 # AND (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + and_a(TDAT8); + +fda7 # DB FD + illegal_1(); + call jump 00a7 + +fda8 # DB FD + illegal_1(); + call jump 00a8 + +fda9 # DB FD + illegal_1(); + call jump 00a9 + +fdaa # DB FD + illegal_1(); + call jump 00aa + +fdab # DB FD + illegal_1(); + call jump 00ab + +fdac # XOR HY + xor_a(HY); + +fdad # XOR LY + xor_a(LY); + +fdae # XOR (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + xor_a(TDAT8); + +fdaf # DB FD + illegal_1(); + call jump 00af + +fdb0 # DB FD + illegal_1(); + call jump 00b0 + +fdb1 # DB FD + illegal_1(); + call jump 00b1 + +fdb2 # DB FD + illegal_1(); + call jump 00b2 + +fdb3 # DB FD + illegal_1(); + call jump 00b3 + +fdb4 # OR HY + or_a(HY); + +fdb5 # OR LY + or_a(LY); + +fdb6 # OR (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + or_a(TDAT8); + +fdb7 # DB FD + illegal_1(); + call jump 00b7 + +fdb8 # DB FD + illegal_1(); + call jump 00b8 + +fdb9 # DB FD + illegal_1(); + call jump 00b9 + +fdba # DB FD + illegal_1(); + call jump 00ba + +fdbb # DB FD + illegal_1(); + call jump 00bb + +fdbc # CP HY + cp(HY); + +fdbd # CP LY + cp(LY); + +fdbe # CP (IY+o) + call eay + 5 * call nomreq_addr PC-1 + call rm m_ea + cp(TDAT8); + +fdbf # DB FD + illegal_1(); + call jump 00bf + +fdc0 # DB FD + illegal_1(); + call jump 00c0 + +fdc1 # DB FD + illegal_1(); + call jump 00c1 + +fdc2 # DB FD + illegal_1(); + call jump 00c2 + +fdc3 # DB FD + illegal_1(); + call jump 00c3 + +fdc4 # DB FD + illegal_1(); + call jump 00c4 + +fdc5 # DB FD + illegal_1(); + call jump 00c5 + +fdc6 # DB FD + illegal_1(); + call jump 00c6 + +fdc7 # DB FD + illegal_1(); + call jump 00c7 + +fdc8 # DB FD + illegal_1(); + call jump 00c8 + +fdc9 # DB FD + illegal_1(); + call jump 00c9 + +fdca # DB FD + illegal_1(); + call jump 00ca + +fdcb # ** FD CB xx + call eay + call arg + 2 * call nomreq_addr PC-1 + call jump_prefixed 0xfe + +fdcc # DB FD + illegal_1(); + call jump 00cc + +fdcd # DB FD + illegal_1(); + call jump 00cd + +fdce # DB FD + illegal_1(); + call jump 00ce + +fdcf # DB FD + illegal_1(); + call jump 00cf + +fdd0 # DB FD + illegal_1(); + call jump 00d0 + +fdd1 # DB FD + illegal_1(); + call jump 00d1 + +fdd2 # DB FD + illegal_1(); + call jump 00d2 + +fdd3 # DB FD + illegal_1(); + call jump 00d3 + +fdd4 # DB FD + illegal_1(); + call jump 00d4 + +fdd5 # DB FD + illegal_1(); + call jump 00d5 + +fdd6 # DB FD + illegal_1(); + call jump 00d6 + +fdd7 # DB FD + illegal_1(); + call jump 00d7 + +fdd8 # DB FD + illegal_1(); + call jump 00d8 + +fdd9 # DB FD + illegal_1(); + call jump 00d9 + +fdda # DB FD + illegal_1(); + call jump 00da + +fddb # DB FD + illegal_1(); + call jump 00db + +fddc # DB FD + illegal_1(); + call jump 00dc + +fddd # DB FD + illegal_1(); + call jump 00dd + +fdde # DB FD + illegal_1(); + call jump 00de + +fddf # DB FD + illegal_1(); + call jump 00df + +fde0 # DB FD + illegal_1(); + call jump 00e0 + +fde1 # POP IY + call pop + IY = TDAT; + +fde2 # DB FD + illegal_1(); + call jump 00e2 + +fde3 # EX (SP),IY + call ex_sp IY + +fde4 # DB FD + illegal_1(); + call jump 00e4 + +fde5 # PUSH IY + call push IY + +fde6 # DB FD + illegal_1(); + call jump 00e6 + +fde7 # DB FD + illegal_1(); + call jump 00e7 + +fde8 # DB FD + illegal_1(); + call jump 00e8 + +fde9 # JP (IY) + PC = IY; + +fdea # DB FD + illegal_1(); + call jump 00ea + +fdeb # DB FD + illegal_1(); + call jump 00eb + +fdec # DB FD + illegal_1(); + call jump 00ec + +fded # DB FD + illegal_1(); + call jump 00ed + +fdee # DB FD + illegal_1(); + call jump 00ee + +fdef # DB FD + illegal_1(); + call jump 00ef + +fdf0 # DB FD + illegal_1(); + call jump 00f0 + +fdf1 # DB FD + illegal_1(); + call jump 00f1 + +fdf2 # DB FD + illegal_1(); + call jump 00f2 + +fdf3 # DB FD + illegal_1(); + call jump 00f3 + +fdf4 # DB FD + illegal_1(); + call jump 00f4 + +fdf5 # DB FD + illegal_1(); + call jump 00f5 + +fdf6 # DB FD + illegal_1(); + call jump 00f6 + +fdf7 # DB FD + illegal_1(); + call jump 00f7 + +fdf8 # DB FD + illegal_1(); + call jump 00f8 + +fdf9 # LD SP,IY + call nomreq_ir 2 + SP = IY; + +fdfa # DB FD + illegal_1(); + call jump 00fa + +fdfb # DB FD + illegal_1(); + call jump 00fb + +fdfc # DB FD + illegal_1(); + call jump 00fc + +fdfd # DB FD + illegal_1(); + call jump 00fd + +fdfe # DB FD + illegal_1(); + call jump 00fe + +fdff # DB FD + illegal_1(); + call jump 00ff + + +########################################################## +# special opcodes (ED prefix) +########################################################## +ed00 # DB ED + illegal_2(); + +ed01 # DB ED + illegal_2(); + +ed02 # DB ED + illegal_2(); + +ed03 # DB ED + illegal_2(); + +ed04 # DB ED + illegal_2(); + +ed05 # DB ED + illegal_2(); + +ed06 # DB ED + illegal_2(); + +ed07 # DB ED + illegal_2(); + +ed08 # DB ED + illegal_2(); + +ed09 # DB ED + illegal_2(); + +ed0a # DB ED + illegal_2(); + +ed0b # DB ED + illegal_2(); + +ed0c # DB ED + illegal_2(); + +ed0d # DB ED + illegal_2(); + +ed0e # DB ED + illegal_2(); + +ed0f # DB ED + illegal_2(); + +ed10 # DB ED + illegal_2(); + +ed11 # DB ED + illegal_2(); + +ed12 # DB ED + illegal_2(); + +ed13 # DB ED + illegal_2(); + +ed14 # DB ED + illegal_2(); + +ed15 # DB ED + illegal_2(); + +ed16 # DB ED + illegal_2(); + +ed17 # DB ED + illegal_2(); + +ed18 # DB ED + illegal_2(); + +ed19 # DB ED + illegal_2(); + +ed1a # DB ED + illegal_2(); + +ed1b # DB ED + illegal_2(); + +ed1c # DB ED + illegal_2(); + +ed1d # DB ED + illegal_2(); + +ed1e # DB ED + illegal_2(); + +ed1f # DB ED + illegal_2(); + +ed20 # DB ED + illegal_2(); + +ed21 # DB ED + illegal_2(); + +ed22 # DB ED + illegal_2(); + +ed23 # DB ED + illegal_2(); + +ed24 # DB ED + illegal_2(); + +ed25 # DB ED + illegal_2(); + +ed26 # DB ED + illegal_2(); + +ed27 # DB ED + illegal_2(); + +ed28 # DB ED + illegal_2(); + +ed29 # DB ED + illegal_2(); + +ed2a # DB ED + illegal_2(); + +ed2b # DB ED + illegal_2(); + +ed2c # DB ED + illegal_2(); + +ed2d # DB ED + illegal_2(); + +ed2e # DB ED + illegal_2(); + +ed2f # DB ED + illegal_2(); + +ed30 # DB ED + illegal_2(); + +ed31 # DB ED + illegal_2(); + +ed32 # DB ED + illegal_2(); + +ed33 # DB ED + illegal_2(); + +ed34 # DB ED + illegal_2(); + +ed35 # DB ED + illegal_2(); + +ed36 # DB ED + illegal_2(); + +ed37 # DB ED + illegal_2(); + +ed38 # DB ED + illegal_2(); + +ed39 # DB ED + illegal_2(); + +ed3a # DB ED + illegal_2(); + +ed3b # DB ED + illegal_2(); + +ed3c # DB ED + illegal_2(); + +ed3d # DB ED + illegal_2(); + +ed3e # DB ED + illegal_2(); + +ed3f # DB ED + illegal_2(); + +ed40 # IN B,(C) + call in BC + B = TDAT8; set_f((F & CF) | SZP[B]); WZ = BC + 1; + +ed41 # OUT (C),B + TDAT8 = B; + call out BC + WZ = BC + 1; + +ed42 # SBC HL,BC + TDAT = BC; + call sbc_hl + +ed43 # LD (w),BC + call arg16 + m_ea = TDAT; TDAT = BC; + call wm16 m_ea + WZ = m_ea + 1; + +ed44 # NEG + neg(); + +ed45 # RETN + call retn + +ed46 # IM 0 + m_im = 0; + +ed47 # LD i,A + call ld_i_a + +ed48 # IN C,(C) + call in BC + C = TDAT8; set_f((F & CF) | SZP[C]); WZ = BC + 1; + +ed49 # OUT (C),C + TDAT8 = C; + call out BC + WZ = BC + 1; + +ed4a # ADC HL,BC + TDAT = BC; + call adc_hl + +ed4b # LD BC,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + BC = TDAT; WZ = m_ea + 1; + +ed4c # NEG + neg(); + +ed4d # RETI + call reti + +ed4e # IM 0 + m_im = 0; + +ed4f # LD r,A + call ld_r_a + +ed50 # IN D,(C) + call in BC + D = TDAT8; set_f((F & CF) | SZP[D]); WZ = BC + 1; + +ed51 # OUT (C),D + TDAT8 = D; + call out BC + WZ = BC + 1; + +ed52 # SBC HL,DE + TDAT = DE; + call sbc_hl + +ed53 # LD (w),DE + call arg16 + m_ea = TDAT; TDAT = DE; + call wm16 m_ea + WZ = m_ea + 1; + +ed54 # NEG + neg(); + +ed55 # RETN + call retn + +ed56 # IM 1 + m_im = 1; + +ed57 # LD A,i + call ld_a_i + +ed58 # IN E,(C) + call in BC + E = TDAT8; set_f((F & CF) | SZP[E]); WZ = BC + 1; + +ed59 # OUT (C),E + TDAT8 = E; + call out BC + WZ = BC + 1; + +ed5a # ADC HL,DE + TDAT = DE; + call adc_hl + +ed5b # LD DE,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + DE = TDAT; WZ = m_ea + 1; + +ed5c # NEG + neg(); + +ed5d # RETI + call reti + +ed5e # IM 2 + m_im = 2; + +ed5f # LD A,r + call ld_a_r + +ed60 # IN H,(C) + call in BC + H = TDAT8; set_f((F & CF) | SZP[H]); WZ = BC + 1; + +ed61 # OUT (C),H + TDAT8 = H; + call out BC + WZ = BC + 1; + +ed62 # SBC HL,HL + TDAT = HL; + call sbc_hl + +ed63 # LD (w),HL + call arg16 + m_ea = TDAT; TDAT = HL; + call wm16 m_ea + WZ = m_ea + 1; + +ed64 # NEG + neg(); + +ed65 # RETN + call retn + +ed66 # IM 0 + m_im = 0; + +ed67 # RRD (HL) + call rrd + +ed68 # IN L,(C) + call in BC + L = TDAT8; set_f((F & CF) | SZP[L]); WZ = BC + 1; + +ed69 # OUT (C),L + TDAT8 = L; + call out BC + WZ = BC + 1; + +ed6a # ADC HL,HL + TDAT = HL; + call adc_hl + +ed6b # LD HL,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + HL = TDAT; WZ = m_ea + 1; + +ed6c # NEG + neg(); + +ed6d # RETI + call reti + +ed6e # IM 0 + m_im = 0; + +ed6f # RLD (HL) + call rld + +ed70 # IN 0,(C) + call in BC + set_f((F & CF) | SZP[TDAT8]); WZ = BC + 1; + +ed71 # OUT (C),0 + TDAT8 = 0; + call out BC + WZ = BC + 1; + +ed72 # SBC HL,SP + TDAT = SP; + call sbc_hl + +ed73 # LD (w),SP + call arg16 + m_ea = TDAT; TDAT = SP; + call wm16 m_ea + WZ = m_ea + 1; + +ed74 # NEG + neg(); + +ed75 # RETN + call retn + +ed76 # IM 1 + m_im = 1; + +ed77 # DB ED,77 + illegal_2(); + +ed78 # IN A,(C) + call in BC + A = TDAT8; set_f((F & CF) | SZP[A]); WZ = BC + 1; + +ed79 # OUT (C),A + TDAT8 = A; + call out BC + WZ = BC + 1; + +ed7a # ADC HL,SP + TDAT = SP; + call adc_hl + +ed7b # LD SP,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + SP = TDAT; WZ = m_ea + 1; + +ed7c # NEG + neg(); + +ed7d # RETI + call reti + +ed7e # IM 2 + m_im = 2; + +ed7f # DB ED,7F + illegal_2(); + +ed80 # DB ED + illegal_2(); + +ed81 # DB ED + illegal_2(); + +ed82 # DB ED + illegal_2(); + +ed83 # DB ED + illegal_2(); + +ed84 # DB ED + illegal_2(); + +ed85 # DB ED + illegal_2(); + +ed86 # DB ED + illegal_2(); + +ed87 # DB ED + illegal_2(); + +ed88 # DB ED + illegal_2(); + +ed89 # DB ED + illegal_2(); + +ed8a # DB ED + illegal_2(); + +ed8b # DB ED + illegal_2(); + +ed8c # DB ED + illegal_2(); + +ed8d # DB ED + illegal_2(); + +ed8e # DB ED + illegal_2(); + +ed8f # DB ED + illegal_2(); + +ed90 # DB ED + illegal_2(); + +ed91 # DB ED + illegal_2(); + +ed92 # DB ED + illegal_2(); + +ed93 # DB ED + illegal_2(); + +ed94 # DB ED + illegal_2(); + +ed95 # DB ED + illegal_2(); + +ed96 # DB ED + illegal_2(); + +ed97 # DB ED + illegal_2(); + +ed98 # DB ED + illegal_2(); + +ed99 # DB ED + illegal_2(); + +ed9a # DB ED + illegal_2(); + +ed9b # DB ED + illegal_2(); + +ed9c # DB ED + illegal_2(); + +ed9d # DB ED + illegal_2(); + +ed9e # DB ED + illegal_2(); + +ed9f # DB ED + illegal_2(); + +eda0 # LDI + call ldi + +eda1 # CPI + call cpi + +eda2 # INI + call ini + +eda3 # OUTI + call outi + +eda4 # DB ED + illegal_2(); + +eda5 # DB ED + illegal_2(); + +eda6 # DB ED + illegal_2(); + +eda7 # DB ED + illegal_2(); + +eda8 # LDD + call ldd + +eda9 # CPD + call cpd + +edaa # IND + call ind + +edab # OUTD + call outd + +edac # DB ED + illegal_2(); + +edad # DB ED + illegal_2(); + +edae # DB ED + illegal_2(); + +edaf # DB ED + illegal_2(); + +edb0 # LDIR + call ldir + +edb1 # CPIR + call cpir + +edb2 # INIR + call inir + +edb3 # OTIR + call otir + +edb4 # DB ED + illegal_2(); + +edb5 # DB ED + illegal_2(); + +edb6 # DB ED + illegal_2(); + +edb7 # DB ED + illegal_2(); + +edb8 # LDDR + call lddr + +edb9 # CPDR + call cpdr + +edba # INDR + call indr + +edbb # OTDR + call otdr + +edbc # DB ED + illegal_2(); + +edbd # DB ED + illegal_2(); + +edbe # DB ED + illegal_2(); + +edbf # DB ED + illegal_2(); + +edc0 # DB ED + illegal_2(); + +edc1 # DB ED + illegal_2(); + +edc2 # DB ED + illegal_2(); + +edc3 # DB ED + illegal_2(); + +edc4 # DB ED + illegal_2(); + +edc5 # DB ED + illegal_2(); + +edc6 # DB ED + illegal_2(); + +edc7 # DB ED + illegal_2(); + +edc8 # DB ED + illegal_2(); + +edc9 # DB ED + illegal_2(); + +edca # DB ED + illegal_2(); + +edcb # DB ED + illegal_2(); + +edcc # DB ED + illegal_2(); + +edcd # DB ED + illegal_2(); + +edce # DB ED + illegal_2(); + +edcf # DB ED + illegal_2(); + +edd0 # DB ED + illegal_2(); + +edd1 # DB ED + illegal_2(); + +edd2 # DB ED + illegal_2(); + +edd3 # DB ED + illegal_2(); + +edd4 # DB ED + illegal_2(); + +edd5 # DB ED + illegal_2(); + +edd6 # DB ED + illegal_2(); + +edd7 # DB ED + illegal_2(); + +edd8 # DB ED + illegal_2(); + +edd9 # DB ED + illegal_2(); + +edda # DB ED + illegal_2(); + +eddb # DB ED + illegal_2(); + +eddc # DB ED + illegal_2(); + +eddd # DB ED + illegal_2(); + +edde # DB ED + illegal_2(); + +eddf # DB ED + illegal_2(); + +ede0 # DB ED + illegal_2(); + +ede1 # DB ED + illegal_2(); + +ede2 # DB ED + illegal_2(); + +ede3 # DB ED + illegal_2(); + +ede4 # DB ED + illegal_2(); + +ede5 # DB ED + illegal_2(); + +ede6 # DB ED + illegal_2(); + +ede7 # DB ED + illegal_2(); + +ede8 # DB ED + illegal_2(); + +ede9 # DB ED + illegal_2(); + +edea # DB ED + illegal_2(); + +edeb # DB ED + illegal_2(); + +edec # DB ED + illegal_2(); + +eded # DB ED + illegal_2(); + +edee # DB ED + illegal_2(); + +edef # DB ED + illegal_2(); + +edf0 # DB ED + illegal_2(); + +edf1 # DB ED + illegal_2(); + +edf2 # DB ED + illegal_2(); + +edf3 # DB ED + illegal_2(); + +edf4 # DB ED + illegal_2(); + +edf5 # DB ED + illegal_2(); + +edf6 # DB ED + illegal_2(); + +edf7 # DB ED + illegal_2(); + +edf8 # DB ED + illegal_2(); + +edf9 # DB ED + illegal_2(); + +edfa # DB ED + illegal_2(); + +edfb # DB ED + illegal_2(); + +edfc # DB ED + illegal_2(); + +edfd # DB ED + illegal_2(); + +edfe # DB ED + illegal_2(); + +edff # DB ED + illegal_2(); + + +########################################################## +# main opcodes +########################################################## +0000 # NOP + +0001 # LD BC,w + call arg16 + BC = TDAT; + +0002 # LD (BC),A + TDAT8 = A; + call wm BC + WZ_L = (BC + 1) & 0xFF; WZ_H = A; + +0003 # INC BC + call nomreq_ir 2 + BC++; + +0004 # INC B + inc(B); + +0005 # DEC B + dec(B); + +0006 # LD B,n + call arg + B = TDAT8; + +0007 # RLCA + rlca(); + +0008 # EX AF,AF' + using std::swap; swap(m_af, m_af2); + +0009 # ADD HL,BC + TDAT = HL; TDAT2 = BC; + call add16 + HL = TDAT; + +000a # LD A,(BC) + call rm BC + A = TDAT8; WZ = BC+1; + +000b # DEC BC + call nomreq_ir 2 + BC--; + +000c # INC C + inc(C); + +000d # DEC C + dec(C); + +000e # LD C,n + call arg + C = TDAT8; + +000f # RRCA + rrca(); + +0010 # DJNZ o + call nomreq_ir 1 + TDAT8 = --B; + call jr_cond + +0011 # LD DE,w + call arg16 + DE = TDAT; + +0012 # LD (DE),A + TDAT8 = A; + call wm DE + WZ_L = (DE + 1) & 0xFF; WZ_H = A; + +0013 # INC DE + call nomreq_ir 2 + DE++; + +0014 # INC D + inc(D); + +0015 # DEC D + dec(D); + +0016 # LD D,n + call arg + D = TDAT8; + +0017 # RLA + rla(); + +0018 # JR o + call jr + +0019 # ADD HL,DE + TDAT = HL; TDAT2 = DE; + call add16 + HL = TDAT; + +001a # LD A,(DE) + call rm DE + A = TDAT8; WZ = DE + 1; + +001b # DEC DE + call nomreq_ir 2 + DE--; + +001c # INC E + inc(E); + +001d # DEC E + dec(E); + +001e # LD E,n + call arg + E = TDAT8; + +001f # RRA + rra(); + +0020 # JR NZ,o + TDAT8 = !(F & ZF); + call jr_cond + +0021 # LD HL,w + call arg16 + HL = TDAT; + +0022 # LD (w),HL + call arg16 + m_ea = TDAT; TDAT = HL; + call wm16 m_ea + WZ = m_ea + 1; + +0023 # INC HL + call nomreq_ir 2 + HL++; + +0024 # INC H + inc(H); + +0025 # DEC H + dec(H); + +0026 # LD H,n + call arg + H = TDAT8; + +0027 # DAA + daa(); + +0028 # JR Z,o + TDAT8 = F & ZF; + call jr_cond + +0029 # ADD HL,HL + TDAT = HL; TDAT2 = HL; + call add16 + HL = TDAT; + +002a # LD HL,(w) + call arg16 + m_ea = TDAT; + call rm16 m_ea + HL = TDAT; WZ = m_ea + 1; + +002b # DEC HL + call nomreq_ir 2 + HL--; + +002c # INC L + inc(L); + +002d # DEC L + dec(L); + +002e # LD L,n + call arg + L = TDAT8; + +002f # CPL + A ^= 0xff; set_f((F & (SF | ZF | PF | CF)) | HF | NF | (A & (YF | XF))); + +0030 # JR NC,o + TDAT8 = !(F & CF); + call jr_cond + +0031 # LD SP,w + call arg16 + SP = TDAT; + +0032 # LD (w),A + call arg16 + m_ea = TDAT; TDAT8 = A; + call wm m_ea + WZ_L = (m_ea + 1) & 0xFF; WZ_H = A; + +0033 # INC SP + call nomreq_ir 2 + SP++; + +0034 # INC (HL) + call rm_reg HL + inc(TDAT8); + call wm HL + +0035 # DEC (HL) + call rm_reg HL + dec(TDAT8); + call wm HL + +0036 # LD (HL),n + call arg + call wm HL + +0037 # SCF + set_f((F & (SF | ZF | PF)) | CF | (((F & Q) | A) & (YF | XF))); + +0038 # JR C,o + TDAT8 = F & CF; + call jr_cond + +0039 # ADD HL,SP + TDAT = HL; TDAT2 = SP; + call add16 + HL = TDAT; + +003a # LD A,(w) + call arg16 + m_ea = TDAT; + call rm m_ea + A = TDAT8; WZ = m_ea + 1; + +003b # DEC SP + call nomreq_ir 2 + SP--; + +003c # INC A + inc(A); + +003d # DEC A + dec(A); + +003e # LD A,n + call arg + A = TDAT8; + +003f # CCF + set_f(((F & (SF | ZF | PF | CF)) ^ CF) | ((F & CF) << 4) | (((F & Q) | A) & (YF | XF))); + +0040 # LD B,B + +0041 # LD B,C + B = C; + +0042 # LD B,D + B = D; + +0043 # LD B,E + B = E; + +0044 # LD B,H + B = H; + +0045 # LD B,L + B = L; + +0046 # LD B,(HL) + call rm HL + B = TDAT8; + +0047 # LD B,A + B = A; + +0048 # LD C,B + C = B; + +0049 # LD C,C + +004a # LD C,D + C = D; + +004b # LD C,E + C = E; + +004c # LD C,H + C = H; + +004d # LD C,L + C = L; + +004e # LD C,(HL) + call rm HL + C = TDAT8; + +004f # LD C,A + C = A; + +0050 # LD D,B + D = B; + +0051 # LD D,C + D = C; + +0052 # LD D,D + +0053 # LD D,E + D = E; + +0054 # LD D,H + D = H; + +0055 # LD D,L + D = L; + +0056 # LD D,(HL) + call rm HL + D = TDAT8; + +0057 # LD D,A + D = A; + +0058 # LD E,B + E = B; + +0059 # LD E,C + E = C; + +005a # LD E,D + E = D; + +005b # LD E,E + +005c # LD E,H + E = H; + +005d # LD E,L + E = L; + +005e # LD E,(HL) + call rm HL + E = TDAT8; + +005f # LD E,A + E = A; + +0060 # LD H,B + H = B; + +0061 # LD H,C + H = C; + +0062 # LD H,D + H = D; + +0063 # LD H,E + H = E; + +0064 # LD H,H + +0065 # LD H,L + H = L; + +0066 # LD H,(HL) + call rm HL + H = TDAT8; + +0067 # LD H,A + H = A; + +0068 # LD L,B + L = B; + +0069 # LD L,C + L = C; + +006a # LD L,D + L = D; + +006b # LD L,E + L = E; + +006c # LD L,H + L = H; + +006d # LD L,L + +006e # LD L,(HL) + call rm HL + L = TDAT8; + +006f # LD L,A + L = A; + +0070 # LD (HL),B + TDAT = B; + call wm HL + +0071 # LD (HL),C + TDAT = C; + call wm HL + +0072 # LD (HL),D + TDAT = D; + call wm HL + +0073 # LD (HL),E + TDAT = E; + call wm HL + +0074 # LD (HL),H + TDAT = H; + call wm HL + +0075 # LD (HL),L + TDAT = L; + call wm HL + +0076 # HALT + halt(); + +0077 # LD (HL),A + TDAT = A; + call wm HL + +0078 # LD A,B + A = B; + +0079 # LD A,C + A = C; + +007a # LD A,D + A = D; + +007b # LD A,E + A = E; + +007c # LD A,H + A = H; + +007d # LD A,L + A = L; + +007e # LD A,(HL) + call rm HL + A = TDAT8; + +007f # LD A,A + +0080 # ADD A,B + add_a(B); + +0081 # ADD A,C + add_a(C); + +0082 # ADD A,D + add_a(D); + +0083 # ADD A,E + add_a(E); + +0084 # ADD A,H + add_a(H); + +0085 # ADD A,L + add_a(L); + +0086 # ADD A,(HL) + call rm HL + add_a(TDAT8); + +0087 # ADD A,A + add_a(A); + +0088 # ADC A,B + adc_a(B); + +0089 # ADC A,C + adc_a(C); + +008a # ADC A,D + adc_a(D); + +008b # ADC A,E + adc_a(E); + +008c # ADC A,H + adc_a(H); + +008d # ADC A,L + adc_a(L); + +008e # ADC A,(HL) + call rm HL + adc_a(TDAT8); + +008f # ADC A,A + adc_a(A); + +0090 # SUB B + sub_a(B); + +0091 # SUB C + sub_a(C); + +0092 # SUB D + sub_a(D); + +0093 # SUB E + sub_a(E); + +0094 # SUB H + sub_a(H); + +0095 # SUB L + sub_a(L); + +0096 # SUB (HL) + call rm HL + sub_a(TDAT8); + +0097 # SUB A + sub_a(A); + +0098 # SBC A,B + sbc_a(B); + +0099 # SBC A,C + sbc_a(C); + +009a # SBC A,D + sbc_a(D); + +009b # SBC A,E + sbc_a(E); + +009c # SBC A,H + sbc_a(H); + +009d # SBC A,L + sbc_a(L); + +009e # SBC A,(HL) + call rm HL + sbc_a(TDAT8); + +009f # SBC A,A + sbc_a(A); + +00a0 # AND B + and_a(B); + +00a1 # AND C + and_a(C); + +00a2 # AND D + and_a(D); + +00a3 # AND E + and_a(E); + +00a4 # AND H + and_a(H); + +00a5 # AND L + and_a(L); + +00a6 # AND (HL) + call rm HL + and_a(TDAT8); + +00a7 # AND A + and_a(A); + +00a8 # XOR B + xor_a(B); + +00a9 # XOR C + xor_a(C); + +00aa # XOR D + xor_a(D); + +00ab # XOR E + xor_a(E); + +00ac # XOR H + xor_a(H); + +00ad # XOR L + xor_a(L); + +00ae # XOR (HL) + call rm HL + xor_a(TDAT8); + +00af # XOR A + xor_a(A); + +00b0 # OR B + or_a(B); + +00b1 # OR C + or_a(C); + +00b2 # OR D + or_a(D); + +00b3 # OR E + or_a(E); + +00b4 # OR H + or_a(H); + +00b5 # OR L + or_a(L); + +00b6 # OR (HL) + call rm HL + or_a(TDAT8); + +00b7 # OR A + or_a(A); + +00b8 # CP B + cp(B); + +00b9 # CP C + cp(C); + +00ba # CP D + cp(D); + +00bb # CP E + cp(E); + +00bc # CP H + cp(H); + +00bd # CP L + cp(L); + +00be # CP (HL) + call rm HL + cp(TDAT8); + +00bf # CP A + cp(A); + +00c0 # RET NZ + TDAT8 = !(F & ZF); + call ret_cond + +00c1 # POP BC + call pop + BC = TDAT; + +00c2 # JP NZ,a + TDAT8 = !(F & ZF); + call jp_cond + +00c3 # JP a + call jp + +00c4 # CALL NZ,a + TDAT8 = !(F & ZF); + call call_cond + +00c5 # PUSH BC + call push BC + +00c6 # ADD A,n + call arg + add_a(TDAT8); + +00c7 # RST 0 + call rst 0x00 + +00c8 # RET Z + TDAT8 = (F & ZF); + call ret_cond + +00c9 # RET + call pop + PC = TDAT; WZ = PC; + +00ca # JP Z,a + TDAT8 = F & ZF; + call jp_cond + +00cb # **** CB xx + call rop + call jump_prefixed 0xcb + +00cc # CALL Z,a + TDAT8 = F & ZF; + call call_cond + +00cd # CALL a + call arg16_call + +00ce # ADC A,n + call arg + adc_a(TDAT8); + +00cf # RST 1 + call rst 0x08 + +00d0 # RET NC + TDAT8 = !(F & CF); + call ret_cond + +00d1 # POP DE + call pop + DE = TDAT; + +00d2 # JP NC,a + TDAT8 = !(F & CF); + call jp_cond + +00d3 # OUT (n),A + call arg + TDAT2 = TDAT8 | (A << 8); + TDAT = A; + call out TDAT2 + WZ_L = ((TDAT2 & 0xff) + 1) & 0xff; WZ_H = A; + +00d4 # CALL NC,a + TDAT8 = !(F & CF); + call call_cond + +00d5 # PUSH DE + call push DE + +00d6 # SUB n + call arg + sub_a(TDAT8); + +00d7 # RST 2 + call rst 0x10 + +00d8 # RET C + TDAT8 = (F & CF); + call ret_cond + +00d9 # EXX + exx(); + +00da # JP C,a + TDAT8 = F & CF; + call jp_cond + +00db # IN A,(n) + call arg + TDAT2 = TDAT8 | (A << 8); + call in TDAT2 + A = TDAT8; WZ = TDAT2 + 1; + +00dc # CALL C,a + TDAT8 = F & CF; + call call_cond + +00dd # **** DD xx + call rop + call jump_prefixed 0xdd + +00de # SBC A,n + call arg + sbc_a(TDAT8); + +00df # RST 3 + call rst 0x18 + +00e0 # RET PO + TDAT8 = !(F & PF); + call ret_cond + +00e1 # POP HL + call pop + HL = TDAT; + +00e2 # JP PO,a + TDAT8 = !(F & PF); + call jp_cond + +00e3 # EX HL,(SP) + call ex_sp HL + +00e4 # CALL PO,a + TDAT8 = !(F & PF); + call call_cond + +00e5 # PUSH HL + call push HL + +00e6 # AND n + call arg + and_a(TDAT8); + +00e7 # RST 4 + call rst 0x20 + +00e8 # RET PE + TDAT8 = (F & PF); + call ret_cond + +00e9 # JP (HL) + PC = HL; + +00ea # JP PE,a + TDAT8 = F & PF; + call jp_cond + +00eb # EX DE,HL + using std::swap; swap(DE, HL); + +00ec # CALL PE,a + TDAT8 = F & PF; + call call_cond + +00ed # **** ED xx + call rop + call jump_prefixed 0xed + +00ee # XOR n + call arg + xor_a(TDAT8); + +00ef # RST 5 + call rst 0x28 + +00f0 # RET P + TDAT8 = !(F & SF); + call ret_cond + +00f1 # POP AF + call pop + AF = TDAT; + +00f2 # JP P,a + TDAT8 = !(F & SF); + call jp_cond + +00f3 # DI + m_iff1 = m_iff2 = 0; + +00f4 # CALL P,a + TDAT8 = !(F & SF); + call call_cond + +00f5 # PUSH AF + call push AF + +00f6 # OR n + call arg + or_a(TDAT8); + +00f7 # RST 6 + call rst 0x30 + +00f8 # RET M + TDAT8 = (F & SF); + call ret_cond + +00f9 # LD SP,HL + call nomreq_ir 2 + SP = HL; + +00fa # JP M,a + TDAT8 = F & SF; + call jp_cond + +00fb # EI + ei(); + +00fc # CALL M,a + TDAT8 = F & SF; + call call_cond + +00fd # **** FD xx + call rop + call jump_prefixed 0xfd + +00fe # CP n + call arg + cp(TDAT8); + +00ff # RST 7 + call rst 0x38 + + + +########################################################## +# R800 +########################################################## + +r800:fe00 # illegal + illegal_1(); + +r800:fe01 # illegal + illegal_1(); + +r800:fe02 # illegal + illegal_1(); + +r800:fe03 # illegal + illegal_1(); + +r800:fe04 # illegal + illegal_1(); + +r800:fe05 # illegal + illegal_1(); + +r800:fe07 # illegal + illegal_1(); + +r800:fe08 # illegal + illegal_1(); + +r800:fe09 # illegal + illegal_1(); + +r800:fe0a # illegal + illegal_1(); + +r800:fe0b # illegal + illegal_1(); + +r800:fe0c # illegal + illegal_1(); + +r800:fe0d # illegal + illegal_1(); + +r800:fe0f # illegal + illegal_1(); + +r800:fe10 # illegal + illegal_1(); + +r800:fe11 # illegal + illegal_1(); + +r800:fe12 # illegal + illegal_1(); + +r800:fe13 # illegal + illegal_1(); + +r800:fe14 # illegal + illegal_1(); + +r800:fe15 # illegal + illegal_1(); + +r800:fe17 # illegal + illegal_1(); + +r800:fe18 # illegal + illegal_1(); + +r800:fe19 # illegal + illegal_1(); + +r800:fe1a # illegal + illegal_1(); + +r800:fe1b # illegal + illegal_1(); + +r800:fe1c # illegal + illegal_1(); + +r800:fe1d # illegal + illegal_1(); + +r800:fe1f # illegal + illegal_1(); + +r800:fe20 # illegal + illegal_1(); + +r800:fe21 # illegal + illegal_1(); + +r800:fe22 # illegal + illegal_1(); + +r800:fe23 # illegal + illegal_1(); + +r800:fe24 # illegal + illegal_1(); + +r800:fe25 # illegal + illegal_1(); + +r800:fe27 # illegal + illegal_1(); + +r800:fe28 # illegal + illegal_1(); + +r800:fe29 # illegal + illegal_1(); + +r800:fe2a # illegal + illegal_1(); + +r800:fe2b # illegal + illegal_1(); + +r800:fe2c # illegal + illegal_1(); + +r800:fe2d # illegal + illegal_1(); + +r800:fe2f # illegal + illegal_1(); + +r800:fe30 # illegal + illegal_1(); + +r800:fe31 # illegal + illegal_1(); + +r800:fe32 # illegal + illegal_1(); + +r800:fe33 # illegal + illegal_1(); + +r800:fe34 # illegal + illegal_1(); + +r800:fe35 # illegal + illegal_1(); + +r800:fe37 # illegal + illegal_1(); + +r800:fe38 # illegal + illegal_1(); + +r800:fe39 # illegal + illegal_1(); + +r800:fe3a # illegal + illegal_1(); + +r800:fe3b # illegal + illegal_1(); + +r800:fe3c # illegal + illegal_1(); + +r800:fe3d # illegal + illegal_1(); + +r800:fe3f # illegal + illegal_1(); + +r800:fe40 # illegal + illegal_1(); + +r800:fe41 # illegal + illegal_1(); + +r800:fe42 # illegal + illegal_1(); + +r800:fe43 # illegal + illegal_1(); + +r800:fe44 # illegal + illegal_1(); + +r800:fe45 # illegal + illegal_1(); + +r800:fe47 # illegal + illegal_1(); + +r800:fe48 # illegal + illegal_1(); + +r800:fe49 # illegal + illegal_1(); + +r800:fe4a # illegal + illegal_1(); + +r800:fe4b # illegal + illegal_1(); + +r800:fe4c # illegal + illegal_1(); + +r800:fe4d # illegal + illegal_1(); + +r800:fe4f # illegal + illegal_1(); + +r800:fe50 # illegal + illegal_1(); + +r800:fe51 # illegal + illegal_1(); + +r800:fe52 # illegal + illegal_1(); + +r800:fe53 # illegal + illegal_1(); + +r800:fe54 # illegal + illegal_1(); + +r800:fe55 # illegal + illegal_1(); + +r800:fe57 # illegal + illegal_1(); + +r800:fe58 # illegal + illegal_1(); + +r800:fe59 # illegal + illegal_1(); + +r800:fe5a # illegal + illegal_1(); + +r800:fe5b # illegal + illegal_1(); + +r800:fe5c # illegal + illegal_1(); + +r800:fe5d # illegal + illegal_1(); + +r800:fe5f # illegal + illegal_1(); + +r800:fe60 # illegal + illegal_1(); + +r800:fe61 # illegal + illegal_1(); + +r800:fe62 # illegal + illegal_1(); + +r800:fe63 # illegal + illegal_1(); + +r800:fe64 # illegal + illegal_1(); + +r800:fe65 # illegal + illegal_1(); + +r800:fe67 # illegal + illegal_1(); + +r800:fe68 # illegal + illegal_1(); + +r800:fe69 # illegal + illegal_1(); + +r800:fe6a # illegal + illegal_1(); + +r800:fe6b # illegal + illegal_1(); + +r800:fe6c # illegal + illegal_1(); + +r800:fe6d # illegal + illegal_1(); + +r800:fe6f # illegal + illegal_1(); + +r800:fe70 # illegal + illegal_1(); + +r800:fe71 # illegal + illegal_1(); + +r800:fe72 # illegal + illegal_1(); + +r800:fe73 # illegal + illegal_1(); + +r800:fe74 # illegal + illegal_1(); + +r800:fe75 # illegal + illegal_1(); + +r800:fe77 # illegal + illegal_1(); + +r800:fe78 # illegal + illegal_1(); + +r800:fe79 # illegal + illegal_1(); + +r800:fe7a # illegal + illegal_1(); + +r800:fe7b # illegal + illegal_1(); + +r800:fe7c # illegal + illegal_1(); + +r800:fe7d # illegal + illegal_1(); + +r800:fe7f # illegal + illegal_1(); + +r800:fe80 # illegal + illegal_1(); + +r800:fe81 # illegal + illegal_1(); + +r800:fe82 # illegal + illegal_1(); + +r800:fe83 # illegal + illegal_1(); + +r800:fe84 # illegal + illegal_1(); + +r800:fe85 # illegal + illegal_1(); + +r800:fe87 # illegal + illegal_1(); + +r800:fe88 # illegal + illegal_1(); + +r800:fe89 # illegal + illegal_1(); + +r800:fe8a # illegal + illegal_1(); + +r800:fe8b # illegal + illegal_1(); + +r800:fe8c # illegal + illegal_1(); + +r800:fe8d # illegal + illegal_1(); + +r800:fe8f # illegal + illegal_1(); + +r800:fe90 # illegal + illegal_1(); + +r800:fe91 # illegal + illegal_1(); + +r800:fe92 # illegal + illegal_1(); + +r800:fe93 # illegal + illegal_1(); + +r800:fe94 # illegal + illegal_1(); + +r800:fe95 # illegal + illegal_1(); + +r800:fe97 # illegal + illegal_1(); + +r800:fe98 # illegal + illegal_1(); + +r800:fe99 # illegal + illegal_1(); + +r800:fe9a # illegal + illegal_1(); + +r800:fe9b # illegal + illegal_1(); + +r800:fe9c # illegal + illegal_1(); + +r800:fe9d # illegal + illegal_1(); + +r800:fe9f # illegal + illegal_1(); + +r800:fea0 # illegal + illegal_1(); + +r800:fea1 # illegal + illegal_1(); + +r800:fea2 # illegal + illegal_1(); + +r800:fea3 # illegal + illegal_1(); + +r800:fea4 # illegal + illegal_1(); + +r800:fea5 # illegal + illegal_1(); + +r800:fea7 # illegal + illegal_1(); + +r800:fea8 # illegal + illegal_1(); + +r800:fea9 # illegal + illegal_1(); + +r800:feaa # illegal + illegal_1(); + +r800:feab # illegal + illegal_1(); + +r800:feac # illegal + illegal_1(); + +r800:fead # illegal + illegal_1(); + +r800:feaf # illegal + illegal_1(); + +r800:feb0 # illegal + illegal_1(); + +r800:feb1 # illegal + illegal_1(); + +r800:feb2 # illegal + illegal_1(); + +r800:feb3 # illegal + illegal_1(); + +r800:feb4 # illegal + illegal_1(); + +r800:feb5 # illegal + illegal_1(); + +r800:feb7 # illegal + illegal_1(); + +r800:feb8 # illegal + illegal_1(); + +r800:feb9 # illegal + illegal_1(); + +r800:feba # illegal + illegal_1(); + +r800:febb # illegal + illegal_1(); + +r800:febc # illegal + illegal_1(); + +r800:febd # illegal + illegal_1(); + +r800:febf # illegal + illegal_1(); + +r800:fec0 # illegal + illegal_1(); + +r800:fec1 # illegal + illegal_1(); + +r800:fec2 # illegal + illegal_1(); + +r800:fec3 # illegal + illegal_1(); + +r800:fec4 # illegal + illegal_1(); + +r800:fec5 # illegal + illegal_1(); + +r800:fec7 # illegal + illegal_1(); + +r800:fec8 # illegal + illegal_1(); + +r800:fec9 # illegal + illegal_1(); + +r800:feca # illegal + illegal_1(); + +r800:fecb # illegal + illegal_1(); + +r800:fecc # illegal + illegal_1(); + +r800:fecd # illegal + illegal_1(); + +r800:fecf # illegal + illegal_1(); + +r800:fed0 # illegal + illegal_1(); + +r800:fed1 # illegal + illegal_1(); + +r800:fed2 # illegal + illegal_1(); + +r800:fed3 # illegal + illegal_1(); + +r800:fed4 # illegal + illegal_1(); + +r800:fed5 # illegal + illegal_1(); + +r800:fed7 # illegal + illegal_1(); + +r800:fed8 # illegal + illegal_1(); + +r800:fed9 # illegal + illegal_1(); + +r800:feda # illegal + illegal_1(); + +r800:fedb # illegal + illegal_1(); + +r800:fedc # illegal + illegal_1(); + +r800:fedd # illegal + illegal_1(); + +r800:fedf # illegal + illegal_1(); + +r800:fee0 # illegal + illegal_1(); + +r800:fee1 # illegal + illegal_1(); + +r800:fee2 # illegal + illegal_1(); + +r800:fee3 # illegal + illegal_1(); + +r800:fee4 # illegal + illegal_1(); + +r800:fee5 # illegal + illegal_1(); + +r800:fee7 # illegal + illegal_1(); + +r800:fee8 # illegal + illegal_1(); + +r800:fee9 # illegal + illegal_1(); + +r800:feea # illegal + illegal_1(); + +r800:feeb # illegal + illegal_1(); + +r800:feec # illegal + illegal_1(); + +r800:feed # illegal + illegal_1(); + +r800:feef # illegal + illegal_1(); + +r800:fef0 # illegal + illegal_1(); + +r800:fef1 # illegal + illegal_1(); + +r800:fef2 # illegal + illegal_1(); + +r800:fef3 # illegal + illegal_1(); + +r800:fef4 # illegal + illegal_1(); + +r800:fef5 # illegal + illegal_1(); + +r800:fef7 # illegal + illegal_1(); + +r800:fef8 # illegal + illegal_1(); + +r800:fef9 # illegal + illegal_1(); + +r800:fefa # illegal + illegal_1(); + +r800:fefb # illegal + illegal_1(); + +r800:fefc # illegal + illegal_1(); + +r800:fefd # illegal + illegal_1(); + +r800:feff # illegal + illegal_1(); + +r800:cb30 # SLL B + B = r800_sll(B); + +r800:cb31 # SLL C + C = r800_sll(C); + +r800:cb32 # SLL D + D = r800_sll(D); + +r800:cb33 # SLL E + E = r800_sll(E); + +r800:cb34 # SLL H + H = r800_sll(H); + +r800:cb35 # SLL L + L = r800_sll(L); + +r800:cb36 # SLL (HL) + call rm_reg HL + TDAT8 = r800_sll(TDAT8); + call wm HL + +r800:cb37 # SLL A + A = r800_sll(A); + +r800:dd00 # illegal + illegal_1(); + +r800:dd01 # illegal + illegal_1(); + +r800:dd02 # illegal + illegal_1(); + +r800:dd03 # illegal + illegal_1(); + +r800:dd04 # illegal + illegal_1(); + +r800:dd05 # illegal + illegal_1(); + +r800:dd06 # illegal + illegal_1(); + +r800:dd07 # illegal + illegal_1(); + +r800:dd08 # illegal + illegal_1(); + +r800:dd0a # illegal + illegal_1(); + +r800:dd0b # illegal + illegal_1(); + +r800:dd0c # illegal + illegal_1(); + +r800:dd0d # illegal + illegal_1(); + +r800:dd0e # illegal + illegal_1(); + +r800:dd0f # illegal + illegal_1(); + +r800:dd10 # illegal + illegal_1(); + +r800:dd11 # illegal + illegal_1(); + +r800:dd12 # illegal + illegal_1(); + +r800:dd13 # illegal + illegal_1(); + +r800:dd14 # illegal + illegal_1(); + +r800:dd15 # illegal + illegal_1(); + +r800:dd16 # illegal + illegal_1(); + +r800:dd17 # illegal + illegal_1(); + +r800:dd18 # illegal + illegal_1(); + +r800:dd1a # illegal + illegal_1(); + +r800:dd1b # illegal + illegal_1(); + +r800:dd1c # illegal + illegal_1(); + +r800:dd1d # illegal + illegal_1(); + +r800:dd1e # illegal + illegal_1(); + +r800:dd1f # illegal + illegal_1(); + +r800:dd20 # illegal + illegal_1(); + +r800:dd27 # illegal + illegal_1(); + +r800:dd28 # illegal + illegal_1(); + +r800:dd2f # illegal + illegal_1(); + +r800:dd30 # illegal + illegal_1(); + +r800:dd31 # illegal + illegal_1(); + +r800:dd32 # illegal + illegal_1(); + +r800:dd33 # illegal + illegal_1(); + +r800:dd37 # illegal + illegal_1(); + +r800:dd38 # illegal + illegal_1(); + +r800:dd3a # illegal + illegal_1(); + +r800:dd3b # illegal + illegal_1(); + +r800:dd3c # illegal + illegal_1(); + +r800:dd3d # illegal + illegal_1(); + +r800:dd3e # illegal + illegal_1(); + +r800:dd3f # illegal + illegal_1(); + +r800:dd40 # illegal + illegal_1(); + +r800:dd41 # illegal + illegal_1(); + +r800:dd42 # illegal + illegal_1(); + +r800:dd43 # illegal + illegal_1(); + +r800:dd47 # illegal + illegal_1(); + +r800:dd48 # illegal + illegal_1(); + +r800:dd49 # illegal + illegal_1(); + +r800:dd4a # illegal + illegal_1(); + +r800:dd4b # illegal + illegal_1(); + +r800:dd4f # illegal + illegal_1(); + +r800:dd50 # illegal + illegal_1(); + +r800:dd51 # illegal + illegal_1(); + +r800:dd52 # illegal + illegal_1(); + +r800:dd53 # illegal + illegal_1(); + +r800:dd57 # illegal + illegal_1(); + +r800:dd58 # illegal + illegal_1(); + +r800:dd59 # illegal + illegal_1(); + +r800:dd5a # illegal + illegal_1(); + +r800:dd5b # illegal + illegal_1(); + +r800:dd5f # illegal + illegal_1(); + +r800:dd76 # illegal + illegal_1(); + +r800:dd78 # illegal + illegal_1(); + +r800:dd79 # illegal + illegal_1(); + +r800:dd7a # illegal + illegal_1(); + +r800:dd7b # illegal + illegal_1(); + +r800:dd7f # illegal + illegal_1(); + +r800:dd80 # illegal + illegal_1(); + +r800:dd81 # illegal + illegal_1(); + +r800:dd82 # illegal + illegal_1(); + +r800:dd83 # illegal + illegal_1(); + +r800:dd87 # illegal + illegal_1(); + +r800:dd88 # illegal + illegal_1(); + +r800:dd89 # illegal + illegal_1(); + +r800:dd8a # illegal + illegal_1(); + +r800:dd8b # illegal + illegal_1(); + +r800:dd8f # illegal + illegal_1(); + +r800:dd90 # illegal + illegal_1(); + +r800:dd91 # illegal + illegal_1(); + +r800:dd92 # illegal + illegal_1(); + +r800:dd93 # illegal + illegal_1(); + +r800:dd97 # illegal + illegal_1(); + +r800:dd98 # illegal + illegal_1(); + +r800:dd99 # illegal + illegal_1(); + +r800:dd9a # illegal + illegal_1(); + +r800:dd9b # illegal + illegal_1(); + +r800:dd9f # illegal + illegal_1(); + +r800:dda0 # illegal + illegal_1(); + +r800:dda1 # illegal + illegal_1(); + +r800:dda2 # illegal + illegal_1(); + +r800:dda3 # illegal + illegal_1(); + +r800:dda7 # illegal + illegal_1(); + +r800:dda8 # illegal + illegal_1(); + +r800:dda9 # illegal + illegal_1(); + +r800:ddaa # illegal + illegal_1(); + +r800:ddab # illegal + illegal_1(); + +r800:ddaf # illegal + illegal_1(); + +r800:ddb0 # illegal + illegal_1(); + +r800:ddb1 # illegal + illegal_1(); + +r800:ddb2 # illegal + illegal_1(); + +r800:ddb3 # illegal + illegal_1(); + +r800:ddb7 # illegal + illegal_1(); + +r800:ddb8 # illegal + illegal_1(); + +r800:ddb9 # illegal + illegal_1(); + +r800:ddba # illegal + illegal_1(); + +r800:ddbb # illegal + illegal_1(); + +r800:ddbf # illegal + illegal_1(); + +r800:ddc0 # illegal + illegal_1(); + +r800:ddc1 # illegal + illegal_1(); + +r800:ddc2 # illegal + illegal_1(); + +r800:ddc3 # illegal + illegal_1(); + +r800:ddc4 # illegal + illegal_1(); + +r800:ddc5 # illegal + illegal_1(); + +r800:ddc6 # illegal + illegal_1(); + +r800:ddc7 # illegal + illegal_1(); + +r800:ddc8 # illegal + illegal_1(); + +r800:ddc9 # illegal + illegal_1(); + +r800:ddca # illegal + illegal_1(); + +r800:ddcc # illegal + illegal_1(); + +r800:ddcd # illegal + illegal_1(); + +r800:ddce # illegal + illegal_1(); + +r800:ddcf # illegal + illegal_1(); + +r800:ddd0 # illegal + illegal_1(); + +r800:ddd1 # illegal + illegal_1(); + +r800:ddd2 # illegal + illegal_1(); + +r800:ddd3 # illegal + illegal_1(); + +r800:ddd4 # illegal + illegal_1(); + +r800:ddd5 # illegal + illegal_1(); + +r800:ddd6 # illegal + illegal_1(); + +r800:ddd7 # illegal + illegal_1(); + +r800:ddd8 # illegal + illegal_1(); + +r800:ddd9 # illegal + illegal_1(); + +r800:ddda # illegal + illegal_1(); + +r800:dddb # illegal + illegal_1(); + +r800:dddc # illegal + illegal_1(); + +r800:dddd # illegal + illegal_1(); + +r800:ddde # illegal + illegal_1(); + +r800:dddf # illegal + illegal_1(); + +r800:dde0 # illegal + illegal_1(); + +r800:dde2 # illegal + illegal_1(); + +r800:dde4 # illegal + illegal_1(); + +r800:dde6 # illegal + illegal_1(); + +r800:dde7 # illegal + illegal_1(); + +r800:dde8 # illegal + illegal_1(); + +r800:ddea # illegal + illegal_1(); + +r800:ddeb # illegal + illegal_1(); + +r800:ddec # illegal + illegal_1(); + +r800:dded # illegal + illegal_1(); + +r800:ddee # illegal + illegal_1(); + +r800:ddef # illegal + illegal_1(); + +r800:ddf0 # illegal + illegal_1(); + +r800:ddf1 # illegal + illegal_1(); + +r800:ddf2 # illegal + illegal_1(); + +r800:ddf3 # illegal + illegal_1(); + +r800:ddf4 # illegal + illegal_1(); + +r800:ddf5 # illegal + illegal_1(); + +r800:ddf6 # illegal + illegal_1(); + +r800:ddf7 # illegal + illegal_1(); + +r800:ddf8 # illegal + illegal_1(); + +r800:ddfa # illegal + illegal_1(); + +r800:ddfb # illegal + illegal_1(); + +r800:ddfc # illegal + illegal_1(); + +r800:ddfd # illegal + illegal_1(); + +r800:ddfe # illegal + illegal_1(); + +r800:ddff # illegal + illegal_1(); + +r800:fd00 # illegal + illegal_1(); + +r800:fd01 # illegal + illegal_1(); + +r800:fd02 # illegal + illegal_1(); + +r800:fd03 # illegal + illegal_1(); + +r800:fd04 # illegal + illegal_1(); + +r800:fd05 # illegal + illegal_1(); + +r800:fd06 # illegal + illegal_1(); + +r800:fd07 # illegal + illegal_1(); + +r800:fd08 # illegal + illegal_1(); + +r800:fd0a # illegal + illegal_1(); + +r800:fd0b # illegal + illegal_1(); + +r800:fd0c # illegal + illegal_1(); + +r800:fd0d # illegal + illegal_1(); + +r800:fd0e # illegal + illegal_1(); + +r800:fd0f # illegal + illegal_1(); + +r800:fd10 # illegal + illegal_1(); + +r800:fd11 # illegal + illegal_1(); + +r800:fd12 # illegal + illegal_1(); + +r800:fd13 # illegal + illegal_1(); + +r800:fd14 # illegal + illegal_1(); + +r800:fd15 # illegal + illegal_1(); + +r800:fd16 # illegal + illegal_1(); + +r800:fd17 # illegal + illegal_1(); + +r800:fd18 # illegal + illegal_1(); + +r800:fd1a # illegal + illegal_1(); + +r800:fd1b # illegal + illegal_1(); + +r800:fd1c # illegal + illegal_1(); + +r800:fd1d # illegal + illegal_1(); + +r800:fd1e # illegal + illegal_1(); + +r800:fd1f # illegal + illegal_1(); + +r800:fd20 # illegal + illegal_1(); + +r800:fd27 # illegal + illegal_1(); + +r800:fd28 # illegal + illegal_1(); + +r800:fd2f # illegal + illegal_1(); + +r800:fd30 # illegal + illegal_1(); + +r800:fd31 # illegal + illegal_1(); + +r800:fd32 # illegal + illegal_1(); + +r800:fd33 # illegal + illegal_1(); + +r800:fd37 # illegal + illegal_1(); + +r800:fd38 # illegal + illegal_1(); + +r800:fd3a # illegal + illegal_1(); + +r800:fd3b # illegal + illegal_1(); + +r800:fd3c # illegal + illegal_1(); + +r800:fd3d # illegal + illegal_1(); + +r800:fd3e # illegal + illegal_1(); + +r800:fd3f # illegal + illegal_1(); + +r800:fd40 # illegal + illegal_1(); + +r800:fd41 # illegal + illegal_1(); + +r800:fd42 # illegal + illegal_1(); + +r800:fd43 # illegal + illegal_1(); + +r800:fd47 # illegal + illegal_1(); + +r800:fd48 # illegal + illegal_1(); + +r800:fd49 # illegal + illegal_1(); + +r800:fd4a # illegal + illegal_1(); + +r800:fd4b # illegal + illegal_1(); + +r800:fd4f # illegal + illegal_1(); + +r800:fd50 # illegal + illegal_1(); + +r800:fd51 # illegal + illegal_1(); + +r800:fd52 # illegal + illegal_1(); + +r800:fd53 # illegal + illegal_1(); + +r800:fd57 # illegal + illegal_1(); + +r800:fd58 # illegal + illegal_1(); + +r800:fd59 # illegal + illegal_1(); + +r800:fd5a # illegal + illegal_1(); + +r800:fd5b # illegal + illegal_1(); + +r800:fd5f # illegal + illegal_1(); + +r800:fd76 # illegal + illegal_1(); + +r800:fd78 # illegal + illegal_1(); + +r800:fd79 # illegal + illegal_1(); + +r800:fd7a # illegal + illegal_1(); + +r800:fd7b # illegal + illegal_1(); + +r800:fd7f # illegal + illegal_1(); + +r800:fd80 # illegal + illegal_1(); + +r800:fd81 # illegal + illegal_1(); + +r800:fd82 # illegal + illegal_1(); + +r800:fd83 # illegal + illegal_1(); + +r800:fd87 # illegal + illegal_1(); + +r800:fd88 # illegal + illegal_1(); + +r800:fd89 # illegal + illegal_1(); + +r800:fd8a # illegal + illegal_1(); + +r800:fd8b # illegal + illegal_1(); + +r800:fd8f # illegal + illegal_1(); + +r800:fd90 # illegal + illegal_1(); + +r800:fd91 # illegal + illegal_1(); + +r800:fd92 # illegal + illegal_1(); + +r800:fd93 # illegal + illegal_1(); + +r800:fd97 # illegal + illegal_1(); + +r800:fd98 # illegal + illegal_1(); + +r800:fd99 # illegal + illegal_1(); + +r800:fd9a # illegal + illegal_1(); + +r800:fd9b # illegal + illegal_1(); + +r800:fd9f # illegal + illegal_1(); + +r800:fda0 # illegal + illegal_1(); + +r800:fda1 # illegal + illegal_1(); + +r800:fda2 # illegal + illegal_1(); + +r800:fda3 # illegal + illegal_1(); + +r800:fda7 # illegal + illegal_1(); + +r800:fda8 # illegal + illegal_1(); + +r800:fda9 # illegal + illegal_1(); + +r800:fdaa # illegal + illegal_1(); + +r800:fdab # illegal + illegal_1(); + +r800:fdaf # illegal + illegal_1(); + +r800:fdb0 # illegal + illegal_1(); + +r800:fdb1 # illegal + illegal_1(); + +r800:fdb2 # illegal + illegal_1(); + +r800:fdb3 # illegal + illegal_1(); + +r800:fdb7 # illegal + illegal_1(); + +r800:fdb8 # illegal + illegal_1(); + +r800:fdb9 # illegal + illegal_1(); + +r800:fdba # illegal + illegal_1(); + +r800:fdbb # illegal + illegal_1(); + +r800:fdbf # illegal + illegal_1(); + +r800:fdc0 # illegal + illegal_1(); + +r800:fdc1 # illegal + illegal_1(); + +r800:fdc2 # illegal + illegal_1(); + +r800:fdc3 # illegal + illegal_1(); + +r800:fdc4 # illegal + illegal_1(); + +r800:fdc5 # illegal + illegal_1(); + +r800:fdc6 # illegal + illegal_1(); + +r800:fdc7 # illegal + illegal_1(); + +r800:fdc8 # illegal + illegal_1(); + +r800:fdc9 # illegal + illegal_1(); + +r800:fdca # illegal + illegal_1(); + +r800:fdcc # illegal + illegal_1(); + +r800:fdcd # illegal + illegal_1(); + +r800:fdce # illegal + illegal_1(); + +r800:fdcf # illegal + illegal_1(); + +r800:fdd0 # illegal + illegal_1(); + +r800:fdd1 # illegal + illegal_1(); + +r800:fdd2 # illegal + illegal_1(); + +r800:fdd3 # illegal + illegal_1(); + +r800:fdd4 # illegal + illegal_1(); + +r800:fdd5 # illegal + illegal_1(); + +r800:fdd6 # illegal + illegal_1(); + +r800:fdd7 # illegal + illegal_1(); + +r800:fdd8 # illegal + illegal_1(); + +r800:fdd9 # illegal + illegal_1(); + +r800:fdda # illegal + illegal_1(); + +r800:fddb # illegal + illegal_1(); + +r800:fddc # illegal + illegal_1(); + +r800:fddd # illegal + illegal_1(); + +r800:fdde # illegal + illegal_1(); + +r800:fddf # illegal + illegal_1(); + +r800:fde0 # illegal + illegal_1(); + +r800:fde2 # illegal + illegal_1(); + +r800:fde4 # illegal + illegal_1(); + +r800:fde6 # illegal + illegal_1(); + +r800:fde7 # illegal + illegal_1(); + +r800:fde8 # illegal + illegal_1(); + +r800:fdea # illegal + illegal_1(); + +r800:fdeb # illegal + illegal_1(); + +r800:fdec # illegal + illegal_1(); + +r800:fded # illegal + illegal_1(); + +r800:fdee # illegal + illegal_1(); + +r800:fdef # illegal + illegal_1(); + +r800:fdf0 # illegal + illegal_1(); + +r800:fdf1 # illegal + illegal_1(); + +r800:fdf2 # illegal + illegal_1(); + +r800:fdf3 # illegal + illegal_1(); + +r800:fdf4 # illegal + illegal_1(); + +r800:fdf5 # illegal + illegal_1(); + +r800:fdf6 # illegal + illegal_1(); + +r800:fdf7 # illegal + illegal_1(); + +r800:fdf8 # illegal + illegal_1(); + +r800:fdfa # illegal + illegal_1(); + +r800:fdfb # illegal + illegal_1(); + +r800:fdfc # illegal + illegal_1(); + +r800:fdfd # illegal + illegal_1(); + +r800:fdfe # illegal + illegal_1(); + +r800:fdff # illegal + illegal_1(); + +r800:ed46 # IM 0 + m_im = 0; T(1); + +r800:ed4c # illegal + illegal_2(); + +r800:ed4e # illegal + illegal_2(); + +r800:ed54 # illegal + illegal_2(); + +r800:ed55 # illegal + illegal_2(); + +r800:ed56 # IM 1 + m_im = 1; T(1); + +r800:ed5c # illegal + illegal_2(); + +r800:ed5d # illegal + illegal_2(); + +r800:ed5e # IM 2 + m_im = 2; T(1); + +r800:ed64 # illegal + illegal_2(); + +r800:ed65 # illegal + illegal_2(); + +r800:ed66 # illegal + illegal_2(); + +r800:ed6c # illegal + illegal_2(); + +r800:ed6e # IM 0 + m_im = 0; T(1); + +# ed70 became legal IN F,(C) + +r800:ed71 # illegal + illegal_2(); + +r800:ed74 # illegal + illegal_2(); + +r800:ed75 # illegal + illegal_2(); + +r800:ed76 # illegal + illegal_2(); + +r800:ed7c # illegal + illegal_2(); + +r800:ed7d # illegal + illegal_2(); + +r800:ed7e # illegal + illegal_2(); + +r800:ed7f # illegal + illegal_2(); + +r800:edc1 # MULUB A,B + mulub(B); T(12); + +r800:edc3 # MULUW HL,BC + muluw(BC); T(34); + +r800:edc9 # MULUB A,C + mulub(C); T(12); + +r800:edd1 # MULUB A,D + mulub(D); T(12); + +r800:edd9 # MULUB A,E + mulub(E); T(12); + +r800:ede1 # MULUB A,H (undocumented) + mulub(H); T(12); + +r800:ede9 # MULUB A,L (undocumented) + mulub(L); T(12); + +r800:edf1 # MULUB A,A (undocumented) + mulub(A); T(12); + +r800:edf3 # MULUW HL,SP + muluw(SP); T(34); + +r800:edf9 # MULUB A,A (undocumented) + mulub(A); T(12); + +r800:00f3 # DI + m_iff1 = m_iff2 = 0; T(1); + + + +########################################################## +# Z80N +########################################################## +macro ldix + { + call rm HL + if (TDAT8 != A) { + call wm DE + ; + } + HL++; + DE++; + BC--; + } + +macro lddx + { + call rm HL + if (TDAT8 != A) { + call wm DE + ; + } + DE++; + HL--; + BC--; + } + +z80n:ed23 # swapnib + A = (A << 4) | (A >> 4); + +z80n:ed24 # mirror a + A = bitswap<8>(A, 0, 1, 2, 3, 4, 5, 6, 7); + +z80n:ed27 # test * + TDAT_H = A; + call arg + and_a(TDAT8); + A = TDAT_H; + +z80n:ed28 # bsla de,b + DE <<= std::min(B & 31, 16); + +z80n:ed29 # bsra de,b + { + const u16 fill = (DE & 0x8000) ? ~u16(0) : u16(0); + DE = (DE >> std::min(B & 31, 16)) | (fill << (16 - std::min(B & 31, 16))); + } + +z80n:ed2a # bsrl de,b + DE >>= std::min(B & 31, 16); + +z80n:ed2b # bsrf de,b + DE = (DE >> std::min(B & 31, 16)) | (~u16(0) << (16 - std::min(B & 31, 16))); + +z80n:ed2c # brlc de,b + DE = (DE << (B & 15)) | (DE >> (16 - (B & 15))); + +z80n:ed30 # mul d,e + DE = D * E; + +z80n:ed31 # add hl,a + HL += A; + +z80n:ed32 # add de,a + DE += A; + +z80n:ed33 # add bc,a + BC += A; + +z80n:ed34 # add hl,** + call arg16 + HL += TDAT; + +z80n:ed35 # add de,** + call arg16 + DE += TDAT; + +z80n:ed36 # add bc,** + call arg16 + BC += TDAT; + +z80n:ed8a # push ** + call arg + TDAT_H = TDAT_L; + call arg + call push TDAT + +z80n:ed90 # outinb + call rm HL + call out BC + HL++; + +z80n:ed91 # nextreg *,* + call arg16 + m_out_nextreg_cb(TDAT_L, TDAT_H); + +z80n:ed92 # nextreg *,a + call arg + m_out_nextreg_cb(TDAT8, A); + +z80n:ed93 # pixeldn + if (0x07 != (H & 0x07)) + HL = HL + 0x100; + else if (0xe0 != (L & 0xe0)) + HL = (HL & 0xf8ff) + 0x20; + else + HL = (HL & 0xf81f) + 0x800; + +z80n:ed94 # pixelad + HL = 0x4000 + ((D & 0xc0) << 5) + ((D & 0x07) << 8) + ((D & 0x38) << 2) + (E >> 3); + +z80n:ed95 # setae + A = 0x80 >> (E & 7); + +z80n:ed98 # jp (c) + call in BC + PC = (PC & 0xc000) + (TDAT8 << 6); + +z80n:eda4 # ldix + call ldix + +z80n:eda5 # ldws + call rm HL + call wm DE + L++; + inc(D); + +z80n:edac # lddx + call lddx + +z80n:edb4 # ldirx + call ldix + if (BC != 0) + PC -= 2; + +z80n:edb7 # ldpirx + call rm (HL & 0xfff8) + (E & 7) + if (TDAT8 != A) { + call wm DE + ; + } + DE++; + BC--; + if (BC != 0) + PC -= 2; + +z80n:edbc # lddrx + call lddx + if (BC != 0) + PC -= 2; diff --git a/src/devices/cpu/z80/z80dasm.cpp b/src/devices/cpu/z80/z80dasm.cpp index f579fd6d62d..fcd358c3c78 100644 --- a/src/devices/cpu/z80/z80dasm.cpp +++ b/src/devices/cpu/z80/z80dasm.cpp @@ -2,13 +2,12 @@ // copyright-holders:Juergen Buchmueller /***************************************************************************** * - * z80dasm.c + * z80dasm.cpp * Portable Z80 disassembler * *****************************************************************************/ #include "emu.h" -#include "debugger.h" #include "z80dasm.h" @@ -23,19 +22,31 @@ static const char *const s_mnemonic[] = "retn","rl" ,"rla" ,"rlc" ,"rlca","rld" ,"rr" ,"rra" , "rrc" ,"rrca","rrd" ,"rst" ,"sbc" ,"scf" ,"set" ,"sla" , "sll" ,"sra" ,"srl" ,"sub" ,"xor " + + // z80n + ,"swap","mirr","test", + "bsla","bsra","bsrl","bsrf","brlc","mul" ,"otib","nreg", + "pxdn","pxad","stae","ldix","ldws","lddx","lirx","lprx", + "ldrx" }; const u32 z80_disassembler::s_flags[] = { 0 ,0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 , STEP_OVER,0 ,STEP_OVER,0 ,0 ,0 ,0 ,0 , - STEP_OVER,0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 , + STEP_COND,0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 , 0 ,STEP_OVER,0 ,STEP_OVER,0 ,0 ,0 ,0 , STEP_OVER,0 ,STEP_OVER,0 ,0 ,0 ,STEP_OVER,STEP_OVER, 0 ,0 ,0 ,0 ,0 ,0 ,STEP_OUT ,STEP_OUT , STEP_OUT ,0 ,0 ,0 ,0 ,0 ,0 ,0 , 0 ,0 ,0 ,STEP_OVER,0 ,0 ,0 ,0 , 0 ,0 ,0 ,0 ,0 + + // z80n + ,0 ,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 , + 0 }; const z80_disassembler::z80dasm z80_disassembler::mnemonic_xx_cb[256] = @@ -216,13 +227,13 @@ const z80_disassembler::z80dasm z80_disassembler::mnemonic_ed[256] = {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, - {zLDI,nullptr}, {zCPI,nullptr}, {zINI,nullptr}, {zOUTI,nullptr}, + {zLDI,nullptr}, {zCPI,nullptr}, {zINI,nullptr}, {zOUTI,nullptr}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, - {zLDD,nullptr}, {zCPD,nullptr}, {zIND,nullptr}, {zOUTD,nullptr}, + {zLDD,nullptr}, {zCPD,nullptr}, {zIND,nullptr}, {zOUTD,nullptr}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, - {zLDIR,nullptr}, {zCPIR,nullptr}, {zINIR,nullptr}, {zOTIR,nullptr}, + {zLDIR,nullptr},{zCPIR,nullptr},{zINIR,nullptr},{zOTIR,nullptr}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, - {zLDDR,nullptr}, {zCPDR,nullptr}, {zINDR,nullptr}, {zOTDR,nullptr}, + {zLDDR,nullptr},{zCPDR,nullptr},{zINDR,nullptr},{zOTDR,nullptr}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, @@ -341,7 +352,7 @@ const z80_disassembler::z80dasm z80_disassembler::mnemonic_main[256] = {zLD,"l,b"}, {zLD,"l,c"}, {zLD,"l,d"}, {zLD,"l,e"}, {zLD,"l,h"}, {zLD,"l,l"}, {zLD,"l,(hl)"}, {zLD,"l,a"}, {zLD,"(hl),b"}, {zLD,"(hl),c"}, {zLD,"(hl),d"}, {zLD,"(hl),e"}, - {zLD,"(hl),h"}, {zLD,"(hl),l"}, {zHLT,nullptr}, {zLD,"(hl),a"}, + {zLD,"(hl),h"}, {zLD,"(hl),l"}, {zHLT,nullptr}, {zLD,"(hl),a"}, {zLD,"a,b"}, {zLD,"a,c"}, {zLD,"a,d"}, {zLD,"a,e"}, {zLD,"a,h"}, {zLD,"a,l"}, {zLD,"a,(hl)"}, {zLD,"a,a"}, {zADD,"a,b"}, {zADD,"a,c"}, {zADD,"a,d"}, {zADD,"a,e"}, @@ -380,7 +391,7 @@ const z80_disassembler::z80dasm z80_disassembler::mnemonic_main[256] = char z80_disassembler::sign(s8 offset) { - return (offset < 0)? '-':'+'; + return (offset < 0) ? '-' : '+'; } u32 z80_disassembler::offs(s8 offset) @@ -415,7 +426,7 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data d = &mnemonic_cb[op]; break; case 0xed: - d = &mnemonic_ed[opcodes.r8(pos++)]; + d = &get_mnemonic_ed(opcodes.r8(pos++)); if (d->mnemonic == zDB) pos--; break; @@ -423,7 +434,7 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data { ixy = "ix"; u8 op1 = opcodes.r8(pos++); - if( op1 == 0xcb ) + if (op1 == 0xcb) { offset = params.r8(pos++); op1 = params.r8(pos++); @@ -441,7 +452,7 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data { ixy = "iy"; u8 op1 = opcodes.r8(pos++); - if( op1 == 0xcb ) + if (op1 == 0xcb) { offset = params.r8(pos++); op1 = params.r8(pos++); @@ -460,44 +471,49 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data break; } - if( d->arguments ) + uint32_t flags = s_flags[d->mnemonic]; + if (d->arguments) { util::stream_format(stream, "%-4s ", s_mnemonic[d->mnemonic]); const char *src = d->arguments; - while( *src ) + while (*src) { - switch( *src ) + switch (*src) { - case '?': /* illegal opcode */ + case '?': // illegal opcode util::stream_format(stream, "$%02x", op ); break; case 'A': util::stream_format(stream, "$%04X", params.r16(pos) ); pos += 2; + if (src != d->arguments) + flags |= STEP_COND; break; - case 'B': /* Byte op arg */ + case 'B': // Byte op arg util::stream_format(stream, "$%02X", params.r8(pos++) ); break; - case 'N': /* Immediate 16 bit */ + case 'N': // Immediate 16 bit util::stream_format(stream, "$%04X", params.r16(pos) ); pos += 2; break; - case 'O': /* Offset relative to PC */ + case 'O': // Offset relative to PC util::stream_format(stream, "$%04X", (pc + s8(params.r8(pos++)) + 2) & 0xffff); + if (src != d->arguments) + flags |= STEP_COND; break; - case 'P': /* Port number */ + case 'P': // Port number util::stream_format(stream, "$%02X", params.r8(pos++) ); break; - case 'V': /* Restart vector */ + case 'V': // Restart vector util::stream_format(stream, "$%02X", op & 0x38 ); break; - case 'W': /* Memory address word */ + case 'W': // Memory address word util::stream_format(stream, "$%04X", params.r16(pos) ); pos += 2; break; case 'X': offset = params.r8(pos++); - /* fall through */ + [[fallthrough]]; case 'Y': util::stream_format(stream,"(%s%c$%02x)", ixy, sign(offset), offs(offset) ); break; @@ -506,14 +522,17 @@ offs_t z80_disassembler::disassemble(std::ostream &stream, offs_t pc, const data break; default: stream << *src; + break; } src++; } + if (d->mnemonic == zRET) + flags |= STEP_COND; } else { util::stream_format(stream, "%s", s_mnemonic[d->mnemonic]); } - return (pos - pc) | s_flags[d->mnemonic] | SUPPORTED; + return (pos - pc) | flags | SUPPORTED; } diff --git a/src/devices/cpu/z80/z80dasm.h b/src/devices/cpu/z80/z80dasm.h index 774f4df89a8..5067e7f25e2 100644 --- a/src/devices/cpu/z80/z80dasm.h +++ b/src/devices/cpu/z80/z80dasm.h @@ -30,6 +30,7 @@ protected: enum e_mnemonics { + // z80 zADC ,zADD ,zAND ,zBIT ,zCALL ,zCCF ,zCP ,zCPD , zCPDR ,zCPI ,zCPIR ,zCPL ,zDAA ,zDB ,zDEC ,zDI , zDJNZ ,zEI ,zEX ,zEXX ,zHLT ,zIM ,zIN ,zINC , @@ -39,6 +40,12 @@ protected: zRETN ,zRL ,zRLA ,zRLC ,zRLCA ,zRLD ,zRR ,zRRA , zRRC ,zRRCA ,zRRD ,zRST ,zSBC ,zSCF ,zSET ,zSLA , zSLL ,zSRA ,zSRL ,zSUB ,zXOR + + // z80n + ,zSWAP ,zMIRR ,zTEST , + zBSLA ,zBSRA ,zBSRL ,zBSRF ,zBRLC ,zMUL ,zOTIB ,zNREG , + zPXDN ,zPXAD ,zSTAE ,zLDIX ,zLDWS ,zLDDX ,zLIRX ,zLPRX , + zLDRX }; static inline char sign(s8 offset); @@ -51,6 +58,7 @@ protected: static const z80dasm mnemonic_xx[256]; static const z80dasm mnemonic_main[256]; + virtual const z80dasm &get_mnemonic_ed(u8 opcode) { return mnemonic_ed[opcode]; } }; #endif diff --git a/src/devices/cpu/z80/z80make.py b/src/devices/cpu/z80/z80make.py new file mode 100644 index 00000000000..023cdfd29ba --- /dev/null +++ b/src/devices/cpu/z80/z80make.py @@ -0,0 +1,351 @@ +#!/usr/bin/python +# license:BSD-3-Clause +# copyright-holders:Andre I. Holub +from __future__ import print_function + +USAGE = """ +Usage: +%s [type] z80.lst z80.inc +""" +import sys + +class IndStr: + def __init__(self, src, indent = None): + self.str = src.strip() + self.indent = indent + if not indent: + self.indent = src[:len(src) - len(src.lstrip())] + + def line(self): + return self.str + + def get_indent(self): + return self.indent + + def is_comment(self): + return self.str.startswith("#") and not self.str.startswith("#if") and not self.str.startswith("#endif") + + def is_blank(self): + return not self.str + + def has_indent(self): + return self.indent != '' + + def strip_indent(self, n): + if self.indent != '': + self.indent = self.indent[n:] + + def replace(self, new): + self.str = new + + def replace(self, old, new): + return IndStr(self.str.replace(old, new), self.indent) + + def with_str(self, new_str): + return IndStr(new_str, self.indent) + + def split(self): + return self.str.split() + + def print(self, str, f): + print("\t\t%s%s" % (self.indent, str), file=f) + + + +class Opcode: + def __init__(self, prefix, code): + self.prefix = prefix + self.code = code + self.source = [] + + def add_source_lines(self, lines): + self.source.extend(lines) + + def with_steps(self): + for i in range(0, len(self.source)): + tokens = self.source[i].line().split() + if (tokens[0] == '+') or (len(tokens) > 2 and tokens[1] == "!!"): + return True + return False + + def save_dasm(self, step_switch: bool, f): + has_steps = self.with_steps() + if has_steps: + if step_switch: + print("\t\tswitch (u8(m_ref))", file=f) + print("\t\t{", file=f) + print("\t\tcase 0x00:", file=f) + else: + print("\t\t//case 0x00:", file=f) + step = 0 + for i in range(0, len(self.source)): + il = self.source[i] + if not has_steps or not step_switch: + il.strip_indent(1) + line = il.line() + tokens = line.split() + last_line = i + 1 == len(self.source) + + if tokens[0] == '+': + il.print("m_icount -= %s;" % (" ".join(tokens[1:])), f) + step += 1 + il.print("if (m_icount <= 0) {", f) + if not last_line: + to_step = hex(256 + step)[3:] + il.print(" m_ref = 0x%s%s%s;" % (self.prefix, self.code, to_step), f) + il.print(" return;", f) + il.print("}", f) + if step_switch: + il.print("[[fallthrough]];", f) + print("\t\tcase 0x%s:" % (to_step), file=f) + else: + print("\t\t//case 0x%s:" % (to_step), file=f) + else: + il.print(" m_ref = 0xffff00;", f) + il.print(" return;", f) + il.print("}", f) + elif (len(tokens) > 2 and tokens[1] == "!!"): + step += 1; + if step_switch: + il.print("[[fallthrough]];", f) + print("\t\tcase 0x%s:" % (hex(256 + step)[3:]), file=f) + else: + print("\t\t//case 0x%s:" % (hex(256 + step)[3:]), file=f) + il.print("%s" % " ".join(tokens[2:]), f) + il.print("m_icount -= %s;" % (tokens[0]), f) + il.print("if (m_icount <= 0) {", f) + il.print(" if (access_to_be_redone()) {", f) + il.print(" m_icount += %s;" % (tokens[0]), f) + il.print(" m_ref = 0x%s%s%s;" % (self.prefix, self.code, hex(256 + step)[3:]), f) + il.print(" } else {", f) + if not last_line: + step += 1 + to_step = hex(256 + step)[3:] + il.print(" m_ref = 0x%s%s%s;" % (self.prefix, self.code, to_step), f) + il.print(" }", f) + il.print(" return;", f) + il.print("}", f) + if step_switch: + il.print("[[fallthrough]];", f) + print("\t\tcase 0x%s:" % (to_step), file=f) + else: + print("\t\t//case 0x%s:" % (to_step), file=f) + else: + il.print(" m_ref = 0xffff00;", f) + il.print(" }", f) + il.print(" return;", f) + il.print("}", f) + else: + il.print("%s" % line, f) + if has_steps and step_switch: + print("\t\t}", file=f) + +class Macro: + def __init__(self, name, arg_name = None): + self.name = name + self.source = [] + self.arg_name = arg_name + + def apply(self, arg): + if self.arg_name is not None: + return [ r.replace(self.arg_name, arg) for r in self.source ] + else: + return self.source + + def add_source_lines(self, lines): + self.source.extend(lines) + +class OpcodeList: + def __init__(self, gen, fname): + self.gen = gen + self.opcode_info = {} # prefix -> [Opcode] + self.macros = {} + + try: + f = open(fname, "r") + except Exception: + err = sys.exc_info()[1] + sys.stderr.write("Cannot read opcodes file %s [%s]\n" % (fname, err)) + sys.exit(1) + + inf = None + for ln in f: + line = IndStr(ln) + # Skip comments except macros + if line.is_comment() or line.is_blank(): + continue + if line.has_indent(): + if inf is not None: + if isinstance(inf, Macro): + inf.add_source_lines([line]) + else: + inf.add_source_lines(self.pre_process(line)) + else: + # New opcode + tokens = line.split() + if tokens[0] == "macro": + arg_name = None + if len(tokens) > 2: + arg_name = tokens[2] + nnames = tokens[1].split(":") + if len(nnames) == 2: + inf = Macro(nnames[1], arg_name) + if nnames[0] == self.gen: + self.macros[nnames[1]] = inf + else: + inf = Macro(nnames[0], arg_name) + if None == self.gen: + if nnames[0] in self.macros: + sys.stderr.write("Replacing macro: %s\n" % nnames[0]) + self.macros[nnames[0]] = inf + else: + if not nnames[0] in self.macros: + self.macros[nnames[0]] = inf + else: + ntokens = tokens[0].split(":") + gen = None if len(ntokens) == 1 else ntokens[0] + prefix = ntokens[0][:2] if len(ntokens) == 1 else ntokens[1][:2] + opcode = ntokens[0][2:] if len(ntokens) == 1 else ntokens[1][2:] + if self.opcode_info.get(prefix) is None: + self.opcode_info[prefix] = [] + opcodes = self.opcode_info[prefix] + + if None == gen: + inf = Opcode(prefix, opcode) + opcodes.append(inf) + elif gen == self.gen: + # Replace for ext generator + found = False + found_index = 0 + for i in range(len(opcodes)): + if opcodes[i].code == opcode: + found = True + found_index = i + if found: + inf = Opcode(prefix, opcode) + opcodes[found_index] = inf + else: + sys.stderr.write("[%s] Cannot find opcode: %s%s\n" % (gen, prefix, opcode)) + sys.exit(1) + else: + inf = Opcode(prefix, '/dev/null') + + def pre_process(self, iline): + out = [] + line = iline.str + line_toc = line.split() + times = 1 + if len(line_toc) > 2 and line_toc[1] == "*": + times = int(line_toc[0]) + line_toc = line_toc[2:] + line = " ".join(line_toc) + for i in range(times): + if line_toc[0] == 'call': + name = line_toc[1] + arg = None + if len(line_toc) > 2: + arg = " ".join(line_toc[2:]) + if name in self.macros: + macro = self.macros[name] + ([out.extend(self.pre_process(il)) for il in macro.apply(arg)]) + else: + sys.stderr.write("Macro not found %s\n" % name) + out.append(iline.with_str("... %s" % name)) + else: + out.append(iline.with_str(line)) + return out + + def switch_prefix(self, prefixes, reenter: bool, f): + prefix_switch = len(prefixes) > 1 + + if prefix_switch: + print("switch (u8(m_ref >> 16)) // prefix", file=f) + print("{", file=f) + + for prefix in sorted(prefixes): + is_rop = prefix == 'ff' + opc_switch = not is_rop + if prefix_switch: + print("case 0x%s:" % (prefix), file=f) + print("{", file=f) + if opc_switch: + print("\tswitch (u8(m_ref >> 8)) // opcode", file=f) + print("\t{", file=f) + for opc in self.opcode_info[prefix]: + # reenter loop only process steps > 0 + if not reenter or opc.with_steps(): + if opc_switch: + print("\tcase 0x%s:" % (opc.code), file=f) + opc.save_dasm(step_switch=reenter, f=f) + print("\t\tcontinue;", file=f) + print("", file=f) + if opc_switch: + print("\t}", file=f) + + if prefix_switch: + print("} break; // prefix: %s" % (prefix), file=f) + print("", file=f) + if prefix_switch: + print("} // switch prefix", file=f) + + def save_exec(self, f): + print("if (m_wait_state)", file=f) + print("{", file=f) + print("\tm_icount = 0; // stalled", file=f) + print("\treturn;", file=f) + print("}", file=f) + print("", file=f) + print("const bool nomemrq_en = !m_nomreq_cb.isunset();", file=f) + print("[[maybe_unused]] const bool refresh_en = !m_refresh_cb.isunset();", file=f) + print("", file=f) + print("bool interrupted = true;", file=f) + print("while (u8(m_ref) != 0x00) {", file=f) + print("// slow re-enter", file=f) + print("\t// workaround to simulate main loop behavior where continue statement relays on having it set after", file=f) + print("\tif (!interrupted) {", file=f) + print("\t\tm_ref = 0xffff00;", file=f) + print("\t\tcontinue;", file=f) + print("\t}", file=f) + print("\tinterrupted = false;", file=f) + print("", file=f) + self.switch_prefix(self.opcode_info.keys(), reenter=True, f=f) + print("", file=f) + print('assert((void("switch statement above must cover all possible cases!"), false));', file=f) + print("} // end: slow", file=f) + print("if (m_ref != 0xffff00) goto process;", file=f) + print("", file=f) + print("while (true) { // fast process", file=f) + print("\t\t// rop: unwrapped ff prefix", file=f) + self.switch_prefix(['ff'], reenter=False, f=f) + print("", file=f) + print("process:", file=f) + self.switch_prefix(self.opcode_info.keys() - ['ff'], reenter=False, f=f) + print("} // end: fast", file=f) + print('assert((void("unreachable!"), false));', file=f) + +def main(argv): + if len(argv) != 3 and len(argv) != 4: + print(USAGE % argv[0]) + return 1 + + fidx = 1 + gen = None + if len(argv) == 4: + gen = argv[1] + fidx = 2 + + opcodes = OpcodeList(gen, argv[fidx]) + + try: + f = open(argv[fidx + 1], "w") + except Exception: + err = sys.exc_info()[fidx] + sys.stderr.write("cannot write file %s [%s]\n" % (argv[fidx + 1], err)) + sys.exit(1) + + opcodes.save_exec(f) + f.close() + +# ====================================================================== +if __name__ == "__main__": + sys.exit(main(sys.argv)) diff --git a/src/devices/cpu/z80/z80n.cpp b/src/devices/cpu/z80/z80n.cpp new file mode 100644 index 00000000000..52e804d69d1 --- /dev/null +++ b/src/devices/cpu/z80/z80n.cpp @@ -0,0 +1,49 @@ +// license:BSD-3-Clause +// copyright-holders:Andrei I. Holub +/*************************************************************************** + Z80N +***************************************************************************/ + +#include "emu.h" +#include "z80n.h" +#include "z80ndasm.h" + +#include "z80.inc" + +#define LOG_INT (1U << 1) // z80.lst + +//#define VERBOSE (LOG_INT) +#include "logmacro.h" + + +DEFINE_DEVICE_TYPE(Z80N, z80n_device, "z80n", "Z80N") + +std::unique_ptr<util::disasm_interface> z80n_device::create_disassembler() +{ + return std::make_unique<z80n_disassembler>(); +} + +z80n_device::z80n_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) + : z80_device(mconfig, Z80N, tag, owner, clock) + , m_out_retn_seen_cb(*this) + , m_in_nextreg_cb(*this, 0) + , m_out_nextreg_cb(*this) +{ +} + +void z80n_device::execute_run() +{ + #include "cpu/z80/z80n.hxx" +} + +void z80n_device::device_start() +{ + z80_device::device_start(); + save_item(NAME(m_stackless)); +} + +void z80n_device::device_reset() +{ + z80_device::device_reset(); + m_stackless = 0; +} diff --git a/src/devices/cpu/z80/z80n.h b/src/devices/cpu/z80/z80n.h new file mode 100644 index 00000000000..d4d452955fd --- /dev/null +++ b/src/devices/cpu/z80/z80n.h @@ -0,0 +1,45 @@ +// license:BSD-3-Clause +// copyright-holders:Andrei I. Holub +#ifndef MAME_CPU_Z80_Z80N_H +#define MAME_CPU_Z80_Z80N_H + +#pragma once + +#include "z80.h" + +class z80n_device : public z80_device +{ +public: + // construction/destruction + z80n_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); + + auto in_nextreg_cb() { return m_in_nextreg_cb.bind(); } + auto out_nextreg_cb() { return m_out_nextreg_cb.bind(); } + auto out_retn_seen_cb() { return m_out_retn_seen_cb.bind(); } + + bool nmi_stackless_r() { return m_stackless; } + void nmi_stackless_w(bool data) { m_stackless = data; } + + void nmi() { set_service_attention<SA_NMI_PENDING, 1>(); } + +protected: + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; + + // device_execute_interface implementation + virtual void execute_run() override; + + devcb_write8 m_out_retn_seen_cb; + devcb_read8 m_in_nextreg_cb; + devcb_write8 m_out_nextreg_cb; + + virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; + +private: + bool m_stackless; + +}; + +DECLARE_DEVICE_TYPE(Z80N, z80n_device) + +#endif // MAME_CPU_Z80_Z80N_H diff --git a/src/devices/cpu/z80/z80ndasm.cpp b/src/devices/cpu/z80/z80ndasm.cpp new file mode 100644 index 00000000000..ccf5be7ef98 --- /dev/null +++ b/src/devices/cpu/z80/z80ndasm.cpp @@ -0,0 +1,77 @@ +// license:BSD-3-Clause +/***************************************************************************** + * + * Z80N disassembler + * + *****************************************************************************/ + +#include "emu.h" +#include "z80ndasm.h" + +const z80_disassembler::z80dasm z80n_disassembler::mnemonic_ed_n[256] = +{ + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zSWAP,nullptr}, + {zMIRR,nullptr},{zDB,"?"}, {zDB,"?"}, {zTEST,"B"}, + {zBSLA,"de,b"}, {zBSRA,"de,b"}, {zBSRL,"de,b"}, {zBSRF,"de,b"}, + {zBRLC,"de,b"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zMUL,"d,e"}, {zADD,"hl,a"}, {zADD,"de,a"}, {zADD,"bc,a"}, + {zADD,"hl,W"}, {zADD,"de,W"}, {zADD,"bc,W"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zIN,"b,(c)"}, {zOUT,"(c),b"}, {zSBC,"hl,bc"}, {zLD,"(W),bc"}, + {zNEG,nullptr}, {zRETN,nullptr},{zIM,"0"}, {zLD,"i,a"}, + {zIN,"c,(c)"}, {zOUT,"(c),c"}, {zADC,"hl,bc"}, {zLD,"bc,(W)"}, + {zNEG,"*"}, {zRETI,nullptr},{zIM,"0"}, {zLD,"r,a"}, + {zIN,"d,(c)"}, {zOUT,"(c),d"}, {zSBC,"hl,de"}, {zLD,"(W),de"}, + {zNEG,"*"}, {zRETN,nullptr},{zIM,"1"}, {zLD,"a,i"}, + {zIN,"e,(c)"}, {zOUT,"(c),e"}, {zADC,"hl,de"}, {zLD,"de,(W)"}, + {zNEG,"*"}, {zRETI,nullptr},{zIM,"2"}, {zLD,"a,r"}, + {zIN,"h,(c)"}, {zOUT,"(c),h"}, {zSBC,"hl,hl"}, {zLD,"(W),hl"}, + {zNEG,"*"}, {zRETN,nullptr},{zIM,"0"}, {zRRD,"(hl)"}, + {zIN,"l,(c)"}, {zOUT,"(c),l"}, {zADC,"hl,hl"}, {zLD,"hl,(W)"}, + {zNEG,"*"}, {zRETI,nullptr},{zIM,"0"}, {zRLD,"(hl)"}, + {zIN,"0,(c)"}, {zOUT,"(c),0"}, {zSBC,"hl,sp"}, {zLD,"(W),sp"}, + {zNEG,"*"}, {zRETN,nullptr},{zIM,"1"}, {zDB,"?"}, + {zIN,"a,(c)"}, {zOUT,"(c),a"}, {zADC,"hl,sp"}, {zLD,"sp,(W)"}, + {zNEG,"*"}, {zRETI,nullptr},{zIM,"2"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zPUSH,"B,B"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zOTIB,nullptr},{zNREG,"B,B"}, {zNREG,"B,a"}, {zPXDN,nullptr}, + {zPXAD,nullptr},{zSTAE,nullptr},{zDB,"?"}, {zDB,"?"}, + {zJP,"(c)"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLDI,nullptr}, {zCPI,nullptr}, {zINI,nullptr}, {zOUTI,nullptr}, + {zLDIX,nullptr},{zLDWS,nullptr},{zDB,"?"}, {zDB,"?"}, + {zLDD,nullptr}, {zCPD,nullptr}, {zIND,nullptr}, {zOUTD,nullptr}, + {zLDDX,nullptr},{zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zLDIR,nullptr},{zCPIR,nullptr},{zINIR,nullptr},{zOTIR,nullptr}, + {zLIRX,nullptr},{zDB,"?"}, {zDB,"?"}, {zLPRX,nullptr}, + {zLDDR,nullptr},{zCPDR,nullptr},{zINDR,nullptr},{zOTDR,nullptr}, + {zLDRX,nullptr},{zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, + {zDB,"?"}, {zDB,"?"}, {zDB,"?"}, {zDB,"?"} +}; diff --git a/src/devices/cpu/z80/z80ndasm.h b/src/devices/cpu/z80/z80ndasm.h new file mode 100644 index 00000000000..7ae021ced93 --- /dev/null +++ b/src/devices/cpu/z80/z80ndasm.h @@ -0,0 +1,23 @@ +// license:BSD-3-Clause +/***************************************************************************** + * + * Z80N disassembler + * + *****************************************************************************/ + +#ifndef MAME_CPU_Z80_Z80NDASM_H +#define MAME_CPU_Z80_Z80NDASM_H + +#pragma once + +#include "z80dasm.h" + +class z80n_disassembler : public z80_disassembler +{ +protected: + static const z80dasm mnemonic_ed_n[256]; + + virtual const z80dasm &get_mnemonic_ed(u8 opcode) override { return mnemonic_ed_n[opcode]; } +}; + +#endif diff --git a/src/devices/cpu/z80/z84c015.cpp b/src/devices/cpu/z80/z84c015.cpp new file mode 100644 index 00000000000..60108e15c0d --- /dev/null +++ b/src/devices/cpu/z80/z84c015.cpp @@ -0,0 +1,133 @@ +// license:BSD-3-Clause +/*************************************************************************** + + Zilog Z84C015, MPUZ80/Z8400/84C00 Family + Z80 CPU, SIO, CTC, CGC, PIO, WDT + +***************************************************************************/ + +#include "emu.h" +#include "z84c015.h" + +#include "z80.inc" + +DEFINE_DEVICE_TYPE(Z84C015, z84c015_device, "z84c015", "Zilog Z84C015") + +void z84c015_device::internal_io_map(address_map &map) const +{ + tmpz84c015_device::internal_io_map(map); + map(0xee, 0xee).mirror(0xff00).rw(FUNC(z84c015_device::scrp_r), FUNC(z84c015_device::scrp_w)); + map(0xef, 0xef).mirror(0xff00).rw(FUNC(z84c015_device::scdp_r), FUNC(z84c015_device::scdp_w)); +} + +z84c015_device::z84c015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : tmpz84c015_device(mconfig, Z84C015, tag, owner, clock, address_map_constructor(FUNC(z84c015_device::internal_io_map), this)) + , m_program_space_config("program", ENDIANNESS_LITTLE, 8, 18, 0, 16, 0) + , m_opcodes_space_config("opcodes", ENDIANNESS_LITTLE, 8, 18, 0, 16, 0) +{ +} + +device_memory_interface::space_config_vector z84c015_device::memory_space_config() const +{ + auto r = z80_device::memory_space_config(); + for (auto it = r.begin(); it != r.end(); ++it) + { + if ((*it).first == AS_IO) + (*it).second = &m_io_space_config; + else if ((*it).first == AS_OPCODES) + (*it).second = &m_opcodes_space_config; + else if ((*it).first == AS_PROGRAM) + (*it).second = &m_program_space_config; + } + + return r; +} + +bool z84c015_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) +{ + if (spacenum == AS_PROGRAM || spacenum == AS_OPCODES) + address = translate_memory_address(address); + + target_space = &space(spacenum); + return true; +} + +u32 z84c015_device::translate_memory_address(u16 addr) +{ + const u8 csbr = csbr_r(); + const u8 at = BIT(addr, 12, 4); + return ((BIT(m_mcr, 0) && ((csbr & 0x0f) >= at)) // cs0 + ? 0x10000 + : (BIT(m_mcr, 1) && ((csbr >> 4) >= at) && (at > (csbr & 0x0f))) // cs1 + ? 0x20000 : 0) | addr; +} + +u8 z84c015_device::data_read(u16 addr) +{ + return m_data.read_interruptible(translate_memory_address(addr)); +} + +void z84c015_device::data_write(u16 addr, u8 value) +{ + m_data.write_interruptible(translate_memory_address(addr), value); +} + +u8 z84c015_device::opcode_read() +{ + return m_opcodes.read_byte(translate_memory_address(PC)); +} + +u8 z84c015_device::arg_read() +{ + return m_args.read_byte(translate_memory_address(PC)); +} + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- +void z84c015_device::device_start() +{ + tmpz84c015_device::device_start(); + + // register for save states + save_item(NAME(m_scrp)); + save_item(NAME(m_wcr)); + save_item(NAME(m_mwbr)); + save_item(NAME(m_csbr)); + save_item(NAME(m_mcr)); + + scrp_w(0); + m_wcr = 0x00; // 0xff, then 0x00 on 16th M1 + m_mwbr = 0xf0; + m_csbr = 0xff; // Must be `|= 0x0f` but keep ff for reproducible startup + m_mcr = 0x01; + + state_add_divider(-1); + state_add(Z84_WCR, "WCR", m_wcr); + state_add(Z84_MWBR, "MWBR", m_mwbr); + state_add(Z84_CSBR, "CSBR", m_csbr); + state_add(Z84_MCR, "MCR", m_mcr); +} + +u8 z84c015_device::scdp_r() +{ + if (m_scrp < 0x04) + { + const u8 regs[4] = { m_wcr, m_mwbr, m_csbr, m_mcr }; + return regs[m_scrp]; + } + else + return 0xff; +} + +void z84c015_device::scdp_w(u8 data) +{ + if (m_scrp == 0x00) + m_wcr = data; + else if (m_scrp == 0x01) + m_mwbr = data; + else if (m_scrp == 0x02) + m_csbr = data; + else if (m_scrp == 0x03) + m_mcr = data; +} diff --git a/src/devices/cpu/z80/z84c015.h b/src/devices/cpu/z80/z84c015.h new file mode 100644 index 00000000000..0b5261cba34 --- /dev/null +++ b/src/devices/cpu/z80/z84c015.h @@ -0,0 +1,69 @@ +// license:BSD-3-Clause +/*************************************************************************** + + Zilog Z84C015, MPUZ80/Z8400/84C00 Family + Z80 CPU, SIO, CTC, CGC, PIO, WDT + +***************************************************************************/ + +#ifndef MAME_CPU_Z80_Z84C015_H +#define MAME_CPU_Z80_Z84C015_H + +#pragma once + +#include "tmpz84c015.h" + + +enum +{ + Z84_WCR = Z80_WZ + 1, Z84_MWBR, Z84_CSBR, Z84_MCR +}; + +/*************************************************************************** + TYPE DEFINITIONS +***************************************************************************/ + +class z84c015_device : public tmpz84c015_device +{ +public: + z84c015_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + u8 csbr_r() { return m_csbr; } + +protected: + // device-level overrides + virtual void device_start() override ATTR_COLD; + + const address_space_config m_program_space_config; + const address_space_config m_opcodes_space_config; + + void internal_io_map(address_map &map) const; + virtual space_config_vector memory_space_config() const override; + virtual bool memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) override; + + u8 data_read(u16 addr) override; + void data_write(u16 addr, u8 value) override; + u8 opcode_read() override; + u8 arg_read() override; + +private: + u32 translate_memory_address(u16 address); + + // system control registers + u8 m_scrp; + u8 m_wcr; + u8 m_mwbr; + u8 m_csbr; + u8 m_mcr; + + u8 scrp_r() { return m_scrp; }; + void scrp_w(u8 data) { m_scrp = data; }; + u8 scdp_r(); + void scdp_w(u8 data); +}; + +// device type definition +DECLARE_DEVICE_TYPE(Z84C015, z84c015_device) + + +#endif // MAME_CPU_Z80_Z84C015_H |